CN116776787A - Automatic recognition method of signal alias, electronic equipment and medium - Google Patents
Automatic recognition method of signal alias, electronic equipment and medium Download PDFInfo
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Abstract
The invention relates to the technical field of chips, in particular to an automatic identification method of signal aliases, electronic equipment and a medium, wherein the method comprises the following steps of S1, obtaining a target signal list { A } 1 ,A 2 ,…,A m ,…,A M -a }; step S2, for each A m Setting a corresponding signal alias mapping set B m Each B is m Initially empty, traversing the design code, obtaining each A m Signal aliases of (2), and values corresponding to the signal aliases, generate each A m Corresponding B m The method comprises the steps of carrying out a first treatment on the surface of the Step S3, obtaining A in the chip design simulation process m Based on the current value of A m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a). The invention can automatically identify signal aliases in the chip design simulation process, and improves the readability of the chip design simulation.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method for automatically identifying signal aliases, an electronic device, and a medium.
Background
In the chip design process, when the code is written, a corresponding data structure is usually defined for the realization of the algorithm, and the data needs to be constantly assigned in the simulation process. During chip verification, it is often necessary to check whether the signal values of the critical signals at different times meet expectations. Also for some data structures, it is more desirable to display the signal alias corresponding to the signal value than the corresponding signal value. For example, in a finite state machine design, each state would correspond to a signal value and a signal alias for that signal value, with the developer being more concerned with the signal alias than the signal value. However, in the actual simulation process, the existing simulation software often records the state change of the finite state machine by adopting a signal value mode of an output signal, and can not automatically identify and display signal aliases, so that the readability of chip design simulation is poor. Therefore, how to realize the automatic identification of signal aliasing in the chip design simulation process and improve the readability of the chip design simulation becomes a technical problem to be solved.
Disclosure of Invention
The invention aims to provide an automatic identification method, electronic equipment and medium for signal aliases, which can automatically identify the signal aliases in the chip design simulation process and improve the readability of the chip design simulation.
According to a first aspect of the present invention, there is provided a method for automatically identifying signal aliases, comprising:
step S1, obtaining a target signal list { A } 1 ,A 2 ,…,A m ,…,A M }，A m For the mth target signal, the value range of M is 1 to M, and the target signal is a signal which needs to display signal alias in the chip design simulation process;
step S2, for each A m Setting a correspondingSignal alias mapping set B of (2) m Each B is m Initially empty, traversing the design code, obtaining each A m Signal aliases of (2), and values corresponding to the signal aliases, generate each A m Corresponding B m ；
Step S3, obtaining A in the chip design simulation process m Based on the current value of A m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a).
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the automatic identification method of the signal alias, the electronic equipment and the medium provided by the invention can achieve quite technical progress and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:
according to the embodiment of the invention, the signal alias is quickly positioned through the signal numerical value by constructing the signal alias mapping set, so that the corresponding signal alias is presented, the readability of the running state of the chip simulation design is greatly improved, and the chip design efficiency is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for automatically identifying signal aliases according to an embodiment of the invention;
fig. 2 is a code example provided in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides an automatic signal alias identification method, which is shown in fig. 1 and comprises the following steps:
step S1, obtaining a target signal list { A } 1 ,A 2 ,…,A m ,…,A M }，A m And for the mth target signal, the value range of M is 1 to M, and the target signal is a signal which needs to display signal aliases in the chip design simulation process.
It should be noted that, in the hardware description language (Hardware Description Language, abbreviated as HDL), a local parameter may be predefined, and a readable name may be set for each parameter, as illustrated in fig. 2, where st_start, st_progress, st_panding, st_end are local parameters, st_start corresponds to 0, st_progress corresponds to 1, st_panding corresponds to 2, and st_end corresponds to 3. The corresponding values of the parameters are fixed in the design process. In the chip simulation process, the program code continuously updates the value of a Finite State Machine (FSM) signal through defined parameters. Other chip simulation processes can respond according to specific needs or FSM values. The signal FSM assigns different parameters at different times, such as st_start, st_progress, st_end, it being understood that st_start, st_progress, st_end are signal aliases of the FSM.
Step S2, for each A m Setting a corresponding signal alias mapping set B m Each B is m Initially empty, traversing the design code, obtaining each A m Signal aliases of (2), and values corresponding to the signal aliases, generate each A m Corresponding B m 。
In the example shown in fig. 2, four values { st_start, st_progress, st_panding, st_end } can be obtained based on step S2, and the values for one based on each parameter are as follows: st_start- >0, a signal alias mapping set of FSM can be obtained { (st_start, 0), (st_progress, 1), (st_progress, 2), (st_end, 3) }.
Step S3, obtaining A in the chip design simulation process m Based on the current value of A m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a).
The step S3 can be used for acquiring A in the chip design simulation process according to the simulation time or the operation step m By means of the signal alias mapping set of FSM { (st_start, 0), (st_progress, 1), (st_progress, 2), (st_end, 3) }, it can be determined that the signal corresponding to the current value of FSM is named st_progress, and when the data of FSM is displayed, the alias can be directly displayed, thereby improving the readability.
It should be noted that, in the embodiment of the present invention, each a may be pre-generated directly based on the design code m Corresponding B m Or synchronously generating each A in the chip design simulation process m Corresponding B m 。
As an embodiment, the method further comprises:
step S10, acquiring a chip design code from a preset first database to execute a chip design simulation process, generating simulation data, and storing the simulation data in a preset second database, wherein the simulation data comprises a signal identifier, a signal value and corresponding clock information.
It should be noted that the first database and the second database are set independently. Generated signal alias mapping set B m Can be stored in a memory or can be provided withPlacing a third database to map the signal alias into a set B m Stored in a third database.
The target signal list may have only one target signal or may have a plurality of target signals, where the target signals may be signals that are directly specified by the user and are focused by the user, or may be predicted according to the simulation result, and specifically, as an embodiment, the step S1 includes:
and S11, determining candidate signals based on all simulation data stored in the preset second database, wherein the number of signal values of the candidate signals is more than or equal to 2.
It will be appreciated that only if the number of signal values of the candidate signals is equal to or greater than 2, there is a need to display signal aliases, and therefore, the candidate signal whose number of signal values is equal to or greater than 2 is determined as a candidate signal.
Step S12, selecting M candidate signals as the target signal list { A } 1 ,A 2 ,…,A m ,…,A M }。
Wherein, according to the specific application requirement, M candidate signals can be selected from the candidate signals as the target signal list.
As another embodiment, the target signal is directly specified by the user, specifically, the step S1 includes:
step R11, generating the target signal list { A } based on the target signals specified by the user 1 ,A 2 ,…,A m ,…,A M }。
As an embodiment, the step S2 includes:
step S21, traversing A in chip design codes m Is to obtain A m Signal alias C in an assignment statement of (2) i m 。
Step S22, judging the current C i m Whether or not it has been stored in B m If so, step S24 is performed, otherwise, step S23 is performed.
S23, obtaining the current C from the parameter definition statement in the chip design code i m Corresponding value D i m Signal alias map pair (C i m ，D i m ) Stored in B m Is a kind of medium.
Step S24, if the traversing chip design code is completed, generating each A m Corresponding B m Otherwise, the process returns to step S21.
Through steps S21-S24, A can be obtained m Signal alias mapping pairs composed of all signal aliases and corresponding signal values, all of which are spread and stored in B m Is a kind of medium. It should be noted that, the steps S21 to S24 may be performed in advance before the chip simulation, or may be performed synchronously during the chip simulation, that is, each a may be dynamically generated while the chip is simulated m Corresponding B m 。
In some application scenarios, different A m There is also a hierarchical relationship between, e.g., in the chip source code, there is a i =A j As will be appreciated, A i And A j Are all { A ] 1 ,A 2 ,…,A m ,…,A M The range of the values of i and j of one target signal in the sequence is 1 to M, and i is not equal to j. In this case, if each A is obtained by adopting the steps S21-S24 m Corresponding B m Based on the fact that repeated computation is generated and the hierarchical relationship between signals cannot be obtained clearly, the embodiment of the invention further provides a method for generating each A m Corresponding B m As an embodiment, the step S2 includes:
step R21, traversing A in chip design codes m Is to obtain A m Signal alias C in an assignment statement of (2) i m 。
Step R22, judging the current C i m Whether or not it has been stored in B m If so, step R27 is performed, otherwise, step R23 is performed.
Step R23, judging C i m Whether or not it is { A 1 ,A 2 ,…,A m ,…,A M If yes, go to step R25, otherwise, go to step R26.
Step R25, judge B m Whether or not to store C i m If yes, executing a step R27, otherwise executing a step R26.
Step R26, at B m Added with D i m Reference identification of corresponding signal alias mapping set, B m Enabling referencing D based on the referencing identity i m The corresponding set of signal alias mappings is then executed in step R27.
Wherein the reference identifier may specifically be in the form of a pointer or the like.
R27, if the traversing chip design code is completed, executing R28, otherwise, returning to execute R21;
step R28, the reference mark of the signal alias mapping set exists in the signal alias mapping set corresponding to the reference mark of the signal alias mapping set and A also exists m The alias signal in (a) is from A m Removing to generate each A m Corresponding B m 。
Note that { a 1 ,A 2 ,…,A m ,…,A M The element in the assignment statement should normally appear to the left of the assignment statement, the right of the assignment statement is the signal alias, when { A 1 ,A 2 ,…,A m ,…,A M When the element in the assignment statement appears on the right side of the assignment statement, the target signals on the left side and the right side of the assignment statement are in a hierarchical relationship, and then the signal alias mapping set corresponding to the target signals on the right side of the assignment statement is a subset of the signal alias mapping set corresponding to the target signals on the left side of the assignment statement. If obtained one by one according to S21-step S24, a huge repetition of calculation is required and it is impossible to obtain from each A m The corresponding signal alias mapping set intuitively obtains the hierarchical relationship, and the calculation amount for generating the signal alias mapping set can be reduced through the steps R25-R28, and the hierarchical relationship can also be intuitively obtained through the signal alias mapping set.
As an embodiment, the step S3 includes:
step S31, obtaining a chip original code corresponding to the current chip design simulation process from a preset first database, and displaying the corresponding chip original code on a preset first display interface.
Step S32, obtaining A corresponding to the current chip design simulation process from a preset second database m Based on the current value of A m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a).
Step S33, A m Signal alias corresponding to the current value of (a) is identified at a m On the waveform diagram of (a), A is presented on a preset second display interface m Is a waveform diagram of (a).
It should be noted that, the first display interface and the second display interface are independently set, so that information corresponding to the current chip design simulation process can be visually displayed at the same time, and associated information is set for skipping.
As an embodiment, in the step S32, the method is based on the a m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a), comprising:
step S321, if A m The current value of B m In the signal alias mapping set referenced in (a), step S322 is performed, if a m The current value of the current value is directly stored in B m Step S323 is executed.
Step S322, generate B m The reference relation information is integrated with A m The current value of B m Signal alias splice generation A in the signal alias mapping set referenced in m Signal aliases corresponding to the current value of (a).
Step S323, directly follow B m Acquisition of A m Signal aliases corresponding to the current value of (a).
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, the signal alias is quickly positioned through the signal numerical value by constructing the signal alias mapping set, so that the corresponding signal alias is presented, the readability of the running state of the chip simulation design is greatly improved, and the chip design efficiency is greatly improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. An automatic recognition method of signal aliases, comprising:
step S1, obtaining a target signal list { A } 1 ,A 2 ,…,A m ,…,A M }，A m For the mth target signal, the value range of M is 1 to M, and the target signal is a signal which needs to display signal alias in the chip design simulation process;
step S2, for each A m A pair is arrangedSignal alias mapping set B m Each B is m Initially empty, traversing the design code, obtaining each A m Signal aliases of (2), and values corresponding to the signal aliases, generate each A m Corresponding B m ；
Step S3, obtaining A in the chip design simulation process m Based on the current value of A m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a).
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the method further comprises the steps of:
step S10, acquiring a chip design code from a preset first database to execute a chip design simulation process, generating simulation data, and storing the simulation data in a preset second database, wherein the simulation data comprises a signal identifier, a signal value and corresponding clock information.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the step S1 includes:
step S11, determining candidate signals based on all simulation data stored in the preset second database, wherein the number of signal values of the candidate signals is more than or equal to 2;
step S12, selecting M candidate signals as the target signal list { A } 1 ,A 2 ,…,A m ,…,A M }。
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S1 includes:
step R11, generating the target signal list { A } based on the target signals specified by the user 1 ,A 2 ,…,A m ,…,A M }。
5. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the step S2 includes:
step S21, traversing A in chip design codes m Is to obtain A m Signal alias C in an assignment statement of (2) i m ；
Step S22, judging the current C i m Whether or not it has been stored in B m If yes, executing step S24, otherwise, executing step S23;
s23, obtaining the current C from the parameter definition statement in the chip design code i m Corresponding value D i m Signal alias map pair (C i m ，D i m ) Stored in B m In (a) and (b);
step S24, if the traversing chip design code is completed, generating each A m Corresponding B m Otherwise, the process returns to step S21.
6. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the step S2 includes:
step R21, traversing A in chip design codes m Is to obtain A m Signal alias C in an assignment statement of (2) i m ；
Step R22, judging the current C i m Whether or not it has been stored in B m If yes, executing the step R27, otherwise, executing the step R23;
step R23, judging C i m Whether or not it is { A 1 ,A 2 ,…,A m ,…,A M If yes, executing a step R25, otherwise, executing a step R26;
step R25, judge B m Whether or not to store C i m If yes, executing a step R27, otherwise, executing a step R26;
step R26, at B m Added with D i m Reference identification of corresponding signal alias mapping set, B m Enabling referencing D based on the referencing identity i m A corresponding signal alias mapping set, executing step R27;
r27, if the traversing chip design code is completed, executing R28, otherwise, returning to execute R21;
step R28, the reference mark of the signal alias mapping set exists in the signal alias mapping set corresponding to the reference mark of the signal alias mapping set and A also exists m The alias signal in (a) is from A m Removing to generate each A m Corresponding B m 。
7. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the step S3 includes:
step S31, acquiring a chip original code corresponding to a current chip design simulation process from a preset first database, and presenting the corresponding chip original code on a preset first display interface;
step S32, obtaining A corresponding to the current chip design simulation process from a preset second database m Based on the current value of A m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a);
step S33, A m Signal alias corresponding to the current value of (a) is identified at a m On the waveform diagram of (a), A is presented on a preset second display interface m Is a waveform diagram of (a).
8. The method of claim 7, wherein the step of determining the position of the probe is performed,
in the step S32, based on the a m Corresponding B is queried for the current value of (B) m Determination of A m Signal aliases corresponding to the current value of (a), comprising:
step S321, if A m The current value of B m In the signal alias mapping set referenced in (a), step S322 is performed, if a m The current value of the current value is directly stored in B m Step S323 is executed;
step S322, generate B m The reference relation information is integrated with A m The current value of B m Signal alias splice generation A in the signal alias mapping set referenced in m Signal aliases corresponding to the current value of (a);
step S323, directly follow B m Acquisition of A m Signal aliases corresponding to the current value of (a).
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117150995A (en) * | 2023-10-30 | 2023-12-01 | 北京云枢创新软件技术有限公司 | Driving source code tracking method, electronic equipment and medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410841A (en) * | 2006-05-03 | 2009-04-15 | 国际商业机器公司 | Method, system and program product supporting specification of signals for simulation result viewing |
| WO2016112161A1 (en) * | 2015-01-08 | 2016-07-14 | BlueTalon, Inc. | Distributed storage and distributed processing query statement reconstruction in accordance with a policy |
| CN114896173A (en) * | 2022-07-12 | 2022-08-12 | 北京云枢创新软件技术有限公司 | Data processing system for target data path display |
-
2023
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410841A (en) * | 2006-05-03 | 2009-04-15 | 国际商业机器公司 | Method, system and program product supporting specification of signals for simulation result viewing |
| WO2016112161A1 (en) * | 2015-01-08 | 2016-07-14 | BlueTalon, Inc. | Distributed storage and distributed processing query statement reconstruction in accordance with a policy |
| CN114896173A (en) * | 2022-07-12 | 2022-08-12 | 北京云枢创新软件技术有限公司 | Data processing system for target data path display |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117150995A (en) * | 2023-10-30 | 2023-12-01 | 北京云枢创新软件技术有限公司 | Driving source code tracking method, electronic equipment and medium |
| CN117150995B (en) * | 2023-10-30 | 2024-01-23 | 北京云枢创新软件技术有限公司 | Driving source code tracking method, electronic equipment and medium |
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