CN116775525A - Data transmission circuit, method, device, equipment and medium - Google Patents

Data transmission circuit, method, device, equipment and medium Download PDF

Info

Publication number
CN116775525A
CN116775525A CN202310654883.7A CN202310654883A CN116775525A CN 116775525 A CN116775525 A CN 116775525A CN 202310654883 A CN202310654883 A CN 202310654883A CN 116775525 A CN116775525 A CN 116775525A
Authority
CN
China
Prior art keywords
pin
data transmission
level
usb
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310654883.7A
Other languages
Chinese (zh)
Inventor
罗健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vivo Mobile Communication Co Ltd
Original Assignee
Vivo Mobile Communication Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Priority to CN202310654883.7A priority Critical patent/CN116775525A/en
Publication of CN116775525A publication Critical patent/CN116775525A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application discloses a data transmission circuit, a method, a device, equipment and a medium, and belongs to the technical field of electronic circuits. The circuit comprises: the system on chip comprises a system on chip, a USB interface and a first level clamping unit, wherein the USB interface comprises a first side pin and a second side pin, and the system on chip comprises a first control pin, a first group of pins corresponding to the first side pin and a second group of pins corresponding to the second side pin; the first side pins are correspondingly and electrically connected with the first group of pins, and the second side pins are correspondingly and electrically connected with the second group of pins; the first level clamping unit is connected between a first control pin and a first target pin, wherein the first target pin is a pin used for communication handshake based on a first USB communication protocol in the first side pin; when the communication handshake based on the first USB communication protocol is successful and the data transmission is interrupted, the level of the first control pin is a second level, and the first level clamping unit clamps the level of the first target pin to the second level.

Description

Data transmission circuit, method, device, equipment and medium
Technical Field
The present application relates to electronic circuits, and more particularly, to a data transmission circuit, a data transmission method, a data transmission device, an electronic apparatus, and a readable storage medium.
Background
Data transmission between two electronic devices, such as a mobile phone and a computer, through a USB interface has become a common data transmission mode. Currently, USB interfaces typically employ the communication protocol of USB 3.0. The high-speed data transmission bandwidth of the USB3.0 can reach more than 5Gbps, so that the USB3.0 can support more and larger data transmission, and therefore, the USB3.0 is more applied to the field requiring high-speed data transmission.
For USB3.0, it is USB 2.0-compatible downward. And in the standard USB protocol, after the two electronic devices complete the USB3.0 handshake successfully, the handshake of the USB2.0 is not performed any more. When the USB3.0 handshake fails, the USB2.0 handshake is performed. That is, in the case that the two electronic devices interrupt data transmission due to poor signal quality after completing the USB3.0 handshake successfully, the two electronic devices will not actively perform a USB2.0 communication handshake with a lower and more stable rate. Which can lead to a complete interruption of the data transmission between the two electronic devices.
Disclosure of Invention
The embodiment of the application aims to provide a data transmission circuit, a method, a device, equipment and a medium, which can solve the problem that two electronic equipment cannot actively carry out communication handshake of USB2.0 with lower speed and more stability under the condition that the data transmission is interrupted due to poor signal quality and the like after the handshake of USB3.0 is successful.
In a first aspect, an embodiment of the present application provides a data transmission circuit, including: system on chip, USB interface and first level clamping unit, wherein:
the USB interface comprises a first side pin and a second side pin, and the system on chip comprises a first control pin, a first group of pins corresponding to the first side pin and a second group of pins corresponding to the second side pin;
the first side pins are correspondingly and electrically connected with the first group of pins, and the second side pins are correspondingly and electrically connected with the second group of pins;
the first level clamping unit is connected between the first control pin and a first target pin, wherein the first target pin is a pin used for communication handshake based on a first USB communication protocol in the first side pin;
under the condition that communication handshake based on the first USB communication protocol is successful and data transmission is continuous, the first control pin is in a high-resistance state, the first target pin is in a first level, the first side pin is communicated with the first group of pins, and the first level is the level of the first target pin when the communication handshake based on the first USB communication protocol is successful;
When the communication handshake based on the first USB communication protocol is successful and data transmission is interrupted, the level of the first control pin is a second level, the first level clamping unit clamps the level of the first target pin to a second level, the second side pin is communicated with the second group of pins, and the second level is the level of the first target pin when the communication handshake based on the first USB communication protocol fails.
In a second aspect, an embodiment of the present application provides a data transmission method, applied to the data transmission circuit in the first aspect, where the method includes:
restarting the communication handshake when the data transmission circuit is in the condition that the communication handshake based on the first USB communication protocol is successful and the data communication is interrupted;
setting the level of the first control pin as a second level;
and setting the first control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a first USB communication protocol and data transmission is continuous.
In a third aspect, an embodiment of the present application provides a data transmission device applied to the data transmission circuit as described in the first aspect, the data transmission device including:
A restarting module, configured to restart the communication handshake when the data transmission circuit is in a condition that the communication handshake based on the first USB communication protocol is successful and the data communication is interrupted;
the control module is used for setting the level of the first control pin as a second level, and setting the first control pin as a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a first USB communication protocol and data transmission is continuous.
In a fourth aspect, embodiments of the present application provide an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method as described in the second aspect;
alternatively, the electronic device comprises the data transmission circuit of the first aspect.
In a fifth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor implement the steps of the method according to the second aspect.
In a sixth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and where the processor is configured to execute a program or instructions to implement a method according to the second aspect.
In a seventh aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement the method according to the second aspect.
The embodiment of the application provides a data transmission circuit, which comprises: the USB interface comprises a first side pin and a second side pin, and the system on a chip comprises a first control pin, a first group of pins corresponding to the first side pin and a second group of pins corresponding to the second side pin; the first side pins are correspondingly and electrically connected with the first group of pins, and the second side pins are correspondingly and electrically connected with the second group of pins; the first level clamping unit is connected between a first control pin and a first target pin, wherein the first target pin is a pin used for communication handshake based on a first USB communication protocol in the first side pin; under the conditions that communication handshake based on a first USB communication protocol is successful and data transmission is continuous, the first control pin is in a high-resistance state, the first target pin is in a first level, the first side pin is communicated with the first group of pins, and the first level is the level of the first target pin when the communication handshake based on the first USB communication protocol is successful; when the communication handshake based on the first USB communication protocol is successful and the data transmission is interrupted, the level of the first control pin is a second level, the first level clamping unit clamps the level of the first target pin to the second level, the second side pin is communicated with the second group of pins, and the second level is the level of the first target pin when the communication handshake based on the first USB communication protocol fails. The data transmission circuit provided by the embodiment of the application provides a hardware foundation for the two electronic devices to actively perform USB2.0 communication handshake under the condition that the data transmission is interrupted due to poor signal quality and the like after the two electronic devices complete USB3.0 handshake successfully.
Drawings
Fig. 1 is a schematic diagram of a data transmission circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a data transmission circuit according to an embodiment of the present application;
fig. 3 is a schematic diagram of a data transmission circuit according to an embodiment of the present application;
fig. 4 is a flow chart of a data transmission method according to an embodiment of the application;
fig. 5 is a schematic structural diagram of a data transmission device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application;
fig. 7 is a schematic diagram of a hardware structure of an electronic device for implementing an embodiment of the present application.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or otherwise described herein, and that the objects identified by "first," "second," etc. are generally of a type not limited to the number of objects, for example, the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The data transmission circuit, the method, the device, the equipment and the medium provided by the embodiment of the application are described in detail through specific embodiments and application scenes thereof by combining the attached drawings.
An embodiment of the present application provides a data transmission circuit 100, as shown in fig. 1, the data transmission circuit 100 includes: a system on chip 110, a USB interface 120, and a first level clamping unit 130, wherein:
the USB interface 120 includes a first side pin 121 and a second side pin 122, and the system on chip 110 includes a first control pin 113, a first set of pins 111 corresponding to the first side pin 121, and a second set of pins 112 corresponding to the second side pin 122;
the first side pins 121 are correspondingly and electrically connected with the first group of pins 111, and the second side pins 122 are correspondingly and electrically connected with the second group of pins 112;
the first level clamping unit 130 is connected between the first control pin 113 and a first target pin, the first target pin being a pin in the first side pin 121 for a communication handshake based on the first USB communication protocol;
under the condition that the communication handshake based on the first USB communication protocol is successful and the data transmission is continuous, the first control pin is in a high-resistance state, the first target pin is in a first level, the first side pin 121 is communicated with the first group of pins 111, and the first level is the level of the first target pin when the communication handshake based on the first USB communication protocol is successful;
When the handshake based on the first USB communication protocol is successful and the data transmission is interrupted, the level of the first control pin 113 is a second level, the first level clamping unit 130 clamps the level of the first target pin to the second level, the second side pin 122 is communicated with the second group of pins 112, and the second level is the level of the first target pin when the handshake based on the first USB communication protocol fails.
In one embodiment of the present application, USB interface 120 may be a front-back interface or a one-way interface. The front and back interfaces can be USB Type-c interfaces, and the single-sided interfaces can be USB Type-a interfaces.
The first side pin 121 includes a set of pins for a communication handshake based on a first USB communication protocol. The second side pin 122 includes a set of pins for a communication handshake based on a second USB communication protocol. For the USB interface of the single-sided socket, the first side pin 121 and the second side pin 122 are pins of the same single side. For the USB interface with the front-back interface, the first side interface 121 and the second side interface 122 are pins on the same surface. That is, the description about "side" in the embodiment of the present application is merely to distinguish pins, not "side" in the spatial concept.
The first set of pins 111 is identical to the corresponding pins of the first side pins 121, except that the first set of pins 111 is located on the system on chip 110 and the first side pins 121 are located in the USB interface 120. As are the second set of pins 112 and the second side pins 122.
The first side pins 121 are in communication with the first set of pins 111, which means that data communication is performed on the basis of an electrical connection, such as performing a first USB communication protocol handshake, performing output transmission based on the first USB communication handshake, etc.
The second side pins 122 are in communication with the second set of pins 112, which refers to data communication based on electrical connection, such as performing a second USB communication protocol handshake, performing output transmission based on the second USB communication handshake, and so on. Wherein the first USB communication protocol handshake is downward compatible with the second USB communication protocol handshake.
In one example, the first USB communication protocol is USB3.0 and the first USB communication protocol is USB2.0.
It should be noted that, in fig. 1, USB interface 120 is shown as an example of the USB Type-c interface, and only some pins in the USB Type-c interface are shown in fig. 1: TX1+, TX1-, RX1+, RX1-, DP1, DM1, VBUS, part of pins in system on chip 110: TX1+, TX1-, RX1+, RX1-, DP1, DM1, SPMI. And, in FIG. 1, taking TX1+, TX1-, RX1+, RX 1-pins in the system-on-chip 110 as the first set of pins 111, DP1, DM1 in the system-on-chip 110 as the second set of pins 112, TX1-, RX1+, RX 1-in the USB Type-c interface as the first side pin 121, and DP1, DM1 pins in the USB Type-c interface as the second side pin 122 as examples.
In an embodiment of the present application, a GPIO pin that is not used on the system on chip 110 may be used as the first control pin 113 in an embodiment of the present application. The first control pin 113 may be shown as a GPIO1 pin in fig. 1. And, the first control pin 113 is set to a second level or a high resistance state.
The first target pin is a pin in the first side pin 121 for a communication handshake based on the first USB communication protocol. For example, in the case where the first USB communication protocol is USB3.0, the first target pin is a pin used in the first side pin 121 when performing a USB3.0 based communication handshake on the USB interface 120.
Based on the example shown in fig. 1, the first target pin may be any one of TX1+, TX1-, RX1+, RX 1-on the USB interface 120.
The first level clamping unit 130 does not affect the level of the first target pin in the case where the first control pin is in the high resistance state. And in case that the first control pin is at the second level, the first clamping unit 130 clamps the level of the first target pin to the second level.
Typically, the level on the first target pin is a bias level during a communication handshake based on the first USB communication protocol. Based on this, the second level may be a high level or a low level.
In one embodiment of the present application, as shown in fig. 3, the first level clamping unit 130 may be a first resistor 131. Based on this, the second level may be set to a low level by setting the first control pin 113 to ground. And, the second level may be set to a high level by setting the first control pin 113 to be connected to the power source.
In combination with the above, in the case where the first control pin 113 is at the second level, the first level clamp clamps the first target pin to the second level. In combination with the definition of the second level, in this case, the data transmission circuit 100 cannot perform the communication handshake according to the first USB communication protocol, and the communication handshake according to the first USB communication protocol fails. Taking the first USB communication protocol as USB3.0 as an example, at this time, the data transmission circuit 100 cannot perform the communication handshake of USB3.0, and the communication handshake of USB3.0 fails.
Based on the above, on the basis that the external USB data communication device is connected to the first side pin 121 and the second side pin 122 of the USB interface 120, in the case that the first USB communication protocol USB3.0 communication handshake is successful but the data transmission is interrupted, the data transmission circuit 100 may be set to restart the communication handshake by means of software and/or hardware, while setting the level of the first control pin 113 to the second level. In this way, after the data transmission circuit 100 can restart the communication handshake, the first clamping unit 130 clamps the level of the first target pin to the second level, so that the communication handshake of USB3.0 cannot be performed, and the communication handshake of USB3.0 fails. At this time, according to the standard USB protocol, the data transmission circuit 100 performs handshake with the second side pin 122 through the second set of pins 112 according to the second USB communication protocol USB 2.0. In this way, the data transmission circuit can actively perform the communication handshake of the USB2.0 after restarting the communication handshake under the condition that the communication handshake of the USB3.0 is successful but the data transmission is interrupted. In case the communication handshake of USB2.0 is successful, the data transfer may continue. That is, the data transmission circuit 100 provided by the embodiment of the present application provides a hardware basis for the two electronic devices to actively perform the communication handshake of USB2.0 under the condition that the two electronic devices complete the handshake of USB3.0 and then the data transmission is interrupted due to the poor signal quality and other reasons.
Correspondingly, under the condition that the communication handshake based on the first USB communication protocol is successful and the data transmission is continuous, the first control pin is set to be in a high-resistance state. At this time, the first level clamping unit 130 does not affect the first control pin, and the first target pin is at a level that can be successfully handshaking based on the first USB communication protocol, so as to continue to maintain data transmission based on the first USB communication protocol.
The embodiment of the application provides a data transmission circuit, which comprises: the USB interface comprises a first side pin and a second side pin, and the system on a chip comprises a first control pin, a first group of pins corresponding to the first side pin and a second group of pins corresponding to the second side pin; the first side pins are correspondingly and electrically connected with the first group of pins, and the second side pins are correspondingly and electrically connected with the second group of pins; the first level clamping unit is connected between a first control pin and a first target pin, wherein the first target pin is a pin used for communication handshake based on a first USB communication protocol in the first side pin; under the conditions that communication handshake based on a first USB communication protocol is successful and data transmission is continuous, the first control pin is in a high-resistance state, the first target pin is in a first level, the first side pin is communicated with the first group of pins, and the first level is the level of the first target pin when the communication handshake based on the first USB communication protocol is successful; when the communication handshake based on the first USB communication protocol is successful and the data transmission is interrupted, the level of the first control pin is a second level, the first level clamping unit clamps the level of the first target pin to the second level, the second side pin is communicated with the second group of pins, and the second level is the level of the first target pin when the communication handshake based on the first USB communication protocol fails. The data transmission circuit provided by the embodiment of the application provides a hardware foundation for the two electronic devices to actively perform USB2.0 communication handshake under the condition that the data transmission is interrupted due to poor signal quality and the like after the two electronic devices complete USB3.0 handshake successfully.
In an embodiment of the present application, as shown in fig. 2, the data transmission circuit 100 provided in the embodiment of the present application further includes a second level clamping unit 140, the usb interface 120 further includes a third side pin 123 disposed symmetrically in parallel with the first side pin 121, and a fourth side pin 124 disposed symmetrically in parallel with the second side pin 122, and the system on chip 110 further includes a third group of pins 115 corresponding to the third side pin 123 and a fourth group of pins 116 corresponding to the fourth side pin 124, which are the second control pins 114;
the third side pins 123 are correspondingly electrically connected to the third set of pins 115, and the fourth side pins 124 are correspondingly electrically connected to the fourth set of pins 116;
the second level clamping unit 140 is connected between the second control pin 114 and a second target pin, which is a pin for communication handshake based on the first USB communication protocol in the third side pin 123;
under the condition that handshake is successful and data transmission is continuous based on the first USB communication protocol, the second control pin is in a high-resistance state, the second target pin is in a first level, and the third side pin 123 is communicated with the third group of pins 115;
when the communication handshake based on the first USB communication protocol is successful and the data transmission is interrupted, the level of the second control pin is the second level, the second level clamping unit 140 clamps the level of the second target pin to the second level, and the fourth side pin 124 communicates with the fourth group of pins 116.
In the embodiment of the application, the USB interface is a front-back interface. The third side pin 123 contains another set of pins for performing a communication handshake based on the first USB communication protocol. The fourth side pin 124 contains another set of pins for a communication handshake based on the second USB communication protocol. And, in the case that the USB interface is plugged into an external USB data communication device, the external USB data communication device communicates with the first side pin 121 and the second side pin 122, or communicates with the third side pin 123 and the fourth side pin 124.
The third set of pins 115 is identical to the corresponding pins of the third side pin 123, except that the third set of pins 115 is located on the system-on-chip 110 and the third side pin 123 is located in the USB interface 120. As are the fourth set of pins 116 and the fourth side pins 124.
The third side pin 123 communicates with the third set of pins 115, which refers to data communication based on an electrical connection, such as performing a first USB communication protocol handshake, performing output transmission based on the first USB communication handshake, and so on.
The fourth side pin 124 communicates with the fourth set of pins 116, which refers to data communication based on an electrical connection, such as performing a second USB communication protocol handshake, performing output transmission based on the second USB communication handshake, and so on. Wherein the first USB communication protocol handshake is downward compatible with the second USB communication protocol handshake.
In one embodiment of the present application, as shown in fig. 2 or 3, in the case that the first side pins 121 and the first set 111 of pins are TX1+, TX1-, RX1+, RX1-, the second side pins 122 and the second set of pins are DP1, DM1, the third side pins 123 and the third set 115 of pins are TX2+, TX2-, RX2+, RX2-, and the fourth side pins 124 and the fourth set 116 of pins are DP2, DM2. Alternatively, where the first side pin 121 and the first set 111 of pins are Tx2+, tx2-, rx2+, rx2-, the second side pin 122 and the second set of pins are DP2, DM2, the second side pin 122 and the second set 112 of pins are Tx1+, tx1-, rx1+, rx1-, and the fourth side pin 124 and the fourth set 116 of pins are DP1, DM1.
In an embodiment of the present application, one GPIO pin on the system on chip that is not used may be used as the second control pin 114 in an embodiment of the present application. The second control pin 114 may be as shown in the GPIO2 pin in fig. 2 or fig. 3.
The second target pin is a pin of the third side pin 123 for a communication handshake based on the first USB communication protocol. For example, in the case where the first USB communication protocol is USB3.0, the second target pin is a pin used in the third side pin 123 when performing a USB3.0 based communication handshake on the USB interface 120.
Based on the example shown in fig. 1, the second target pin may be any one of TX2+, TX2-, RX2+, RX 2-on USB interface 120, as shown in fig. 2.
The second level clamping unit 140 is configured to not affect the level of the second target pin in the case where the second control pin is in a high resistance state. And in case that the second control pin is at the second level, the second clamping unit 140 clamps the level of the second target pin to the second level.
Typically, the level on the second target pin is a bias level during a communication handshake based on the first USB communication protocol. Based on this, the second level may be a high level or a low level.
In one embodiment of the present application, as shown in fig. 3, the second level clamp 140 may be a second resistor 141. Based on this, the second level may be set to a low level by setting the second control pin 114 to ground. And, the second level may be set to a high level by setting the second control pin 114 to connect to the power supply.
In combination with the above, where the second control pin 114 is at a second level, the second level clamp clamps the second target pin to the second level. In combination with the definition of the second level, in this case, the data transmission circuit 100 cannot perform the communication handshake according to the first USB communication protocol, and the communication handshake according to the first USB communication protocol fails. Taking the first USB communication protocol as USB3.0 as an example, at this time, the data transmission circuit 100 cannot perform the communication handshake of USB3.0, and the communication handshake of USB3.0 fails.
Based on the above, on the basis that the external USB data communication device is connected to the third side pin 123 and the fourth side pin 124 of the USB interface 120, in the case that the first USB communication protocol USB3.0 communication handshake is successful but the data transmission is interrupted, the data transmission circuit 100 may be set to restart the communication handshake by means of software and/or hardware, and at the same time, set the level of the second control pin 114 to the second level. In this way, after the data transmission circuit 100 can restart the communication handshake, the second clamping unit 140 clamps the level of the second target pin to the second level, so that the communication handshake of USB3.0 cannot be performed, and the communication handshake of USB3.0 fails. At this time, according to the standard USB protocol, the data transmission circuit 100 performs handshake with the fourth side pin 124 through the fourth set of pins 116 according to the second USB communication protocol USB 2.0. In this way, it can be realized that the data transmission circuit 100 can actively perform the communication handshake of USB2.0 after restarting the communication handshake in the case that the communication handshake of USB3.0 is successful but the data transmission is interrupted. In case the communication handshake of USB2.0 is successful, the data transfer may continue. That is, the data transmission circuit 100 provided by the embodiment of the present application provides a hardware basis for the two electronic devices to actively perform the communication handshake of USB2.0 under the condition that the two electronic devices complete the handshake of USB3.0 and then the data transmission is interrupted due to the poor signal quality and other reasons.
Correspondingly, under the condition that the communication handshake based on the first USB communication protocol is successful and the data transmission is continuous, the second control pin is set to be in a high-resistance state. At this time, the second level clamping unit 140 does not affect the first control pin, and the second target pin is at a level when the communication handshake based on the first USB communication protocol is successful, so as to continue to maintain the data transmission based on the first USB communication protocol.
In the embodiment of the present application, no matter the external USB data communication device is connected to the first side pin 121 and the second side pin 122 in the USB interface 120, or the third side pin 123 and the fourth side pin 124 in the USB interface 120, the data transmission circuit 100 provided in the embodiment of the present application may provide a hardware basis for the two electronic devices to actively perform the communication handshake of USB2.0 under the condition that the two electronic devices complete the handshake of USB3.0 and then interrupt the data transmission due to the reasons of poor signal quality and the like.
It should be noted that, as shown in fig. 1 to 3, a dc blocking capacitor is generally disposed between one of the pins 111 of the first group and the corresponding pin 121 of the first side. A blocking capacitor is typically provided between one of the third set of pins 115 and its corresponding pin of the third side pin 123. The data transmission circuit 100 further includes a power management unit (PMIC) 150, where the power management unit 150 is connected between the SPMI pin and the VBUS pin. The system on chip 110 may control whether the battery management unit 150 supplies power to the VBUS pin of the USB interface 120 through the SPMI pin.
It can be understood that, in the case where the USB interface 120 is a front-back interface, the USB interface specifically includes two VBUS pins: VBUS1 and VBUS2 pins. In the case where the USB interface 120 is a single-sided interface, the USB interface specifically includes a VBUS pin.
It should be noted that, as shown in fig. 1 to 3, the USB interface 120 is used as a front-back interface, and one of the VBUS pins is used as an example.
The application also provides a data transmission method which is applied to the data transmission circuit 100 shown in fig. 1 or fig. 2, and the USB interface also comprises a power pin. As shown in fig. 4, the method includes S4100 to S4300 as follows:
s4100, restarting the communication handshake if the data transfer circuit is in the communication handshake based on the first USB communication protocol and the data communication is interrupted.
In an embodiment of the present application, an execution body for executing the data transmission method provided by the embodiment of the present application may be specifically a system on a chip on the data transmission circuit.
In an embodiment of the present application, it may be determined according to a conventional manner whether the data transmission circuit is in a condition that handshake is successful and data transmission is interrupted based on the first USB communication protocol. And restarting the communication handshake if the handshake is successful and the data transfer is interrupted based on the first USB communication protocol.
In one embodiment of the present application, the restart communication handshake may be implemented through S4110 and S4111 described below.
S4110, controlling the power pin to be powered off.
S4111, after a preset time period, controlling the power pin to be electrified.
In the embodiment of the application, the USB interface in the data transmission circuit further comprises a power pin. The power pin is specifically the VBUS pin shown in fig. 1-3. In the standard USB protocol, the communication handshake may be restarted when the control power pin is powered off and then the control power pin is powered on.
In the embodiment of the application, the preset time period is in the millisecond level. After the preset time period, the power pin is controlled to be powered on, so that the problem that the system on chip mistakenly considers the power pin power failure in the step S4110 as a power burr can be avoided, and the communication handshake based on the second USB communication protocol is not restarted.
Of course, the communication handshake may be restarted in other ways.
S4200, setting the level of the first control pin to the second level.
The first level clamping unit clamps the first target pin to a second level when the level of the first control pin is a second level, and the second level is the level of the first target pin when communication handshake based on the first USB communication protocol fails.
In the embodiment of the present application, on the basis that the external USB data communication device is connected to the first side pin and the second side pin of the USB interface, in the case that the USB3.0 communication handshake is successful but the data transmission is interrupted, the restart communication handshake is implemented through the above S4100, and the handshake failure based on the first USB communication protocol is implemented through the above S4200. At this time, taking the first USB communication protocol as USB3.0 as an example, according to the standard USB protocol, the data transmission circuit performs a communication handshake of USB 2.0. Therefore, the data transmission circuit can actively perform the communication handshake of the USB2.0 after restarting the communication handshake under the condition that the communication handshake of the USB3.0 is successful but the data transmission is interrupted. In case the communication handshake of USB2.0 is successful, the data transfer may continue. That is, the method provided by the embodiment of the application can realize that the two electronic devices actively perform the communication handshake of the USB2.0 under the condition that the data transmission is interrupted due to the reasons of poor signal quality and the like after the two electronic devices complete the handshake of the USB 3.0.
S4300, setting the first control pin to be in a high-impedance state under the condition that the data transmission circuit is in a communication handshake based on the first USB communication protocol and data transmission is continuous.
In the embodiment of the present application, corresponding to S4100 and S4200 described above, the first control pin is set to a high impedance state in the case that the communication handshake based on the first USB communication protocol is successful and the data transmission is continuous. At this time, the first level clamping unit does not affect the first control pin, and the first target pin is at a level when the communication handshake based on the first USB communication protocol is successful, so as to continuously maintain the data transmission based on the first USB communication protocol.
The embodiment of the application provides a data transmission method, which is applied to the data transmission circuit provided by any one of the embodiments, and comprises the following steps: restarting the communication handshake when the data transmission circuit is in the condition that the communication handshake based on the first USB communication protocol is successful and the data communication is interrupted; setting the level of the first control pin as a second level; and setting the first control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on the first USB communication protocol and data transmission is continuous. Based on the connection of the external USB data communication equipment to the first side pin and the second side pin of the USB interface, the method can realize that the two electronic equipment actively performs the communication handshake of the USB2.0 under the condition that the data transmission is interrupted due to the reasons of poor signal quality and the like after the two electronic equipment completes the handshake of the USB 3.0.
In one embodiment of the present application, the data transmission method provided in the embodiment of the present application further includes the following S4400 and S4500:
s4400, in a case that the data transmission circuit is in a communication handshake based on the first USB communication protocol and the data transmission is interrupted, sets the level of the second control pin to the second level.
And the second level clamping unit clamps the second target pin to a second level when the level of the second control pin is the second level, wherein the second level is the level of the first target pin when communication handshake based on the first USB communication protocol fails.
In the embodiment of the present application, S4200 and S4400 described above may be performed simultaneously.
In the embodiment of the present application, on the basis that the external USB data communication device is connected to the third side pin and the fourth side pin of the USB interface, in the case that the USB3.0 communication handshake is successful but the data transmission is interrupted, the restart communication handshake is implemented through the above S4100, and the handshake failure based on the first USB communication protocol is implemented through the above S4400. At this time, taking the first USB communication protocol as USB3.0 as an example, according to the standard USB protocol, the data transmission circuit performs a communication handshake of USB 2.0. Therefore, the data transmission circuit can actively perform the communication handshake of the USB2.0 after restarting the communication handshake under the condition that the communication handshake of the USB3.0 is successful but the data transmission is interrupted. In case the communication handshake of USB2.0 is successful, the data transfer may continue. That is, the method provided by the embodiment of the application can realize that the two electronic devices actively perform the communication handshake of the USB2.0 under the condition that the data transmission is interrupted due to the reasons of poor signal quality and the like after the two electronic devices complete the handshake of the USB 3.0.
S4500, under the condition that the data transmission circuit is in communication handshake based on the first USB communication protocol successfully and data transmission continues, the second control pin is set to be in a high-impedance state.
In the embodiment of the present application, corresponding to S4100 and S4400 described above, the second control pin is set to a high impedance state under the condition that the communication handshake based on the first USB communication protocol is successful and the data transmission is continuous. At this time, the second level clamping unit does not affect the second control pin, and the second target pin is at a level when the communication handshake based on the first USB communication protocol is successful, so as to continuously maintain the data transmission based on the first USB communication protocol.
In combination with S4100 and S4200, in the embodiment of the present application, whether the external USB data communication device is connected to the first side pin and the second side pin in the USB interface, or the third side pin and the fourth pin in the USB interface, the data transmission method provided in the embodiment of the present application may realize that the two electronic devices actively perform the communication handshake of USB2.0 when the two electronic devices complete the handshake of USB3.0 and then interrupt the data transmission due to the reasons of poor signal quality and the like.
In one embodiment of the present application, the data transmission method provided in the embodiment of the present application further includes the following S4600 and S4700:
S4600, determining the current data transmission position as a transmission suspension position in the case that the data transmission circuit is in the handshake based on the first USB communication protocol successfully and the data transmission is interrupted.
In the embodiment of the application, when the data transmission circuit is in the condition of successful handshake based on the first USB communication protocol and data transmission is interrupted, the interruption of data content transmission to be transmitted is indicated. At this time, the current data transmission position is taken as a transmission suspension position.
It should be noted that the current data transmission position may be determined according to a log recorded by the system on chip.
S4700, transmitting the data content to be transmitted according to the transmission suspension position when the data transmission circuit is in the communication handshake based on the second USB communication protocol successfully.
In the embodiment of the application, when the data transmission circuit is in the condition of successful communication handshake based on the second USB communication protocol, the data transmission can be continued. On the basis of this, the data content to be transmitted is continued to be transmitted from the transmission suspension position.
In one embodiment of the present application, the data transmission method provided in the embodiment of the present application includes the following steps S4800:
s4800, setting the first control pin to be in a high-impedance state under the condition that the data transmission circuit is in a communication handshake based on the second USB communication protocol.
In the embodiment of the present application, the first target pin is not affected by the first level clamping unit when the first control pin is set to be in a high-resistance state. Therefore, after the data transmission based on the second USB communication protocol is finished, if the external USB data communication equipment is pulled out, the external USB data communication equipment is inserted into the USB interface again, and when the external USB data communication equipment is connected with the first side pin and the second side pin in the USB interface, the communication handshake of the first USB communication protocol with higher transmission efficiency can be performed first.
In one embodiment of the present application, the data transmission method provided in the embodiment of the present application includes the following steps S4900:
s4900, setting the second control pin to be in a high-impedance state under the condition that the data transmission circuit is in a communication handshake based on the second USB communication protocol.
In the embodiment of the present application, the first target pin is not affected by the second level clamping unit when the second control pin is set to be in a high-resistance state. In this way, after the data transmission based on the second USB communication protocol is finished, if the external USB data communication device is pulled out, the external USB data communication device is inserted into the USB interface again, and when the external USB data communication device is connected with the third side pin and the fourth side pin in the USB interface, the communication handshake of the first USB communication protocol with higher transmission efficiency can be performed first.
According to the data transmission method provided by the embodiment of the application, the execution main body can be a data transmission device. In the embodiment of the present application, a method for executing data transmission by a data transmission device is taken as an example, and the data transmission device provided by the embodiment of the present application is described.
An embodiment of the present application provides a data transmission device 500, which is applied to the data transmission circuit 100 provided in any one of the embodiments described above, as shown in fig. 5, where the data transmission device 500 includes:
a restarting module 510, configured to restart the communication handshake if the data transmission circuit is in a condition that the communication handshake based on the first USB communication protocol is successful and the data communication is interrupted;
the control module 520 is configured to set the level of the first control pin to be a second level, and set the first control pin to be in a high-impedance state when the data transmission circuit is in a communication handshake based on the first USB communication protocol and the data transmission is continuous.
By the data transmission device provided by the embodiment of the application, the two electronic devices can actively carry out the communication handshake of the USB2.0 under the condition that the data transmission is interrupted due to the reasons of poor signal quality and the like after the two electronic devices finish the handshake of the USB 3.0.
In one embodiment of the present application, the control module 520 is further configured to:
setting the level of the second control pin as a second level under the condition that the data transmission circuit is in communication handshake based on the first USB communication protocol and data transmission is interrupted;
and setting the second control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on the first USB communication protocol and output transmission is continuous.
In one embodiment of the present application, the USB interface in the data transmission circuit further includes a power pin, and based on this, the restart module 510 is specifically configured to:
controlling the power pin to be powered off;
and after a preset time period, controlling the power pin to be electrified.
In one embodiment of the present application, the data transmission device 500 provided in the embodiment of the present application further includes:
a determining module, configured to determine, when the data transmission circuit is in a handshake based on the first USB communication protocol and data transmission is interrupted, a current data transmission position as a transmission suspension position;
the transmission module is used for transmitting the data content to be transmitted according to the transmission suspension position under the condition that the data transmission circuit is in the communication handshake based on the second USB communication protocol successfully;
Wherein the first USB communication protocol is downward compatible with the second USB communication protocol.
In one embodiment of the present application, the control module 520 is further configured to:
and setting the first control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a second USB communication protocol.
In one embodiment of the present application, the control module 520 is further configured to:
and setting the level of the second control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a second USB communication protocol.
The data transmission device in the embodiment of the application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. By way of example, the electronic device may be a mobile phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, mobile internet appliance (Mobile Internet Device, MID), augmented reality (augmented reality, AR)/Virtual Reality (VR) device, robot, wearable device, ultra-mobile personal computer, UMPC, netbook or personal digital assistant (personal digital assistant, PDA), etc., but may also be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., and the embodiments of the present application are not limited in particular.
The data transmission device in the embodiment of the application can be a device with an operating system. The operating system may be an Android operating system, an ios operating system, or other possible operating systems, and the embodiment of the present application is not limited specifically.
The data transmission device provided in the embodiment of the present application can implement each process implemented by the method embodiment of fig. 4, and in order to avoid repetition, a description is omitted here.
Optionally, as shown in fig. 6, the embodiment of the present application further provides an electronic device 600, including a processor 601 and a memory 602, where the memory 602 stores a program or an instruction that can be executed on the processor 601, and the program or the instruction implements each step of the above-mentioned embodiment of the data transmission method when executed by the processor 601, and the steps achieve the same technical effects, so that repetition is avoided, and no further description is given here.
Alternatively, the electronic device 600 includes the data transmission circuit 100 provided in any of the above embodiments.
Fig. 7 is a schematic diagram of a hardware structure of an electronic device for implementing an embodiment of the present application.
The electronic device 100 includes, but is not limited to: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.
Those skilled in the art will appreciate that the electronic device 100 may further include a power source (e.g., a battery) for powering the various components, and that the power source may be logically coupled to the processor 110 via a power management system to perform functions such as managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 7 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.
Wherein, the processor 110 is configured to restart the communication handshake if the data transmission circuit is in the condition that the communication handshake based on the first USB communication protocol is successful and the data communication is interrupted;
setting the level of the first control pin as a second level;
and setting the first control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a first USB communication protocol and data transmission is continuous.
By the electronic equipment provided by the embodiment of the application, the two electronic equipment can actively carry out the communication handshake of the USB2.0 under the condition that the data transmission is interrupted due to the reasons of poor signal quality and the like after the two electronic equipment completes the handshake of the USB 3.0.
Optionally, the processor 110 is further configured to set the level of the second control pin to a second level if the data transmission circuit is in a condition that the communication handshake based on the first USB communication protocol is successful and the data transmission is interrupted;
and setting the second control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on the first USB communication protocol and output transmission is continuous.
Optionally, the processor 110 is specifically configured to control the power pin to be powered off;
and after a preset time period, controlling the power pin to be electrified.
Optionally, the processor 110 is further configured to determine the current data transmission position as a transmission suspension position in a case where the data transmission circuit is in a handshake based on the first USB communication protocol and the data transmission is interrupted;
transmitting the data content to be transmitted according to the transmission suspension position under the condition that the data transmission circuit is in a communication handshake based on a second USB communication protocol;
wherein the first USB communication protocol is downward compatible with the second USB communication protocol.
Optionally, the processor 110 is further configured to set the level of the first control pin to a high impedance state when the data transmission circuit is in a communication handshake based on the second USB communication protocol.
Optionally, the processor 110 is further configured to set the level of the second control pin to a high impedance state when the data transmission circuit is in a communication handshake based on the second USB communication protocol.
It should be appreciated that in embodiments of the present application, the input unit 104 may include a graphics processor (Graphics Processing Unit, GPU) 1041 and a microphone 1042, the graphics processor 1041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also referred to as a touch screen. The touch panel 1071 may include two parts of a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.
Memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 109 may include volatile memory or nonvolatile memory, or the memory x09 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (Enhanced SDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). Memory 109 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.
Processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 110.
The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above-mentioned data transmission method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here.
Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.
The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the data transmission method embodiment, and the same technical effects can be achieved, so that repetition is avoided, and the description is omitted here.
It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the above-described data transmission method embodiments, and achieve the same technical effects, and for avoiding repetition, a detailed description is omitted herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims (11)

1. A data transmission circuit, comprising: system on chip, USB interface and first level clamping unit, wherein:
the USB interface comprises a first side pin and a second side pin, and the system on chip comprises a first control pin, a first group of pins corresponding to the first side pin and a second group of pins corresponding to the second side pin;
the first side pins are correspondingly and electrically connected with the first group of pins, and the second side pins are correspondingly and electrically connected with the second group of pins;
the first level clamping unit is connected between the first control pin and a first target pin, wherein the first target pin is a pin used for communication handshake based on a first USB communication protocol in the first side pin;
under the condition that communication handshake based on the first USB communication protocol is successful and data transmission is continuous, the first control pin is in a high-resistance state, the first target pin is in a first level, the first side pin is communicated with the first group of pins, and the first level is the level of the first target pin when the communication handshake based on the first USB communication protocol is successful;
when the communication handshake based on the first USB communication protocol is successful and data transmission is interrupted, the level of the first control pin is a second level, the first level clamping unit clamps the level of the first target pin to a second level, the second side pin is communicated with the second group of pins, and the second level is the level of the first target pin when the communication handshake based on the first USB communication protocol fails.
2. The circuit of claim 1, wherein the data transmission circuit further comprises a second level clamp, wherein the USB interface further comprises a third side pin arranged in parallel symmetry with the first side pin, a fourth side pin arranged in parallel symmetry with the second side pin, and wherein the system-on-chip further comprises a second control pin, a third set of pins corresponding to the third side pin, and a fourth set of pins corresponding to the fourth side pin;
the third side pins are correspondingly and electrically connected with the third group of pins, and the fourth side pins are correspondingly and electrically connected with the fourth group of pins;
the second level clamping unit is connected between the second control pin and a second target pin, wherein the second target pin is a pin used for communication handshake based on a first USB communication protocol in the third side pin;
under the condition that the communication handshake is successful and the data transmission is continuous based on the first USB communication protocol, the second control pin is in a high-resistance state, the second target pin is in a first level, and the third side pin is communicated with the third group of pins;
when the communication handshake based on the first USB communication protocol is successful and data transmission is interrupted, the level of the second control pin is a second level, the second level clamping unit clamps the level of the second target pin to the second level, and the fourth side pin is communicated with the fourth group of pins.
3. A data transmission method applied to the data transmission circuit according to claim 1 or 2, the method comprising:
restarting the communication handshake when the data transmission circuit is in the condition that the communication handshake based on the first USB communication protocol is successful and the data communication is interrupted;
setting the level of the first control pin as a second level;
and setting the first control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a first USB communication protocol and data transmission is continuous.
4. A method according to claim 3, characterized in that the method further comprises:
setting the level of the second control pin as a second level under the condition that the data transmission circuit is in communication handshake based on the first USB communication protocol and data transmission is interrupted;
and setting the second control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on the first USB communication protocol and output transmission is continuous.
5. A method according to claim 3, wherein the USB interface in the data transfer circuit further comprises a power pin, and the restarting communication handshake comprises:
Controlling the power pin to be powered off;
and after a preset time period, controlling the power pin to be electrified.
6. The method according to claim 4, wherein the method further comprises:
determining a current data transmission position as a transmission suspension position under the condition that the data transmission circuit is successful in handshake based on a first USB communication protocol and data transmission is interrupted;
transmitting the data content to be transmitted according to the transmission suspension position under the condition that the data transmission circuit is in a communication handshake based on a second USB communication protocol;
wherein the first USB communication protocol is downward compatible with the second USB communication protocol.
7. The method of claim 6, wherein the method further comprises:
and setting the first control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a second USB communication protocol.
8. The method of claim 6, wherein the method further comprises:
and setting the second control pin to be in a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a second USB communication protocol.
9. A data transmission apparatus, characterized in that it is applied to the data transmission circuit according to claim 1 or 2, comprising:
a restarting module, configured to restart the communication handshake when the data transmission circuit is in a condition that the communication handshake based on the first USB communication protocol is successful and the data communication is interrupted;
the control module is used for setting the level of the first control pin as a second level, and setting the first control pin as a high-resistance state under the condition that the data transmission circuit is in a communication handshake based on a first USB communication protocol and data transmission is continuous.
10. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the data transmission method of any one of claims 3-8;
alternatively, the electronic device comprises a data transmission circuit as claimed in claim 1 or 2.
11. A readable storage medium, characterized in that the readable storage medium has stored thereon a program or instructions which, when executed by a processor, implement the steps of the data transmission method according to any of claims 3-8.
CN202310654883.7A 2023-06-02 2023-06-02 Data transmission circuit, method, device, equipment and medium Pending CN116775525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310654883.7A CN116775525A (en) 2023-06-02 2023-06-02 Data transmission circuit, method, device, equipment and medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310654883.7A CN116775525A (en) 2023-06-02 2023-06-02 Data transmission circuit, method, device, equipment and medium

Publications (1)

Publication Number Publication Date
CN116775525A true CN116775525A (en) 2023-09-19

Family

ID=87987090

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310654883.7A Pending CN116775525A (en) 2023-06-02 2023-06-02 Data transmission circuit, method, device, equipment and medium

Country Status (1)

Country Link
CN (1) CN116775525A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117640702A (en) * 2024-01-26 2024-03-01 深圳市星卡科技股份有限公司 Communication protocol acquisition method and device, electronic equipment and storage medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117640702A (en) * 2024-01-26 2024-03-01 深圳市星卡科技股份有限公司 Communication protocol acquisition method and device, electronic equipment and storage medium

Similar Documents

Publication Publication Date Title
JP6875547B2 (en) Adapters, terminals, and adapter systems
JP6742465B2 (en) Method, device and bluetooth speaker for continuous wakeup delay reduction in bluetooth speaker
US11113224B2 (en) Display driver board with multiple TYPE-C full-function interfaces
EP3869346B1 (en) Apparatus and method of recognizing external device in a communication system
US9395781B2 (en) Electronic device to perform enumeration without power request to an external device when electronic device is on
CN116775525A (en) Data transmission circuit, method, device, equipment and medium
WO2023125658A1 (en) Electronic device, control method, control apparatus, and readable storage medium
CN104252203B (en) Electronic device, method for controlling electronic device, and program
US20140344704A1 (en) Electronic system
CN112269086A (en) Charging cable identification method and device, charging cable and readable storage medium
US20220132250A1 (en) Mobile Terminal and Control Method
WO2024099182A1 (en) Master/slave node determination method and apparatus, and electronic device and storage medium
US7552245B2 (en) Communication card with three operational states
RU2679253C1 (en) Method, device and terminal for processing fingerprint event
US9570922B2 (en) Charging method and electronic device
US20230378767A1 (en) Charging control method and apparatus, electronic device, and charger
KR20130003645A (en) Method for establishing connection between external device and mobile terminal docking thereat
CN210006035U (en) USB and OTG function switching control circuit, device and mobile terminal
CA2809874A1 (en) Hot swapping swap media at a computing device
CN114598770A (en) Earphone, electronic equipment and control method and device of electronic equipment
CN108777627B (en) Power supply method and device
US20130198417A1 (en) Electronic apparatus
TWI579704B (en) Ssic device and link control method for ssic device
WO2019071380A1 (en) Sleep control method, terminal, and computer readable medium
CN112290639A (en) Interface circuit and electronic equipment charge

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination