CN116775512A

CN116775512A - Page table management device and method, graphics processor and electronic equipment

Info

Publication number: CN116775512A
Application number: CN202311059717.9A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2023-08-22
Filing date: 2023-08-22
Publication date: 2023-09-19
Anticipated expiration: 2043-08-22
Also published as: CN116775512B

Abstract

The invention relates to the field of chips and provides a page table management device, a page table management method, a graphic processor and electronic equipment, wherein the device comprises a page table caching module, an address allocation module and a data output module, and the page table caching module is used for caching available page tables; the address allocation module is used for reading a page table once from the page table cache module when the parameter of one primitive block is read every time, and when the read page table can completely store the primitive block, taking the read page table as a page table allocated to the primitive block, and recording the address of the page table allocated to the primitive block; the data output module is used for reading the address of the page table allocated to the primitive block from the address allocation module when one primitive block is read each time, and outputting the read primitive block after matching with the read address. According to the page table management device disclosed by the embodiment of the invention, the page table allocation flow can be simplified, the flexibility is improved, and the performance of the graphics processor is improved by optimizing the page table allocation mode.

Description

Page table management device and method, graphics processor and electronic equipment

Technical Field

The present disclosure relates to the field of chips, and in particular, to a page table management apparatus, a page table management method, a graphics processor, and an electronic device.

Background

Graphics processors (graphics processing unit, GPUs) typically have a variety of graphics processing engines that spatially transform the coordinates of the input geometric vertices and descriptions of the topology, etc., to generate primitive blocks for subsequent pixel processing. The functions implemented by the GPU geometry processing engine include coordinate transformation, tessellation, clipping, viewport transformation, primitive block generation and output, and the like. After the geometric data processing is completed, the GPU geometry processing engine writes the primitive blocks to an external cache.

For GPU geometry processing engines, primitive blocks are often committed to a particular segment of physical addresses stored in an external cache. Whereas GPUs typically use only virtual addresses, page tables are used in the output of primitive blocks. A page table is a data structure that can be used to record the correspondence between physical addresses and virtual addresses. In the prior art, by applying for the page table, the physical address recorded by the page table belongs to a contracted physical address segment, and the page table is distributed to the corresponding primitive block, so that the primitive block can be stored in the contracted physical address segment after being output.

However, the prior art has complex flow and poor flexibility when realizing page table allocation, and reduces the performance of the graphics processor.

Disclosure of Invention

In view of this, the disclosure provides a page table management device, a method, a graphics processor and an electronic device, where the page table management device according to the embodiments of the disclosure can simplify the page table allocation flow and improve the flexibility by optimizing the page table allocation manner, and improve the performance of the graphics processor.

According to an aspect of the present disclosure, there is provided a page table management apparatus, the apparatus including a page table cache module, an address allocation module, and a data output module, where the page table cache module is configured to cache available page tables; the address allocation module is used for reading a page table once from the page table cache module when the parameter of one primitive block is read every time, taking the read page table as the page table allocated to the primitive block when the read page table can completely store the primitive block, and recording the address of the page table allocated to the primitive block; the data output module is used for reading the address of the page table allocated to the primitive block from the address allocation module when one primitive block is read each time, and outputting the read primitive block after matching with the read address.

In one possible implementation manner, the apparatus further includes a page table control module, where the page table control module is configured to, in an initial state, issue a first page table application signal, where the first page table application signal indicates that a number of page tables equal to a first threshold is generated; in the end state, the generated and unassigned page table in the page table cache module is popped, and a first page table closing signal is sent out, wherein the first page table closing signal indicates closing of the generated and unassigned page table.

In one possible implementation, the data output module is further configured to output, when the address of the current reading is different from the address of the previous reading, the address of the previous reading and a valid enable signal to the page table control module; the page table control module is further configured to send a second page table closing signal when receiving the valid enabling signal and the address read in the previous time, where the second page table closing signal indicates to close a page table corresponding to the address read in the previous time; and after the second page table closing signal is sent out, sending out a second page table application signal, wherein the number of the generated page tables indicated by the second page table application signal is the same as the number of the closed page tables indicated by the second page table closing signal.

In one possible implementation, the address allocation module includes a page table space prediction unit and an address storage unit, where the page table space prediction unit is configured to read a page table from the page table cache module once each time a parameter of a primitive block is read; determining the available data quantity of the read page table according to the pointer stored by the page table space estimating unit; determining the data volume of the primitive block according to the parameters, and judging whether the available data volume of the read page table is larger than or equal to the data volume of the primitive block; when the available data amount of the read page table is larger than or equal to the data amount of the primitive block, determining that the read page table can completely store the primitive block, taking the read page table as a page table allocated to the primitive block, and writing an address of the page table allocated to the primitive block into the address storage unit; and taking the pointer as a starting position, determining an ending position after the read page table is allocated to the primitive block, and updating the pointer according to the ending position.

In one possible implementation manner, the page table space estimating unit is further configured to, when the available data size of the read page table is smaller than the data size of the primitive block, control the page table cache module to pop the page table, and re-execute the operations of reading the page table once and thereafter from the page table cache module; wherein after reading the page table once again, the pointer is updated according to the address lower limit value of the page table read again.

In one possible implementation manner, the address storage unit is configured to record, in order of reading parameters by the page table space estimating unit, addresses allocated to primitive blocks corresponding to the parameters.

In one possible implementation, the page table caching module caches available page tables in the order in which the page tables were generated, and the address allocation module outputs the earliest generated page table each time the page table is read from the page table caching module.

In one possible implementation, the page table cache module caches consecutive or non-consecutive addresses of adjacent page tables.

In one possible implementation manner, one primitive block includes multiple sets of data, the data output module further records an address offset, and the matching between the read primitive block and the read address is output, including: when the address read at this time is different from the address read at the previous time, resetting the address offset; each time data with the data quantity equal to the second threshold value is read, an address corresponding to the data is obtained according to the address offset when the data is read and the address read when the data is read; matching the data with the address corresponding to the data and then outputting the data; and updating the address offset according to the address bit number occupied by the data with the data quantity equal to the second threshold value.

According to another aspect of the present disclosure, there is provided a page table management method applied to a page table management apparatus, the apparatus including a page table cache module, an address allocation module, and a data output module, the method including: the page table caching module caches available page tables; when the parameter of a primitive block is read each time, the address allocation module reads a page table once from the page table cache module, and when the read page table can completely store the primitive block, the address allocation module takes the read page table as a page table allocated to the primitive block and records the address of the page table allocated to the primitive block; and when one primitive block is read each time, the data output module reads the address of the page table allocated to the primitive block from the address allocation module, and outputs the read primitive block after matching with the read address.

In one possible implementation, the apparatus further includes a page table control module, and the method further includes: in an initial state, a page table control module sends out a first page table application signal, wherein the first page table application signal indicates that page tables with the number equal to a first threshold value are generated; in the end state, the page table control module pops the generated and unassigned page table in the page table cache module, and sends a first page table closing signal indicating closing of the generated and unassigned page table.

In one possible implementation, the method further includes: when the address read at this time is different from the address read at the previous time, the data output module outputs the address read at the previous time and a valid enabling signal to the page table control module; when receiving the effective enabling signal and the address read in the previous time, the page table control module sends a second page table closing signal, wherein the second page table closing signal indicates closing of a page table corresponding to the address read in the previous time; after sending the second page table closing signal, the page table control module sends a second page table application signal, wherein the number of the generated page tables indicated by the second page table application signal is the same as the number of the page tables indicated by the second page table closing signal.

In one possible implementation manner, the address allocation module includes a page table space estimating unit and an address storing unit, the address allocation module reads a page table from the page table cache module once each time a parameter of a primitive block is read, and when the read page table can completely store the primitive block, the address allocation module uses the read page table as a page table allocated to the primitive block, and records an address of the page table allocated to the primitive block, including: when the parameter of a primitive block is read each time, a page table space estimating unit reads a page table once from the page table caching module; the page table space estimating unit determines the available data quantity of the read page table according to the pointer stored by the page table space estimating unit; the page table space estimating unit determines the data volume of the primitive block according to the parameters and judges whether the available data volume of the read page table is larger than or equal to the data volume of the primitive block; when the available data volume of the read page table is larger than or equal to the data volume of the primitive block, the page table space estimating unit determines that the read page table can completely store the primitive block, takes the read page table as the page table allocated to the primitive block, and writes the address of the page table allocated to the primitive block into the address storage unit; and the page table space estimating unit takes the pointer as a starting position, determines an ending position after the read page table is allocated to the primitive block, and updates the pointer according to the ending position.

In one possible implementation manner, the address allocation module reads the page table once from the page table cache module each time the parameter of a primitive block is read, and when the read page table can completely store the primitive block, the address allocation module uses the read page table as the page table allocated to the primitive block, records the address of the page table allocated to the primitive block, and further includes: when the available data volume of the read page table is smaller than the data volume of the primitive block, the page table space estimating unit controls the page table caching module to pop the page table, and the operation of reading the page table once and later from the page table caching module is re-executed; after the page table is read again, the page table space estimating unit updates the pointer according to the address lower limit value of the page table read again.

In one possible implementation manner, the address storage unit records addresses allocated to primitive blocks corresponding to the parameters according to the order in which the parameters are read by the page table space estimating unit.

According to another aspect of the present disclosure, there is provided a graphics processor including the page table management apparatus described above.

According to another aspect of the present disclosure, there is provided an electronic device including the graphics processor described above.

According to the page table management device of the embodiment of the disclosure, an available page table is cached through a page table caching module, the page table is read once from the page table caching module through an address allocation module when parameters of a primitive block are read each time, when the read page table can completely store the primitive block, the read page table is used as the page table allocated to the primitive block, and an address of the page table allocated to the primitive block is recorded. Because each primitive block in the embodiment of the disclosure only allocates one page table, the problem of writing the primitive block across page tables does not exist, so that page table addresses of adjacent page tables stored by a page table cache module can be continuous or discontinuous, and adjacent primitive blocks are not required to be stored in adjacent physical addresses after being output by a data output module, thereby enabling a page table allocation mode to be more flexible; when one primitive block is read each time through the data output module, the address of the page table allocated to the primitive block is read from the address allocation module, the read primitive block is output after being matched with the read address, and address transmission is carried out in a pipelining mode, so that the simplification of the page table flow is realized, and the output efficiency of the primitive block is further improved. The page table management device of the embodiment of the disclosure simplifies the page table allocation flow and improves the flexibility of page table allocation modes, thereby improving the performance of the graphics processor.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of a prior art page table management device.

FIG. 2 illustrates an example of a page table applied by a prior art page table management device and an exemplary method of assigning page tables to primitive blocks.

Fig. 3a shows a schematic diagram of the structure of a page table management apparatus according to an embodiment of the present disclosure.

Fig. 3b shows a schematic diagram of an address of a page table cached by a page table caching module according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram showing the structure of an address allocation module according to an embodiment of the present disclosure.

Fig. 5 illustrates an exemplary structural diagram of a page table management apparatus according to an embodiment of the present disclosure.

Fig. 6 illustrates a schematic diagram of a structure of a data output module according to an embodiment of the present disclosure.

Fig. 7 illustrates an exemplary application scenario of a page table management apparatus according to an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of a flow of a page table management method according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

The principles of the prior art for implementing page table application and page table allocation are described below.

Fig. 1 shows a schematic diagram of a prior art page table management device. FIG. 2 illustrates an example of a page table applied by a prior art page table management device and an exemplary method of assigning page tables to primitive blocks.

As shown in FIG. 1, the prior art page table management device mainly comprises a page table cache module, a page table space estimating module, a data output module and a page table control module.

In general, in an initial situation, the page table control module sends a page table application signal for the first time, and a device (e.g., a processor, not shown) receiving the page table application signal generates a fixed number of page tables. The generated page table corresponds to a fixed pre-allocated address segment (physical address) on the external cache, and the page table addresses of adjacent page tables are continuous. As shown in FIG. 2, the fixed number may be n+1 (N is a natural number), and after the page table control module signals a page table application for the first time, the generated page table may include page table 0-page table N.

After each time, after a plurality of page tables are full of data, the page table control module sends out page table closing signals, and then sends out page table application signals with the same number. Means (e.g., a processor, not shown) receiving the page table closing signal will close the page table full of data and newly generate a corresponding number of page tables so that the data of the available page tables remains constant.

The page table cache module is used for storing available page tables. The page table cache module can be realized by adopting a first-in first-out memory (first input first output, FIFO) to ensure that the output page table addresses are continuous.

When a page table is allocated for a primitive block, a page table space estimating module firstly reads page table addresses of available page tables in a page table caching module and parameters of a current primitive block, calculates data quantity of the current primitive block through the parameters of the primitive block, and estimates an end address written into the current primitive block according to an internal address pointer. The address pointer indicates the end address after the last write primitive block. Because the addresses of the multiple page tables belonging to the same pre-allocated address segment are consecutive, the prior art supports primitive block writing to a single page table, as well as primitive block cross page table writing. For example, in the example of FIG. 2, primitive block 0 is written to page table 0, primitive block i is a primitive block written across page tables, and page table addresses corresponding to page table 0 and page table 1 are written.

If the end address is found not to exceed the address upper limit of the pre-allocated address segment (in the example of fig. 2, the start address of page table 0 may be the address lower limit of the pre-allocated address segment, and the end address of page table N may be the address upper limit of the pre-allocated address segment), it is feasible to allocate the current page table to the current primitive block, and the current page table is valid. The page table space estimation module starts to read the parameters of the next primitive block. If the end address is found to exceed the address upper limit value of the pre-allocated address segment, it is indicated that if the current page table is allocated to the current primitive block, the writing of the primitive block exceeds the pre-allocated address segment, so that the current page table and the page tables behind the current page table in the page table cache module are invalid. In the example of FIG. 2, because primitive block j does not exceed the address upper limit of the pre-allocated address segment when written to page table N, primitive block j+1 does exceed the address upper limit of the pre-allocated address segment when written to page table N, the current page table may refer to page table N, which may be invalid, as well as page tables (not shown) generated after page table N.

In this regard, the page table space estimating module resets and winds back the address lower limit value of the pre-allocated address segment with the internal address pointer, and simultaneously sends out a page table clearing signal to the page table control module, when receiving the page table clearing signal, the page table control module sends out a page table closing signal of a fixed number (n+1) to clear the page table cache module, and sends out a page table applying signal of a fixed number (n+1) to apply for a fixed number of page tables again. The page table space estimating module also sends out effective data blocking signals to the data output module, which are used for preventing the data output module from reading invalid page tables from the page table buffer module to carry out the writing and outputting of the primitive blocks before the page table buffer module is emptied. The data blocking signal may be toggled inactive after the page table cache module is emptied and rewritten to the newly applied page table.

The data output module is used for reading the page table address of the available page table from the page table caching module when the data blocking signal is not received, processing according to the read address to obtain a specific address matched with the primitive block, and outputting the primitive block. When the data blocking signal is received, the data output module outputs the primitive block which is processed to obtain the specific address before receiving the data blocking signal, and blocks from the primitive block which is not processed to obtain the specific address until the data blocking signal is invalid. When the address of one page table is full, the data output module transmits the page table address of the page table to the page table control module, the page table is closed by the page table control module, and the page table address of the next page table is read from the page table cache module.

When all primitive blocks processed by the GPU geometry processing engine are output by the data output module, the page table control module can clear all unused page tables in the page table cache module and close the page tables.

It can be seen that the prior art has complex flow when implementing page table application and page table allocation, and increases the difficulty of implementation. The inter-dependent conditions among the modules are more, and the inter-operation is mutually restricted, so that the pipelining of the flow is not facilitated. In addition, the fixed pre-allocation address segments, the fixed number of page tables, greatly reduce the flexibility of page table application and page table allocation. Because of the complex flow and poor flexibility, there is room for optimization of the performance of the GPU geometry processing engine.

As shown in fig. 3a, the present disclosure proposes a page table management device, which includes a page table cache module, an address allocation module, a data output module,

The page table caching module is used for caching available page tables;

the address allocation module is used for reading a page table once from the page table cache module when the parameter of one primitive block is read every time, taking the read page table as the page table allocated to the primitive block when the read page table can completely store the primitive block, and recording the address of the page table allocated to the primitive block;

the data output module is used for reading the address of the page table allocated to the primitive block from the address allocation module when one primitive block is read each time, and outputting the read primitive block after matching with the read address.

For example, the page table caching module of embodiments of the present disclosure is used to cache available page tables, which may be implemented using first-in-first-out memory (first input first output, FIFO). In the example of FIG. 3a, the available page tables cached by the page table caching module may include page table 0-page table N. How page table 0-page table N is applied for can be seen from the relevant description of fig. 5.

The address allocation module is used for estimating whether the page table can completely store the primitive block before allocating the page table to the primitive block, and recording the address of the page table allocated to each primitive block. In order to make the primitive block correspond to the recorded address, the address allocation module may read the page table once from the page table cache module when reading the parameter of one primitive block each time, and predict whether the read page table can completely store the primitive block according to the read parameter. If the primitive block can be stored completely, the read page table is used as the page table allocated to the primitive block, and the address of the page table allocated to the primitive block is recorded. Exemplary structure and function of the address assignment module may be found below and in the related description of fig. 4.

In the example of fig. 3a, when reading the parameters of primitive block i, the address allocation module reads the page table once from the page table cache module, assuming page table 1 is read. When the page table 1 can completely store the primitive block i, the page table 1 is used as a page table allocated to the primitive block i, and the address of the page table 1 is recorded.

In one possible implementation, the addresses of adjacent page tables cached by the page table caching module are contiguous or non-contiguous. Fig. 3b shows a schematic diagram of an address of a page table cached by a page table caching module according to an embodiment of the present disclosure.

In the embodiment of the disclosure, one page table can be allocated to a plurality of primitive blocks, but only one page table is allocated to one primitive block, so that the problem of writing the primitive block across page tables does not exist, and page table addresses of adjacent page tables stored by a page table cache module can be continuous or discontinuous. Thereby enhancing flexibility in page table settings. As shown in FIG. 3b, the addresses of Page Table 0, page Table 1, page Table N are discontinuous. Wherein page table 0 is assigned to primitive block 0-primitive block i-1, page table 1 is assigned to primitive block i, and page table N is assigned to primitive block j.

The data output module can read the address of the page table allocated to the primitive block from the address allocation module when one primitive block is read each time, and output the read primitive block after matching with the read address. Matching the read primitive block with the read address may refer to intercepting a specific address segment from the read address according to the read address, so that the address segment just stores the read primitive block completely and does not affect other primitive blocks in which the read address is already stored. Exemplary implementations thereof may be found in the following further description of the functionality of the data output module.

In the example of fig. 3a, when the data output module reads the primitive block i, the address of the page table 1 allocated to the primitive block i may be read from the address allocation module, and the primitive block i may be output after matching with the address of the page table 1 allocated to the primitive block i.

For example, the address allocation module may increase the identifier of the primitive block i when recording the address of the page table 1 allocated to the primitive block i, so that when the data output module reads the address of the page table allocated to the primitive block i, the address with the same identifier is found and read according to the identifier of the primitive block i, and the read address is the address of the page table 1 allocated to the primitive block i. Alternatively, when the addresses of the page tables allocated to the primitive blocks are recorded, the recording order of the addresses may be set so that when the data output module reads the address of page table 1 allocated to primitive block i, the address of page table 1 is just readable, and no confirmation based on the identification is necessary. For a specific implementation, see below and fig. 4 for a further description of the structure and function of the address assignment module.

Exemplary structures and functions of the address assignment module of the embodiments of the present disclosure are described below. Fig. 4 is a schematic diagram showing the structure of an address allocation module according to an embodiment of the present disclosure.

As shown in fig. 4, in one possible implementation, the address allocation module includes a page table space prediction unit and an address storage unit, where the page table space prediction unit is configured to,

reading a page table from a page table cache module once when reading parameters of a primitive block each time;

determining the available data quantity of the read page table according to the pointer stored by the page table space estimating unit;

determining the data volume of the primitive block according to the parameters, and judging whether the available data volume of the read page table is larger than or equal to the data volume of the primitive block;

when the available data amount of the read page table is larger than or equal to the data amount of the primitive block, determining that the read page table can completely store the primitive block, taking the read page table as a page table allocated to the primitive block, and writing an address of the page table allocated to the primitive block into an address storage unit;

and determining an end position after the read page table is allocated to the primitive block by taking the pointer as a start position, and updating the pointer according to the end position.

For example, one of the functions of the page table space prediction unit is to predict whether a page table can fully store a primitive block before allocating the page table to the primitive block. For example, the page table space estimation unit may read the page table from the page table cache module once every time the parameter of one primitive block is read, where the read page table is the estimation object.

The page table space prediction unit may store pointers. If the page table is one that has not been assigned to any of the primitive blocks, the pointer may indicate the address lower limit value of the page table. If the page table has been allocated to at least one primitive block, the pointer may indicate the end position of the page table at the previous allocation. Referring to FIG. 3b, if page table 0 has not been allocated to any of the primitive blocks when page table 0 is read, then the pointer may indicate the address lower limit value for page table 0; if page table 0 is read with page table 0 already allocated to primitive block 0, then the pointer may indicate the ending location after primitive block 0 is written to the physical address to which page table 0 corresponds.

Based on the stored pointer, the page table space estimation unit may determine the amount of data available for the read page table. The amount of data available may be equal to the amount of data between the upper address limit of the page table and the location indicated by the pointer. This part of the address has not yet been allocated and can be used for storing primitive blocks.

The page table space estimating unit may determine the data amount of the primitive block according to the read parameters of the primitive block. Wherein a primitive block comprises a plurality of sets of data, and parameters of the primitive block may comprise, for example, the number of sets, the amount of data per set, accuracy, and the like. The data amount of the primitive block may be equal to (the number of groups×the data amount of each group) ×the precision.

The parameters of the primitive block may also include an initial identifier or an end identifier. Wherein the primitive block including the initial identification may be the first primitive block read and the primitive block including the end identification may be the last primitive block read.

When the available data amount of the read page table is greater than or equal to the data amount of the primitive block, the page table space estimating unit may determine that the read page table can completely store the primitive block. The read page table may serve as the page table assigned to the primitive block. Then, the page table space estimating unit writes the address of the page table allocated to the primitive block into the address storing unit. The address written into the address storage unit here may be the complete address of the page table, i.e. the address lower limit value and the address upper limit value of the page table. Which segment of the address of the page table the primitive block matches in particular may be determined by the data output unit.

In this way, an estimate of whether the page table is capable of storing the primitive block in its entirety can be made. When the page table can completely store the primitive blocks, the page table is allocated to the primitive blocks, so that the accuracy of page table allocation is ensured.

In one possible implementation, the page table space prediction unit is further configured to,

when the available data volume of the read page table is smaller than the data volume of the primitive block, controlling a page table cache module to pop the page table, and re-executing operations of reading the page table once and later from the page table cache module;

wherein after reading the page table once again, the pointer is updated according to the address lower limit value of the page table read again.

For example, when the amount of data available to the read page table is less than the amount of data for the primitive block, the page table space prediction unit may determine that the read page table is not capable of fully storing the primitive block. In this case, the page table space estimating unit may control the page table buffer module to pop the page table, and then re-execute the operations of reading the page table from the page table buffer module and thereafter.

The page table re-read at this time may be the first page table generated after the popped page table. For example, referring to the example of FIG. 3b, if page table 0 is popped, the re-read page table may be page table 1. After the page table is read again, the pointer is updated according to the address lower limit value of the page table read again. If the read page table can completely store the primitive block, distributing the read page table to the primitive block and writing the address of the page table into an address storage unit; if the read page table can not completely store the primitive block, the read page table is popped off again, and the page table is continuously read until the read heating page table can completely store the primitive block and the address of the page table is written into the address storage unit.

In this way, when the page table can not completely store the primitive block, a proper page table can be allocated for the primitive block, so that the management range of the page table is improved.

In one possible implementation, the address storage unit is used to,

and recording addresses of the primitive blocks corresponding to the parameters according to the sequence of reading the parameters by the page table space estimating unit.

For example, referring to the description above, in recording the addresses of the page tables allocated to the primitive blocks, the recording order of the addresses may be set so that the data output module reads the address of the page table allocated to the primitive block i just as it can read the address of the page table i, without confirmation based on the identification.

For example, the address storage unit may be configured to record addresses allocated to primitive blocks corresponding to the respective parameters in the order in which the page table space estimation unit reads the parameters. The data output module may read the primitive blocks sequentially, and may be consistent with the order in which the page table space prediction unit reads the parameters. That is, as long as the addresses allocated to the primitive blocks corresponding to the respective parameters are recorded in the order in which the page table space estimating unit reads the parameters, the order of the recorded addresses is also consistent with the order in which the data output module reads the primitive blocks. The address storage unit may be a first-in first-out memory, in which case the address read by the data output unit must be the address assigned to the read primitive block, and therefore no identification has to be used.

In this way, the data storage cost of the address storage unit can be reduced.

In one possible implementation, the apparatus further comprises a page table control module, the page table control module being configured to,

in an initial state, sending out a first page table application signal, wherein the first page table application signal indicates that page tables with the number equal to a first threshold value are generated;

in the end state, the generated and unassigned page table in the page table cache module is popped off and a first page table close signal is sent, the first page table close signal indicating that the generated and unassigned page table is closed.

For example, as shown in fig. 5, the page table management device may further include a page table control module for applying for a page table, closing the page table, popping the page table stored by the page table cache module, and so on. Embodiments of the present disclosure set a parameter, a first threshold, for a page table management device to indicate a maximum value of the number of page tables that may be present at the same time. The first threshold may be parameterized, i.e. may be increased or decreased according to the user's needs, and is not limited to a fixed value.

The page table control module is configured to, in an initial state, send a first page table application signal, where the first page table application signal indicates that a number of page tables equal to a first threshold (e.g., equal to n+1) are generated. The initial state may refer to a state that no page table allocation has been performed, may be that the page table control module enters once started, or may further set parameters of the primitive block read by the page table control module to monitor the address allocation module, and determine to enter the initial state when the parameters of the primitive block are monitored to include an initial identifier, and so on. The embodiments of the present disclosure do not limit how the page table control module enters the initial state. The first page table application signal may be sent to a processor (not shown), where the processor generates the page table and outputs it to the page table cache module for storage.

Then, the page table management device starts to allocate the page table and output the primitive block. In one possible implementation, the data output module is further configured to output, when the address of the current reading is different from the address of the previous reading, the address of the previous reading and a valid enable signal to the page table control module;

the page table control module is further configured to send a second page table closing signal when receiving a valid enabling signal and a previously read address, where the second page table closing signal indicates to close a page table corresponding to the previously read address; after sending the second page table closing signal, sending a second page table application signal, wherein the number of the generated page tables indicated by the second page table application signal is the same as the number of the closed page tables indicated by the second page table closing signal.

Fig. 6 illustrates a schematic diagram of a structure of a data output module according to an embodiment of the present disclosure. As shown in fig. 6, the data output module may include a register for storing the address of the previous read and a comparator for comparing the address of the current read with the address of the previous read.

If the comparator determines that the address read at this time (e.g., the address assigned to page table 1 of primitive block i) is different from the address read last time (e.g., the address assigned to page table 0 of primitive block i-1), a valid enable signal may be output, such as a "1" indicating that page table 0 to which the address read last time belongs is already an unavailable page table that cannot store the complete primitive block. The data output module may output the address of the previous read (address of page table 0) to the page table control module along with a valid enable signal.

If the comparator determines that the address at the present read is the same as the address at the previous read, an invalid enable signal may be output, such as a "0" output, indicating that the page table to which the address at the previous read belongs is still available. The data output module may output the address of the previous read to the page table control module along with an invalid enable signal.

The page table control module is further configured to send a second page table closing signal when receiving the valid enable signal and the address read last time, where the second page table closing signal indicates to close the page table corresponding to the address read last time. After sending the second page table closing signal, a second page table application signal can also be sent, and the number of the generated page tables indicated by the second page table application signal is the same as the number of the closed page tables indicated by the second page table closing signal, so that the number of the available page tables is complemented, and the first threshold value is reached. The second page table closing signal and the second page table applying signal may be sent to a processor (not shown), and the processor closes the page table, or generates the page table and outputs the page table to the page table cache module for storage.

The page table control module is further configured to pop the generated and unassigned page table in the page table cache module in the end state. The ending state may refer to a state that page table allocation of all primitive blocks is completed, and a page table control module may be set to monitor parameters of the primitive blocks read by the address allocation module, and determine to enter the ending state when the parameters of the primitive blocks read by the address allocation module include an ending identifier. The embodiments of the present disclosure do not limit how the page table control module enters the end state. In the end state, the page table control module also issues a first page table close signal indicating that the generated and unassigned page table is closed. The first page table close signal may be sent to a processor (not shown) which closes the page table.

In this way, the application number of the page tables in the constraint initial state in the traditional page table application rule is changed into the page table application number parameterization, so that the page tables can be dynamically applied, and the flexibility of page table management is further improved.

In one possible implementation, the data output module also records an address offset,

matching the read primitive block with the read address and outputting the matched primitive block, wherein the method comprises the following steps:

when the address read at this time is different from the address read at the previous time, resetting the address offset;

each time data with the data quantity equal to the second threshold value is read, an address corresponding to the data is obtained according to the address offset when the data is read and the address read when the data is read;

matching the data with the address corresponding to the data and then outputting the data;

and updating the address offset according to the number of address bits occupied by the data with the data quantity equal to the second threshold value.

For example, the data output module may preset the data amount output to the external buffer each time to a second threshold, typically 128 bits or 256 bits or other values. Thus, when the data output module outputs one primitive block, the primitive block may be output in multiple times. And outputting the read primitive block after matching the read address, wherein when the data quantity of the primitive block is equal to the data of the second threshold value, the read data is output after matching the corresponding address until all the data of the whole primitive block are output.

In this regard, the data output module also records an address offset in the page table, which represents an offset between the starting location of the address to which the data to be output next matches and the starting location of the address to be read. First, when the address read by the data output module is different from the address read by the previous time, the page table corresponding to the address read by the previous time is not available, and the recorded address offset is invalid, so that the address offset can be cleared. Then, each time data with the data quantity equal to the second threshold value is read, an address corresponding to the data can be obtained according to the address offset when the data is read and the address read when the data is read, and the data is output after being matched with the address corresponding to the data; finally, the address offset may be updated according to the number of address bits occupied by data having a data size equal to the second threshold, and the updating may be by increasing the number of address bits based on the current address offset.

An example of updating the address offset according to the number of address bits is given below. For example, assume that the second threshold is set to 128 bits, occupying 16byte address bits. When the data output module reads the primitive block i, the address read at this time is the address of the page table 1, and the address read at the previous time is the address of the page table 0, and then the address offset can be cleared. When the data output module outputs the data of the pixel block i for the first time, outputting 128-bit data, and updating the address offset to 16 bytes (16 bytes+0) according to the address bit number of 16 bytes; when the data output module outputs the data of the pixel block i for the second time, 128bit data is output, and at the moment, the address offset is updated to 32 bytes (16byte+16byte) according to the address bit number of 16 bytes. And so on until the data of the primitive block i is completely output.

In this way, pipelined data output is achieved.

In one possible implementation, the page table caching module caches available page tables in the order in which they were generated, and the address assignment module outputs the earliest generated page table each time the page table is read from the page table caching module.

For example, the page table cache module may be configured to cache available page tables in the order they were generated. The address allocation module outputs the earliest generated page table each time the page table is read from the page table cache module. In this case, the page table generated thereafter is not read out until a certain page table becomes an unavailable page table, so that the memory addresses of the adjacent primitive blocks are also continuous as much as possible, and convenience is provided for the subsequent memory of the primitive blocks to the external cache.

As shown in fig. 7, the page table management apparatus according to the embodiment of the present disclosure may be disposed in a graphics processor, and the graphics processor may be further disposed with a primitive block storage module and a primitive block compression module. The primitive block storage module and the primitive block compression module may be located in a GPU geometry processing engine.

The primitive block storage module is used for storing parameters of the primitive block and the primitive block. The page table management device can read parameters of the primitive block from the primitive block storage module, can read the original primitive block from the primitive block storage module, and can also read the compressed primitive block from the primitive block compression module.

The primitive block compression module may compress the primitive block by using a method of the prior art, and the primitive block compression module may be responsible for determining and storing the compression policy. Alternatively, the embodiments of the present disclosure further provide for determining the compression policy before the primitive block is stored in the primitive block storage module, and causing the compression policy to be stored in the primitive block storage module along with the primitive block. In this case, the primitive block compression module may directly obtain the determined compression policy from the primitive block storage module.

The primitive block includes a plurality of sets of data, each set of data including a plurality of primitives, and when the primitive block is compressed, vertex coordinates of the primitive block are compressed mainly. The vertex coordinates of the different primitives may be duplicated, which may result in unnecessary cost increases if directly compressed. In order to reduce the compression cost, an index can be constructed for the vertex coordinates of the primitives, and the index indicates the index value combination of the vertex coordinates corresponding to each primitive, so that the same vertex coordinate is compressed only once, and the index of the vertex coordinate can not be compressed. After the vertex coordinates are compressed, the vertex coordinates are spliced with indexes of the vertex coordinates, and the compressed primitive blocks are read by a page table management device. And finding out vertex coordinates corresponding to each primitive according to the index value in the subsequent decompression and reducing the primitive block.

The page table management device may also communicate with a processor external to the graphics processor, and output page table application signals/closing signals (including the first page table application signal, the first page table closing signal, the second page table application signal, and the second page table closing signal described above) to the processor, where the processor completes application and closing of the page table according to the instruction.

The page table management device is used for providing available page tables for the GPU geometry management engine to determine the storage position of the primitive block, starting to apply for the page tables when the parameters of the primitive block including the initial identification are read, and caching the applied page tables. When the number of available page tables is insufficient, the page table management device can send page table application signals (including the first page table application signal and the second page table application signal) to the processor to carry out page table application, and store newly generated page tables, so that the number of available page tables meets the requirement; when the page table is not available, the page table management device may send a page table closing signal (the second page table application signal described above) to the processor to perform page table closing, and pop the cached unavailable page table. And closing the unused page table when the parameter of the primitive block including the end identifier is read, and popping the cached unused page table.

The page table management device is also responsible for distributing page tables for the primitive blocks, determining specific addresses (addresses on an external cache) matched with the primitive blocks according to the distributed page tables after completing page table distribution, and outputting the primitive blocks to the specific addresses.

The page table management device of the present disclosure cancels the rule of fixing pre-allocated address segments, and instead supports receiving discontinuous, currently available page tables, which not only relaxes the constraint on input page tables, increases flexibility, but also can omit complex address wrap logic. Secondly, the page table application rule is changed, the page table application number is parameterized instead of restraining the page table with fixed number (first threshold value) in the initial state, and when the available page table number is lower than the value (first threshold value), the page table can be dynamically applied, so that the flexibility is further improved. In addition, the page table management device realizes page table transfer in a pipelining mode until the page table is closed, and further improves the performance of the graphics processor.

As shown in fig. 8, the embodiment of the present disclosure further provides a page table management method, which is applied to a page table management device, where the device includes a page table cache module, an address allocation module, and a data output module, and the method includes steps S81-S83:

Step S81, a page table caching module caches available page tables;

step S82, when the parameter of a primitive block is read each time, the address allocation module reads a page table once from the page table cache module, when the read page table can completely store the primitive block, the address allocation module takes the read page table as the page table allocated to the primitive block, and records the address allocated to the page table of the primitive block;

in step S83, when one primitive block is read each time, the data output module reads the address allocated to the primitive block from the address allocation module, and matches the read primitive block with the read address and outputs the result.

In one possible implementation, the apparatus further includes a page table control module, and the method further includes:

in an initial state, a page table control module sends out a first page table application signal, wherein the first page table application signal indicates that page tables with the number equal to a first threshold value are generated;

in the end state, the page table control module pops the generated and unassigned page table in the page table cache module, and sends a first page table closing signal indicating closing of the generated and unassigned page table.

In one possible implementation, the method further includes:

When the address read at this time is different from the address read at the previous time, the data output module outputs the address read at the previous time and a valid enabling signal to the page table control module;

when receiving the effective enabling signal and the address read in the previous time, the page table control module sends a second page table closing signal, wherein the second page table closing signal indicates closing of a page table corresponding to the address read in the previous time;

after sending the second page table closing signal, the page table control module sends a second page table application signal, wherein the number of the generated page tables indicated by the second page table application signal is the same as the number of the page tables indicated by the second page table closing signal.

In one possible implementation manner, the address allocation module includes a page table space estimating unit and an address storing unit, the address allocation module reads a page table from the page table cache module once each time a parameter of a primitive block is read, and when the read page table can completely store the primitive block, the address allocation module uses the read page table as a page table allocated to the primitive block, and records an address of the page table allocated to the primitive block, including:

when the parameter of a primitive block is read each time, a page table space estimating unit reads a page table once from the page table caching module;

The page table space estimating unit determines the available data quantity of the read page table according to the pointer stored by the page table space estimating unit;

the page table space estimating unit determines the data volume of the primitive block according to the parameters and judges whether the available data volume of the read page table is larger than or equal to the data volume of the primitive block;

when the available data volume of the read page table is larger than or equal to the data volume of the primitive block, the page table space estimating unit determines that the read page table can completely store the primitive block, takes the read page table as the page table allocated to the primitive block, and writes the address of the page table allocated to the primitive block into the address storage unit;

and the page table space estimating unit takes the pointer as a starting position, determines an ending position after the read page table is allocated to the primitive block, and updates the pointer according to the ending position.

In one possible implementation manner, the address allocation module reads the page table once from the page table cache module each time the parameter of a primitive block is read, and when the read page table can completely store the primitive block, the address allocation module uses the read page table as the page table allocated to the primitive block, records the address of the page table allocated to the primitive block, and further includes:

When the available data volume of the read page table is smaller than the data volume of the primitive block, the page table space estimating unit controls the page table caching module to pop the page table, and the operation of reading the page table once and later from the page table caching module is re-executed;

after the page table is read again, the page table space estimating unit updates the pointer according to the address lower limit value of the page table read again.

In one possible implementation, one primitive block includes multiple sets of data, the data output module also records address offsets,

the step of outputting the read primitive block after matching with the read address comprises the following steps:

matching the data with the address corresponding to the data and then outputting the data; and updating the address offset according to the address bit number occupied by the data with the data quantity equal to the second threshold value.

The embodiment of the disclosure also provides a graphics processor, which comprises the page table management device.

The embodiment of the disclosure also provides an electronic device comprising the graphics processor.

The electronic device may be a smart phone, a netbook, a tablet computer, a notebook computer, a wearable electronic device, a TV, a virtual reality device, etc., as long as the electronic device may include a graphics processor, and the embodiments of the present disclosure are not limited to a specific type of electronic device.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A page table management device is characterized in that the device comprises a page table cache module, an address allocation module and a data output module,

the page table caching module is used for caching available page tables;

2. The apparatus of claim 1, further comprising a page table control module for,

in the end state, the generated and unassigned page table in the page table cache module is popped, and a first page table closing signal is sent out, wherein the first page table closing signal indicates closing of the generated and unassigned page table.

3. The apparatus of claim 2, wherein the data output module is further configured to output a last read address and a valid enable signal to the page table control module when the last read address is different from the last read address;

the page table control module is further configured to send a second page table closing signal when receiving the valid enabling signal and the address read in the previous time, where the second page table closing signal indicates to close a page table corresponding to the address read in the previous time; and after the second page table closing signal is sent out, sending out a second page table application signal, wherein the number of the generated page tables indicated by the second page table application signal is the same as the number of the closed page tables indicated by the second page table closing signal.

4. The apparatus of claim 1, wherein the address allocation module comprises a page table space prediction unit and an address storage unit, the page table space prediction unit configured to,

reading a page table from the page table cache module once when reading parameters of one primitive block each time;

when the available data amount of the read page table is larger than or equal to the data amount of the primitive block, determining that the read page table can completely store the primitive block, taking the read page table as a page table allocated to the primitive block, and writing an address of the page table allocated to the primitive block into the address storage unit;

and taking the pointer as a starting position, determining an ending position after the read page table is allocated to the primitive block, and updating the pointer according to the ending position.

5. The apparatus of claim 4, wherein the page table space predictor unit is further configured to,

when the available data volume of the read page table is smaller than the data volume of the primitive block, controlling the page table caching module to pop the page table, and re-executing operations of reading the page table once and later from the page table caching module;

6. The apparatus of claim 4, wherein the address storage unit is configured to,

And recording addresses allocated to the primitive blocks corresponding to the parameters according to the sequence of reading the parameters by the page table space estimating unit.

7. The apparatus of claim 1 wherein the page table caching module caches available page tables in order of page table generation, the address assignment module outputting an earliest generated page table each time a page table is read from the page table caching module.

8. The apparatus of claim 1, wherein addresses of adjacent page tables cached by the page table caching module are contiguous or non-contiguous.

9. The apparatus of claim 3, wherein the data output module further records an address offset,

and updating the address offset according to the address bit number occupied by the data with the data quantity equal to the second threshold value.

10. A method for managing a page table, which is applied to a page table management device, the device comprises a page table cache module, an address allocation module and a data output module, the method comprises:

the page table caching module caches available page tables;

when the parameter of a primitive block is read each time, the address allocation module reads a page table once from the page table cache module, and when the read page table can completely store the primitive block, the address allocation module takes the read page table as a page table allocated to the primitive block and records the address of the page table allocated to the primitive block;

and when one primitive block is read each time, the data output module reads the address of the page table allocated to the primitive block from the address allocation module, and outputs the read primitive block after matching with the read address.

11. A graphics processor comprising the page table management apparatus of any one of claims 1-9.

12. An electronic device comprising the graphics processor of claim 11.