CN116775509A

CN116775509A - Cache consistency verification method, device, equipment and storage medium

Info

Publication number: CN116775509A
Application number: CN202310641321.9A
Authority: CN
Inventors: 沈秀红; 刘扬帆
Original assignee: Hexin Technology Suzhou Co ltd; Hexin Technology Co ltd
Current assignee: Hexin Technology Suzhou Co ltd; Hexin Technology Co ltd
Priority date: 2023-05-31
Filing date: 2023-05-31
Publication date: 2023-09-19
Anticipated expiration: 2043-05-31
Also published as: CN116775509B; CN118132463A

Abstract

The application relates to a cache consistency verification method, a device, equipment and a storage medium, which are applied to a multi-core system based on an AMBA CHI protocol, wherein the method comprises the steps of respectively obtaining a target state type of a target cache line in a target cache and a to-be-verified state type of a first cache line in a first cache; the target cache and the first cache belong to different cores, and the target cache line and the first cache line both store data under the same data address; according to the target state type, matching a state transition rule corresponding to the target state type; the state transition rule is used for indicating that the first cache line meets the state type of cache consistency and data consistency under the target state type; and verifying whether the multi-core system meets cache consistency according to the state conversion rule, the state type to be verified and the data stored in the first cache line, obtaining a verification result, and returning the verification result. And the cache consistency of the multi-core system based on the AMBA CHI protocol is verified.

Description

Cache consistency verification method, device, equipment and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a cache consistency verification method, device, equipment, and storage medium.

Background

The multi-core technology is widely applied by virtue of the advantage of reducing the power consumption of the system while improving the performance of the system on the premise of keeping the same performance as that of a single core. The multi-core technology is based on cache (cache) consistency in the system, and the method for maintaining the cache consistency by the software is not ideal, so that the prior art adopts hardware to maintain the cache consistency.

In the prior art, a cache line (cache) state machine mechanism matched with different bus protocols is mostly adopted to realize the maintenance of cache consistency, for example, the maintenance of cache consistency is realized through a MESI protocol, a MOESI protocol or an AMBA CHI protocol.

However, there is currently no efficient and uniform method to verify cache coherency for AMBA CHI protocol based multi-core systems.

Disclosure of Invention

The application provides a cache consistency verification method, device, equipment and storage medium, which are used for verifying cache consistency of a multi-core system based on an AMBA CHI protocol.

In one aspect, a cache consistency verification method is provided, which is applied to a multi-core system based on AMBA CHI protocol, and the method includes:

respectively acquiring a target state type of a target cache line in a target cache and a to-be-verified state type of a first cache line in a first cache; the target cache and the first cache belong to different cores, and the target cache line and the first cache line both store data under the same data address;

according to the target state type, matching a state transition rule corresponding to the target state type; the state conversion rule is used for indicating that the first cache line meets the state type of cache consistency and data consistency under the target state type;

and verifying whether the multi-core system meets cache consistency according to the state conversion rule, the state type to be verified and the data stored in the first cache line, obtaining a verification result, and returning the verification result.

In the above technical solution, the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache except the target cache are respectively obtained; and then matching a state transition rule corresponding to the target state type, and verifying whether the state type to be verified and the data stored in the first cache line are the state types meeting the cache consistency by using the state transition rule when the target cache behavior is the target state type, further determining a verification result of the cache consistency of the multi-core system, and returning the verification result. And the verification of cache consistency in the multi-core system supporting the AMBA CHI protocol is realized.

Optionally, verifying whether the multi-core system meets cache consistency according to the state conversion rule, the state type to be verified and the data stored in the first cache line, obtaining a verification result, and returning the verification result includes:

when the verification result is that the cache consistency is met, returning the verification result;

when the verification result is that the cache consistency is not met, acquiring alarm information of the system; the alarm information comprises at least one of an address, index information, tag information, stored data of a target cache line and a first cache line, identification information of an affiliated kernel, a state type and a state conversion rule corresponding to the target state type;

and taking the alarm information as a verification result, and returning the verification result.

In the technical scheme, when the verification result is that the cache consistency is met, the verification result is directly returned to inform an operator that the multi-core system meets the cache consistency. When the verification result is that the cache consistency is not met, at least one of the address, index information, tag information, stored data, identification information of the core, state type and state conversion rule corresponding to the target cache line is taken as alarm information, the alarm information is taken as the verification result to be returned, and an operator can quickly position the problem that the multi-core system does not meet the cache consistency according to the returned alarm information, so that the multi-core system is debugged, and the debugging efficiency of the operator is improved.

Optionally, before the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache are respectively acquired, the method further includes:

the state types UD, SD, UC, SC and I in the AMBA CHI protocol are respectively in one-to-one correspondence with the state types M, O, E, S and I in the MOESI protocol, and the state conversion principle corresponding to each state type in the MOESI protocol is determined as the state conversion rule corresponding to UD, SD, UC, SC and I state types in the AMBA CHI protocol.

In the above technical solution, the state transition rules corresponding to the state types UD, SD, UC, SC and I in the AMBA CHI protocol are respectively corresponding to the state transition rules of the state types M, O, E, S and I in the mosi protocol, so that the state transition rules do not need to be reset, and the design complexity of the state transition rules based on the AMBA CHI protocol is reduced.

Optionally, verifying whether the multi-core system meets cache consistency according to a state conversion rule, a state type to be verified and data stored in the first cache line, and obtaining a verification result includes:

when the target state type is UD, verifying whether the state type to be verified is I, if so, determining that the verification result meets cache consistency;

When the target state type is SD, verifying whether the state type to be verified is SC or I, verifying whether the data stored in the first cache line is consistent with the data stored in the target cache line, and if so, determining that the verification result meets cache consistency;

when the target state type is UC, verifying whether the state type to be verified is I, verifying whether the data stored in the target cache line is consistent with the corresponding data in the main memory, and if so, determining that the verification result meets the cache consistency;

when the target state type is SC, verifying whether the state type to be verified is SC, SD or I, verifying whether the data stored in the target cache line is consistent with the corresponding data in the main memory and whether the data stored in the first cache line is consistent with the data stored in the target cache line, and if so, determining that the cache consistency is met by the verification result;

and when the target state type is I, determining that the verification result is that cache consistency is met.

According to the technical scheme, aiming at different target state types, the state types of which the to-be-verified state types meet the cache consistency are verified, and the data consistency when the data stored in the target cache line and/or the first cache line meet the cache consistency is used for determining whether the verification result meets the cache consistency or not, and returning the verification result, so that the verification of the cache consistency in the multi-core system supporting the AMBA CHI protocol is realized.

Optionally, the multi-core system comprises at least one core, the core comprises a full-consistency request node, the full-consistency request node comprises a first-level cache and a second-level cache, and the first-level cache and the second-level cache are in a containing relationship; the target cache and the first cache are two-level caches; before respectively acquiring the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache, the method further comprises:

respectively acquiring a first state type of a first level cache and a second state type of a target level cache;

verifying whether the first state type meets cache consistency according to a preset multi-level cache verification rule corresponding to the second state type; the preset multi-level cache verification rule is a rule determined according to an MOESI protocol and is used for indicating the state types of a first-level cache and a second-level cache in the multi-core system when the multi-core system meets cache consistency;

when the first state type meets the cache consistency, respectively acquiring the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache so as to verify whether the multi-core system meets the cache consistency.

In the technical scheme, when the multi-core system comprises a first-level cache and a second-level cache, respectively acquiring a first state type of the first-level cache and a second state type of the target second-level cache, and further verifying whether the first state type meets cache consistency according to the first state type, the second state type and a preset multi-level cache verification rule; when the first state type meets the cache consistency, the first-level cache currently in the multi-core system meets the cache consistency. And further, whether the second-level cache in the multi-core system meets consistency needs to be verified, and cache consistency verification is performed on the multi-core system by respectively acquiring the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache. The cache consistency verification of the multi-core system of different multi-core environments is realized, the number of cores in the multi-core system and the configurability of different multi-core environments are supported, and the scalability is realized.

Optionally, verifying whether the first state type meets the cache consistency according to a preset multi-level cache verification rule corresponding to the second state type includes:

when the second state type is UD and the first state type is UD or UC, acquiring a third state type of the second-level cache, and verifying whether the third state type is I, if so, the first state type meets cache consistency;

When the second state type is SD, verifying whether the first state type is SC or I, and if so, the first state type meets cache consistency;

when the second state type is UC, determining that the first state type meets cache consistency;

when the second state type is SC, verifying whether the first state type is SC, SD or I, and if so, the first state type meets cache consistency;

when the second state type is I, verifying whether the first state type is I, and if so, enabling the first state type to meet cache consistency.

According to the technical scheme, whether the state types corresponding to the first-level cache and the second-level cache in the multi-core system meet cache consistency is verified by the preset multi-level cache verification rule, so that cache consistency verification of multi-core systems in different multi-core environments is realized, and the multi-core system has expandability.

Optionally, after obtaining the target state type of the target cache line in the target cache, the method further includes:

verifying whether a first cache line storing first data exists in a first cache, wherein the data address of the first data is the same as the data address of target data stored in the target cache line;

when a first cache line exists in the first cache, acquiring the type of the state to be verified of the first cache line in the first cache;

And when the first cache line does not exist in the first cache, verifying whether the multi-core system meets the cache consistency according to the data stored in the target cache line and the state conversion rule corresponding to the target cache line, and returning a verification result.

In the above technical solution, after obtaining the target state type of the target cache line in the target cache, preferentially verifying whether the first cache line corresponding to the target cache line exists in the multi-core system; when a first cache line exists, acquiring the type of the state to be verified of the first cache line in the first cache so as to verify the cache consistency of the multi-core system; and when the data stored in the target cache line does not exist, verifying whether the multi-core system meets cache consistency according to the data stored in the target cache line and the state conversion rule corresponding to the target cache line, and returning a verification result. And the cache consistency verification of the multi-core system based on the AMBA CHI protocol is realized by considering the cache consistency verification of the multi-core system under different conditions.

In yet another aspect, a cache consistency verification device is provided, applied to a system supporting AMBA CHI protocol, the device includes:

the acquisition module is used for respectively acquiring the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache; the target cache and the first cache belong to different cores, and the target cache line and the first cache line both store data under the same data address;

The matching module is used for matching the state conversion rule corresponding to the target state type according to the target state type; the state conversion rule is used for indicating that the first cache line meets the state type of cache consistency and data consistency under the target state type;

and the verification module is used for verifying whether the multi-core system meets cache consistency according to the state conversion rule, the state type to be verified and the data stored in the first cache line, obtaining a verification result and returning the verification result.

In yet another aspect, a computer device is provided, the computer device including a processor and a memory, the memory storing at least one instruction, the at least one instruction loaded and executed by the processor to implement the cache coherence verification method described above.

In yet another aspect, a computer readable storage medium having stored therein at least one instruction loaded and executed by a processor to implement the cache coherence verification method described above is provided.

In yet another aspect, a computer program product or computer program is provided, the computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the cache consistency verification method.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram illustrating a multi-core system based on AMBA CHI protocol according to an exemplary embodiment.

FIG. 2 is a flowchart illustrating a cache coherency verification method according to an exemplary embodiment.

FIG. 3 is a flowchart illustrating a cache coherency verification method according to an exemplary embodiment.

Fig. 4 shows a schematic diagram of a state model of a cache in a multi-core system based on AMBA CHI protocol according to an embodiment of the present application.

Fig. 5 is a flowchart illustrating a cache coherence verification method in an application scenario, according to an exemplary embodiment.

FIG. 6 is a flowchart illustrating a cache coherency verification method according to an exemplary embodiment.

Fig. 7 is a block diagram showing the structure of a cache coherency verification apparatus according to an exemplary embodiment.

Fig. 8 shows a block diagram of a computer device according to an exemplary embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be understood that the "indication" mentioned in the embodiments of the present application may be a direct indication, an indirect indication, or an indication having an association relationship. For example, a indicates B, which may mean that a indicates B directly, e.g., B may be obtained by a; it may also indicate that a indicates B indirectly, e.g. a indicates C, B may be obtained by C; it may also be indicated that there is an association between a and B.

In the description of the embodiments of the present application, the term "corresponding" may indicate that there is a direct correspondence or an indirect correspondence between the two, or may indicate that there is an association between the two, or may indicate a relationship between the two and the indicated, configured, etc.

In the embodiment of the present application, the "predefining" may be implemented by pre-storing corresponding codes, tables or other manners that may be used to indicate relevant information in devices (including, for example, terminal devices and network devices), and the present application is not limited to the specific implementation manner thereof.

Fig. 1 is a schematic diagram illustrating a multi-core system based on AMBA CHI protocol according to an exemplary embodiment. The multi-core system comprises at least two cores, wherein the cores comprise a full consistency request node (Fully coherent Request Node, RN-F), an interconnection line (ICN), a main memory (System level cache, SLC) and a verification IP (CHI verification IP, CHI VIP) supporting an AMBA CHI protocol.

The RN-F comprises a cache, the RN-F supports all the transaction types and the snoop types in the AMBA CHI protocol, the RN-F is connected with the ICN through the AMBA CHI protocol, the ICN comprises an SLC, and the SLC and the cache in the RN-F meet a cache consistency protocol. The ICN is connected to the CHI VIP, which contains a register, which receives requests from the ICN and gives corresponding responses. The embodiment of the application does not have specific requirements on the number of the cores, and can have different numbers of cores according to different multi-core systems, and takes 4 cores, wherein each core comprises an RN-F as an example.

The multi-core system monitors data cache update information of caches in RN-F in each core, wherein the data cache update information comprises updated index (index) information, tag (tag) information and state types of cache lines; and recording the address of the current cache line (cache line) according to the updated index information and tag information, marking the state type of the updated cache line, and simultaneously storing the data of the cache line. And further, according to the state type of the updated cache line and the corresponding state transition rule, verifying whether the multi-core system meets the cache consistency, and further verifying the cache consistency in the multi-core system supporting the AMBA CHI protocol. The data cache update information is used for indicating the change of data in the cache and the change of cache lines, and the data cache update information can be write information of cache directors.

FIG. 2 is a flowchart illustrating a cache coherency verification method according to an exemplary embodiment. The method is performed by an AMBA CHI protocol based multi-core system, which may be a multi-core system as shown in fig. 1. As shown in fig. 2, the cache consistency verification method may include the following steps:

Step 201, respectively obtaining a target state type of a target cache line in a target cache and a to-be-verified state type of a first cache line in a first cache.

The target cache and the first cache belong to different cores, and the target cache line and the first cache line both store data under the same data address. The multi-core system monitors data cache update information of the cache in each kernel, determines the cache in the RN-F as a target cache when detecting that the data cache update information of the cache in the RN-F changes, wherein the change of the data cache update information means that an updated cache line exists in the target cache, and the multi-core system takes the updated cache line as the target cache line and marks more state types of the target cache line according to index information and tag information in the data cache update information to obtain a target state type; and searching first cache lines in at least one first cache matched with the target cache line in other cores through interconnection lines (i.e. buses) in the multi-core system, and reading the state types of the first cache lines according to tag information of each first cache line to obtain at least one state type to be verified.

It should be noted that, the specific meaning of the first cache line in the first cache matched with the target cache line is that a cache line with a data address corresponding to the stored data as a target address is searched in other cores, the cache line is determined as the first cache line, and the cache in the first cache line is determined as the first cache; the target address is a data address corresponding to the data stored in the target cache line in the main memory.

Step 202, according to the target state type, matching the state transition rule corresponding to the target state type.

The state conversion rule is used for indicating that the first cache line meets the state type of cache consistency and data consistency under the target state type. After the multi-core system acquires the target state type, the state transition rule to be used subsequently is verified according to the target state type.

Step 203, verifying whether the multi-core system meets cache consistency according to the state conversion rule, the state type to be verified and the data stored in the first cache line, obtaining a verification result, and returning the verification result.

The multi-core system verifies whether each state type to be verified is a state type meeting cache consistency according to a state conversion rule corresponding to the target state type, verifies whether data stored in each first cache line meet cache consistency according to the state conversion rule at the same time to obtain a verification result, and returns the verification result.

In summary, the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache except the target cache are respectively obtained; and then matching a state transition rule corresponding to the target state type, and verifying whether the state type to be verified and the data stored in the first cache line are the state types meeting the cache consistency by using the state transition rule when the target cache behavior is the target state type, further determining a verification result of the cache consistency of the multi-core system, and returning the verification result. And the verification of cache consistency in the multi-core system supporting the AMBA CHI protocol is realized.

FIG. 3 is a flowchart illustrating a cache coherency verification method according to an exemplary embodiment. The method is performed by an AMBA CHI protocol based multi-core system, which may be a multi-core system as shown in fig. 1. As shown in fig. 3, the cache consistency verification method may include the following steps:

step 301, respectively obtaining a target state type of a target cache line in a target cache and a to-be-verified state type of a first cache line in a first cache.

Please refer to step 201 in the embodiment shown in fig. 2 in detail, which is not described herein.

The inventor considers that the state model of the cache in the multi-core system based on AMBA CHI protocol is as shown in fig. 4, and there are UC, SC, UCE, UD, SD, UDP and I seven states for representing the state type of the current cache or the cache line, wherein Valid represents that the cache line is Valid in the cache under the current state type, and Invalid represents that the cache line is Invalid in the cache under the current state type; unique, shared, clean and Dirty represent the status type of each cache line in main memory. UD, SD, UC, SC in AMBA CHI protocol, and five status types I satisfy MOESI protocol. While Modified (M), issued (O), exclusive (E), shared (S), and invite (I) of five status types in the MOESI protocol satisfy the mol sei protocol status conversion rule as shown in table 1, the first column in table 1 indicates the status type of a cache line in a certain cache, the first row indicates the status type of the cache line in other caches, no indicates that such status combination is not allowed to exist, and Yes indicates that such status combination is allowed to exist.

Table 1MOSEI protocol state transition rules

Status type	M(UD)	O(SD)	E(UC)	S(SC)	I(I)
						M(UD)	No	No	No	No	Yes
O(SD)	No	No	No	Yes	Yes
						E(UC)	No	No	No	No	Yes
S(SC)	No	Yes	No	Yes	Yes
						I(I)	Yes	Yes	Yes	Yes	Yes

Therefore, the inventor thinks that each state type in the MOESI protocol corresponds to UD, SD, UC, SC and I five state types in the AMBA CHI protocol, and further applies the MOSEI protocol state transition rule to the AMBA CHI protocol state transition rule, without resetting the state transition rule, thereby reducing the design complexity of the AMBA CHI protocol-based state transition rule.

Therefore, before step 301, the cache consistency verification method further includes:

the state types UD, SD, UC, SC and I in the AMBACHI protocol are respectively in one-to-one correspondence with the state types M, O, E, S and I in the MOESI protocol, and the state conversion principle corresponding to each state type in the MOESI protocol is determined as the state conversion rule corresponding to UD, SD, UC, SC and I state types in the AMBACHI protocol.

Specifically, the multi-core system corresponds UD and M in the AMBACHI protocol, and determines a state transition rule corresponding to M as a state transition rule corresponding to UD, that is, when a certain cache line state type of the current cache is updated to UD: this cache line should not exist in other caches, even if it exists, the state type can only be I; the data in the current cache line is not consistent with the data in the main memory SLC or register memory (the case where the updated data value is consistent with the pre-update data value is not precluded).

Corresponding SD and O in the AMBACHI protocol, and determining a state transition rule corresponding to O as a state transition rule corresponding to SD, namely when the state type of a certain cache line currently cached is updated to SD: allowing the cache line to exist in other caches, wherein the state type is SC or I; for this line, the data for this line is the same in all caches and is not consistent with the data in the main memory SLC or register memory (the case where the updated data value is consistent with the pre-update data value is not precluded).

Corresponding UC and E in the AMBA CHI protocol, and determining a state transition rule corresponding to E as a state transition rule corresponding to UC, namely when the state type of a certain cache line currently cached is updated to UC: this cache line should not exist in other caches, even if it exists, the state type can only be I; the data in the current cache line is consistent with the data in the main memory SLC, if the state type of the cache line in the main memory SLC is dirty state, the data of the cache line in the current cache is not necessarily consistent with the data in the register memory, and if the state type of the cache line in the main memory SLC is clean state, the data of the cache line in the current cache is consistent with the data in the memory.

Corresponding the SC in the AMBA CHI protocol to the S, and determining the state transition rule corresponding to the S as the state transition rule corresponding to the SC, namely when the state type of a certain cache line currently cached is updated to the SC: allowing the cache line to exist in other caches, wherein the state type is SC, SD or I; for the cache line, the data of the cache line in all caches are the same; if the cache line with the SD state type does not exist in other caches, the data of the cache line in all caches are consistent with the data in the main memory SLC or the register memory; if the other caches have the cache line with the state type of SD, the data of the cache line in all caches is inconsistent with the data in the main memory SLC or the register memory (the case that the updated data is consistent with the previous data is not excluded).

Corresponding I in the AMBACHI protocol and I in the MOSEI protocol, and determining a state transition rule corresponding to the I in the MOSEI protocol as a state transition rule corresponding to the I in the AMBA CHI protocol, namely when a certain cache line state type of the current cache is updated to be I: the current cache kicks out the cache line, and other caches allow the cache line to exist without limitation of state types; the current cache does not have the cache line, and the data of the cache line is not checked. And finally, the state conversion rules corresponding to the state types UD, SD, UC, SC and I in the AMBA CHI protocol shown in the table 1 are obtained, so that the MOSEI protocol state conversion rules are directly applied to the AMBA CHI protocol state conversion rules, the state conversion rules do not need to be reset, and the design complexity of the state conversion rules based on the AMBA CHI protocol is reduced.

Step 302, according to the target state type, matching the state transition rule corresponding to the target state type.

Please refer to step 202 in the embodiment shown in fig. 2 in detail, which is not described herein.

Step 303, verifying whether the multi-core system meets cache consistency according to the state conversion rule, the state type to be verified and the data stored in the first cache line, obtaining a verification result, and returning the verification result.

Optionally, in order to improve efficiency of cache consistency verification, according to a state conversion rule, a state type to be verified, and data stored in a first cache line, verifying whether the multi-core system meets cache consistency, and obtaining a verification result may include:

in step 3031, when the target state type is UD, it is verified whether the state type to be verified is I, and if so, the verification result is determined to satisfy the cache consistency.

When the multi-core system monitors that the state type of the target cache line is UD according to the data cache updating information of the target cache, verifying whether the state type to be verified is I or not, and if so, determining that the verification result meets cache consistency; and if the type of the state to be verified is not I, the verification result is alarm information.

In an application scenario, as shown in fig. 5, a multi-core system monitors write information of a cache directory of a cache in each core, and when it is monitored that a cache line is updated in the cache, the state type of the updated cache line is marked according to the write information of the cache directory of the cache, so as to obtain the updated state type of the updated cache line. When the state type of the cache line is updated to UD, checking the state of other caches, namely verifying the state type of the cache line in the caches of other cores, verifying whether the state type of the cache line in the caches of other cores is I, and if not, returning alarm information to finish the error reporting operation.

Step 3032, when the target state type is SD, verifying whether the state type to be verified is SC or I, and verifying whether the data stored in the first cache line is consistent with the data stored in the target cache line, if so, determining that the verification result meets the cache consistency.

When the multi-core system monitors that the state type of the target cache line is SD according to the data cache updating information of the target cache, verifying whether the state type to be verified is SC or I, and verifying whether the data stored in each first cache line is consistent with the target data stored in the cache line; if the respective status type to be verified is not SC or I, or the data stored in the first cache line is inconsistent with the data stored in the target cache line, the alarm information is determined as a verification result. If each state type to be verified is SC or I, and the data stored in the first cache line is consistent with the data stored in the target cache line, the verification result is determined to meet the cache consistency.

In the multi-core system based on AMBA CHI protocol, although the status type of the cache line requires consistency between the data stored in the cache line and the data stored in the main memory SLC and/or the register memory, the condition that the data after the update of the cache line is consistent with the data before the update of the cache line is not excluded. That is, there are cases in which: although the state type of the cache line requires that the data stored in the cache line is inconsistent with the data stored in the main memory SLC and/or the register memory, the multi-core system still satisfies the cache consistency when the data stored in the current cache line is consistent with the data stored in the main memory SLC and/or the register memory. In addition, a great deal of time is wasted in reading the data stored in the main memory SLC and/or the register memory, so in order to improve the efficiency of verifying cache consistency, in the embodiment of the present application, in step 3031 and step 3032, the consistency between the data stored in the cache line and the data stored in the main memory SLC and/or the register memory is not verified.

With reference to the above application scenario and fig. 5, when the multi-core system monitors that the state type of a cache line in the cache is updated to SD, checking the state of other caches, that is, verifying the state type of the cache line in the cache of other cores, and verifying whether the state type of the cache line in the cache of other cores is I or SC, if not, returning alarm information to complete the error reporting operation; and checking other cache data, namely verifying whether the data stored by the cache line in the cache of other cores is consistent with the data stored by the cache line, and if not, returning alarm information to complete error reporting operation.

Step 3033, when the target state type is UC, verifying whether the state type to be verified is I, and verifying whether the data stored in the target cache line is consistent with the corresponding data in the main memory, if so, determining that the verification result meets the cache consistency.

The corresponding data in the main memory is the data with the data address consistent with the data address of the data in the target cache line; when the multi-core system monitors that the state type of the target cache line is UC according to the data cache update information of the target cache, verifying whether the state type to be verified is I or not, and verifying whether the data with the data address stored in the target cache line as the target address in the main memory is consistent with the data indicated by the target address stored in the SLC or not; and if the type of each state to be verified is not I, or the data stored in the target cache line is inconsistent with the corresponding data in the main memory, determining the alarm information as a verification result. If each state type to be verified is I and the data stored in the target cache line is consistent with the corresponding data in the main memory, the verification result is determined to meet the cache consistency.

With reference to the application scenario and fig. 5, when the multi-core system monitors that the state type of a cache line in the cache is updated to UC, checking the state of other caches, that is, verifying whether the state type of the cache line in the cache of other cores is I, and if not, returning alarm information to complete the error reporting operation; checking SLC data, namely verifying whether the data address stored in the cache line is consistent with the system data indicated by the address stored in the main memory SLC; if the alarm information is inconsistent, the alarm information is returned to finish the error reporting operation.

Step 3034, when the target state type is SC, verifying whether the state type to be verified is SC, SD or I, and verifying whether the data stored in the target cache line is consistent with the corresponding data in the main memory and whether the data stored in the first cache line is consistent with the data stored in the target cache line, if so, determining that the verification result is that the cache consistency is satisfied.

When the multi-core system monitors that the state type of the target cache line is SC according to the data cache updating information of the target cache, verifying whether the state type to be verified is SC, SD or I; and verifying whether the first data is consistent with the target data, and simultaneously verifying whether the data stored in the target cache line is consistent with the corresponding data in the main memory when the type of the state to be verified is not SD. And when the type of the state to be verified is not SC, SD or I, or when the type of the state to be verified is not SD, the data stored in the target cache line is inconsistent with the corresponding data in the main memory, or the data stored in the first cache line is inconsistent with the data stored in the target cache line, determining the alarm information as a verification result. If each state type to be verified is SC or I, and the data stored in the first cache line is consistent with the data stored in the target cache line and the data stored in the target cache line is consistent with the corresponding data in the main memory, determining that the verification result meets the cache consistency; if the SD exists in each state type to be verified, whether the data stored in the target cache line is consistent with the corresponding data in the main memory is not verified, and the verification result is determined to meet the cache consistency as long as the data stored in the first cache line is consistent with the data stored in the target cache line.

It can be understood that, when the SD exists in the state type to be verified, which is required by the corresponding state transition rule when the target state type is SC, the case that the target data is inconsistent with the system data does not exclude the case that the data after the update of the target cache line is consistent with the data before the update, that is, the case that the data after the update of the target cache line is consistent with the system data. Therefore, in order to improve the verification efficiency of cache consistency, step 3034 in the embodiment of the present application does not verify that the target data is inconsistent with the system data when the SD exists in the state type to be verified.

It should be noted that, when the state type of the cache line is UC or SC, a requirement is made on consistency between the data stored in the cache line and the data stored in the register memory in the corresponding state transition rule, but the requirement requires to read the state type of the main memory SLC or the data stored in the register memory, and reading the state type of the SLC or the data stored in the register memory requires a lot of simulation time, which is not suitable for practical work. Therefore, in order to improve the efficiency of verifying cache coherency, in the embodiment of the present application, step 3033 and step 3034 do not verify the consistency of the data stored in the cache line and the data stored in the register memory.

With reference to the application scenario and fig. 5, when the multi-core system monitors that the state type of a cache line in the cache is updated to SC, checking the state of other caches, that is, verifying whether the state type of the cache line in the cache of other cores is SC, SD or I, and if not, returning alarm information to complete the error reporting operation; and checking other cache data, namely verifying whether the data stored by the cache line in the cache of other cores is consistent with the data stored by the cache line, and if not, returning alarm information to complete error reporting operation. And meanwhile, checking SLC data, namely, when the state type of the cache line in the cache of other cores is verified to be free of SD, if the data address stored in the cache line is consistent with the system data indicated by the address stored in the main memory SLC, returning alarm information to complete error reporting operation.

In step 3035, when the target state type is I, it is determined that the verification result is that cache consistency is satisfied.

When the multi-core system monitors that the state type of the target cache line is I according to the data cache updating information of the target cache, whether the state type to be verified is UD, SD, UC, SC or I or not determines that the verification result meets the cache consistency.

Optionally, when the target state type is I, the cache coherency verification method further includes marking the target cache line as invalid from the target cache (i.e., kicking the target cache line from the target cache).

With reference to the application scenario and fig. 5, when the multi-core system monitors that the state type of a cache line in a cache is updated to I, it is not necessary to check other caches, that is, to verify whether the data stored in the cache line in other cores is consistent with the data stored in the cache line, and the process of verifying cache consistency is ended.

Optionally, before acquiring the to-be-verified state type of the first cache line in the first cache, the cache consistency verification method further includes:

verifying whether a first cache line storing first data exists in a first cache, wherein the data address of the first data is the same as the data address of target data stored in the target cache line; when a first cache line exists in the first cache, respectively acquiring a target state type of a target cache line in a target cache and a to-be-verified state type of the first cache line in the first cache; and when the first cache line does not exist in the first cache, verifying whether the multi-core system meets cache consistency according to the data stored in the target cache line and the state conversion rule corresponding to the target cache line, and returning the verification result.

The multi-core system monitors the change of the data cache update information cached in each core, and when the target state type is obtained, the cache consistency verification needs to be carried out on the current multi-core system. Before the to-be-verified state type of the first cache line in the first cache is obtained, firstly verifying whether the first cache line with the data address corresponding to the stored data as the target address exists in other cores, wherein the target address is the data address corresponding to the data stored in the target cache line in the main memory.

When a first cache line exists in other cores, acquiring the type of the state to be verified of the first cache line in the first cache; and when the first cache line does not exist in other cores, verifying whether the current multi-core system meets cache consistency according to a state transition rule corresponding to the target state type of the target cache line and data stored in the target cache line. The specific verification steps are similar to the above embodiments, except that verification of the to-be-verified state type of the first cache line is not required, but when the target state type is UD, SD or I, the verification result is directly determined to satisfy cache consistency and the verification result is returned. When the target state type is UC or SC, directly verifying whether the target data is consistent with the system data to determine a verification result. The verification of cache consistency of the multi-core system based on the AMBA CHI protocol is realized.

Optionally, for the debugging efficiency of the operator, after obtaining the verification result, the method may include:

step 3036, when the verification result is that the cache consistency is satisfied, returning the verification result.

When the multi-core system verifies that the multi-core system meets the cache consistency as a verification result, the information used for representing that the current multi-core system meets the cache consistency is taken as the verification result and returned to the front end, so that operators can clearly see that the current multi-core system meets the cache consistency.

And step 3037, when the verification result is that the cache consistency is not met, acquiring alarm information of the system.

The alarm information comprises at least one of an address, index information, tag information, stored data of a target cache line and a first cache line, identification information of a core to which the alarm information belongs, a state type and a state transition rule corresponding to the target state type. When the multi-core system verifies that the verification result is that the multi-core system does not meet the cache consistency, reading addresses, index information (i.e. index information), tag information (i.e. tag information) of a target cache line and a first cache line, stored data, identification information and state types of cores to which the target cache line belongs, reading a state transition rule corresponding to the target cache line, and taking at least one of the read information as alarm information.

Step 3038, the alarm information is used as a verification result, and the verification result is returned.

The multi-core system verifies the alarm information and returns the alarm information to the front end, so that operators can clearly know the specific condition that the current multi-core system does not meet the cache consistency, and the subsequent operators can conveniently and rapidly and effectively locate the problem.

In summary, the state types to be verified are verified to satisfy the state types of cache coherence through different target state types, and the data coherence when the data stored in the target cache line and/or the first cache line satisfy the cache coherence determines whether the verification result is that the cache coherence is satisfied, and returns the verification result, thereby realizing the verification of the cache coherence in the multi-core system supporting the AMBA CHI protocol. And when the verification result is that the cache consistency is met, the verification result is directly returned to inform an operator that the multi-core system does not need to be debugged. When the verification result is that the cache consistency is not met, the alarm information including at least one of the address, index information, label information, stored data, identification information of the core, state type and state conversion rule corresponding to the target cache line is returned as the verification result, so that an operator can quickly position the problem that the multi-core system does not meet the cache consistency according to the returned alarm information, debug the multi-core system, and improve the debugging efficiency of the operator.

FIG. 6 is a flowchart illustrating a cache coherency verification method according to an exemplary embodiment. The method is performed by an AMBA CHI protocol based multi-core system, which may be a multi-core system as shown in fig. 1. As shown in fig. 6, before the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache are respectively acquired, the cache consistency verification method may further include the following steps:

step 601, a first state type of a first primary cache and a second state type of a target secondary cache are respectively acquired.

Wherein, the first-level cache line and the second-level cache line both store data under the same data address; the multi-core system comprises at least one core, the core comprises a full-consistency request node, the full-consistency request node comprises a first-level cache and a second-level cache, and the first-level cache and the second-level cache are in an inclusive relationship. When a primary cache and a secondary cache exist in a full-consistency request node (namely RN-F) of a kernel in the multi-core system, the verification of the cache consistency of the multi-core system comprises the verification of the cache consistency between the primary cache and the secondary cache.

Specifically, the multi-core system can monitor the change of the update information of the data caches of the secondary caches in the multi-core system through the secondary cache monitor. When the data cache update information changes, which means that there is an updated second-level cache line in the RN-F, the multi-core system uses the second-level cache to which the updated second-level cache line belongs as a target second-level cache, updates tag information, index information and bank information of the second-level cache line, and records the state type of the second-level cache line to obtain a second state type. The state type of the first-level cache connected to the second-level cache is recorded in the second-level cache, so that the state type of the relevant first-level cache line in the first-level cache can be obtained when the tag information, index information and bank information of the cache line in the second-level cache are updated by the multi-core system. Therefore, the multi-core system can acquire the state type of each cache line in the primary cache in each core according to the data cache update information of the secondary cache connected with each primary cache. The multi-core system determines the first level cache in each core as each first level cache, and obtains the first state type of the first level cache line corresponding to the second level cache line in the target second level cache. The specific meaning of the first-level cache line corresponding to the second-level cache line in the target second-level cache is as follows: the second level cache line in the target second level cache stores data at an address in main memory, and the first level cache line also stores data at the address.

Step 602, verifying whether the first state type satisfies cache consistency according to a preset multi-level cache verification rule corresponding to the second state type.

The method comprises the steps that a multi-level cache verification rule is preset and is a rule determined according to an MOESI protocol, and the rule is used for indicating the state types of a first-level cache and a second-level cache in the multi-core system when the multi-core system meets cache consistency; the multi-core system matches a preset multi-level cache verification rule corresponding to the second state type, so as to verify whether the first state type meets the preset multi-level cache verification rule, when the first state type meets the preset multi-level cache verification rule, the first state type meets the cache consistency, and otherwise, the first state type does not meet the cache consistency. When the first state type does not meet the cache consistency, namely the cache consistency between the first-level cache and the second-level cache in the multi-core system is not met, the multi-core system can acquire at least one of addresses, index information, label information, state type and preset multi-level cache verification rules corresponding to the second-level cache line in the target second-level cache and the first-level cache as alarm information, and returns the alarm information.

The preset multi-level cache verification rule determined according to the MOESI protocol is specifically as follows:

when the update state of the second-level cache is the I state, the state of the first-level cache of each core must be the I state, otherwise, the error is reported;

when the state type of the second-level cache update is UD, if the state type of the first-level cache update of one core is UD or UC, the state type of the first-level cache of other cores is I, otherwise, reporting errors;

when the state type of the second-level cache update is SC, the state type of the first-level cache of each core cannot be UD or UC, otherwise, reporting errors;

when the state type of the second-level cache update is UC, the state type of the first-level cache of each core can be any one of UD, UC, SD, UC or I without verification;

when the state type of the second-level cache update is SD, the first-level cache state of each core cannot be UD, SD or UC, otherwise, error is reported.

and when the second state type is UD and the first state type is UD or UC, acquiring a third state type of the second-level cache, and verifying whether the third state type is I, and if so, the first state type meets cache consistency.

When the multi-core system monitors that the second state type is changed into UD, simultaneously monitoring whether UD or UC exists in the first state type of each first-level cache, if UD or UC exists in the first state type of each first-level cache, taking the first-level caches except the state types of UD and UC as the second-level cache, and acquiring the third state type of each second-level cache according to the data cache updating information of the second-level cache connected with the second-level cache. Further verifying whether each third state type is I, and if so, enabling the first state type to meet cache consistency; if not, the first state type does not satisfy cache coherency.

When the second state type is SD, verifying whether the first state type is SC or I, and if so, the first state type meets cache consistency.

When the multi-core system monitors that the second state type is changed into SD, verifying whether each first state type is SC or I, and if so, enabling the first state type to meet cache consistency; if not, the first state type does not satisfy cache coherency.

When the second state type is UC, the first state type is determined to meet cache consistency.

When the multi-core system monitors that the second state type is changed to UC, the state type of the first-level cache can be any one of UC, UD, SC, SD and I, so that the state type of the first-level cache is not verified, and the first state type is directly determined to meet cache consistency.

When the second state type is SC, verifying whether the first state type is SC, SD or I, and if so, the first state type meets cache consistency.

When the multi-core system monitors that the second state type is changed into SC, verifying whether each first state type is SC, SD or I, and if so, enabling the first state type to meet cache consistency; if not, the first state type does not satisfy cache coherency.

When the multi-core system monitors that the second state type is changed into I, verifying whether each first state type is I, and if so, enabling the first state type to meet cache consistency; if not, the first state type does not satisfy cache coherency. And verifying whether the state types corresponding to the first-level cache and the second-level cache in the multi-core system meet cache consistency or not by a preset multi-level cache verification rule, so that cache consistency verification of the multi-core system in different multi-core environments is realized, and the multi-core system has expandability.

Step 603, when the first state type satisfies the cache consistency, the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache are respectively obtained, so as to verify whether the multi-core system satisfies the cache consistency.

When the first state type meets the cache consistency, proving that the first level cache and the second level cache in the multi-core system meet the cache consistency, but not meaning that the multi-core system meets the cache consistency, therefore, the cache consistency verification needs to be carried out on each second level cache in the multi-core system, and the cache consistency verification is carried out on the second level cache. Specifically, the multi-core system obtains the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache, respectively, and performs the subsequent steps with the embodiments described in fig. 2 or fig. 3 to verify whether the multi-core system meets the cache consistency.

In summary, when the multi-core system includes the first-level cache and the second-level cache, a first state type of the first-level cache and a second state type of the target second-level cache are respectively obtained, and whether the first state type meets cache consistency is verified according to the first state type, the second state type and a preset multi-level cache verification rule; when the first state type meets the cache consistency, the first-level cache currently in the multi-core system meets the cache consistency. And further, whether the second-level cache in the multi-core system meets consistency needs to be verified, and cache consistency verification is performed on the multi-core system by respectively acquiring the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache. The cache consistency verification of the multi-core system of different multi-core environments is realized, the number of cores in the multi-core system and the configurability of different multi-core environments are supported, and the scalability is realized.

Fig. 7 is a block diagram showing a structure of a cache coherency verification apparatus according to an exemplary embodiment, which is applied to a system supporting AMBA CHI protocol, the cache coherency verification apparatus including:

an obtaining module 701, configured to obtain a target state type of a target cache line in a target cache and a to-be-verified state type of a first cache line in a first cache, respectively; the target cache and the first cache belong to different cores, and the target cache line and the first cache line both store data under the same data address;

the matching module 702 is configured to match a state transition rule corresponding to a target state type according to the target state type; the state conversion rule is used for indicating that the first cache line meets the state type of cache consistency and data consistency under the target state type;

and the verification module 703 is configured to verify whether the multi-core system meets cache consistency according to the state conversion rule, the state type to be verified, and the data stored in the first cache line, obtain a verification result, and return the verification result.

In some alternative embodiments, the verification module 703 includes:

the return unit is used for returning the verification result when the verification result meets the cache consistency;

The acquisition unit is used for acquiring alarm information of the system when the verification result is that the cache consistency is not met; the alarm information comprises at least one of an address, index information, tag information, stored data of the first cache line, identification information of the core, a state type and a state transition rule corresponding to the target state type;

and the return unit is also used for taking the alarm information as a verification result and returning the verification result.

In some optional embodiments, before the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache are respectively acquired, the cache consistency verification device further includes:

the determining module is configured to correspond the state types UD, SD, UC, SC and I in the AMBA CHI protocol to the state types M, O, E, S and I in the MOESI protocol one by one, and determine the state conversion rule corresponding to each state type in the MOESI protocol as the state conversion rule corresponding to UD, SD, UC, SC and I state types in the AMBA CHI protocol.

In some alternative embodiments, the verification module 703 includes:

the verification unit is used for verifying whether the state type to be verified is I when the target state type is UD, and if so, determining that the verification result meets cache consistency;

The verification unit is further used for verifying whether the state type to be verified is SC or I when the target state type is SD, verifying whether the data stored in the first cache line are consistent with the data stored in the target cache line, and determining that cache consistency is met if the data stored in the first cache line are consistent with the data stored in the target cache line;

the verification unit is also used for verifying whether the state type to be verified is I or not when the target state type is UC, verifying whether the data stored in the target cache line is consistent with the corresponding data in the main memory or not, and determining that the cache consistency is met according to the verification result if the data stored in the target cache line is consistent with the corresponding data in the main memory;

the verification unit is further used for verifying whether the state type to be verified is SC, SD or I when the target state type is SC, verifying whether the data stored in the target cache line is consistent with the corresponding data in the main memory and whether the data stored in the first cache line is consistent with the data stored in the target cache line, and if so, determining that the cache consistency is met according to the verification result;

and the verification unit is also used for determining that the verification result meets the cache consistency when the target state type is I.

In some optional embodiments, the multi-core system comprises at least one core, the core comprises a full-consistency request node, the full-consistency request node comprises a first-level cache and a second-level cache, the first-level cache and the second-level cache are in an inclusive relationship, and the target cache and the first cache are the second-level caches; before respectively acquiring the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache, the cache consistency verification device further comprises:

The acquiring module 701 is further configured to acquire a first state type of the first primary cache and a second state type of the target secondary cache respectively;

the verification module 703 is further configured to verify whether the first state type meets cache consistency according to a preset multi-level cache verification rule corresponding to the second state type; the preset multi-level cache verification rule is a rule determined according to an MOESI protocol and is used for indicating the state types of a first-level cache and a second-level cache in the multi-core system when the multi-core system meets cache consistency;

In some alternative embodiments, the verification module 703 is further configured to,

In some optional embodiments, the verification module 703 is further configured to, after obtaining the target state type of the target cache line in the target cache, verify that the first cache line in which the first data is stored is further used to verify whether the data address of the first data is the same as the data address of the target data stored in the target cache line;

the obtaining module 701 is further configured to obtain a to-be-verified state type of the first cache line in the first cache when the first cache line exists in the first cache;

the verification module 703 is further configured to verify whether the multi-core system meets cache consistency according to the data stored in the target cache line and the state conversion rule corresponding to the target cache line when the first cache line does not exist in the first cache, and return a verification result.

Fig. 8 shows a block diagram of a computer device 800 in accordance with an exemplary embodiment of the present application. The computer device may be implemented as a server in the above-described aspects of the present application. The computer device 800 includes a central processing unit (Central Processing Unit, CPU) 801, a system Memory 804 including a random access Memory (Random Access Memory, RAM) 802 and a Read-Only Memory (ROM) 803, and a system bus 805 connecting the system Memory 804 and the central processing unit 801. Computer device 800 also includes a mass storage device 806 for storing an operating system 809, application programs 810, and other program modules 811.

The mass storage device 806 is connected to the central processing unit 801 through a mass storage controller (not shown) connected to the system bus 805. The mass storage device 806 and its associated computer-readable media provide non-volatile storage for the computer device 800. That is, the mass storage device 806 may include a computer-readable medium (not shown) such as a hard disk or a compact disk-Only (CD-ROM) drive.

Computer readable media may include computer storage media and communication media without loss of generality. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes RAM, ROM, erasable programmable read-Only register (Erasable Programmable Read Only Memory, EPROM), electrically erasable programmable read-Only Memory (EEPROM) flash Memory or other solid state Memory technology, CD-ROM, digital versatile disks (Digital Versatile Disc, DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices. Of course, those skilled in the art will recognize that computer storage media are not limited to the ones described above. The system memory 804 and mass storage device 806 described above may be collectively referred to as memory.

According to various embodiments of the present disclosure, the computer device 800 may also operate by a remote computer connected to the network through a network, such as the Internet. I.e., the computer device 800 may be connected to the network 808 through a network interface unit 807 coupled to the system bus 805, or other types of networks or remote computer systems (not shown) may also be coupled to the computer device using the network interface unit 807.

The memory further comprises at least one computer program, which is stored in the memory, and by executing which the central processing unit 801 implements all or part of the steps of the method shown in the various embodiments described above.

In an exemplary embodiment, a computer readable storage medium is also provided for storing at least one computer program, the at least one computer program being loaded and executed by a processor to implement all or part of the steps of the above method. For example, the computer readable storage medium may be Read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), compact disc Read-Only Memory (CD-ROM), magnetic tape, floppy disk, optical data storage device, and the like.

In an exemplary embodiment, a computer program product or a computer program is also provided, the computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium and executes the computer instructions to cause the computer device to perform all or part of the steps of the method shown in any of the embodiments of fig. 2 or 3 or 6 described above.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A cache consistency verification method, which is applied to a multi-core system based on AMBA CHI protocol, the method comprising:

according to the target state type, matching a state transition rule corresponding to the target state type; the state transition rule is used for indicating that the first cache line meets the state type of cache consistency and data consistency under the target state type;

and verifying whether the multi-core system meets cache consistency according to the state transition rule, the state type to be verified and the data stored in the first cache line, obtaining a verification result, and returning the verification result.

2. The method of claim 1, wherein verifying whether the multi-core system satisfies cache coherency according to the state transition rule, the state type to be verified, and the data stored in the first cache line, obtaining a verification result, and returning the verification result comprises:

When the verification result is that cache consistency is met, returning the verification result;

when the verification result is that cache consistency is not met, acquiring alarm information of the system; the alarm information comprises at least one of an address, index information, tag information, stored data, identification information of a core to which the alarm information belongs, a state type and a state transition rule corresponding to the target state type of the target cache line and the first cache line;

and taking the alarm information as the verification result and returning the verification result.

3. The method of claim 1, wherein prior to separately obtaining the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache, the method further comprises:

and (3) respectively corresponding the state types UD, SD, UC, SC and I in the AMBA CHI protocol to the state types M, O, E, S and I in the MOESI protocol one by one, and determining the state conversion principle corresponding to each state type in the MOESI protocol as the state conversion rule corresponding to the state types UD, SD, UC, SC and I in the AMBA CHI protocol.

4. The method of claim 3, wherein verifying whether the multi-core system satisfies cache coherency according to the state transition rule, the type of state to be verified, and the data stored in the first cache line, the obtaining a verification result comprises:

when the target state type is UD, verifying whether the state type to be verified is I, and if so, determining that cache consistency is met by the verification result;

when the target state type is SD, verifying whether the state type to be verified is SC or I, verifying whether the data stored in the first cache line are consistent with the data stored in the target cache line, and if so, determining that cache consistency is met by the verification result;

when the target state type is UC, verifying whether the state type to be verified is I, verifying whether the data stored in the target cache line are consistent with the corresponding data in the main memory, and if so, determining that the verification result meets cache consistency;

when the target state type is SC, verifying whether the state type to be verified is SC, SD or I, verifying whether the data stored in the target cache line is consistent with corresponding data in main memory and whether the data stored in the first cache line is consistent with the data stored in the target cache line, and if so, determining that cache consistency is met by the verification result;

And when the target state type is I, determining that the verification result meets cache consistency.

5. The method of claim 1, wherein the multi-core system comprises at least one core, the core comprising a full coherence request node, the full coherence request node comprising a primary cache and a secondary cache, the primary cache being in inclusive relationship with the secondary cache, the target cache being in secondary cache with the first cache; before respectively acquiring the target state type of the target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache, the method further comprises:

when the first state type meets the cache consistency, respectively acquiring the target state type of a target cache line in the target cache and the to-be-verified state type of the first cache line in the first cache so as to verify whether the multi-core system meets the cache consistency.

6. The method of claim 5, wherein verifying whether the first state type satisfies cache coherency according to a preset multi-level cache verification rule corresponding to the second state type comprises:

when the second state type is UD and the first state type is UD or UC, acquiring a third state type of a second-level cache, and verifying whether the third state type is I, if so, the first state type meets cache consistency;

and when the second state type is I, verifying whether the first state type is I, and if so, enabling the first state type to meet cache consistency.

7. The method of any of claims 1-4, wherein after obtaining the target state type of the target cache line in the target cache, the method further comprises:

Verifying whether the first cache line exists in the first cache;

when the first cache line exists in the first cache, acquiring the to-be-verified state type of the first cache line in the first cache;

and when the first cache line does not exist in the first cache, verifying whether the multi-core system meets cache consistency according to the data stored in the target cache line and the state conversion rule corresponding to the target cache line, and returning the verification result.

8. A cache coherency verification apparatus, for use in a multi-core system supporting AMBA CHI protocol, the apparatus comprising:

the matching module is used for matching the state transition rule corresponding to the target state type according to the target state type; the state transition rule is used for indicating that the first cache line meets the state type of cache consistency and data consistency under the target state type;

9. A computer device comprising a processor and a memory having stored therein at least one instruction that is loaded and executed by the processor to implement a cache coherence validation method as recited in any one of claims 1 to 7.

10. A computer readable storage medium having stored therein at least one instruction that is loaded and executed by a processor to implement the cache coherence verification method of any one of claims 1 to 7.