CN116775327A

CN116775327A - Application programming interface for storing data

Info

Publication number: CN116775327A
Application number: CN202310259242.1A
Authority: CN
Inventors: L·昆杜; N·托马尔; 吴金友
Original assignee: Nvidia Corp
Current assignee: Nvidia Corp
Priority date: 2022-03-16
Filing date: 2023-03-16
Publication date: 2023-09-19
Also published as: DE102023106288A1

Abstract

The application discloses an application programming interface for storing data, and in particular discloses a device, a system and a technology for executing one or more APIs. In at least one embodiment, the processor is configured to execute the API to store data in a selected store to be used for transmitting information between a plurality of fifth generation new radio (5G-NR) computations using different transmission protocols.

Description

Application programming interface for storing data

Cross Reference to Related Applications

The present application is a continuation of the application No. pct/CN2022/081192, filed on 3/16 of 2022, entitled "application programming interface for selection of storage (APPLICATION PROGRAMMING INTERFACE TO SELECT STORAGE)", the disclosure of which is incorporated herein by reference in its entirety. The present application is also incorporated by reference for all purposes for all disclosures of the following applications: co-pending U.S. patent application Ser. No. 17/720,196 entitled "for selecting stored application Programming interface (APPLICATION PROGRAMMING INTERFACE TO SELECT STORAGE)", co-pending U.S. patent application Ser. No. 17/720,199 entitled "for preventing deselection of stored application Programming interface (APPLICATION PROGRAMMING INTERFACE TO PREVENT DESELECTION OF STORAGE)", co-pending U.S. patent application Ser. No. 17/720,203 entitled "for deselecting stored application Programming interface (APPLICATION PROGRAMMING INTERFACE TO DESELECT STORAGE)", and co-pending U.S. patent application Ser. No. 17/720,205 entitled "application Programming interface for obtaining data" (APPLICATION PROGRAMMING INTERFACE TO OBTAIN DATA) ".

Technical Field

At least one embodiment relates to processing resources for fifth generation new radio ("5G-NR") operations. For example, a processor includes one or more circuits for executing an Application Programming Interface (API) to select a store (store) for transferring information between a plurality of fifth generation new radio (5G-NR) computing resources.

Background

Creating interoperability between separate computing resources used in a 5G-NR architecture can use a significant amount of time, computing, or human resources. The amount of time, computing resources, or human resources used to create interoperability between separate computing resources used in the 5G-NR architecture may be improved.

Drawings

FIG. 1 is a schematic block diagram of a network protocol stack in accordance with at least one embodiment;

FIG. 2 illustrates a transport abstraction framework in accordance with at least one embodiment;

FIG. 3 illustrates a schematic flow diagram for transmitting data using a transmission abstraction and a non-zero replication method in accordance with at least one embodiment;

FIG. 4 illustrates a schematic flow diagram for transmitting data using a transmission abstraction and zero-copy method in accordance with at least one embodiment;

FIG. 5 illustrates a schematic flow diagram for transmitting data using a transmission abstraction and zero-copy method in accordance with at least one embodiment;

FIG. 6 illustrates a schematic flow diagram for receiving data using a transmission abstraction and a non-zero replication method in accordance with at least one embodiment;

FIG. 7 illustrates a schematic flow diagram for receiving data using a transmission abstraction and zero-copy method in accordance with at least one embodiment;

FIG. 8 illustrates a schematic flow diagram for receiving data using a transmission abstraction and a non-zero replication method in accordance with at least one embodiment;

FIG. 9 illustrates a schematic flow diagram for receiving data using a transmission abstraction and zero-copy method in accordance with at least one embodiment;

FIG. 10 illustrates a schematic block diagram of mapping a transport abstraction API to a transport configuration based on peripheral component interconnect express (PCIe) in accordance with at least one embodiment;

FIG. 11 illustrates a schematic block diagram of mapping a transport abstraction API to a transport configuration based on shared memory in accordance with at least one embodiment;

FIG. 12 illustrates a schematic block diagram of mapping a transport abstraction API to a transport configuration based on User Datagram Protocol (UDP), in accordance with at least one embodiment;

FIG. 13 illustrates a schematic block diagram of making calls between a network coordinator, an application, and a hardware accelerator, in accordance with at least one embodiment;

FIG. 14 illustrates a schematic block diagram of calls between a network coordinator, a plurality of applications, and an accelerator running a virtual device, in accordance with at least one embodiment;

FIG. 15A illustrates a process flow diagram for abstractly transferring information between two computing resources in accordance with at least one embodiment;

FIG. 15B illustrates a table of transport abstraction APIs and associated reference counts in accordance with at least one embodiment;

FIG. 16 illustrates an example data center system in accordance with at least one embodiment;

FIG. 17A illustrates an example of an autonomous vehicle in accordance with at least one embodiment;

FIG. 17B illustrates an example of camera position and field of view of the autonomous vehicle in FIG. 17A in accordance with at least one embodiment;

FIG. 17C is a block diagram illustrating an example system architecture of the autonomous vehicle in FIG. 17A in accordance with at least one embodiment;

FIG. 17D is a diagram illustrating a system for communicating between a cloud-based server and the autonomous vehicle in FIG. 17A in accordance with at least one embodiment;

FIG. 18 is a block diagram illustrating a computer system in accordance with at least one embodiment;

FIG. 19 is a block diagram illustrating a computer system in accordance with at least one embodiment;

FIG. 20 illustrates a computer system in accordance with at least one embodiment;

FIG. 21 illustrates a computer system in accordance with at least one embodiment;

FIG. 22A illustrates a computer system in accordance with at least one embodiment;

FIG. 22B illustrates a computer system in accordance with at least one embodiment;

FIG. 22C illustrates a computer system in accordance with at least one embodiment;

FIG. 22D illustrates a computer system in accordance with at least one embodiment;

FIGS. 22E and 22F illustrate a shared programming model in accordance with at least one embodiment;

FIG. 23 illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

24A and 24B illustrate an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

FIGS. 25A and 25B illustrate additional example graphics processor logic in accordance with at least one embodiment;

FIG. 26 illustrates a computer system in accordance with at least one embodiment;

FIG. 27A illustrates a parallel processor in accordance with at least one embodiment;

FIG. 27B illustrates a partition unit in accordance with at least one embodiment;

FIG. 27C illustrates a processing cluster in accordance with at least one embodiment;

FIG. 27D illustrates a graphics multiprocessor in accordance with at least one embodiment;

FIG. 28 illustrates a multiple Graphics Processing Unit (GPU) system in accordance with at least one embodiment;

FIG. 29 illustrates a graphics processor in accordance with at least one embodiment;

FIG. 30 is a block diagram illustrating a processor microarchitecture for a processor in accordance with at least one embodiment;

FIG. 31 illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

FIG. 32 illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

FIG. 33 illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

FIG. 34 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

FIG. 35 is a block diagram of at least a portion of a graphics processor core in accordance with at least one embodiment;

36A and 36B illustrate thread execution logic including an array of processing elements of a graphics processor core;

FIG. 37 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

FIG. 38 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

FIG. 39 illustrates a memory partition unit of a parallel processing unit ("PPU") in accordance with at least one embodiment;

FIG. 40 illustrates a streaming multiprocessor in accordance with at least one embodiment;

fig. 41 illustrates a network for transmitting data within a 5G wireless communication network in accordance with at least one embodiment;

Fig. 42 illustrates a network architecture for a 5G LTE wireless network in accordance with at least one embodiment;

fig. 43 is a diagram illustrating some basic functions of a mobile telecommunications network/system operating in accordance with LTE and 5G principles in accordance with at least one embodiment;

fig. 44 illustrates a radio access network that may be part of a 5G network architecture in accordance with at least one embodiment;

FIG. 45 provides an example illustration of a 5G mobile communication system in which a plurality of different types of devices are used in accordance with at least one embodiment;

FIG. 46 illustrates an example high-level system in accordance with at least one embodiment;

FIG. 47 illustrates an architecture of a network system in accordance with at least one embodiment;

FIG. 48 illustrates example components of a device in accordance with at least one embodiment;

FIG. 49 illustrates an example interface of a baseband circuit in accordance with at least one embodiment;

fig. 50 illustrates an example of an uplink channel in accordance with at least one embodiment;

FIG. 51 illustrates an architecture of a network system in accordance with at least one embodiment;

FIG. 52 illustrates a control plane protocol stack in accordance with at least one embodiment;

FIG. 53 illustrates a user plane protocol stack in accordance with at least one embodiment;

fig. 54 illustrates components of a core network in accordance with at least one embodiment; and

Fig. 55 illustrates components of a system supporting Network Function Virtualization (NFV) in accordance with at least one embodiment.

Detailed Description

Numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. It will be apparent, however, to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details, and that aspects of one or more of the embodiments described herein may be combined.

In at least one embodiment, in an open radio access network ("O-RAN") deployment, one or more central processing units ("CPUs") process functional operations that are part of a distributed unit ("DU") or a central unit ("CU"). In at least one embodiment, in an O-RAN deployment, one or more CPUs may offload operations for computationally intensive algorithms (such as physical layer signal processing, game processing, and video processing) to a hardware accelerator in a lower layer of the O-RAN network protocol stack. In at least one embodiment, the hardware accelerator may be a GPU, a field programmable gate array ("FPGA"), an application specific integrated circuit ("ASIC"), a system on a chip ("SoC"), or another processor (e.g., a Data Processing Unit (DPU), PPU) dedicated to accelerating processing. In at least one embodiment, the hardware accelerators provide performance enhancements to processing operations in the O-RAN because they are designed to accelerate processing. For example, a GPU may perform thousands of operations in parallel, as compared to a CPU that performs operations serially. Although a wireless radio network such as 5G is used herein for illustrative purposes, any one or more aspects of any of the embodiments described herein may be used in any other suitable computer model, architecture, framework, protocol, and/or network.

In at least one embodiment, the 5G-NR service provider uses an O-RAN to provide a range of services. In at least one embodiment, the hardware accelerator may have different capabilities for handling different types of 5G-NR workloads (e.g., for handling workloads in different network slices with different quality of service (QoS) requirements). In at least one embodiment, different hardware accelerators may be used for different purposes. For example, due to the parallel processing architecture, a particular GPU or group of GPUs may inherently be better than a CPU for performing a large machine type communication (mctc) workload associated with a game; as another example, an FPGA or group of FPGAs programmed for low latency workloads may be better than a CPU when executing URLLC workloads to meet QoS requirements due to programming designs for reducing latency in the FPGA or group of FPGAs. Different hardware accelerators may use different communication or transmission protocols.

In at least one embodiment, an application deployed on an O-RAN network may not receive or access information regarding whether a hardware accelerator in a lower layer (e.g., layer 1) supports transport protocols that are also supported by the application. To account for differences in transport protocols used between hardware accelerators and applications, in at least one embodiment, the apparatus, systems, and techniques execute one or more APIs that transfer data between layer 2 ("L2") and layer 1 ("L1") of an O-RAN network protocol stack without requiring any modification to the applications in L2. In at least one embodiment, the one or more APIs may be executed by one or more processors to exchange information between L2 and L1 of an O-RAN network protocol stack, as described below, despite the different transport protocols associated with L2 and L1.

Fig. 1 is a schematic overview block diagram of a network protocol stack 100 in accordance with at least one embodiment. In at least one embodiment, the network protocol stack 100 corresponds to or is used to perform one or more operations of an O-RAN network or other network protocol stack for providing 5G-NR services, in other embodiments the network protocol stack 100 corresponds to providing sixth generation (6G) new radio network services or another wireless communication protocol stack (e.g., any third generation partnership project (3 GPP) wireless communication standard). In at least one embodiment, the network protocol stack 100 is used to support at least the network described in connection with FIG. 47.

Fig. 1 includes a network protocol stack 100, an application 105, a layer 2 ("L2") or higher layer 110 (also referred to as "l2+), a layer 2 to layer 1 interface 115 (also referred to as" L2-L1 interface "), a transport abstraction layer 117, a driver 120, a first processor 125, a second processor 130, and a network interface controller 135. In at least one embodiment, L2 relates to a data link layer of 5G-NR that is responsible for scheduling 5G-NR workload-related functions. In at least one embodiment, layer 1 ("L1") refers to the physical layer of the RAN protocol stack, which may be implemented as an L1 software library running on the first processor 125 (e.g., CPU) and/or the second processor 130 (e.g., acceleration L1 run by FPGA, GPU, ASIC or SoC). In at least one embodiment, a layer refers to an abstraction of hardware that performs the function or operation of a system, network, or computer, e.g., L2 is an abstraction of hardware that performs the data link and scheduling operations of an O-RAN network, while L1 is an abstraction of real-time hardware that performs the physical layer operations of an O-RAN network (e.g., an O-RAN network). For example, a layer corresponds to an Open Systems Interconnection (OSI) model (e.g., L1, L2, L3) exposed by one or more interfaces for the function or operation of responsible (handle) 5G-NR.

In at least one embodiment, the transport abstraction layer 115 of the 5G-NR network protocol stack is located between layer 1 (L1) and layer 2 plus (l2+) and includes one or more Application Programming Interfaces (APIs) and abstracts the transport associated with l2+, such that software and/or hardware associated with L1 may respond to requests from l2+, regardless of which type of transport protocol or type of information transport (e.g., peripheral component interconnect express (PCIe), shared memory, user Datagram Protocol (UDP)) the l2+ is using. In at least one embodiment, abstracting includes mapping a set of functions to corresponding functions included in a plurality of transport protocols. In at least one embodiment, the information transmission types include one or more information transmission types used within a transmission to transfer information between two 5G-NR computing resources. In at least one embodiment, the first and second information transmission types correspond to different messages carried over one transmission, and one or more associated buffer allocations occur with different processes and/or devices, e.g., the first transmission type has a corresponding buffer allocated from a buffer pool in the CPU and the second transmission type has a corresponding buffer allocated in a hardware accelerator (e.g., GPU), where the first information transmission type corresponds to a control plane message and the second information transmission type corresponds to a user plane (e.g., transport block) message. In at least one embodiment, both the first information transmission type and the second information transmission type are control plane messages, user plane data, or some combination thereof, mapped to different transmission types.

In at least one embodiment, the application 105 is a RAN protocol stack program running on a host CPU (e.g., the first processor 125). For example, application 105 relates to software that a service provider of 5G-NR provides eMBB, URLLC, mMTC, and/or V2X, for one or more cells in a 5G-NR network. Although one application 105 is shown in fig. 1, several applications may run on the network protocol stack 100, with each application 105 providing the same or different services.

In at least one embodiment, the L2-L1 interface 115 enables the application 105 to communicate with L1 and the driver 120 in L1 to control the first processor 125, the second processor 130, and the network interface controller 135. In at least one embodiment, the application 105 uses the L2-L1 interface 115 and one or more APIs to determine how many 5G-NR cells an L1 resource (e.g., a hardware accelerator) can support simultaneously, schedule or prioritize workloads handled by the L1 resource, and perform operations to reconfigure or update the L1 resource when traffic conditions change in the 5G-NR network. In at least one embodiment, the L2-L1 interface 115 is an interface such as a 5 th generation function application programming interface (5G FAPI) and/or variations thereof. In at least one embodiment, the L2-L1 interface 115 communicates with an Acceleration Abstraction Layer (AAL) interface.

In at least one embodiment, the network protocol stack 100 includes a transport abstraction layer 117, which is further described herein, including at least in connection with fig. 2-15B. In at least one embodiment, a transport abstraction layer 117 exists between the L2-L1 interface 115 and the drive 120. In at least one embodiment, a transport abstraction layer 117 exists between L2+ and L1. In at least one embodiment, the transport abstraction layer 117 includes one or more transport abstraction APIs and one or more transport abstraction realizers. In at least one embodiment, a transport abstraction layer 117 exists below the driver 120. In at least one embodiment, the L2-L1 interface 115 includes a transport abstraction layer 117. In at least one embodiment, the transport abstraction layer 117 allows a RAN application from one vendor to communicate data to and/or from hardware and/or software components from another vendor, e.g., using the transport abstraction layer 117, without the RAN application having information about which transport configurations the components support, RAN applications in l2+ may communicate with L1 software supporting shared memory-based transport and with another L1 software supporting PCIe interconnect-based transport.

In at least one embodiment, the driver 120 includes a library for operating the first processor 125, the second processor 130, and the network interface controller 135. In at least one embodiment, the driver (also referred to as a device driver) is a computer program that operates, controls, or otherwise provides an interface with the various hardware, such as a hardware accelerator device and a network communication/interface device. In at least one embodiment, the driver 120 includes one or more functions, processes, libraries, interfaces, and/or variants thereof that provide support for the L2-L1 interface 115. In at least one embodiment, the driver 120 is implemented such that the functionality of the L2-L1 interface 115 may be properly handled in conjunction with the first processor 125, the second processor 130, and the network interface controller 135.

In at least one embodiment, the first processor 125 is a processor having one or more circuits for performing operations corresponding to the network protocol stack 100. For example, the first processor 125 is a CPU configured to execute or operate on a DU or CU of the O-RAN. In at least one embodiment, the second processor 130 is a hardware accelerator. The hardware accelerator may be a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a system on a chip (SoC), or other processor dedicated to improving performance processing (e.g., parallel processing units). In at least one embodiment, the first processor 125 (e.g., a CPU running DUs in an O-RAN network) may offload operations for computationally intensive algorithms such as Physical (PHY) layer signal processing, game related processing, video processing, and encryption processing to the second processor 130 (e.g., a hardware accelerator).

In at least one embodiment, network Interface Controller (NIC) 135 is a hardware component that connects one or more computing systems to one or more computing networks. In at least one embodiment, the NIC 135 receives data to be processed by the first processor 125 or the second processor 130 (e.g., a hardware accelerator) and transmits the data processed by the first processor 125 or the second processor 130 to another component (e.g., a base station) in the O-RAN network. In at least one embodiment, the NIC 135 receives data to be processed through one or more functions of an accelerated abstraction layer interface (e.g., a transport abstraction layer interface) and transmits data processed through one or more functions of the accelerated abstraction layer interface. In at least one embodiment, NIC 135 interacts with a Remote Radio Head (RRH), also referred to as a Remote Radio Unit (RRU), as part of providing 5G-NR services. One or more aspects of one or more embodiments described in connection with fig. 1 may be combined with one or more aspects of one or more embodiments described in connection with fig. 2-15B.

Fig. 2 illustrates a transport abstraction framework 200 in accordance with at least one embodiment. In at least one embodiment, transport abstraction framework 200 includes L2+210, L1 212, transport abstraction layer 217, transport abstraction API 219, application process 220, acceleration process 222, transport abstraction API 219, transport abstraction implementation 230, shared memory protocol information 232, data Plane Development Kit (DPDK) framework information 234, and User Datagram Protocol (UDP) socket protocol information 236. In at least one embodiment, the transport abstraction API 219 is a unified set of transport abstraction APIs. In at least one embodiment, each transport abstraction API 219 is associated with a different type of transport protocol supported by 5G-NR computing resources (e.g., hardware accelerators). In at least one embodiment, the transmission involves a method and/or protocol for transmitting data from one computing resource to another. In at least one embodiment, a computing resource may support a transport protocol, and when the computing resource is configured to support the transport protocol, the computing resource is said to have a transport configuration. In at least one embodiment, the transport abstraction framework 200 is used, at least in part, to transport data between disaggregated (aggregated) 5G-NR computing resources. In at least one embodiment, the deaggregated 5G-NR computing resources are physically located in a system, e.g., an application on a computer may be deaggregated with a CPU on the computer because the CPU supports a PCIe card interface that is not supported by the application. In at least one embodiment, the deaggregated 5G-NR computing resources are physically deaggregated by a geographic location. In at least one embodiment, the deaggregated computing resources comprise physically separated computing resources. In at least one embodiment, the deaggregated computing resources include communicatively connected computing resources. In at least one embodiment, the deaggregated computing resources include communicatively separated computing resources unless modified (e.g., incompatible without modification, incapable of interoperable execution without modification). In at least one embodiment, each transport abstraction API 219 is conceptually thought of as mapping to a different type of transport protocol. In at least one embodiment, the transport abstraction framework 200 is conceptually considered as abstracting transport protocol changes based at least in part on the transport abstraction API 219. In at least one embodiment, the transport abstraction framework 200 allows application processes 220 associated with L2+210 to interact with L1 212 and use the transport abstraction API 219 to transport data to L1 212 and from L1 212, regardless of which transport protocol (e.g., PCIe, shared memory, UDP) is supported by L1 212. In at least one embodiment, the transport abstraction framework 200 abstracts the application processes 220 in L2+210 from the various L1 212 transport implementations without any modification to code associated with the application processes 220.

In at least one embodiment, the transport abstraction API 219 includes five APIs-buffer_alloc (), buffer_clone (), buffer_send (), buffer_release (), and buffer_recv (). In at least one embodiment, one or more circuits of the processor execute an API (e.g., buffer_alloc ()) to select a store (e.g., memory) to be used for transferring information between the plurality of 5G-NR computing resources. As used herein, a "buffer" includes one or more buffers. In at least one embodiment, the buffer is a circular buffer, although it may be another type of buffer. In at least one embodiment, the application calls buffer_alloc () and in response, the transport abstraction implementer 230 allocates a buffer requested by the application in a pre-configured buffer pool and sends the buffer to the application to transfer data from the application to the transport abstraction implementer 230. In at least one embodiment, buffer_alloc () initializes a reference counter and sets the reference counter to one (e.g., ref_count=1). In at least one embodiment, a reference counter initialized by buffer_alloc () is used to identify when to deallocate or release an allocated buffer. In at least one embodiment, the application calls buffer_alloc () to allocate a buffer.

In at least one embodiment, one or more circuits of the processor execute an API (e.g., buffer_clone (), buffer_return ()) to prevent deselection of storage selected for transferring information between the plurality of 5G-NR computing resources. In at least one embodiment, the application optionally invokes a buffer_clone () when the application is configured to reserve a buffer instead of having the transport abstraction implementer 230 release the buffer. In at least one embodiment, buffer_clone () increments a reference counter associated with the allocated buffer, e.g., if the reference counter maintains a value of 1 before the buffer_clone () is called, then executing buffer_clone () to increment the reference counter to maintain a value of 2 (e.g., ref_count=2).

In at least one embodiment, one or more circuits of the processor execute an API (e.g., buffer_send ()) to cause data to be stored in a store selected for transferring information between the plurality of 5G-NR computing resources. In at least one embodiment, the application calls buffer_send () after the data is filled into the buffer allocated by buffer_alloc (), and in response, buffer_send () causes the transport abstraction implementer 230 to send the data. In at least one embodiment, buffer_send () causes the transport abstraction implementer to decrement the reference counter by one, e.g., if the transport abstraction implementer 230 decrements the reference counter to zero (e.g., ref_count=0) in response to buffer_send (), the transport abstraction implementer 230 releases the allocated buffer. In at least one embodiment, buffer_send () is implemented as an asynchronous (or non-blocking) or synchronous (or blocking) API, e.g., if buffer_send () is implemented as an asynchronous API or in asynchronous mode, then the application (or application thread) calling (invoking) buffer_send () will not be blocked and wait for an API call (call) to respond; the application thread may then query the state of the buffer_send () API with a query such as buffer_status_query (). In another example, where buffer_send () is implemented as a synchronization API or in a synchronization mode, an application (or application thread) that calls buffer_send () may be blocked unless the transport abstraction implementer provides a callback that acknowledges that the buffer has been successfully sent that does not require the application to call buffer_status_query ().

In at least one embodiment, when an application invokes buffer_release (), a transfer of buffer ownership (or to whom a buffer is assigned) from the application to the transport abstraction implementation occurs. In at least one embodiment, a buffer transferred from an application to a transport abstraction implementation is not immediately freed by the transport abstraction implementation; if the transport abstraction implementer has completed an operation caused by buffer_send (), such as sending the buffer, before the application calls buffer_release (), the transport abstraction implementer will release the buffer; however, if a buffer transfer is still in progress, the transfer implementer will not immediately release the buffer and will release the buffer after the transfer is completed. In at least one embodiment, a separate buffer_release () call abstracted from an application is internal to or from a transport abstraction implementation, where, for example, a reference counter will be adjusted accordingly so that the reference counter will only reach 0 when both the application and the transport abstraction implementation have respectively called buffer_release ().

In at least one embodiment, one or more circuits of the processor execute an API (e.g., buffer_release ()) to deselect storage selected for transferring information between the plurality of 5G-NR computing resources. In at least one embodiment, the application calls buffer_release () to cause the transport abstraction implementer 230 to decrement the reference counter, e.g., if the transport abstraction implementer 230 decrements the reference counter to zero (e.g., ref_count=0) in response to buffer_release (), the transport abstraction implementer 230 releases the allocated buffer.

In at least one embodiment, one or more circuits of the processor execute an API (e.g., buffer recv ()) to obtain data from a store selected for transferring information between the plurality of 5G-NR computing resources. In at least one embodiment, an application calls buffer recv () to cause the transport abstraction implementer 230 to allocate a buffer and fill the buffer with data requested by the application to which the data is to be transferred. In at least one embodiment, when the transport abstraction implementer 230 allocates buffers in response to buffer recv (), the reference counter is set to a value of 1 and does not decrement with buffer recv (). In at least one embodiment, after calling buffer recv () to release the allocated buffer into the buffer pool, the application calls buffer release ().

In at least one embodiment, application processes 220 include processes from applications implemented in L2+210. In at least one embodiment, the application processes 220 include processes related to applications that use RAN architecture due to deaggregated computing resources, such as applications implemented in vehicles for providing driving assistance (e.g., sign detection, obstacle detection, navigation) and requiring wireless access to hardware accelerators and/or databases. In at least one embodiment, acceleration process 222 includes processes executed by hardware and/or software based accelerators. In at least one embodiment, acceleration process 222 includes processes executed by hardware accelerators such as GPUs, FPGAs, and ASICs.

In at least one embodiment, the transport abstraction effectuator 230 is at least partially installed on the 5G-NR computing resources. In at least one embodiment, the transport abstraction realizer 230 is installed at least in part on a hardware accelerator. In at least one embodiment, the transport abstraction effectuator 230 is located in L1 of the 5G-NR network protocol stack. In at least one embodiment, the transport abstraction realizer 230 includes libraries, drivers, mappings between transport protocols, or some combination thereof. In at least one embodiment, the transport abstraction effectuator is at least partially installed on a host CPU in a 5G-NR network. In at least one embodiment, the transmission abstraction effectuator 230 comprises any combination of hardware and/or software required to allow one or more 5G-NR computing resources associated with a first transmission profile to transmit data to and/or from one or more other 5G-NR computing resources associated with a second transmission profile. In at least one embodiment, the transport abstraction implementer 230 is an application.

In at least one embodiment, the transport abstraction implementer 230 (also referred to as a transport abstraction API implementer) includes shared memory protocol information 232, DPDK library 234, and UDP socket protocol information 236. In at least one embodiment, the protocol information includes libraries, drivers, protocols, applications, or some combination thereof. In at least one embodiment, the shared memory library 232 includes drivers, functions, operations, protocols, routines, programs, code, or some combination thereof, that are used, at least in part, to perform data transfers using shared memory. In at least one embodiment, the shared memory is located on a hardware accelerator such as a GPU. In at least one embodiment, DPDK library 234 includes drivers, functions, operations, protocols, routines, programs, code, or some combination thereof for performing transmission implementations based at least in part on the DPDK. In at least one embodiment, the UDP socket protocol information 236 includes drivers, functions, operations, protocols, routines, programs, code, or some combination thereof for performing transport implementations based at least in part on socket calls. In at least one embodiment, when an application invokes the transport abstraction API219, the API is sent to the transport abstraction implementer 230. In at least one embodiment, the transport abstraction implementation 230 includes a mapping or set of associations between one or more transport abstraction APIs 219 and one or more operations related to shared memory protocol information 232, DPDK library 234, UDP socket protocol information 236, or some combination thereof. In at least one embodiment, the transport abstraction implementation 230 causes the hardware and/or software accelerator to perform operations associated with the transport profile at least in part in response to the transport abstraction API219 being invoked by an application using a different transport implementation. One or more aspects of one or more embodiments described in connection with fig. 2 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1 and 3-15B.

Fig. 3 illustrates a schematic block diagram of a flow 300 of data transmission utilizing transmission abstraction in accordance with at least one embodiment. In at least one embodiment, moving from top to bottom in flow 300 indicates the progress of time. The flow 300 and its blocks representing one or more operations are not shown to scale. In at least one embodiment, flow 300 illustrates, at least in part, data transmission using a non-zero replication technique. In at least one embodiment, the non-zero replication technique includes the application 320 replicating data into a newly allocated buffer (e.g., using the memcopy function) instead of using a buffer previously allocated and used by the application. In at least one embodiment, the process 300 shares techniques described herein with respect to at least FIGS. 4-14. In at least one embodiment, flow 300 includes an application 320, a transport abstraction API implementer 330, a buffer_allocation () API 350, and a buffer_send () API 352. In at least one embodiment, the process 300 begins with an application calling a buffer_allocation () API 350. In at least one embodiment, in response to the application 320 invoking the buffer_allocation () API 350, the transport abstraction API implementer 330 allocates a buffer, returns the buffer (e.g., buffer identification (buffer id)), and initializes the reference counter 360, as described herein at least in connection with fig. 2. In at least one embodiment, when the application 320 receives a buffer from the transport abstraction API implementer, the application 320 replicates the data in the buffer 342. In at least one embodiment, the application calls the buffer_send () API 352 to send the data in the copied allocated buffer. In at least one embodiment, in response to application 320 calling buffer_send () API 352, transport abstraction API implementer 330 decrements the reference counter by one and releases the allocated buffer back into buffer pool 362 by transmitting the send data. In at least one embodiment, the application 320 initiates a retransmission 344 with the transport abstraction API implementer 330 by calling the buffer_allocate () API 350, which results in allocating buffers in the pre-created pool, returning the allocated buffers to the application, and incrementing a reference counter 364. In at least one embodiment, in response to receiving a buffer, the application 320 replicates the data in the buffer 346 and invokes the buffer_send () API 352, which causes the transport abstraction API implementer to decrement the reference counter by one and release the allocated buffer back to the buffer pool 366 by transmitting the send data. In at least one embodiment, the flow 300 includes one or more blocks between those shown in fig. 3. One or more aspects of one or more embodiments described in connection with fig. 3 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-2 and fig. 4-15B.

Fig. 4 illustrates a schematic block diagram of a flow 400 of data transmission utilizing transmission abstraction in accordance with at least one embodiment. In at least one embodiment, moving from top to bottom in flow 400 indicates the progress of time. The flow 400 and its blocks are not shown to scale. In at least one embodiment, flow 400 illustrates, at least in part, data transmission using a zero-copy technique. In at least one embodiment, the zero copy technique includes the application 420 reserving a buffer during retransmission instead of using memcopy. In at least one embodiment, the process 400 shares techniques described herein with respect to at least fig. 3 and 5-14. In at least one embodiment, the flow 400 includes an application 420, a transport abstraction API implementer 430, a buffer_allocation () API 450, a buffer_send API 452, a buffer_clone () API 454, and a buffer_release API 458. In at least one embodiment, in response to the application 420 calling the buffer_allocation () API 450, the transport abstraction API implementer 430 allocates a buffer, returns the buffer, and initializes the reference counter 460, as described herein at least in connection with fig. 2. In at least one embodiment, the flow 400 includes a buffer_clone () API 454 that reserves a buffer allocated by the buffer_allocate () API 450, which is described herein at least in connection with fig. 2. In at least one embodiment, a user or a separate application configures the application 420 to implement zero copy techniques, and thus, the application 420 calls the buffer_clone () API 454. In at least one embodiment, the buffer_clone () API eliminates the need to reallocate buffers to supply applications for retransmission. In at least one embodiment, the buffer_clone () API 454 increments a reference counter 462 to prevent the buffer from being deallocated after the application 420 calls the buffer_send () API 452. In at least one embodiment, buffer_clone () increments the reference counter to 2, so the allocated buffer is not deallocated after buffer_send () API 452 decrements the reference counter to 1. In at least one embodiment, the application 420 fills the buffer with data 442 that is copied by the buffer_clone () API 454. In at least one embodiment, the application 420 calls the buffer_send API 452 after the data populating 442, which causes the transport abstraction API implementer 430 to send the data via a transport and decrements the reference counter by one 464. In at least one embodiment, after the transport abstraction API implementer 430 sends data via transport, the application 420 initiates the retransmission 444 by calling the buffer_clone API 454. In at least one embodiment, the buffer_send_api 452 causes the transport abstraction API implementer 430 to send data 468 from buffers previously replicated by the buffer_clone API 454. In at least one embodiment, the application 420 calls the buffer_release API 458 to deallocate or release the buffer 446. In at least one embodiment, the buffer_release API 458 decrements the reference counter by 1 such that the reference counter holds a value of 0 and such that the transport abstraction API implementer 430 returns the buffer to the buffer pool 470. In at least one embodiment, the flow 400 includes one or more blocks between those shown in fig. 4. One or more aspects of one or more embodiments described in connection with fig. 4 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-3 and 5-15B.

Fig. 5 illustrates a schematic block diagram of a flow 500 of data transmission utilizing transmission abstraction in accordance with at least one embodiment. In at least one embodiment, moving from top to bottom in flow 500 indicates the progress of time. The flow 500 and its blocks are not shown to scale. In at least one embodiment, flow 500 illustrates, at least in part, the use of zero copy techniques to transfer data without any automatic buffer release. In at least one embodiment, the zero copy technique includes application 520 reserving a buffer instead of using memcopy during retransmission. In at least one embodiment, the process 500 does not release the buffer unless the application 520 calls the buffer_release API 558. In at least one embodiment, the process 500 shares techniques described herein with respect to at least FIGS. 3-4 and 6-14. In at least one embodiment, flow 500 includes an application 520, a transport abstraction API implementer 530, a buffer_allocation () API 550, a buffer_send API 552, and a buffer_release API 558. In at least one embodiment, in response to the application 420 calling the buffer_allocation () API 550, the transport abstraction API implementer 530 allocates a buffer, returns the buffer, and initializes the reference counter 560, as described herein at least in connection with fig. 2. In at least one embodiment, when the application 520 receives a buffer from the transport abstraction API implementer, the application 520 replicates the data in the buffer 542. In at least one embodiment, the application calls the buffer_send () API 552 to send the data in the copied allocated buffer. In at least one embodiment, in response to application 520 calling buffer_send () API 552, transport abstraction API implementer 530 sends data over transport 562 without decrementing the reference counter, thereby not freeing the allocated buffer back into the buffer pool. In at least one embodiment, the application 520 initiates the retransmission 544 with the transport abstraction API implementer 530 by calling another buffer_send () API 552 without decrementing the reference counter. In at least one embodiment, after the buffer_send () API 552 causes the transport abstraction API implementer 530 to send the data 564 via a transport, the application 520 requests the release buffer 546 by calling the buffer_release () API 558. In at least one embodiment, the buffer_release () API 558 decrements the reference counter by 1 such that the reference counter holds a value of 0 and such that the transport abstraction API implementer 530 returns the buffer to the buffer pool 566. In at least one embodiment, flow 500 includes one or more blocks between those shown in fig. 5. One or more aspects of one or more embodiments described in connection with fig. 5 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-4 and 6-15B.

Fig. 6 illustrates a schematic block diagram of a process 600 for receiving data using a transmission abstraction in accordance with at least one embodiment. In at least one embodiment, flow 600 illustrates, at least in part, data transmission using a non-zero replication technique. In at least one embodiment, moving from top to bottom in flow 600 indicates the progress of time. The flow 600 and its blocks representing one or more operations are not shown to scale. In at least one embodiment, the flow 600 includes an application 620, the application 620 having its own copy of the buffer for reorganization (reassembly). In at least one embodiment, reassembly refers to reassembly of fragmented IP packets, such as when the packet size exceeds the Maximum Transmission Unit (MTU) of the ethernet network. In at least one embodiment, reorganization in the context of shared memory refers to scatter and gather operations, such as operations used when Transport Blocks (TBs) are stored in a discontinuous buffer in memory. In at least one embodiment, the non-zero replication technique includes the application 620 replicating data into a buffer allocated to the application 620 (e.g., using the memcopy function). In at least one embodiment, the process 600 shares techniques described herein with respect to at least FIGS. 3-5 and 7-14. In at least one embodiment, the flow 600 includes an application 620, a transport abstraction API implementer 630, a buffer_allocation () API 650, a buffer_recv () API 656, and a buffer_release API 658. In at least one embodiment, in response to application 620 invoking buffer_allocation () API 650, transport abstraction API implementer 630 allocates buffers, returns the buffers, and initializes reference counter 660, as described herein at least in connection with fig. 2. In at least one embodiment, after the application 620 calls the buffer_allocate () API 650, the application calls the buffer_recv () API 656, which causes the transport abstraction API implementer 630 to receive the data 662 into the allocated buffer and does not increment or decrement the reference counter 660. In at least one embodiment, the application 620 performs a memcopy function on the application's own buffer 640. In at least one embodiment, after the application 620 performs the memcopy operation 640, the application 620 initiates the release 642 of the allocated buffer 641 by calling the buffer_release () API 658, which causes the transport abstraction API implementer 630 to decrement the reference counter by one so that the reference counter holds a value of 0, which returns the allocated buffer to the buffer pool 664. In at least one embodiment, flow 600 includes one or more blocks between those shown in fig. 6. One or more aspects of one or more embodiments described in connection with fig. 6 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-5 and 7-15B.

Fig. 7 illustrates a schematic block diagram of a flow 700 of receiving data using a transmission abstraction in accordance with at least one embodiment. In at least one embodiment, flow 700 illustrates, at least in part, data transmission using a zero-copy technique. In at least one embodiment, moving from top to bottom in flow 700 indicates the progress of time. The flow 700 and its blocks representing one or more operations are not shown to scale. In at least one embodiment, flow 700 includes an application 720 that reserves a buffer for reorganization. In at least one embodiment, the flow 700 shares techniques described herein with respect to at least FIGS. 3-6 and 8-14. In at least one embodiment, the flow 700 includes an application 720, a transport abstraction API implementer 730, a buffer_allocation () API 750, a buffer_recv () API 757, and a buffer_release API 758. In at least one embodiment, in response to application 720 invoking buffer_allocation () API 750, transport abstraction API implementer 730 allocates buffers, returns the buffers, and initializes reference counter 760, as described herein at least in connection with fig. 2. In at least one embodiment, after the application 720 calls the buffer_allocate () API 750, the application calls the buffer_recv () API 756, which causes the transport abstraction API implementer 730 to receive the data into the allocated buffer and does not increment or decrement the reference counter 760. In at least one embodiment, application 720 calls buffer_allocation () API 750, e.g., application 720 receives a buffer allocation. In at least one embodiment, the transport abstraction API implementer 730 returns buffers in response to the buffer_allocation () API 750 function call and the buffers are passed by the application 720 in the subsequent buffer_recv () API 756. In at least one embodiment, the transport abstraction API implementer 730 places the received data in a buffer (if provided) 762, the buffer 762 being passed by the application 720 in a subsequent buffer recv () API 756. In at least one embodiment, the application 720 initiates release 740 of the allocated buffer 741 by calling the buffer_release () API 758, which causes the transport abstraction API implementer 730 to decrement the reference counter by one so that the reference counter holds a value of 0, which returns the allocated buffer to the buffer pool 764. In at least one embodiment, flow 700 includes one or more blocks between those shown in fig. 7. One or more aspects of one or more embodiments described in connection with fig. 7 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-6 and 8-15B.

Fig. 8 illustrates a schematic block diagram of a process 800 for receiving data using a transmission abstraction in accordance with at least one embodiment. In at least one embodiment, flow 800 illustrates, at least in part, data transmission using a non-zero replication technique. In at least one embodiment, moving from top to bottom in flow 800 indicates the progress of time. The flow 800 and its blocks representing one or more operations are not shown to scale. In at least one embodiment, the process 800 includes an application 820, the application 820 having its own copy of the buffer for reorganization. In at least one embodiment, the non-zero replication technique includes the application 820 replicating data into a buffer allocated to the application 820 (e.g., using the memcopy function). In at least one embodiment, the process 800 shares techniques described herein with respect to at least FIGS. 3-7 and 9-14. In at least one embodiment, the flow 800 includes an application 820, a transport abstraction API implementer 830, a buffer recv () API 856, and a buffer release API 858. In at least one embodiment, the application calls the buffer recv () API 856, which causes the transport abstraction API implementer 830 to receive the data into the allocated buffer and increment the reference counter 860. In at least one embodiment, the application 820 performs a memcopy function on the application's own buffer 840. In at least one embodiment, after the application 820 performs the memcopy operation 840, the application 820 initiates the release 842 of the allocated buffer 841 by calling the buffer_release () API 858, which causes the transport abstraction API implementer 830 to decrement the reference counter by one so that the reference counter holds a value of 0, which returns the allocated buffer to the buffer pool 862. In at least one embodiment, the flow 800 includes one or more blocks between those shown in fig. 8. One or more aspects of one or more embodiments described in connection with fig. 8 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-7 and 9-15B.

Fig. 9 illustrates a schematic block diagram of a process 900 for receiving data using a transmission abstraction in accordance with at least one embodiment. In at least one embodiment, flow 900 illustrates, at least in part, data transmission using a zero-copy technique. In at least one embodiment, moving from top to bottom in flow 900 indicates the progress of time. The flow 900 and its blocks representing one or more operations are not shown to scale. In at least one embodiment, the process 900 includes an application 920 that reserves a buffer for reorganization. In at least one embodiment, the process 900 shares techniques described herein with respect to at least FIGS. 3-8 and 10-14. In at least one embodiment, the flow 900 includes an application 920, a transport abstraction API implementer 930, a buffer recv () API 956, and a buffer release API 958. In at least one embodiment, the application calls a buffer recv () API 956 that causes the transport abstraction API implementer 930 to receive data into the allocated buffer and increment the reference counter 960. In at least one embodiment, the application 920 initiates release 940 of the allocated buffer 941 by calling a buffer_release () API 958, which causes the transport abstraction API implementer 930 to decrement the reference counter by one so that the reference counter holds a value of 0, which returns the allocated buffer to the buffer pool 962. In at least one embodiment, flow 900 includes one or more blocks between those shown in fig. 9. One or more aspects of one or more embodiments described in connection with fig. 9 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-8 and 10-15B.

Fig. 10 illustrates a schematic block diagram 1000 representing mapping of a transport abstraction API to a transport profile in accordance with at least one embodiment. In at least one embodiment, the process 1000 includes an application 1020, a transport abstraction API implementer 1030, and transport configuration PCIe using a DPDK 1070. In at least one embodiment, block diagram 1000 includes a buffer_allocation () API 1050, a buffer_send () API 1052, a buffer_recv () API 1056, and a buffer_release () API 1058. In at least one embodiment, block diagram 1000 includes PCIe operations mbuff alloy 1072, enqueue, and tx_burst1074, mbuff free 1076, and dequeue and rx_burst1078. In at least one embodiment, during transport, for example, when the application 1020 calls a transport abstraction API, the transport abstraction API implementer 1030 maps the buffer_allocation () API 1050 to mbuff allocation 1072, the buffer_send () API 1052 to enqueue and tx_burst1074, and the buffer_release () API 1058 to mbuff free 1076. In at least one embodiment, during reception, e.g., when a buffer is received from the application 1020, the buffer_allocation () API 1050 maps to mbuff allocation 1072, the buffer_recv () API 1056 maps to dequeue and rx_burst1078, and the buffer_release () API 1058 maps to mbuff free 1076.

In at least one embodiment, as shown in flow 1000, the application 1020 calls a transport abstraction API buffer_allocation (), buffer_send (), buffer_release (), and buffer_recv () during transmit and receive operations. In at least one embodiment, the application 1020 is in L2+ and invokes a transport abstraction API without the information or knowledge of the transport profile associated with L1. In at least one embodiment, when the application 1020 calls a transport abstraction API, the transport abstraction API implementer 1030 calls a corresponding function from the library associated with the transport profile, e.g., when the application calls the buffer_alloc () API 1050, the transport abstraction API implementer 1030 calls a function mbuff alloc from the DPDK library, which corresponds to the buffer_alloc () API 1050. One or more aspects of one or more embodiments described in connection with fig. 10 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-9 and 11-15B.

FIG. 11 illustrates a schematic block diagram 1100 representing mapping of a transport abstraction API to a transport profile in accordance with at least one embodiment. In at least one embodiment, the flow 1100 includes an application 1120, a transport abstraction API implementer 1130, and a transport configuration using a shared memory 1170. In at least one embodiment, the block diagram 1100 includes a buffer_allocation () API 1150, a buffer_send () API1152, a buffer_recv () API 1156, and a buffer_release () API 1158. In at least one embodiment, block diagram 1100 includes shared memory operations to allocate memory 1172 in a pool, enqueue 1174 a buffer, release memory into the pool 1176, and dequeue 1178 a buffer. In at least one embodiment, during transport, for example, when a buffer is sent from application 1120, transport abstraction API implementer 1130 maps buffer_allocation () API 1050 to memory 1172 in the allocation pool, buffer_send () API1152 to enqueue 1174 the buffer, and buffer_release () API 1158 to release memory into pool 1176. In at least one embodiment, during reception, e.g., when a buffer is received from application 1120, buffer_allocation () API 1150 maps to memory 1172 in the allocation pool, buffer_recv () API1152 maps to dequeue 1178 the buffer, and buffer_release () API 1158 maps to release memory into pool 1176. One or more aspects of one or more embodiments described in connection with fig. 11 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-10 and 12-15B.

FIG. 12 illustrates a schematic block diagram 1200 representing mapping of a transport abstraction API to a transport profile in accordance with at least one embodiment. In at least one embodiment, the flow 1200 includes an application 1220, a transport abstraction API implementer 1230, and a transport configuration using a shared memory 1270. In at least one embodiment, block diagram 1200 includes a buffer_allocation () API 1250, a buffer_send () API 1252, a buffer_recv () API 1256, and a buffer_release () API 1258. In at least one embodiment, block diagram 1200 includes shared memory operations to allocate memory 1272 in a pool, enqueue 1274 buffers, release memory 1276 into a pool, and dequeue 1278 buffers. In at least one embodiment, during a transfer, for example, when a buffer is sent from the application 1220, the buffer_allocation () API 1050 maps to memory 1272 in the allocation pool, the buffer_send () API 1252 maps to socket send 1274, and the buffer_release () API 1258 maps to release memory into the pool 1276. In at least one embodiment, during reception, e.g., when a buffer is received from the application 1220, the buffer_allocation () API 1250 maps to memory 1272 in the allocation pool, the buffer_recv () API 1256 maps to socket reception 1278, and the buffer_release () API 1258 maps to release memory into the pool 1276. One or more aspects of one or more embodiments described in connection with fig. 12 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-11 and 13-15B.

FIG. 13 illustrates a call flow diagram 1300 of making a call between a network coordinator 1380, a hardware accelerator 1390, and an application 1320 in accordance with at least one embodiment. In at least one embodiment, network coordinator 1380 comprises any computing component, device, and/or system that manages the flow of information within a 5G-NR network. In at least one embodiment, the network coordinator is referred to as a service management and coordination (SMO) platform. In at least one embodiment, the network coordinator 1380 manages the flow of information between the layers of the 5G-NR network protocol stack. In at least one embodiment, hardware accelerator 1390 comprises any computing component, device, and/or system that performs functions for processing and/or transmitting information within a 5G-NR network. In at least one embodiment, the hardware accelerator 1390 comprises one or more device drivers 1392, one or more libraries 1394, one or more hardware acceleration managers 1396, or some combination thereof. In at least one embodiment, the diagram 1300 begins with the network coordinator 1380 querying the capabilities (capabilities) 1340 of the hardware accelerator, including which transmission profiles the hardware accelerator supports. In at least one embodiment, the hardware accelerator 1390 returns 1342 information associated with its capabilities, including supported transmission profiles, to the network coordinator 1380. In at least one embodiment, the network coordinator 1380 configures 1344 the hardware accelerator 1390 with a transport-specific configuration of supported transport profile types. In at least one embodiment, the hardware accelerator 1390 sends an acknowledgement 1346 to the network coordinator 1380 that the hardware accelerator 1390 has been configured with a transport-specific configuration of supported transport profile types. In at least one embodiment, if the hardware accelerator 1390 supports more than one transmission profile, the network coordinator 1380 selects which transmission profile the hardware accelerator should be configured with. In at least one embodiment, if hardware accelerator 1390 supports instantiation of more than one virtual hardware device (also referred to as a virtual device or virtual machine) from one physical hardware accelerator, different virtual devices may be configured with different transmission profiles.

In at least one embodiment, upon receiving an acknowledgement of the transmission configuration, the network coordinator 1380 deploys the application 1348 with a hardware accelerator configured with a transmission profile (e.g., a file containing transmission configuration parameters) compatible with the application 1302. In at least one embodiment, the application 1320 does not know what resources (including transmission configuration) are available to the hardware accelerator 1390. In at least one embodiment, the application calls a transport abstraction API to send data to and/or receive data from the hardware accelerator through an abstracted transport layer, which is further described herein in connection with FIG. 2. In at least one embodiment, the application 1320 calls a buffer_alloc () API 1350. In at least one embodiment, calling the buffer_alloc () API1350 causes the operation to be performed as follows: pool_id 1351a (memory pool identification information) is returned, as well as ref_count 1351b is incremented, including at least as further described herein in connection with fig. 2. In at least one embodiment, the application 1320 calls a buffer_send () API 1352, which causes operations to be performed as follows: the data 1353a is sent and an Acknowledgement (ACK) 1353b is sent from the hardware accelerator 1390 to the application 1320 that the data was sent. In at least one embodiment, the application 1320 calls the buffer_release () API 1358, which causes the operation to be performed as follows: decrementing the reference counter 1358a and freeing the buffer back to the buffer pool 1358b. One or more aspects of one or more embodiments described in connection with fig. 13 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-12 and 14-15B.

FIG. 14 illustrates a call flow diagram 1400 for making calls between a network coordinator, an application, and an accelerator in accordance with at least one embodiment. In at least one embodiment, diagram 1400 includes a network coordinator 1480, a hardware accelerator 1490 running a virtual device 1498, and an application 1420 for use in a decoupled network that includes a virtual device. In at least one embodiment, the graph 1400 begins with the network coordinator querying 1440 the capabilities of the hardware accelerator 1490, including what transmission profiles the hardware accelerator 1490 supports and how many virtual devices the hardware accelerator 1490 is capable of instantiating. In at least one embodiment, the hardware accelerator 1490 includes a device driver 1492 and a library 1494. In at least one embodiment, the hardware accelerator 1490 returns 1442 its capabilities, including the supported transmission profile and the number of instantiating virtual devices, to the network coordinator 1480. In at least one embodiment, the network coordinator 1480 sets 1444N virtual devices, where N < = N, with a configuration of M transmission profiles, where M < = M. In at least one embodiment, the network coordinator 1480 configures 1446 each virtual device with a transmission profile (e.g., TF1, TF2, …, TFn), which may include one or more types of transmission profiles. In at least one embodiment, if the hardware accelerator 1490 supports more than one transport profile, the network coordinator 1480 selects how to configure each virtual device with its transport profile, e.g., the network coordinator 1480 may select to configure each virtual device with a particular transport profile based on subsequent application deployments.

In at least one embodiment, upon receiving acknowledgement 1448 of the transport configuration of each virtual device, the network coordinator 1480 deploys 1448 multiple applications with the transport-configured virtual devices, e.g., application 1 1420a deploys with virtual device 1 1498a configured with transport profile 1 (TF 1). In at least one embodiment, the applications 1420 include one or more types of applications, e.g., applications include only L2+ applications, or in another example, applications include a combination of Distributed Units (DUs), central Units (CUs), and RAN Intelligent Controller (RIC) applications, each with a different accelerated workload. In at least one embodiment, each of the applications 1420 independently invokes the transport abstraction API 1449 to send and/or receive data to and/or from applications assigned to the virtual devices through the abstracted transport layer. In at least one embodiment, the transport abstraction API is mapped to different transport profiles on the hardware accelerator running the virtual device. One or more aspects of one or more embodiments described in connection with fig. 14 may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-13 and 15A-15B.

Fig. 15A illustrates a process 1500 for abstractly transferring information between two 5G-NR computing resources in accordance with at least one embodiment. In at least one embodiment, process 1500 begins with a 5G-NR computing resource calling API during operation 1310. In at least one embodiment, the 5G-NR computing resource in operation 1510 uses one or more specific transmission configurations. In at least one embodiment, the API in operation 1510 comprises a transport abstraction API further described herein in connection with at least FIGS. 1-14 and 15B. In at least one embodiment, the APIs in operation 1510 include buffer_alloc (), buffer_clone (), buffer_send (), buffer_recv (), and buffer_release (). In at least one embodiment, the 5G-NR computing resource may comprise an L2+ application.

In at least one embodiment, after calling the API with operation 1510, process 1500 includes computing resource abstraction (abstrack) information from the 5G-NR during operation 1515. In at least one embodiment, the abstract information includes a process of mapping operations from one transport configuration to another operation from another transport configuration during operation 1515. In at least one embodiment, abstracting the information during operation 1515 includes identifying what operations related to a particular transport configuration should be performed based on transport abstraction API calls made by the application, which is discussed further herein in connection with at least fig. 1-14 and 15B.

In at least one embodiment, using the abstract information from operation 1515, process 1500 continues by causing operations on another 5G-NR computing resource to be performed during operation 1520. In at least one embodiment, another 5G-NR computing resource in operation 1520 uses one or more particular transmission configurations that are different from the transmission configuration used by the 5G-NR computing resource in operation 1510. In at least one embodiment, various aspects of operation 1520 are further described herein in connection with at least fig. 1-14 and 15B. One or more aspects of one or more embodiments described in connection with fig. 15A may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-14 and 15B.

FIG. 15B illustrates a table 1550 that associates transport abstraction APIs with reference counts in accordance with at least one embodiment. In at least one embodiment, table 1550 illustrates an example of one or more transport abstraction APIs (as discussed herein at least in connection with fig. 2) that may be embedded in a preceding or subsequent (following) API along with additional input parameters, e.g., rather than having a dedicated buffer_clone () API to inform the buffer ownership reservation buffer_clone () by an application, or the like, embedded in a preceding (e.g., buffer_alloy ()) and/or subsequent (e.g., buffer_send ()) API with additional input parameters (indications). In at least one embodiment, the ref_count increment and/or decrement operations on the implementation side may be different (rather than always +1 or-1) due to the APIs embedded in the preceding or subsequent APIs along with additional indications. In at least one embodiment, table 1550 interprets ref_count changes via an example including an explicit buffer_clone () API call for buffer reservation (option 1), an example including an implicit indication of buffer reservation in buffer_alloc () (option 2 a), and an example including an implicit indication of buffer reservation in buffer_send () (option 2 b). In at least one embodiment, options 2a and 2b include a buffer_return () API embedded in the corresponding API. One or more aspects of one or more embodiments described in connection with fig. 15B may be combined with one or more aspects of one or more embodiments described in connection with fig. 1-15A.

Data center

FIG. 16 illustrates an example data center 1600 in which at least one embodiment can be employed. In at least one embodiment, the data center 1600 includes a data center infrastructure layer 1610, a framework layer 1620, a software layer 1630, and an application layer 1640.

In at least one embodiment, as shown in fig. 16, the data center infrastructure layer 1610 can include a resource coordinator 1612, grouped computing resources 1614, and node computing resources ("node c.r.") 1616 (1) -1616 (N), where "N" represents any integer, positive integer. In at least one embodiment, the nodes c.r.1616 (1) -1616 (N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field Programmable Gate Arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read only memory), storage devices (e.g., solid state drives or disk drives), network input/output ("NW I/O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the nodes c.r.1616 (1) -1616 (N) may be a server having one or more of the above-described computing resources.

In at least one embodiment, the grouped computing resources 1614 may include individual groupings of nodes c.r. housed within one or more racks (not shown), or a number of racks (also not shown) housed within a data center at various geographic locations. In at least one embodiment, individual packets of node c.r. within the grouped computing resources 1614 may include computing, network, memory, or storage resources of the packets that may be configured or allocated to support one or more workloads. In at least one embodiment, several nodes c.r. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

In at least one embodiment, the resource coordinator 1612 may configure or otherwise control one or more nodes c.r.1616 (1) -1616 (N) and/or grouped computing resources 1614. In at least one embodiment, the resource coordinator 1612 may include a software design infrastructure ("SDI") management entity for the data center 1600. In at least one embodiment, the resource coordinator may include hardware, software, or some combination thereof.

In at least one embodiment, as shown in FIG. 16, the framework layer 1620 includes a job scheduler 1632, a configuration manager 1634, a resource manager 1636, and a distributed file system 1638. In at least one embodiment, the framework layer 1620 may include a framework of one or more applications 1642 supporting software 1632 of the software layer 1630 and/or the application layer 1640. In at least one embodiment, software 1632 or application 1642 may include Web-based services software or applications, such as those provided by Amazon Web Services, google Cloud, and Microsoft Azure, respectively. In at least one embodiment, the framework layer 1620 may be, but is not limited to, a free and open source software web application framework such as Apache Spark that may utilize a distributed file system 1638 for extensive data processing (e.g., "big data") ^TM (hereinafter referred to as "Spark"). In at least one embodiment, job scheduler 1632 may include a Spark driver to facilitate scheduling of the workloads supported by the various layers of data center 1600. In at least one embodiment, the configuration manager 1634 may be capable of configuring different layers, such as a software layer 1630 and a framework layer 1620 including Spark and a distributed file system 1638 for supporting large-scale data processing. In at least one embodiment, resource manager 1636 is capable of managing mappings to Or to allocate cluster or group computing resources for supporting the distributed file system 1638 and job scheduler 1632. In at least one embodiment, the cluster or group computing resources can include group computing resources 1614 on the data center infrastructure layer 1610. In at least one embodiment, the resource manager 1636 can coordinate with the resource coordinator 1612 to manage these mapped or allocated computing resources.

In at least one embodiment, the software 1632 included in the software layer 1630 can include software used by at least a portion of the nodes c.r.1616 (1) -1616 (N), the grouped computing resources 1614, and/or the distributed file system 1638 of the framework layer 1620. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

In at least one embodiment, the one or more applications 1642 included in the application layer 1640 may include one or more types of applications used by at least a portion of nodes c.r.1616 (1) -1616 (N), the packet computing resources 1614, and/or the distributed file system 1638 of the framework layer 1620. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or reasoning software, machine learning framework software (e.g., pyTorch, tensorFlow, caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

In at least one embodiment, any of configuration manager 1634, resource manager 1636, and resource coordinator 1612 may implement any number and type of self-modifying actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modifying action may mitigate a data center operator of the data center 1600 from making potentially bad configuration decisions and may avoid underutilized and/or poorly performing portions of the data center.

In at least one embodiment, the data center 1600 may include tools, services, software, or other resources to train or use one or more machine learning models to predict or infer information in accordance with one or more embodiments described herein. For example, in at least one embodiment, the machine learning model may be trained from the neural network architecture by calculating weight parameters using the software and computing resources described above with respect to the data center 1600. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, information may be inferred or predicted using the resources described above and with respect to the data center 1600 using a trained machine learning model corresponding to one or more neural networks.

In at least one embodiment, the data center 1600 can use CPU, application Specific Integrated Circuit (ASIC), GPU, FPGA, or other hardware to perform training and/or reasoning using the above resources. Furthermore, one or more of the software and/or hardware resources described above may be configured as a service to allow a user to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services. In at least one embodiment, the data center 1600 includes one or more CPU, ASIC, GPU, FPGA, system on a chip (SoC) or other hardware, circuitry, or integrated circuit components including, for example, an amplifier (upscaler) or upsampler to amplify (upscale) an image, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit configured to perform an amplifier to amplify an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels; the data center 1600 may use the components described in this disclosure to perform methods, operations, or instructions to generate or modify images. In at least one embodiment, at least one component shown or described with respect to fig. 16 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

The autonomous vehicle may be described in terms of an automation level defined by the national highway traffic safety administration ("NHTSA") and society of automotive engineers ("SAE") "related to a driving automation system for road motor vehicles (e.g., standard number J3016-20160806 published on 15 th 6 th 2018, standard number J3016-201609 published on 30 th 2016, and previous and future versions of this version of this standard). In one or more embodiments, vehicle 1700 may be capable of functioning in accordance with one or more of level 1-level 5 of the autopilot level. For example, in at least one embodiment, vehicle 1700 may be capable of conditional automation (level 3), high automation (level 4), and/or full automation (level 5), according to an embodiment.

In at least one embodiment, vehicle 1700 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1700 may include, but is not limited to, a propulsion system 1750, such as an internal combustion engine, a hybrid device, an all-electric engine, and/or another propulsion system type. In at least one embodiment, propulsion system 1750 may be connected to a driveline of vehicle 1700, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1700. In at least one embodiment, the propulsion system 1750 may be controlled in response to receiving a signal from the throttle/accelerator 1752.

In at least one embodiment, a steering system 1754 (which may include, but is not limited to, a steering wheel) is used to steer (e.g., along a desired path or route) the vehicle 1700 when the propulsion system 1750 is running (e.g., when the vehicle 1700 is traveling). In at least one embodiment, the steering system 1754 can receive signals from the steering actuators 1756. In at least one embodiment, the steering wheel may be optional for a fully automated (level 5) function. In at least one embodiment, the brake sensor system 1746 can be used to operate vehicle brakes in response to signals received from the brake actuators 1748 and/or brake sensors.

In at least one embodiment, controller 1736 may include, but is not limited to, one or more systems on a chip ("SoC") (not shown in fig. 17A) and/or a graphics processing unit ("GPU") providing signals (e.g., representing commands) to one or more components and/or systems of vehicle 1700. For example, in at least one embodiment, the controller 1736 may send a signal to operate vehicle braking via the brake actuator 1748, the steering system 1754 via one or more steering actuators 1756, and the propulsion system 1750 via one or more throttle/accelerator 1752. In at least one embodiment, the one or more controllers 1736 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process the sensor signals and output operational commands (e.g., signals representing commands) to enable autopilot and/or assist a driver in driving the vehicle 1700. In at least one embodiment, the one or more controllers 1736 can include a first controller 1736 for an autopilot function, a second controller 1736 for a functional safety function, a third controller 1736 for an artificial intelligence function (e.g., computer vision), a fourth controller 1736 for an infotainment function, a fifth controller 1736 for redundancy in an emergency, and/or other controllers. In at least one embodiment, a single controller 1736 may handle two or more of the above-described functions, and two or more controllers 1736 may handle a single function and/or any combination thereof.

In at least one embodiment, one or more controllers 1736 provide signals for controlling one or more components and/or systems of vehicle 1700 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from sensors of a sensor type such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1758 (e.g., one or more global positioning system ("gps") sensors), one or more RADAR sensors 1760, one or more ultrasonic sensors 1772, one or more LIDAR sensors 1764, one or more Inertial Measurement Unit (IMU) sensors 1766 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1796, one or more stereo cameras 1768, one or more cameras 1770 (e.g., fish eye cameras), one or more infrared cameras 1772, one or more surround cameras 1774 (e.g., 360 degrees), one or more cameras (e.g., remote cameras 17A), one or more cameras (e.g., one or more cameras 1746 a shown in a remote view), one or more sensors for measuring speed, one or more vehicle speed, 1740, or more sensors (e.g., one or more brake systems 1746), and/or more other types of sensors 1746.

In at least one embodiment, one or more controllers 1736 may receive input (e.g., represented by input data) from a dashboard 1732 of the vehicle 1700 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1734, acoustic annunciators, speakers, and/or other components of the vehicle 1700. In at least one embodiment, the output can include information such as vehicle speed, time, map data (e.g., a high definition map (not shown in FIG. 17A), location data (e.g., a location of the vehicle 1700, e.g., on a map), directions, locations of other vehicles (e.g., occupancy gratings), information regarding objects, and status of the objects perceived by the one or more controllers 1736, etc. for example, in at least one embodiment, the HMI display 1734 can display information regarding the presence of one or more objects (e.g., a guideboard, warning sign, traffic light change, etc.) and/or information regarding driving operation that the vehicle has, is, or is about to be made (e.g., now changing lanes, driving out 34B in two miles, etc.).

In at least one embodiment, vehicle 1700 further includes a network interface 1724 that can communicate over one or more networks using one or more wireless antennas 1726 and/or one or more modems. For example, in at least one embodiment, the network interface 1724 may be capable of communicating over long term evolution ("LTE"), wideband code division multiple access ("WCDMA"), universal mobile telecommunications system ("UMTS"), global system for mobile communications ("GSM"), IMT-CDMA multi-carrier ("CDMA 2000") networks, and the like. In at least one embodiment, the one or more wireless antennas 1726 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., bluetooth, bluetooth Low Energy (LE), Z-Wave, zigBee, etc.) and/or one or more low power wide area networks (hereinafter "LPWANs") (e.g., loRaWAN, sigFox, etc. protocols). In at least one embodiment, the vehicle 1700 further includes one or more CPU, ASIC, GPU, FPGA, system on a chip (SoC) or other hardware, circuitry, or integrated circuit components including, for example, an amplifier or upsampler to amplify an image, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit configured to perform an amplifier to amplify an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels. In at least one embodiment, at least one component shown or described with respect to fig. 17A is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 17B illustrates an example of camera position and field of view of the autonomous vehicle 1700 of fig. 17A in accordance with at least one embodiment. In at least one embodiment, the camera and respective field of view are one example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and/or alternative cameras may be included and/or the cameras may be located at different locations on the vehicle 1700.

In at least one embodiment, the type of camera used for the camera may include, but is not limited to, a digital camera that may be suitable for use with the components and/or systems of the vehicle 1700. In at least one embodiment, one or more cameras may operate at an automotive safety integrity level ("ASIL") B and/or other ASIL. In at least one embodiment, according to an embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220fps, 240fps, etc. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent ("RCCC") color filter array, a red transparent blue ("RCCB") color filter array, a red blue green transparent ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and/or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an RCCC, RCCB, and/or RBGC color filter array, may be used in an effort to increase photosensitivity.

In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional mono camera may be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, in order to cut out stray light and reflections from light within the vehicle 1700 (e.g., reflections of an instrument panel reflect light in a windshield), which may interfere with the image data capturing capabilities of the camera. With respect to the rearview mirror mount assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom such that the camera mount plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for a side view camera, one or more cameras may also be integrated within four posts at each corner of the cabin.

In at least one embodiment, a camera (e.g., a forward facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1700 may be used to look around and aid in identifying forward paths and obstacles with the aid of one or more controllers 1736 and/or control socs, thereby providing information critical to generating an occupancy grid and/or determining a preferred vehicle path. In at least one embodiment, the forward facing camera may be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward facing camera may also be used for ADAS functions and systems, including, but not limited to, lane departure warning ("LDW"), automatic cruise control ("ACC"), and/or other functions (e.g., traffic sign recognition).

In at least one embodiment, various cameras may be used in a forward configuration, including, for example, a monocular camera platform including a CMOS ("complementary metal oxide semiconductor") color imager. In at least one embodiment, the wide angle camera 1770 can be used to perceive objects (e.g., pedestrians, road crossing, or bicycles) entering from the periphery. Although only one wide-angle camera 1770 is shown in fig. 17B, in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1700. In at least one embodiment, any number of remote cameras 1798 (e.g., remote stereo camera pairs) may be used for depth-based object detection, particularly for objects that have not yet trained a neural network. In at least one embodiment, the remote camera 1798 can also be used for object detection and classification as well as basic object tracking.

In at least one embodiment, any number of stereo cameras 1768 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1768 may include an integrated control unit including a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a single on-chip integrated controller area network ("CAN") or ethernet interface. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1700, including distance estimates for all points in the image. In at least one embodiment, the one or more stereo cameras 1768 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one each on the left and right) and one image processing chip, which may measure the distance from the vehicle 1700 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1768 may be used in addition to those described herein.

In at least one embodiment, a camera (e.g., a side view camera) having a field of view that includes a portion of the environment to the side of the vehicle 1700 may be used for a surround view to provide information for creating and updating occupancy grids, as well as generating side impact warnings. For example, in at least one embodiment, a surround camera 1774 (e.g., four surround cameras 1774 as shown in fig. 17B) may be positioned on the vehicle 1700. In at least one embodiment, the one or more surround cameras 1774 may include, but are not limited to, any number and combination of wide angle cameras 1770, one or more fish-eye lenses, one or more 360 degree cameras, and/or the like. For example, in at least one embodiment, four fish-eye lens cameras may be located in front, rear, and sides of the vehicle 1700. In at least one embodiment, the vehicle 1700 may use three surround cameras 1774 (e.g., left, right, and rear), and may utilize one or more other cameras (e.g., forward facing cameras) as a fourth look-around camera.

In at least one embodiment, a camera (e.g., a rearview camera) having a field of view that includes a portion of the environment behind the vehicle 1700 may be used for parking assistance, looking around, rear collision warning, and creating and updating occupancy gratings. In at least one embodiment, a wide variety of cameras may be used, including but not limited to cameras that are also suitable as one or more forward facing cameras (e.g., remote camera 1798 and/or one or more mid-range cameras 1776, one or more stereo cameras 1768, one or more infrared cameras 1772, etc.), as described herein. In at least one embodiment, at least one component shown or described with respect to fig. 17B is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 17C illustrates a block diagram of an example system architecture of the autonomous vehicle 1700 of fig. 17A in accordance with at least one embodiment. In at least one embodiment, each of the one or more components, one or more features, and one or more systems of the vehicle 1700 in fig. 17C are shown connected via the bus 1702. In at least one embodiment, the bus 1702 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, the CAN may be a network internal to the vehicle 1700 for helping to control various features and functions of the vehicle 1700, such as brake actuation, acceleration, braking, steering, windshield wipers, and the like. In one embodiment, the bus 1702 may be configured with tens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, the bus 1702 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and/or other vehicle status indicators. In at least one embodiment, bus 1702 may be a CAN bus compliant with ASIL B.

In at least one embodiment, flexRay and/or Ethernet (Ethernet) may be used in addition to or from CAN. In at least one embodiment, there may be any number of buses 1702, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more ethernet buses, and/or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1702 may be used to perform different functions and/or may be used for redundancy. For example, the first bus 1702 may be used for collision avoidance functions, and the second bus 1702 may be used for actuation control. In at least one embodiment, each bus 1702 may communicate with any component of the vehicle 1700, and two or more buses 1702 may communicate with the same component. In at least one embodiment, each of any number of system on a chip ("SoC") 1704, each of the one or more controllers 1736, and/or each computer within the vehicle, CAN access the same input data (e.g., input from sensors of the vehicle 1700), and CAN be connected to a common bus, such as a CAN bus.

In at least one embodiment, the vehicle 1700 may include one or more controllers 1736, such as those described herein with respect to fig. 17A. In at least one embodiment, the controller 1736 may be used for a variety of functions. In at least one embodiment, the controller 1736 may be coupled to any of a variety of other components and systems of the vehicle 1700 and may be used to control the vehicle 1700, the artificial intelligence of the vehicle 1700, the infotainment of the vehicle 1700, and/or other functions.

In at least one embodiment, the vehicle 1700 may include any number of socs 1704. In at least one embodiment, each of the socs 1704 may include, but is not limited to, a central processing unit ("one or more CPUs") 1706, a graphics processing unit ("one or more GPUs") 1708, one or more processors 1710, one or more caches 1712, one or more accelerators 1714, one or more data stores 1716, and/or other components and features not shown. In at least one embodiment, one or more socs 1704 may be used to control vehicle 1700 in various platforms and systems. For example, in at least one embodiment, one or more socs 1704 may be combined with a high definition ("HD") map 1722 in a system (e.g., of vehicle 1700), which high definition map 1722 may obtain map refreshes and/or updates from one or more servers (not shown in fig. 17C) via network interface 1724.

In at least one embodiment, the one or more CPUs 1706 may include a CPU cluster or CPU complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, the one or more CPUs 1706 may include multiple cores and/or level two ("L2") caches. For example, in at least one embodiment, one or more CPUs 1706 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, the one or more CPUs 1706 may include four dual core clusters, with each cluster having a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1706 (e.g., CCPLEX) may be configured to support simultaneous cluster operation such that any combination of clusters of one or more CPUs 1706 may be active at any given time.

In at least one embodiment, one or more CPUs 1706 may implement power management functions including, but not limited to, one or more of the following features: when idle, each hardware module can be automatically clock-gated to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution wait interrupt ("WFI")/event wait ("WFE") instructions; each core can be independently powered; when all cores are clock-or power-gated, each core cluster may be independently clock-gated; and/or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 1706 may further implement an enhanced algorithm for managing power states, in which allowed power states and expected wake-up times are specified, and hardware/microcode determines the optimal power state for core, cluster, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified sequence of power state inputs in software, where work is shared among microcode.

In at least one embodiment, the one or more GPUs 1708 may comprise an integrated GPU (herein or referred to as an "iGPU"). In at least one embodiment, one or more GPUs 1708 may be programmable and may be active for parallel workloads. In at least one embodiment, one or more GPUs 1708 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 1708 may comprise one or more streaming microprocessors, wherein each streaming microprocessor may comprise a level one ("L1") cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, the one or more GPUs 1708 may comprise at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1708 may use a computing Application Programming Interface (API). In at least one embodiment, one or more GPUs 1708 may use one or more parallel computing platforms and/or programming models (e.g., CUDA model of NVIDIA).

In at least one embodiment, one or more GPUs 1708 may be power optimized for best performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1708 may be fabricated on fin field effect transistor ("FinFET") circuits. In at least one embodiment, each streaming microprocessor may contain multiple hybrid precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two hybrid precision NVIDIA tensor cores for deep learning matrix arithmetic, a zero level ("L0") instruction cache, a thread bundle scheduler, a dispatch unit, and/or a 64KB register file. In at least one embodiment, the streaming microprocessor may include separate parallel integer and floating point data paths to provide efficient execution of the workload mixed with computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer granularity synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

In at least one embodiment, one or more GPUs 1708 may include high bandwidth memory ("HBM") and/or 16GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of about 900 GB/sec. In at least one embodiment, a synchronous graphics random access memory ("SGRAM"), such as a graphics double data rate type five synchronous random access memory ("GDDR 5"), may be used in addition to or in place of HBM memory.

In at least one embodiment, one or more of the GPUs 1708 may comprise unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow one or more GPUs 1708 to directly access one or more CPU1706 page tables. In at least one embodiment, when one memory management unit ("MMU") of a GPU of the one or more GPUs 1708 experiences a miss, an address translation request may be sent to the one or more CPUs 1706. In response, in at least one embodiment, the one or more CPUs 1706 may look up a virtual-to-physical mapping of the address in their page tables and transmit the translation back to the one or more GPUs 1708. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory for both the one or more CPUs 1706 and the one or more GPUs 1708, thereby simplifying programming of the one or more GPUs 1708 and porting applications to the one or more GPUs 1708.

In at least one embodiment, the one or more GPUs 1708 may include any number of access counters that can track the frequency of accesses by the one or more GPUs 1708 to memory of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved into the physical memory of the processor that most frequently accesses pages, thereby improving the efficiency of the memory range shared between processors.

In at least one embodiment, one or more socs 1704 may include any number of caches 1712, including those described herein. For example, in at least one embodiment, the one or more caches 1712 may include a three-level ("L3") cache that may be used for the one or more CPUs 1706 and the one or more GPUs 1708 (e.g., connected to the CPUs 1706 and GPUs 1708). In at least one embodiment, the one or more caches 1712 may include a write-back cache that may track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, although smaller cache sizes may be used, depending on the embodiment.

In at least one embodiment, the one or more socs 1704 may include one or more accelerators 1714 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more socs 1704 may include a hardware acceleration cluster, which may include optimized hardware accelerators and/or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement one or more GPUs 1708 and offload some tasks of the one or more GPUs 1708 (e.g., freeing up more cycles of the one or more GPUs 1708 to perform other tasks). In at least one embodiment, one or more accelerators 1714 may be used for target workloads (e.g., perceptions, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are stable enough to withstand acceleration verification. In at least one embodiment, the CNNs may include area or area convolutional neural networks ("RCNNs") and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

In at least one embodiment, the one or more accelerators 1714 (e.g., hardware acceleration clusters) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, the one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs") that may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types and floating point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general purpose GPU, and typically greatly exceeds the performance of the CPU. In at least one embodiment, one or more TPUs may perform several functions, including a single instance convolution function supporting, for example, INT17, INT16, and FP16 data types for features and weights, and a post processor function. In at least one embodiment, one or more DLAs may quickly and efficiently execute a neural network, particularly a CNN, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: CNN for object recognition and detection using data from camera sensors; CNN for distance estimation using data from the camera sensor; CNN for emergency vehicle detection, identification and detection using data from microphone 1796; CNN for face recognition and owner recognition using data from the camera sensor; and/or CNNs for security and/or security related events.

In at least one embodiment, the DLA may perform any of the functions of the one or more GPUs 1708, and by using an inference accelerator, for example, the designer may target the one or more DLAs or the one or more GPUs 1708 for any of the functions. For example, in at least one embodiment, the designer may focus the processing and floating point operations of the CNN on one or more DLAs and leave other functionality to one or more GPUs 1708 and/or one or more accelerators 1714.

In at least one embodiment, the one or more accelerators 1714 (e.g., hardware acceleration clusters) may include a programmable visual accelerator ("PVA"), which may alternatively be referred to herein as a computer visual accelerator. In at least one embodiment, one or more PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1738, autopilot, augmented reality ("AR") applications, and/or virtual reality ("VR") applications. In at least one embodiment, one or more PVA may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and/or any number of vector processors.

In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any of the cameras described herein), an image signal processor, or the like. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, according to an embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and/or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and/or tightly coupled RAM.

In at least one embodiment, the DMA may enable components of the PVA to access system memory independently of the one or more CPUs 1706. In at least one embodiment, the DMA may support any number of features for providing optimization to the PVA, including, but not limited to, supporting multidimensional addressing and/or cyclic addressing. In at least one embodiment, the DMA may support up to six or more addressed dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and/or depth stepping.

In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and to provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and/or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the primary processing engine for the PVA, and may include a vector processing unit ("VPU"), an instruction cache, and/or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, for example, a single instruction multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may improve throughput and speed.

In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processor included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a general purpose computer vision algorithm, except on different areas of the image. In at least one embodiment, the vector processor included in a particular PVA may perform different computer vision algorithms simultaneously on one image, or even on sequential images or portions of images. In at least one embodiment, any number of PVAs may be included in a hardware accelerated cluster, and any number of vector processors may be included in each PVA, among others. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance overall system security.

In at least one embodiment, the one or more accelerators 1714 (e.g., hardware acceleration clusters) may include a computer vision network on a chip and static random access memory ("SRAM") for providing high bandwidth, low latency SRAM for the one or more accelerators 1714. In at least one embodiment, the on-chip memory may comprise at least 4MB of SRAM, including, for example and without limitation, eight field-configurable memory blocks, to which both PVA and DLA may access. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone network that provides high speed access to the memory for the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects PVA and DLA to memory (e.g., using APB).

In at least one embodiment, the on-chip computer vision network may include an interface that determines that both PVA and DLA provide ready and valid signals before transmitting any control signals/addresses/data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transmission. In at least one embodiment, the interface may conform to International organization for standardization ("ISO") 26262 or International electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

In at least one embodiment, one or more of the socs 1704 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, a real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model), to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and/or analysis, for simulation of a sonor system, for general wave propagation simulation, for comparison with LIDAR data for positioning and/or other functions, and/or for other uses.

In at least one embodiment, one or more accelerators 1714 (e.g., a hardware acceleration cluster) have broad utility for autopilot. In at least one embodiment, the PVA can be a programmable vision accelerator for critical processing stages in ADAS and autopilot automobiles. In at least one embodiment, the ability of PVA at low power consumption and low latency matches well with the domain of algorithms that require predictable processing. In other words, PVA performs excellently in semi-dense or dense conventional calculations, even on small data sets, which may require predictable run times with low latency and low power consumption. In at least one embodiment, autonomous vehicles, such as PVA in vehicle 1700, may be designed to run classical computer vision algorithms, as they may be efficient in object detection and integer mathematical operations.

For example, according to at least one embodiment of the technology, PVA is used to perform computer stereoscopic vision. In at least one embodiment, a semi-global matching based algorithm may be used in some examples, although this is not meant to be limiting. In at least one embodiment, an application for 3-5 level autopilot uses dynamic estimation/stereo matching (e.g., recovering structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereoscopic functions on input from two monocular cameras.

In at least one embodiment, PVA may be used to perform dense light flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

In at least one embodiment, the DLA may be used to run any type of network to enhance control and driving safety, including for example, but not limited to, neural networks that output a confidence level for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as a probability, or as providing a relative "weight" for each detection relative to the other detections. In at least one embodiment, the confidence measure enables the system to make further decisions as to which tests should be considered true positive tests rather than false positive tests. In at least one embodiment, the system may set a threshold for the confidence and treat only detections exceeding the threshold as true positive detections. In embodiments using an automatic emergency brake ("AEB") system, false positive detection will result in the vehicle automatically performing emergency braking, which is clearly undesirable. In at least one embodiment, the detection of high confidence may be considered a trigger for AEB. In at least one embodiment, the DLA may run a neural network for regressing the confidence values. In at least one embodiment, the neural network may have as its inputs at least some subset of parameters, such as bounding box dimensions, obtained ground plane estimates (e.g., from another subsystem), outputs of one or more IMU sensors 1766 related to vehicle 1700 direction, distance, 3D position estimates of objects obtained from the neural network and/or other sensors (e.g., one or more LIDAR sensors 1764 or one or more RADAR sensors 1760), etc.

In at least one embodiment, one or more socs 1704 (e.g., hardware acceleration clusters) can include one or more data storage devices 1716 (e.g., memory). In at least one embodiment, the one or more data storage 1716 may be on-chip memory of the one or more socs 1704, which may store a neural network to be executed on the one or more GPUs 1708 and/or DLAs. In at least one embodiment, one or more data storage 1716 may have a capacity large enough to store multiple instances of the neural network for redundancy and security. In at least one embodiment, the one or more data stores 1712 may include an L2 or L3 cache.

In at least one embodiment, the one or more socs 1704 may include any number of processors 1710 (e.g., embedded processors). In at least one embodiment, the one or more processors 1710 can include a startup and power management processor, which can be a dedicated processor and subsystem, to handle startup power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of one or more SoC1704 boot sequences and may provide a runtime power management service. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, one or more SoC1704 thermal and temperature sensor management, and/or one or more SoC1704 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the one or more socs 1704 may use the ring oscillator to detect the temperature of the one or more CPUs 1706, the one or more GPUs 1708, and/or the one or more accelerators 1714. In at least one embodiment, if it is determined that the temperature exceeds the threshold, the start-up and power management processor may enter a temperature fault routine and place one or more socs 1704 into a lower power consumption state and/or place the vehicle 1700 into a safe parking pattern for the driver (e.g., to safely park the vehicle 1700).

In at least one embodiment, the one or more processors 1710 may further comprise a set of embedded processors that may function as an audio processing engine, which may be an audio subsystem, that is capable of providing hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I/O interfaces. In at least one embodiment, the audio processing engine is a special purpose processor core having a digital signal processor with special purpose RAM.

In at least one embodiment, the one or more processors 1710 may further include an always online processor engine. In at least one embodiment, the automated processing engine may provide the necessary hardware features to support low power sensor management and wake-up use cases. In at least one embodiment, processors on an always-on processor engine may include, but are not limited to, processor cores, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I/O controller peripherals, and routing logic.

In at least one embodiment, the one or more processors 1710 may further include a security cluster engine including, but not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and/or routing logic. In the secure mode, in at least one embodiment, two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the one or more processors 1710 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for processing real-time camera management. In at least one embodiment, the one or more processors 1710 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

In at least one embodiment, the one or more processors 1710 can include a video image compositor, which can be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to produce a final video to produce a final image for a player window. In at least one embodiment, the video image compositor may perform lens distortion correction on one or more wide angle cameras 1770, one or more surround cameras 1774, and/or one or more intra-cabin surveillance camera sensors. In at least one embodiment, the in-cabin monitoring camera sensor is preferably monitored by a neural network running on another instance of the SoC 1704, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular services and make phone calls, instruct email, change the destination of the vehicle, activate or change the infotainment system and settings of the vehicle, or provide voice activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, otherwise disabled.

In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in video, noise reduction is appropriately weighted for spatial information, thereby reducing the weight of information provided by neighboring frames. In at least one embodiment, where the image or portion of the image does not include motion, the temporal noise reduction performed by the video image compositor may use information from the previous image to reduce noise in the current image.

In at least one embodiment, the video image compositor may be further configured to perform stereoscopic correction on the input stereoscopic frames. In at least one embodiment, when an operating system desktop is used, the video image compositor may also be used for user interface compositing and one or more GPUs 1708 are not required to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1708 are powered and actively rendered 3D, a video image compositor may be used to offload one or more GPUs 1708 to improve performance and responsiveness.

In at least one embodiment, one or more of the socs 1704 may further include a mobile industrial processor interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and/or a video input block that is available for camera and related pixel input functions. In at least one embodiment, one or more of the socs 1704 may further include an input/output controller that may be controlled by software and may be used to receive I/O signals that are not submitted to a particular role.

In at least one embodiment, one or more of the socs 1704 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoder/decoders ("codecs"), power management, and/or other devices. In at least one embodiment, one or more socs 1704 may be used to process data from (e.g., via gigabit multimedia serial link and ethernet channel connection) cameras, sensors (e.g., one or more LIDAR sensors 1764, one or more RADAR sensors 1760, etc., which may be connected via ethernet channel), data from bus 1702 (e.g., speed of vehicle 1700, steering wheel position, etc.), data from one or more GNSS sensors 1758 (e.g., via ethernet bus or CAN bus connection), etc. In at least one embodiment, one or more of the socs 1704 may further include a dedicated high performance mass storage controller, which may include their own DMA engine, and may be used to shed the one or more CPUs 1706 from conventional data management tasks.

In at least one embodiment, one or more socs 1704 may be end-to-end platforms with flexible architecture that spans automation levels 3-5, providing a functional security architecture that utilizes and efficiently uses computer vision and ADAS technology to achieve a combination of diversity and redundancy, providing a platform that can provide a flexible, reliable driver software stack and deep learning tools. In at least one embodiment, one or more socs 1704 may be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1714, when combined with one or more CPUs 1706, one or more GPUs 1708, and one or more data stores 1716, may provide a fast and efficient platform for 3-5 class autonomous vehicles.

In at least one embodiment, the computer vision algorithms may be executed on a CPU, which may be configured to execute a variety of processing algorithms on a variety of vision data using a high-level programming language (e.g., C). However, in at least one embodiment, the CPU is typically unable to meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs are not capable of executing complex object detection algorithms in real-time, which are used in on-board ADAS applications and in actual class 3-5 autonomous vehicles.

The embodiments described herein allow multiple neural networks to be executed simultaneously and/or sequentially, and allow the results to be combined together to achieve 3-5 level autopilot functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., one or more GPUs 1720) may include text and word recognition, allowing a supercomputer to read and understand traffic signs, including signs that a neural network has not been trained specifically. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing a semantic understanding of the symbol, and communicating the semantic understanding to a path planning module running on the CPU Complex.

In at least one embodiment, multiple neural networks may be operated simultaneously for 3, 4, or 5 stage driving. For example, in at least one embodiment, the warning flag states: the flashing light indicates icing conditions (section: flashing lights indicate icy conditions) "warning signs consisting of connected lamps together may be interpreted by multiple neural networks, either independently or together. In at least one embodiment, the warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icing conditions (flashing lights indicate icy conditions)" may be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on the CPU Complex): when a blinking light is detected, an icing condition may exist. In at least one embodiment, the flashing lights may be identified by operating the third deployed neural network over a plurality of frames, informing the path planning software of the vehicle of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks may run simultaneously, e.g., within a DLA and/or on one or more GPUs 1708.

In at least one embodiment, the CNN for face recognition and vehicle owner recognition may use data from the camera sensors to identify the presence of an authorized driver and/or owner of the vehicle 1700. In at least one embodiment, the normally open sensor processor engine may be used to unlock the vehicle when the owner approaches the driver door and turns on the lights, and may be used to disable the vehicle when the owner leaves the vehicle in a safe mode. In this way, one or more socs 1704 provide safeguarding against theft and/or hijacking.

In at least one embodiment, the CNN for emergency vehicle detection and identification may use data from microphone 1796 to detect and identify an emergency vehicle alarm. In at least one embodiment, the one or more socs 1704 use CNNs to classify environmental and urban sounds, as well as to classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approach speed of the emergency vehicle (e.g., by using the doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1758. In at least one embodiment, the CNN will seek to detect european alarms when operating in europe, and will seek to identify north american alarms only when in the united states. In at least one embodiment, once an emergency vehicle is detected, a control program may be used with the assistance of one or more ultrasonic sensors 1762 to perform an emergency vehicle safety routine, slow the vehicle, drive the vehicle to the curb, park, and/or idle the vehicle until the emergency vehicle passes.

In at least one embodiment, the vehicle 1700 may include one or more CPUs 1718 (e.g., one or more discrete CPUs or one or more dcpus) which may be coupled to one or more socs 1704 via a high speed interconnect (e.g., PCIe). In at least one embodiment, for example, one or more of the CPUs 1718 can include an X86 processor. The one or more CPUs 1718 can be used to perform any of a variety of functions, including, for example, arbitrating the results of potential inconsistencies between the ADAS sensor and the one or more socs 1704, and/or monitoring the status and health of the one or more controllers 1736 and/or the on-chip infotainment system ("infotainment SoC") 1730.

In at least one embodiment, vehicle 1700 may include one or more GPUs 1720 (e.g., one or more discrete GPUs or one or more dGPU) that may be coupled to one or more socs 1704 via a high-speed interconnect (e.g., NVLINK channels of NVIDIA). In at least one embodiment, one or more GPUs 1720 may provide additional artificial intelligence functionality, such as by performing redundancy and/or a different neural network, and may be used to train and/or update the neural network based at least in part on input (e.g., sensor data) from sensors of vehicle 1700.

In at least one embodiment, vehicle 1700 may further include a network interface 1724, which may include, but is not limited to, one or more wireless antennas 1726 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a bluetooth antenna, etc.). In at least one embodiment, the network interface 1724 can be used to enable wireless connection with other vehicles and/or computing devices (e.g., passenger's client devices) through internet cloud services (e.g., employing servers and/or other network devices). In at least one embodiment, a direct link may be established between the vehicle 170 and another vehicle and/or an indirect link may be established (e.g., over a network and over the internet) for communication with other vehicles. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide information to the vehicle 1700 about vehicles in the vicinity of the vehicle 1700 (e.g., vehicles in front of, to the side of, and/or behind the vehicle 1700). In at least one embodiment, the aforementioned functionality may be part of a cooperative adaptive cruise control function of the vehicle 1700.

In at least one embodiment, the network interface 1724 can include a SoC that provides modulation and demodulation functions and enables one or more controllers 1736 to communicate over a wireless network. In at least one embodiment, the network interface 1724 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and/or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, bluetooth LE, wi-Fi, Z-Wave, zigBee, loRaWAN, and/or other wireless protocols.

In at least one embodiment, vehicle 1700 may further include one or more data storage devices 1728, which may include, but are not limited to, off-chip (e.g., one or more socs 1704) storage. In at least one embodiment, the one or more data storage devices 1728 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard disk, and/or other components and/or devices that may store at least one bit of data.

In at least one embodiment, the vehicle 1700 may further include one or more GNSS sensors 1758 (e.g., GPS and/or assisted GPS sensors) to assist in mapping, sensing, occupancy raster generation, and/or path planning functions. In at least one embodiment, any number of GNSS sensors 1758 may be used, including for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

In at least one embodiment, the vehicle 1700 may further include one or more RADAR sensors 1760. In at least one embodiment, one or more RADAR sensors 1760 can be used by the vehicle 1700 for remote vehicle detection, even in dark and/or severe weather conditions. In at least one embodiment, the RADAR function security level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1760 CAN use the CAN bus and/or bus 1702 (e.g., to transmit data generated by one or more RADAR sensors 1760) to control and access object tracking data, in some examples an ethernet channel CAN be accessed to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and without limitation, one or more of RADAR sensors 1760 may be adapted for front, rear, and side RADAR use. In at least one embodiment, the one or more RADAR sensors 1760 are pulsed Doppler RADAR sensors.

In at least one embodiment, the one or more RADAR sensors 1760 can include different configurations, such as long range with a narrow field of view, short range with a wide field of view, short range side coverage, and so forth. In at least one embodiment, remote RADAR may be used for adaptive cruise control functions. In at least one embodiment, the remote RADAR system may provide a wide field of view through two or more independent scans (e.g., within 250 m). In at least one embodiment, one or more RADAR sensors 1760 can help distinguish between static objects and moving objects, and can be used by the ADAS system 1738 for emergency braking assistance and forward collision warning. In at least one embodiment, the one or more sensors 1760 included in the remote RADAR system may include, but are not limited to, a single-base multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, the central four antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 1700 at a higher speed with minimal traffic interference in adjacent lanes. In at least one embodiment, the other two antennas may expand the field of view so that vehicles 1700 entering or exiting the lane may be detected quickly.

In at least one embodiment, as an example, a mid-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear), for example. In at least one embodiment, the short range RADAR system may include, but is not limited to, any number of RADAR sensors 1760 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the vehicle rear direction and nearby blind spots. In at least one embodiment, the short range RADAR system can be used in the ADAS system 1738 for blind spot detection and/or lane change assistance.

In at least one embodiment, the vehicle 1700 may further include one or more ultrasonic sensors 1762. In at least one embodiment, one or more ultrasonic sensors 1762, which may be positioned in front, rear, and/or lateral positions of the vehicle 1700, may be used for parking assistance and/or creating and updating occupancy gratings. In at least one embodiment, a wide variety of ultrasonic sensors 1762 may be used, and different ultrasonic sensors 1762 may be used for different detection ranges (e.g., 2.5m, 4 m). In at least one embodiment, the ultrasonic sensor 1762 can operate at a functional safety level of ASIL B.

In at least one embodiment, the vehicle 1700 may include one or more LIDAR sensors 1764. In at least one embodiment, one or more LIDAR sensors 1764 may be used for object and pedestrian detection, emergency braking, collision avoidance, and/or other functions. In at least one embodiment, one or more LIDAR sensors 1764 may operate at a functional security level ASIL B. In at least one embodiment, the vehicle 1700 may include a plurality (e.g., two, four, six, etc.) of LIDAR sensors 1764 that may use ethernet (e.g., provide data to a gigabit ethernet switch).

In at least one embodiment, one or more LIDAR sensors 1764 may be capable of providing a list of objects and their distances for a 360 degree field of view. In at least one embodiment, one or more LIDAR sensors 1764 commercially available, for example, may have an advertising range of approximately 100m, have a precision of 2cm-3cm, and support 100Mbps Ethernet connections. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such embodiments, the one or more LIDAR sensors 1764 may include small devices that may be embedded in front, rear, sides, and/or corner locations of the vehicle 1700. In at least one embodiment, one or more LIDAR sensors 1764, in such embodiments, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low reflectivity objects, and have a range of 200 m. In at least one embodiment, the forward one or more LIDAR sensors 1764 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, the 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 1700. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse travel time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1700 to the object. In at least one embodiment, the flash LIDAR may allow for the generation of highly accurate and distortion-free images of the surrounding environment with each laser flash. In at least one embodiment, four flashing LIDAR sensors may be deployed, one on each side of the vehicle 1700. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid state 3D line of sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use 5 nanosecond class I (eye-safe) laser pulses per frame and may capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

In at least one embodiment, the vehicle 1700 may also include one or more IMU sensors 1766. In at least one embodiment, one or more IMU sensors 1766 may be located in the rear axle center of the vehicle 1700. In at least one embodiment, the one or more IMU sensors 1766 may include, for example, but are not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one magnetic compass, a plurality of magnetic compasses, and/or other sensor types. In at least one embodiment, for example in a six-axis application, the one or more IMU sensors 1766 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, such as in a nine-axis application, the one or more IMU sensors 1766 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

In at least one embodiment, one or more IMU sensors 1766 may be implemented as a miniature high-performance GPS-assisted inertial navigation system ("GPS/INS") incorporating microelectromechanical system ("MEMS") inertial sensors, high-sensitivity GPS receivers, and advanced kalman filtering algorithms to provide an estimate of position, velocity, and attitude; in at least one embodiment, the one or more IMU sensors 1766 may enable the vehicle 1700 to estimate heading by directly observing and correlating speed changes from GPS to the one or more IMU sensors 1766 without input from the magnetic sensor. In at least one embodiment, one or more IMU sensors 1766 and one or more GNSS sensors 1758 may be combined in a single integrated unit.

In at least one embodiment, the vehicle 1700 may include one or more microphones 1796 disposed within and/or around the vehicle 1700. In at least one embodiment, in addition, one or more microphones 1796 may be used for emergency vehicle detection and identification.

In at least one embodiment, vehicle 1700 may further include any number of camera types including one or more stereo cameras 1768, one or more wide angle cameras 1770, one or more infrared cameras 1772, one or more surround cameras 1774, one or more remote cameras 1798, one or more mid-range cameras 1776, and/or other camera types. In at least one embodiment, a camera may be used to capture image data around the entire periphery of the vehicle 1700. In at least one embodiment, the type of camera used depends on the vehicle 1700. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1700. In at least one embodiment, the number of cameras deployed may vary from embodiment to embodiment. For example, in at least one embodiment, the vehicle 1700 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the camera may support gigabit multimedia serial link ("GMSL") and/or gigabit ethernet communications by way of example and not limitation. In at least one embodiment, each camera may be described in more detail herein before with reference to fig. 17A and 17B.

In at least one embodiment, the vehicle 1700 may further include one or more vibration sensors 1742. In at least one embodiment, one or more vibration sensors 1742 may measure vibrations of a component (e.g., a shaft) of the vehicle 1700. For example, in at least one embodiment, a change in vibration may be indicative of a change in road surface. In at least one embodiment, when two or more vibration sensors 1742 are used, the difference between the vibrations may be used to determine friction or slip of the road surface (e.g., when there is a vibration difference between the powered drive shaft and the free rotating shaft).

In at least one embodiment, the vehicle 1700 can include an ADAS system 1738. In at least one embodiment, the ADAS system 1738 can include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1738 can include, but is not limited to, any number of autonomous/adaptive/auto cruise control ("ACC") systems, collaborative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and/or other systems, features, and/or functions, and combinations thereof.

In at least one embodiment, the ACC system may use one or more RADAR sensors 1760, one or more LIDAR sensors 1764, and/or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and/or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle in close proximity to the vehicle 1700 and automatically adjusts the speed of the vehicle 1700 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance maintenance and recommends the vehicle 1700 to change lanes when needed. In at least one embodiment, the landscape ACC is associated with other ADAS applications, such as LC and CW.

In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via a network interface 1724 and/or one or more wireless antennas 1726 via a wireless link or indirectly via a network connection (e.g., via the internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communication provides information about an immediately preceding vehicle (e.g., a vehicle immediately preceding and on the same lane as vehicle 1700), while I2V communication provides information about more forward traffic. In at least one embodiment, the CACC system may include one or both of I2V and V2V information sources. In at least one embodiment, given the information of the vehicle ahead of the vehicle 1700, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

In at least one embodiment, the FCW system is designed to alert the driver of the danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward facing camera and/or one or more RADAR sensors 1760 coupled to a dedicated processor, DSP, FPGA, and/or ASIC that is electrically coupled to provide driver feedback, such as a display, speaker, and/or vibration component. In at least one embodiment, the FCW system may provide an alert, for example in the form of an audible, visual alert, vibration, and/or rapid braking pulse.

In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and may automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward facing cameras and/or one or more RADAR sensors 1760 coupled to a dedicated processor, DSP, FPGA, and/or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first alerts the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system can automatically apply the brakes in an attempt to prevent, or at least mitigate, the effects of the predicted collision. In at least one embodiment, the AEB system can include techniques such as dynamic brake support and/or impending collision braking.

In at least one embodiment, the LDW system provides visual, audible, and/or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1700 crosses the lane markings. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal light. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and/or ASIC that is electrically coupled to provide driver feedback such as a display, speaker, and/or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1700 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 1700.

In at least one embodiment, the BSW system detects and alerts a driver of the vehicle in a blind spot of the vehicle. In at least one embodiment, the BSW system may provide visual, audible, and/or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide additional warning when the driver uses the turn signal. In at least one embodiment, the BSW system may use one or more rear-facing cameras and/or one or more RADAR sensors 1760 coupled to a dedicated processor, DSP, FPGA, and/or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and/or vibration component.

In at least one embodiment, the RCTW system can provide visual, audible, and/or tactile notification when an object is detected outside the rear camera range when the vehicle 1700 is reversed. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid collisions. In at least one embodiment, the RCTW system can use one or more rearward facing RADAR sensors 1760 coupled to a dedicated processor, DSP, FPGA, and/or ASIC that are electrically coupled to provide driver feedback such as a display, speaker, and/or vibration component.

In at least one embodiment, conventional ADAS systems may be prone to false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems can alert the driver and allow the driver to decide whether a safety condition is actually present and take corresponding action. In at least one embodiment, in the event of a result conflict, the vehicle 1700 itself decides whether to hear the result of the primary or secondary computer (e.g., the first or second controller of the controller 1736). For example, in at least one embodiment, the ADAS system 1738 can be a backup and/or auxiliary computer for providing awareness information to the backup computer rationality module. In at least one embodiment, the standby computer rationality monitor may run redundant various software on hardware components to detect faults in perceived and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1738 can be provided to a monitoring MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervising MCU decides how to coordinate the conflicts to ensure safe operation.

In at least one embodiment, the host computer may be configured to provide a confidence score to the supervising MCU to indicate the host computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervising MCU may follow the direction of the primary computer, regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, where the confidence score does not meet a threshold, and where the primary and secondary computers indicate different results (e.g., conflicts), the supervising MCU may arbitrate between the computers to determine the appropriate result.

In at least one embodiment, the supervising MCU may be configured to run a neural network trained and configured to determine a condition that the auxiliary computer provides a false alarm based at least in part on output from the main computer and output from the auxiliary computer. In at least one embodiment, the neural network in the supervising MCU may learn when the output of the secondary computer can be trusted and when it cannot. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervising MCU may learn when the FCW system identifies metal objects that are not actually dangerous, such as drain grids or manhole covers that would trigger an alarm. In at least one embodiment, when the helper computer is a camera-based LDW system, the neural network in the supervising MCU may learn to cover the LDW when there is a cyclist or pedestrian and in fact lane departure is the safest operation. In at least one embodiment, the supervising MCU may include at least one of a DLA or GPU adapted to run a neural network with associated memory. In at least one embodiment, the supervising MCU may include and/or be included as a component of one or more socs 1704.

In at least one embodiment, the ADAS system 1738 can include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then) and supervising the presence of neural networks in the MCU may improve reliability, security and performance. For example, in at least one embodiment, the varied implementation and intentional non-uniformities make the overall system more fault tolerant, especially to faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software bug or error in the software running on the host computer and the different software code running on the secondary computer provides a consistent overall result, the supervising MCU may more confidently consider the overall result to be correct and the bug in the software or hardware on the host computer does not result in a significant error.

In at least one embodiment, the output of the ADAS system 1738 can be input into a perception module of a host computer and/or a dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1738 indicates a forward collision warning due to an object directly in front, the perception block can use this information in identifying the object. In at least one embodiment, the secondary computer may have its own neural network trained to reduce the risk of false positives, as described herein.

In at least one embodiment, the vehicle 1700 may further include an infotainment SoC1730 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as a SoC, in at least one embodiment, the infotainment system SoC1730 may not be a SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC1730 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistants, navigation instructions, news, broadcast, etc.), video (e.g., television, movies, streaming media, etc.), telephony (e.g., hands-free calls), network connectivity (e.g., LTE, wiFi, etc.), and/or information services (e.g., navigation system, rear parking assistance, radio data system, vehicle related information such as fuel level, total coverage distance, brake fuel level, door opening/closing, air cleaner information, etc.) to the vehicle 1700. For example, the infotainment SoC1730 may include a radio, disk player, navigation system, video player, USB and bluetooth connection, automobile, in-vehicle entertainment system, wiFi, steering wheel audio control, hands-free voice control, head-up display ("HUD"), HMI display 1734, telematics device, control panel (e.g., for controlling and/or interacting with various components, features, and/or systems), and/or other components. In at least one embodiment, the infotainment SoC1730 can be further used to provide information (e.g., visual and/or audible) to a user of the vehicle 1700, such as information from the ADAS system 1738, autopilot information (such as planned vehicle maneuvers), trajectories, ambient information (e.g., intersection information, vehicle information, road information, etc.), and/or other information.

In at least one embodiment, the infotainment SoC 1730 can include any number and type of GPU functions. In at least one embodiment, the infotainment SoC 1730 CAN communicate (e.g., CAN bus, ethernet, etc.) with other devices, systems, and/or components of the vehicle 1700 via the bus 1702. In at least one embodiment, the infotainment SoC 1730 may be coupled to a monitoring MCU such that the GPU of the infotainment system may perform some autopilot functions in the event of a failure of the master controller 1736 (e.g., the host and/or standby computers of the vehicle 1700). In at least one embodiment, the infotainment SoC 1730 can cause the vehicle 1700 to enter a driver to a safe stop mode, as described herein.

In at least one embodiment, the vehicle 1700 may further include an instrument panel 1732 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1732 may include, but is not limited to, a controller and/or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument panel 1732 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine failure lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, and the like. In some examples, information may be displayed and/or shared between the infotainment SoC 1730 and the dashboard 1732. In at least one embodiment, a dashboard 1732 may be included as part of the infotainment SoC 1730, and vice versa. In at least one embodiment, at least one component shown or described with respect to fig. 17C is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 17D is a diagram of a system 1777 for communicating between a cloud-based server and the autonomous vehicle 1700 of fig. 17A, in accordance with at least one embodiment. In at least one embodiment, the system 1777 may include, but is not limited to, one or more servers 1778, one or more networks 1790, and any number and type of vehicles, including the vehicle 1700. In at least one embodiment, the one or more servers 1778 can include, but are not limited to, a plurality of GPUs 1784 (a) -1784 (H) (collectively referred to herein as GPUs 1784), PCIe switches 1782 (a) -1782 (D) (collectively referred to herein as PCIe switches 1782), and/or CPUs 1780 (a) -1780 (B) (collectively referred to herein as CPUs 1780), GPUs 1784, CPUs 1780, and PCIe switches 1782 can be interconnected with high speed connection lines, such as, but not limited to, NVLink interface 1788 and/or PCIe connection 1786 developed by NVIDIA. In at least one embodiment, GPU1784 is connected through an NVLink and/or NVSwitch SoC, and GPU1784 and PCIe switch 1782 are connected through a PCIe interconnect. In at least one embodiment, although eight GPUs 1784, two CPUs 1780, and four PCIe switches 1782 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1778 can include, but is not limited to, any combination of any number of GPUs 1784, CPUs 1780, and/or PCIe switches 1782. For example, in at least one embodiment, the one or more servers 1778 may each include eight, sixteen, thirty-two, and/or more GPUs 1784. In at least one embodiment, the one or more servers 1778 include one or more CPU, ASIC, GPU, FPGA, system on a chip (SoC), or other hardware, circuitry, or integrated circuit components including, for example, an amplifier or upsampler to amplify an image, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit configured to perform an amplifier to amplify an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels; one or more data center servers 1778 may use the components described in this disclosure to perform methods, operations, or instructions to generate or modify images.

In at least one embodiment, one or more servers 1778 may receive image data representing an image from a vehicle over one or more networks 1790, the image showing unexpected or changing road conditions, such as recently initiated road works. In at least one embodiment, one or more servers 1778 may transmit neural networks 1792, updated neural networks 1792, and/or map information 1794, including, but not limited to, information about traffic and road conditions, through one or more networks 1790 and to the vehicle. In at least one embodiment, the update to map information 1794 may include, but is not limited to, an update to HD map 1722, such as information about a building site, a pothole, a passageway, a flood, and/or other obstacle. In at least one embodiment, the neural network 1792, updated neural network 1792, and/or map information 1794 may be generated from new training and/or experience represented in data received from any number of vehicles in the environment, and/or based at least on training performed at the data center (e.g., using one or more servers 1778 and/or other servers).

In at least one embodiment, one or more servers 1778 can be used to train a machine learning model (e.g., neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and/or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any number of training data (e.g., where the associated neural network benefits from supervised learning) is tagged and/or subjected to other preprocessing. In at least one embodiment, no quantity of training data is labeled and/or preprocessed (e.g., where the associated neural network does not need supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle over one or more networks 1790, and/or the machine learning model may be used by one or more servers 1778 to remotely monitor the vehicle.

In at least one embodiment, one or more servers 1778 can receive data from the vehicle and apply the data to the most up-to-date real-time neural network for real-time intelligent reasoning. In at least one embodiment, the one or more servers 1778 can include a deep learning supercomputer powered by one or more GPUs 1784 and/or dedicated AI computers, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the one or more servers 1778 may include a deep learning infrastructure of a data center powered using a CPU.

In at least one embodiment, the deep learning infrastructure of one or more servers 1778 may be capable of fast, real-time reasoning and may use this capability to assess and verify the health of processors, software, and/or related hardware in the vehicle 1700. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1700, such as a sequence of images and/or objects (e.g., by computer vision and/or other machine learning object classification techniques) in which the vehicle 1700 is positioned in the sequence of images. In at least one embodiment, the deep learning infrastructure can run its own neural network to identify objects and compare them to objects identified by the vehicle 1700, and if the results do not match and the deep learning infrastructure concludes that the AI in the vehicle 1700 is malfunctioning, one or more servers 1778 can send signals to the vehicle 1700 to instruct the fail-safe computer of the vehicle 1700 to take control, notify passengers, and complete the safe parking operation.

In at least one embodiment, the one or more servers 1778 can include one or more GPUs 1784 and one or more programmable inference accelerators (e.g., tensorRT 3 of NVIDIA). In at least one embodiment, a combination of GPU-driven servers and inference acceleration may enable real-time responses. In at least one embodiment, servers driven by CPUs, FPGAs and other processors can be used for reasoning, for example, where performance is less critical.

Computer system

FIG. 18 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system on a chip (SOC), or some combination thereof 1800 formed with a processor, which may include an execution unit to execute instructions, in accordance with at least one embodiment. In at least one embodiment, in accordance with the present disclosure, e.g., the embodiments described herein, computer system 1800 may include, but is not limited to, components, e.g., processor 1802, whose execution units include logic to perform algorithms for process data. In at least one embodiment, computer system 1800 may include a processor such as that available from Intel corporation of Santa Clara, calif. (Intel Corporation of Santa Clara, california) Processor family, xeon ^TM 、/>XScale ^TM And-Or StrongARM ^TM ，/>Core ^TM Or-> Nervana ^TM Microprocessors, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1800 may execute a version of the WINDOWS operating system available from microsoft corporation of redmond, washery (Microsoft Corporation of Redmond), although other operating systems (e.g., UNIX and Linux), embedded software, and/or graphical user interfaces may be used.

Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, internet protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that may execute one or more instructions in accordance with at least one embodiment.

In at least one embodiment, the computer system 1800 can include, but is not limited to, a processor 1802, which processor 1802 can include, but is not limited to, one or more execution units 1808 to perform machine learning model training and/or reasoning in accordance with the techniques described herein. In at least one embodiment, system 18 is a single processor desktop or server system, but in another embodiment system 18 may be a multiprocessor system. In at least one embodiment, the processor 1802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1802 may be coupled to a processor bus 1810, which processor bus 1810 may transmit data signals between the processor 1802 and other components in the computer system 1800.

In at least one embodiment, the processor 1802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1804. In at least one embodiment, the processor 1802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to the processor 1802. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and requirements. In at least one embodiment, the register file 1806 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

In at least one embodiment, an execution unit 1808, including but not limited to logic to perform integer and floating point operations, is also located in the processor 1802. In at least one embodiment, the processor 1802 may also include microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1808 may include logic to process the packaged instruction set 1809. In at least one embodiment, the encapsulated data in the general purpose processor 1802 may be used to perform operations for many multimedia application uses by including the encapsulated instruction set 1809 in the instruction set of the general purpose processor, as well as related circuitry for executing instructions. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of a processor's data bus to perform operations on packaged data, which may not require the transmission of smaller data units on the processor's data bus to perform one or more operations of one data element at a time.

In at least one embodiment, the execution unit 1808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1800 can include, but is not limited to, memory 1820. In at least one embodiment, memory 1820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another memory device. In at least one embodiment, the memory 1820 may store instructions 1819 and/or data 1821 represented by data signals that may be executed by the processor 1802.

In at least one embodiment, a system logic chip may be coupled to processor bus 1810 and memory 1820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 1816 and the processor 1802 may communicate with the MCH 1816 via a processor bus 1810. In at least one embodiment, the MCH 1816 may provide a high bandwidth memory path 1818 to memory 1820 for instruction and data storage as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1816 may direct data signals between the processor 1802, the memory 1820, and other components in the computer system 1800, and bridge data signals between the processor bus 1810, the memory 1820, and the system I/O1822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1816 may be coupled to a memory 1820 through a high bandwidth memory path 1818 and the graphics/video card 1812 may be coupled to the MCH 1816 through an accelerated graphics port (Accelerated Graphics Port) ("AGP") interconnect 1814.

In at least one embodiment, the computer system 1800 may use a system I/O1822, which is a proprietary hub interface bus, to couple the MCH 1816 to an I/O controller hub ("ICH") 1830. In at least one embodiment, the ICH 1830 may provide a direct connection to certain I/O devices through a local I/O bus. In at least one embodiment, the local I/O bus may include, but is not limited to, a high-speed I/O bus for connecting peripheral devices to memory 1820, chipset, and processor 1802. Examples may include, but are not limited to, an audio controller 1829, a firmware hub ("Flash BIOS") 1828, a wireless transceiver 1826, a data store 1824, a conventional I/O controller 1823 including user input and a keyboard interface, a serial expansion port 1827 (e.g., universal Serial Bus (USB)), and a network controller 1834. In at least one embodiment, data store 1824 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment, fig. 18 shows a system including interconnected hardware devices or "chips", while in other embodiments, fig. 18 may show a system on a chip (SoC). In at least one embodiment, the devices shown in fig. 18 may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1800 are interconnected using a computing fast link (CXL) interconnect. In at least one embodiment, one or more components of system 1800 include one or more CPU, ASIC, GPU, FPGA or other hardware, circuitry, or integrated circuit components including, for example, an amplifier or upsampler to amplify an image, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit configured to perform an amplifier to amplify an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels; one or more components of system 1800 may perform the methods, operations, or instructions for generating or modifying images using the components described in this disclosure. In at least one embodiment, at least one component shown or described with respect to fig. 18 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 19 is a block diagram illustrating an electronic device 1900 for utilizing a processor 1910 in accordance with at least one embodiment. In at least one embodiment, electronic device 1900 may be, for example, but not limited to, a notebook computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

In at least one embodiment, the system 1900 may include, but is not limited to, a processor 1910 communicatively coupled to any suitable number or variety of components, peripherals, modules, or devices. In at least one embodiment, the processor 1910 uses bus or interface coupling, such as an I ℃ bus, a system management bus ("SMBus"), a Low Pin Count (LPC) bus, a serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (version 1, 2, 3, etc.), or a universal asynchronous receiver/transmitter ("UART") bus. In at least one embodiment, fig. 19 illustrates a system including interconnected hardware devices or "chips", while in other embodiments, fig. 19 may illustrate an exemplary system on a chip (SoC). In at least one embodiment, the devices shown in FIG. 19 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of fig. 19 are interconnected using a computing fast link (CXL) interconnect line.

In at least one embodiment, fig. 19 may include a display 1924, a touch screen 1925, a touch pad 1930, a near field communication unit ("NFC") 1945, a sensor hub 1940, a thermal sensor 1946, a fast chipset ("EC") 1935, a trusted platform module ("TPM") 1938, a BIOS/firmware/Flash ("BIOS, FW Flash") 1922, a DSP1960, a drive "SSD or HDD"1920 (e.g., a solid state disk ("SSD") or hard disk drive ("HDD")), a wireless local area network unit ("WLAN") 1950, a bluetooth unit 1952, a wireless wide area network unit ("WWAN") 1956, a Global Positioning System (GPS) 1955, a camera ("USB 3.0 camera") 1954 (e.g., a USB 3.0 camera), or a low power double data rate ("LPDDR") memory unit ("LPDDR 3") 1915 implemented, for example, in the LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to the processor 1910 via components as described above. In at least one embodiment, an accelerometer 1941, an ambient light sensor ("ALS") 1942, a compass 1943, and a gyroscope 1944 may be communicatively coupled to the sensor hub 1940. In at least one embodiment, a thermal sensor 1939, a fan 1937, a keyboard 1946, and a touchpad 1930 can be communicatively coupled to the EC 1935. In at least one embodiment, a speaker 1963, an earphone 1964, and a microphone ("mic") 1965 may be communicatively coupled to an audio unit ("audio codec and class D amplifier") 1964, which in turn may be communicatively coupled to the DSP 1960. In at least one embodiment, the audio unit 1964 may include, for example, but is not limited to, an audio encoder/decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 1957 can be communicatively coupled to the WWAN unit 1956. In at least one embodiment, components, such as WLAN unit 1950 and bluetooth unit 1952, and WWAN unit 1956, may be implemented as Next Generation Form Factor (NGFF). In at least one embodiment, at least one component shown or described with respect to fig. 19 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 20 illustrates a computer system 2000 in accordance with at least one embodiment. In at least one embodiment, the computer system 2000 is configured to implement the various processes and methods described throughout this disclosure.

In at least one embodiment, computer system 2000 includes, but is not limited to, at least one central processing unit ("CPU") 2002, which CPU 2002 is connected to a communication bus 2010 implemented using any suitable protocol, such as PCI ("peripheral device interconnect"), peripheral component interconnect Express ("PCI-Express"), AGP ("accelerated graphics Port"), hyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 2000 includes, but is not limited to, a main memory 2004 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 2004 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 2022 provides an interface to other computing devices and networks for receiving data from computer system 2000 and transmitting data to other systems.

In at least one embodiment, computer system 2000 includes, in at least one embodiment, but is not limited to, an input device 2008, a parallel processing system 2012, and a display device 2006, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, user input is received from an input device 2008 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may be located on a single semiconductor platform to form a processing system. In at least one embodiment, one or more component computer systems 2000 may be in communication with one or more CPU, ASIC, GPU, FPGA or other hardware, circuits, or integrated circuit components including, for example, an amplifier or upsampler to amplify an image, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit configured to execute an amplifier to amplify an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels; one or more components of computer system 2000 may perform the methods, operations, or instructions for generating or modifying images using the components described in this disclosure. In at least one embodiment, at least one component shown or described with respect to fig. 20 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 21 illustrates a computer system 2100 in accordance with at least one embodiment. In at least one embodiment, computer system 2100 includes, but is not limited to, a computer 2110 and a USB stick 2120. In at least one embodiment, computer 2110 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 2110 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

In at least one embodiment, USB stick 2120 includes, but is not limited to, a processing unit 2130, a USB interface 2140, and USB interface logic 2150. In at least one embodiment, the processing unit 2130 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 2130 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 2130 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 2130 is a tensor processing unit ("TPC") optimized to perform machine learning reasoning operations. In at least one embodiment, the processing core 2130 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

In at least one embodiment, USB interface 2140 may be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 2140 is a USB 3.0Type-C receptacle for data and power. In at least one embodiment, USB interface 2140 is a USB 3.0Type-A connector. In at least one embodiment, USB interface logic 2150 may include any number and type of logic that enables processing unit 2130 to connect with a device (e.g., computer 2110) via USB connector 2140.

In at least one embodiment, one or more components of the processing core 2130 may be in communication with one or more CPU, ASIC, GPU, FPGA or other hardware, circuits, or integrated circuit components including, for example, an amplifier or upsampler to amplify an image, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit configured to execute an amplifier to amplify an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels; one or more components of the processing core 2130 may use the components described in this disclosure to perform methods, operations, or instructions to generate or modify images. In at least one embodiment, at least one component shown or described with respect to fig. 21 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 22A illustrates an exemplary architecture in which a plurality of GPUs 2210-2213 are communicatively coupled to a plurality of multi-core processors 2205-2206 via high speed links 2240-2243 (e.g., bus/point-to-point interconnects, etc.). In one embodiment, the high speed links 2240-2243 support a communication throughput of 4GB/s, 30GB/s, 80GB/s or higher. Various interconnect protocols may be used including, but not limited to, pcie4.0 or 5.0 and NVLink 2.0.

Further, in one embodiment, two or more GPUs 2210-2213 are interconnected by high-speed links 2229-2230, which may be implemented using the same or different protocols/links as those used for high-speed links 2240-2243. Similarly, two or more multi-core processors 2205-2206 may be connected by a high speed link 2228, which may be a Symmetric Multiprocessor (SMP) bus running at 20GB/s, 30GB/s, 120GB/s, or higher. Alternatively, all communications between the various system components shown in FIG. 22A may be accomplished using the same protocol/link (e.g., through a common interconnect structure).

In one embodiment, each multi-core processor 2205-2206 is communicatively coupled to processor memories 2201-2202 via memory interconnects 2226-2227, respectively, and each GPU2210-2213 is communicatively coupled to GPU memories 2220-2223 via GPU memory interconnects 2250-2253, respectively. Memory interconnects 2226-2227 and 2250-2253 may utilize the same or different memory access technologies. By way of example, and not limitation, the processor memories 2201-2202 and GPU memories 2220-2223 may be volatile memory, such as Dynamic Random Access Memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR 6), or High Bandwidth Memory (HBM), and/or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portions of the processor memories 2201-2202 may be volatile memory while other portions may be non-volatile memory (e.g., using a two-level memory (2 LM) hierarchy).

As described herein, while the various processors 2205-2206 and GPUs 2210-2213 may be physically coupled to particular memories 2201-2202, 2220-2223, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, the processor memories 2201-2202 may each contain 64GB of system memory address space, and the GPU memories 2220-2223 may each contain 32GB of system memory address space (resulting in a total of 256GB of addressable memory size in this example).

Fig. 22B illustrates additional details for the interconnection between multi-core processor 2207 and graphics acceleration module 2246, according to one example embodiment. Graphics acceleration module 2246 may include one or more GPU chips integrated on a line card coupled to processor 2207 via high speed link 2240. Alternatively, the graphics acceleration module 2246 may be integrated on the same package or chip as the processor 2207.

In at least one embodiment, the illustrated processor 2207 includes a plurality of cores 2260A-2260D, each having a translation look-aside buffer 2261A-2261D and one or more caches 2262A-2262D. In at least one embodiment, cores 2260A-2260D may include various other components not shown for executing instructions and processing data. Caches 2262A-2262D may include level 1 (L1) and level 2 (L2) caches. Further, one or more shared caches 2256 may be included in caches 2262A-2262D and shared by the respective sets of cores 2260A-2260D. For example, one embodiment of processor 2207 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 2207 and the graphics acceleration module 2246 are connected to a system memory 2218, which system memory 2218 may include the processor memories 2201-2202 in FIG. 22A.

Coherency is maintained for data and instructions stored in the respective caches 2262A-2262D, 2256 and system memory 2218 via inter-core communication by the coherency bus 2264. For example, each cache may have cache coherency logic/circuitry associated therewith to communicate over coherency bus 2264 in response to detecting a read or write to a particular cache line. In one implementation, a cache snoop protocol is implemented over coherency bus 2264 to snoop (snoop) cache accesses.

In one embodiment, proxy circuit 2225 communicatively couples graphics acceleration module 2246 to coherency bus 2264, allowing graphics acceleration module 2246 to participate in the cache coherency protocol as a peer of cores 2260A-2260D. Interface 2235 provides a connection to agent circuit 2225 through high-speed link 2240 (e.g., PCIe bus, NVLink, etc.), and interface 2237 connects graphics acceleration module 2246 to link 2240.

In one implementation, accelerator integrated circuit 2236 provides cache management, memory access, context management, and interrupt management services on behalf of the plurality of graphics processing engines 2231, 2232, n of graphics acceleration module 2246. Graphics processing engines 2231, 2232, n may each include a separate Graphics Processing Unit (GPU). Optionally, the graphics processing engines 2231, 2232, n may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 2246 may be a GPU with multiple graphics processing engines 2231-2232, N, or the graphics processing engines 2231-2232, N may be individual GPUs integrated on a common package, line card, or chip.

In one embodiment, accelerator integrated circuit 2236 includes a Memory Management Unit (MMU) 2239 to perform various memory management functions, such as virtual to physical memory translations (also referred to as active to real memory translations), and memory access protocols to access system memory 2214. The MMU 2239 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual/effective to physical/real address translations. In one implementation, the cache 2238 may store commands and data for efficient access by the graphics processing engines 2231-2232, N. In one embodiment, the data stored in caches 2238 and graphics memories 2233-2234, M are kept consistent with core caches 2262A-2262D, 2256 and system memory 2214. As previously described, this task may be accomplished via proxy circuit 2225 representing caches 2238 and graphics memories 2233-2234, M (e.g., to send updates to cache 2238 regarding modifications/accesses to cache lines on processor caches 2262A-2262D, 2256, and to receive updates from cache 2238).

A set of registers 2245 store context data for threads executed by the graphics processing engines 2231, 2232, n, and the context management circuit 2248 manages thread contexts. For example, the context management circuitry 2248 may perform save and restore operations to save and restore the context of the respective threads during the context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread may be executed by the graphics processing engine). For example, the context management circuit 2248 may store the current register value to a specified region (e.g., identified by the context pointer) in the memory upon a context switch. The register value may then be restored when the context is returned. In one embodiment, the interrupt management circuit 2247 receives and processes interrupts received from system devices.

In one implementation, the MMU 2239 translates virtual/effective addresses from the graphics processing engine 2231 to real/physical addresses in the system memory 2214. One embodiment of accelerator integrated circuit 2236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 2246 and/or other accelerator devices. The graphics accelerator module 2246 may be dedicated to a single application executing on the processor 2207 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 2231, 2232, n are shared with multiple applications or Virtual Machines (VMs). In at least one embodiment, resources may be subdivided into "slices" that are assigned to different VMs and/or applications based on processing requirements and priorities associated with the VMs and/or applications.

In at least one embodiment, accelerator integrated circuit 2236 performs as a bridge to the system of graphics acceleration module 2246 and provides address translation and system memory caching services. In addition, in at least one embodiment, accelerator integrated circuit 2236 may provide a virtualization facility for host processors to manage virtualization, interrupts, and memory management for graphics processing engines 2231-2232.

Since the hardware resources of the graphics processing engines 2231-2232, N are explicitly mapped to the real address space seen by the host processor 2207, any host processor can directly address these resources using the effective address values. In one embodiment, one function of accelerator integrated circuit 2236 is to physically separate graphics processing engines 2231-2232, N so that they appear to the system as separate units.

In at least one embodiment, one or more graphics memories 2233-2234, M are coupled to each graphics processing engine 2231-2232, N, respectively. Graphics memories 2233-2234, M store instructions and data, which are processed by each graphics processing engine 2231-2232, n. Graphics memories 2233-2234, M may be volatile memories, such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR 6), or HBMs, and/or may be nonvolatile memories, such as 3D XPoint or Nano-Ram.

In one embodiment, to reduce data traffic on link 2240, biasing techniques may be used to ensure that the data stored in graphics memories 2233-2234, M is the most commonly used (at least less commonly used) data by graphics processing engines 2231-2232, N, and preferably cores 2260A-2260D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not the graphics processing engines 2231-2232, N) in the caches 2262A-2262D, 2256 of the cores and the system memory 2214.

Fig. 22C illustrates another exemplary embodiment in which accelerator integrated circuit 2236 is integrated within processor 2207. In this embodiment, graphics processing engines 2231-2232, N communicate directly with accelerator integrated circuit 2236 over high-speed link 2240 via interface 2237 and interface 2235 (again, any form of bus or interface protocol may be utilized). The accelerator integrated circuit 2236 may perform the same operations as described with respect to fig. 22B. But may have a higher throughput due to its close proximity to the coherency bus 2264 and caches 2262A-2262D, 2256. One embodiment supports different programming models, including dedicated process programming models (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by accelerator integrated circuit 2236 and programming models controlled by graphics acceleration module 2246.

In at least one embodiment, the graphics processing engines 2231-2232, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may aggregate (fuel) other application requests to the graphics processing engines 2231-2232, N, thereby providing virtualization within the VM/partition.

In at least one embodiment, the graphics processing engines 2231-2232, N may be shared by multiple VM/application partitions. In at least one embodiment, the sharing model may use a hypervisor to virtualize the graphics processing engines 2231-2232, N to allow access by each operating system. In at least one embodiment, for a single partition system without a hypervisor, the operating system has graphics processing engines 2231-2232, N. In at least one embodiment, the operating system can virtualize the graphics processing engines 2231-2232, N to provide access to each process or application.

In at least one embodiment, the graphics acceleration module 2246 or each graphics processing engine 2231-2232, N uses a process handle to select a process element. In at least one embodiment, the process elements are stored in system memory 2214 and are addressable using effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process (i.e., invoking system software to add a process element to the process element linked list) when registering its context with the graphics processing engines 2231-2232, N. In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

Fig. 22D shows an exemplary accelerator integrated slice 2290. As used herein, a "slice" includes a designated portion of the processing resources of accelerator integrated circuit 2236. Application effective address space 2282 in system memory 2218 stores process elements 2283. In one embodiment, process element 2283 is stored in response to GPU call 2281 from application 2280 executing on processor 2207. The process element 2283 contains the process state of the corresponding application 2280. The Work Descriptor (WD) 2284 contained in the process element 2283 may be a single job requested by the application, or may contain a pointer to a job queue. In at least one embodiment, WD2284 is a pointer to a job request queue in address space 2282 of the application.

The graphics acceleration module 2246 and/or the various graphics processing engines 2231-2232, N may be shared by all or a subset of the processes in the system. In at least one embodiment, an infrastructure may be included for setting a process state and sending WD2284 to the graphics acceleration module 2246 to begin a job in a virtualized environment.

In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, a single process owns the graphics acceleration module 2246 or the individual graphics processing engine 2231 in the model. Since the hypervisor initializes the accelerator integrated circuit 2236 for the owned partition when the graphics acceleration module 2246 is owned by a single process, the operating system initializes the accelerator integrated circuit 2236 for the owned process when the graphics acceleration module 2246 is assigned.

In operation, WD acquisition unit 2291 in accelerator integrated slice 2290 acquires a next WD 2284 that includes an indication of the work to be done by one or more graphics processing engines of graphics acceleration module 2246. Data from WD 2284 may be stored in registers 2245 and used by MMU 2239, interrupt management circuit 2247, and/or context management circuit 2248, as shown. For example, one embodiment of MMU 2239 includes a segment/page roaming circuit for accessing segment/page tables 2286 within OS virtual address space 2285. The interrupt management circuitry 2247 may process the interrupt event 2292 received from the graphics acceleration module 2246. When performing graphics operations, the effective address 2293 generated by the graphics processing engines 2231-2232, N is translated to a real address by the MMU 2239.

In one embodiment, the same set of registers 2245 is replicated for each graphics processing engine 2231-2232, N, and/or graphics acceleration module 2246, and the registers 2245 may be initialized by a hypervisor or operating system. Each of these replicated registers may be included in accelerator integrated slice 2290. Exemplary registers that may be initialized by the hypervisor are shown in table 1.

An exemplary register that may be initialized by the operating system is shown in Table 2.

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In one embodiment, each WD 2284 is specific to a particular graphics acceleration module 2246 and/or graphics processing engine 2231-2232, N. It contains all the information needed by the graphics processing engines 2231-2232, N to complete the work, or it can be a pointer to a memory location where the application has set a command queue for the work to complete.

FIG. 22E illustrates additional details of one exemplary embodiment of a sharing model. This embodiment includes a hypervisor real address space 2298 in which a list of process elements 2299 is stored. The hypervisor real address space 2298 may be accessed via a hypervisor 2296, which hypervisor 2296 virtualizes the graphics acceleration module engine for the operating system 2295.

In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 2246. In at least one embodiment, there are two programming models in which the graphics acceleration module 2246 is shared by multiple processes and partitions, time slice sharing and graphics orientation sharing.

In this model, hypervisor 2296 has graphics acceleration module 2246 and makes its functions available to all operating systems 2295. For graphics acceleration module 2246 to support virtualization through hypervisor 2296, graphics acceleration module 2246 may adhere to the following: (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 2246 must provide a context save and restore mechanism, (2) the graphics acceleration module 2246 ensures that the application's job requests are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 2246 provides the ability to preempt job processing, and (3) fairness among the graphics acceleration module 2246 processes must be ensured when operating in the directed shared programming model.

In at least one embodiment, application 2280 is required to make an operating system 2295 system call using the graphics acceleration module 2246 type, work Descriptor (WD), permission mask register (AMR) value, and context save/restore zone pointer (CSRP). In at least one embodiment, the graphics acceleration module 2246 type describes a target acceleration function for a system call. In at least one embodiment, the type of graphics acceleration module 2246 may be a system specific value. In at least one embodiment, WD is specifically formatted for graphics acceleration module 2246 and may take the form of a graphics acceleration module 2246 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing the work to be done by graphics acceleration module 2246. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the values passed to the operating system are similar to the application program setting AMR. In at least one embodiment, if the implementation of accelerator integrated circuit 2236 and graphics acceleration module 2246 does not support a user permission mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing AMR in the hypervisor call. In at least one embodiment, the hypervisor 2296 can selectively apply the current permission mask override register (AMOR) value prior to placing the AMR in the process element 2283. In at least one embodiment, CSRP is one of the registers 2245 that contains the effective address of an area in the address space 2282 of the application for the graphics acceleration module 2246 to save and restore the context state. The pointer is optional if there is no need to save state between jobs or when a job is preempted. In at least one embodiment, the context save/restore area may be a fixed system memory.

Upon receiving a system call, operating system 2295 may verify that application 2280 has been registered and granted permission to use graphics acceleration module 2246. Operating system 2295 then uses

The information shown in table 3 invokes the hypervisor 2296.

Upon receiving the hypervisor call, hypervisor 2296 verifies that operating system 2295 is registered and granted permission to use graphics acceleration module 2246. The hypervisor 2296 then places the process element 2283 in a linked list of process elements of the corresponding type of graphics acceleration module 2246. The process element may include the information shown in table 4.

In at least one embodiment, the hypervisor initializes a plurality of accelerator integrated slices 2290 registers 2245.

As shown in FIG. 22F, in at least one embodiment, unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 2201-2202 and GPU memories 2220-2223. In this implementation, operations executing on GPUs 2210-2213 utilize the same virtual/effective memory address space to access processor memories 2201-2202 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual/effective address space is allocated to processor memory 2201, a second portion is allocated to second processor memory 2202, a third portion is allocated to GPU memory 2220, and so on. In at least one embodiment, the entire virtual/effective memory space (sometimes referred to as an effective address space) is thus distributed in each of the processor memories 2201-2202 and the GPU memories 2220-2223, allowing any processor or GPU to access any physical memory with virtual addresses mapped to that memory.

In one embodiment, the bias/coherency management circuitry 2294A-2294E within the one or more MMUs 2239A-2239E ensures cache coherency between the one or more host processors (e.g., 2205) and the caches of the GPUs 2210-2213 and implements a bias technique that indicates the physical memory in which certain types of data should be stored. In at least one embodiment, although multiple instances of bias/coherency management circuitry 2294A-2294E are shown in fig. 22F, bias/coherency circuitry may be implemented within the MMU of one or more host processors 2205 and/or within accelerator integrated circuit 2236.

One embodiment allows the GPU attached memory 2220-2223 to be mapped as part of the system memory and accessed using Shared Virtual Memory (SVM) techniques, but without suffering from performance deficiencies associated with full system cache coherency. In at least one embodiment, the ability to access the GPU attached memories 2220-2223 as system memory without the heavy cache coherency overhead provides an advantageous operating environment for GPU offloading. This arrangement allows software of the host processor 2205 to set operands and access the results of the computation without the overhead of conventional I/O DMA data replication. Such traditional replicas include driver calls, interrupts, and memory mapped I/O (MMIO) accesses, which are all inefficient relative to simple memory accesses. In at least one embodiment, the ability to access the GPU attached memory 2220-2223 without cache coherency overhead may be critical to the execution time of the offloaded computation. For example, with a large amount of streaming write memory traffic, the cache coherency overhead may significantly reduce the effective write bandwidth seen by GPUs 2210-2213. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computing may play a role in determining the effectiveness of GPU offloading.

In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granularity structure (e.g., controlled at the granularity of memory pages) that includes 1 or 2 bits of memory pages attached per GPU. In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU attached memories 2220-2223 with or without bias caches in the GPUs 2210-2213 (e.g., frequent/recently used entries for caching bias tables). Alternatively, the entire bias table may be maintained within the GPU.

In at least one embodiment, the offset table entries associated with each access to GPU additional memory 2220-2223 are accessed prior to actually accessing the GPU memory, thereby causing the following operations. First, local requests from GPUs 2210-2213 that find their pages in the GPU bias are forwarded directly to the corresponding GPU memories 2220-2223. Local requests from the GPU that find their pages in the host bias are forwarded to the processor 2205 (e.g., over a high speed link as described above). In one embodiment, the request from the processor 2205 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests directed to GPU-biased pages may be forwarded to GPUs 2210-2213. In at least one embodiment, if the GPU is not currently using the page, the GPU may then migrate the page to the host processor bias. In at least one embodiment, the bias state of the page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, by a purely hardware-based mechanism.

One mechanism for changing the bias state employs an API call (e.g., openCL) that then invokes a device driver of the GPU, which then sends a message (or causes a command description Fu Rudui) to the GPU, directs the GPU to change bias state, and in some transitions performs a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migration from host processor 2205 bias to GPU bias, but not for the opposite migration.

In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 2205. To access these pages, the processor 2205 may request access from the GPU 2210, which GPU 2210 may or may not immediately grant access rights. Thus, to reduce communication between the processor 2205 and the GPU 2210, it is beneficial to ensure that the GPU bias pages are pages required by the GPU, rather than pages required by the host processor 2205, and vice versa.

Fig. 23 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores in accordance with various embodiments described herein. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

FIG. 23 is a diagram illustrating a chip integrated circuit that may be fabricated using one or more IP cores in accordance with at least one embodiment2300. In at least one embodiment, the integrated circuit 2300 includes one or more application processors 2305 (e.g., a CPU), at least one graphics processor 2310, and may additionally include an image processor 2315 and/or a video processor 2320, any of which may be a modular IP core. In at least one embodiment, integrated circuit 2300 includes peripheral or bus logic including USB controller 2325, UART controller 2330, SPI/SDIO controller 2335, and I ² S/I ² And a C controller 2340. In at least one embodiment, the integrated circuit 2300 may include a display device 2345 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 2350 and a Mobile Industrial Processor Interface (MIPI) display interface 2355. In at least one embodiment, storage may be provided by flash subsystem 2360, including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via the memory controller 2365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits further include an embedded security engine 2370. In at least one embodiment, at least one component shown or described with respect to fig. 23 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

24A-24B illustrate an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores, in accordance with various embodiments described herein. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

24A-24B are block diagrams illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. FIG. 24A illustrates an exemplary graphics processor 2410 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment. Fig. 24B illustrates an additional exemplary graphics processor 2440 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment. In at least one embodiment, the graphics processor 2410 of fig. 24A is a low power graphics processor core. In at least one embodiment, graphics processor 2440 of FIG. 24B is a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 2410, 2440 may be a variation of the graphics processor 1810 of fig. 18.

In at least one embodiment, graphics processor 2410 includes a vertex processor 2405 and one or more fragment processors 2415A-2415N (e.g., 2415A, 2415B, 2415C, 2415D through 2415N-1 and 2415N). In at least one embodiment, graphics processor 2410 may execute different shader programs via separate logic such that vertex processor 2405 is optimized to perform operations for the vertex shader programs, while one or more fragment processors 2415A-2415N perform fragment (e.g., pixel) shading operations for fragment or pixel or shader programs. In at least one embodiment, vertex processor 2405 performs the vertex processing stages of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, one or more fragment processors 2415A-2415N generate a frame buffer for display on a display device using primitives and vertex data generated by the vertex processor 2405. In at least one embodiment, one or more fragment processors 2415A-2415N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform similar operations to pixel shader programs provided in the Direct 3D API.

In at least one embodiment, the graphics processor 2410 additionally includes one or more Memory Management Units (MMUs) 2420A-2420B, one or more caches 2425A-2425B, and one or more circuit interconnects 2430A-2430B. In at least one embodiment, one or more MMUs 2420A-2420B provide a mapping of virtual to physical addresses for graphics processor 2410, including a mapping of virtual to physical addresses for vertex processor 2405 and/or fragment processors 2415A-2415N, which may reference vertex or image/texture data stored in memory in addition to vertex or image/texture data stored in one or more caches 2425A-2425B. In at least one embodiment, one or more of the MMUs 2420A-2420B may be synchronized with other MMUs within the system, including one or more of the MMUs associated with one or more of the application processors 2305, image processors 2315, and/or video processors 2320 of FIG. 23, such that each of the processors 2305-2320 may participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2430A-2430B enable the graphics processor 2410 to connect with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

In at least one embodiment, graphics processor 2440 includes one or more MMUs 2420A-2420B, cache 2425A-2425B and circuit interconnects 2430A-2430B of graphics processor 2410 of FIG. 24A. In at least one embodiment, graphics processor 2440 includes one or more shader cores 2455A-2455N (e.g., 2455A, 2455B, 2455C, 2455D, 2455E, 2455F-2455N-1, and 2455N) that provide a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, the plurality of shader cores may vary. In at least one embodiment, graphics processor 2440 includes inter-core task manager 2445 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2455A-2455N and block unit 2458 to accelerate block operations based on tile rendering, where rendering operations of a scene are subdivided in image space, e.g., to take advantage of local spatial consistency within the scene or to optimize use of internal caches.

In at least one embodiment, at least one component shown or described with respect to fig. 24A-24B is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIGS. 25A-25B illustrate additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, FIG. 25A illustrates a graphics core 2500 that may be included within the graphics processor 2310 of FIG. 23, and in at least one embodiment, may be unified shader cores 2455A-2455N as shown in FIG. 24B. Fig. 25B illustrates a highly parallel general purpose graphics processing unit 2530 suitable for deployment on a multi-chip module in at least one embodiment.

In at least one embodiment, graphics core 2500 includes shared instruction cache 2502, texture unit 2518, and cache/shared memory 2520, which are common to execution resources within graphics core 2500. In at least one embodiment, graphics core 2500 may include multiple slices 2501A-2501N or partitions of each core, and a graphics processor may include multiple instances of graphics core 2500. The slices 2501A-2501N may include support logic including local instruction caches 2504A-2504N, thread schedulers 2506A-2506N, thread dispatchers 2508A-2508N, and a set of registers 2510A-2510N. In at least one embodiment, the slices 2501A-2501N may include a set of additional functional units (AFUs 2512A-2512N), floating point units (FPUs 2514A-2514N), integer arithmetic logic units (ALUs 2516-2516N), address calculation units (ACUs 2513A-2513N), double precision floating point units (DPFPUs 2515A-2515N) and matrix processing units (MPUs 2517A-2517N).

In at least one embodiment, FPUs 2514A-2514N may perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 2515A-2515N may perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2516A-2516N may perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured as mixed precision operations. In at least one embodiment, MPUs 2517A-2517N may also be configured for mixed precision matrix operations, including half-precision floating point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2517-2517N can perform various matrix operations to accelerate the machine learning application framework, including enabling support for accelerated generic matrix-to-matrix multiplication (GEMM). In at least one embodiment, AFUs 2512A-2512N may perform additional logical operations that are not supported by floating point numbers or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

In at least one embodiment, at least one component shown or described with respect to fig. 25A is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 25B illustrates a general purpose processing unit (GPGPU) 2530 in at least one embodiment, which may be configured to enable highly parallel computing operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 2530 may be directly linked to other instances of the GPGPU 2530 to create multiple GPU clusters to increase training speed for deep neural networks. In at least one embodiment, the GPGPU 2530 includes a host interface 2532 to enable connection with a host processor. In at least one embodiment, host interface 2532 is a PCI Express interface. In at least one embodiment, host interface 2532 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 2530 receives commands for a host processor and uses a global scheduler 2534 to allocate execution threads associated with those commands to a set of computing clusters 2536A-2536H. In at least one embodiment, computing clusters 2536A-2536H share cache memory 2538. In at least one embodiment, cache memory 2538 may be used as a higher level cache for cache memory within compute clusters 2536A-2536H.

In at least one embodiment, GPGPU 2530 includes memories 2544A-2544B, which memories 2544A-2544B are coupled to compute clusters 2536A-2536H via a set of memory controllers 2542A-2542B. In at least one embodiment, the memories 2544A-2544B may comprise various types of memory devices including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory.

In at least one embodiment, the compute clusters 2536A-2536H each include a set of graphics cores, such as graphics core 2500 of FIG. 25A, which may include multiple types of integer and floating point logic units that can perform compute operations over a variety of computer precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each of the compute clusters 2536A-2536H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of the GPGPU 2530 may be configured to function as a compute cluster. In at least one embodiment, the communication used by the computing clusters 2536A-2536H for synchronization and data exchange varies from embodiment to embodiment. In at least one embodiment, multiple instances of the GPGPU 2530 communicate through a host interface 2532. In at least one embodiment, GPGPU 2530 includes an I/O hub 2539 that couples GPGPU 2530 with GPU link 2540 so that it can be directly connected to other instances of GPGPU 2530. In at least one embodiment, GPU link 2540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGP 2530. In at least one embodiment, GPU link 2540 is coupled with a high speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 2530 are located in separate data processing systems and communicate through a network device that is accessible through the host interface 2532. In at least one embodiment, GPU link 2540 may be configured to enable connection to a processor of a host in addition to or instead of host interface 2532.

In at least one embodiment, the GPGPU2530 may be configured to train a neural network. In at least one embodiment, the GPGPU2530 may be used within an inference platform. In at least one embodiment, in the case where GPGPU2530 is used for reasoning, GPGPU2530 may include fewer computing clusters 2536A-2536H relative to when training a neural network using GPGPU 2530. In at least one embodiment, the memory technology associated with memories 2544A-2544B can differ between reasoning and training configurations, with higher bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the reasoning configuration of GPGPU2530 may support reasoning specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

In at least one embodiment, at least one component shown or described with respect to fig. 25B is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 26 illustrates a block diagram of a computer system 2600, in accordance with at least one embodiment. In at least one embodiment, computer system 2600 includes a processing subsystem 2601 with one or more processors 2602 and a system memory 2604, the system memory 2604 communicating via an interconnection path that can include a memory hub 2605. In at least one embodiment, the memory hub 2605 may be a separate component within a chipset component or may be integrated within one or more processors 2602. In at least one embodiment, the memory hub 2605 is coupled to the I/O subsystem 2611 through a communication link 2606. In at least one embodiment, I/O subsystem 2611 includes I/O hub 2607, which may enable computer system 2600 to receive input from one or more input devices 2608. In at least one embodiment, the I/O hub 2607 may cause a display controller, which may be included in the one or more processors 2602, to provide output to the one or more display devices 2610A. In at least one embodiment, the one or more display devices 2610A coupled with the I/O hub 2607 may include local, internal, or embedded display devices.

In at least one embodiment, the processing subsystem 2601 includes one or more parallel processors 2612 coupled to a memory hub 2605 via a bus or other communication link 2613. In at least one embodiment, the communication link 2613 may be any of a number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more of the parallel processors 2612 form a computationally intensive parallel or vector processing system that may include a large number of processing cores and/or processing clusters, such as Multiple Integrated Core (MIC) processors. In at least one embodiment, the one or more parallel processors 2612 form a graphics processing subsystem that can output pixels to one of the one or more display devices 2610A coupled via the I/O hub 2607. In at least one embodiment, the one or more parallel processors 2612 may also include a display controller and a display interface (not shown) to enable direct connection to the one or more display devices 2610B.

In at least one embodiment, system storage unit 2614 may be connected to I/O hub 2607 to provide a storage mechanism for computer system 2600. In at least one embodiment, the I/O switch 2616 may be used to provide an interface mechanism to enable connection between the I/O hub 2607 and other components, such as a network adapter 2618 and/or a wireless network adapter 2619 that may be integrated into a platform, as well as various other devices that may be added by one or more additional devices 2620. In at least one embodiment, the network adapter 2618 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2619 may include one or more of Wi-Fi, bluetooth, near Field Communication (NFC), or other network devices including one or more radios.

In at least one embodiment, computer system 2600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I/O hub 2607. In at least one embodiment, the communication paths interconnecting the various components in FIG. 26 may be implemented using any suitable protocol, such as a PCI (peripheral component interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interfaces and/or protocols, such as the NV-Link high-speed interconnect or interconnect protocol.

In at least one embodiment, the one or more parallel processors 2612 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a Graphics Processing Unit (GPU). In at least one embodiment, the one or more parallel processors 2612 include circuitry optimized for general purpose processing. In at least one embodiment, components of computer system 2600 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more of the parallel processor 2612, the memory hub 2605, the processor 2602, and the I/O hub 2607 may be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, components of computer system 2600 can be integrated into a single package to form a System In Package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 2600 may be integrated into a multi-chip module (MCM) that may be interconnected with other multi-chip modules into a modular computer system. In at least one embodiment, at least one component shown or described with respect to fig. 26 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Processor and method for controlling the same

Fig. 27A illustrates a parallel processor 2700 in accordance with at least one embodiment. In at least one embodiment, the various components of parallel processor 2700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA). In at least one embodiment, the parallel processor 2700 shown is a variation of one or more of the parallel processors 2112 shown in fig. 21 according to an exemplary embodiment.

In at least one embodiment, parallel processor 2700 includes parallel processing unit 2702. In at least one embodiment, parallel processing unit 2702 includes an I/O unit 2704 that enables communication with other devices, including other instances of parallel processing unit 2702. In at least one embodiment, I/O unit 2704 may be directly connected to other devices. In at least one embodiment, the I/O unit 2704 connects with other devices using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between the memory hub 2105 and the I/O unit 2704 forms a communication link 2113. In at least one embodiment, I/O unit 2704 is connected with host interface 2706 and memory crossbar 2716, where host interface 2706 receives commands for performing processing operations and memory crossbar 2716 receives commands for performing memory operations.

In at least one embodiment, when host interface 2706 receives command buffers via I/O unit 2704, host interface 2706 can direct work operations to execute those commands to front end 2708. In at least one embodiment, front end 2708 is coupled to a scheduler 2710, which scheduler 2710 is configured to assign commands or other work items to processing cluster array 2712. In at least one embodiment, scheduler 2710 ensures that processing cluster array 2712 is properly configured and in an active state prior to assigning tasks to processing cluster array 2712. In at least one embodiment, the scheduler 2710 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2710 may be configured to perform complex scheduling and work allocation operations at coarse and fine granularity, enabling fast preemption and context switching of threads executing on processing array 2712. In at least one embodiment, host software can prove a workload for scheduling on processing array 2712 through one of a plurality of graphics processing doorbell. In at least one embodiment, the workload may then be automatically distributed on the processing array 2712 by scheduler 2710 logic within the microcontroller including scheduler 2710.

In at least one embodiment, processing cluster array 2712 may include up to "N" processing clusters (e.g., clusters 2714A, clusters 2714B-2714N). In at least one embodiment, each cluster 2714A-2714N of the processing cluster array 2712 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2710 may allocate work to clusters 2714A-2714N of processing cluster array 2712 using various scheduling and/or work allocation algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be dynamically processed by scheduler 2710 or may be aided in part by compiler logic during compilation of program logic configured to be executed by processing cluster array 2712. In at least one embodiment, different clusters 2714A-2714N of processing cluster array 2712 may be allocated for processing different types of programs or for performing different types of computations.

In at least one embodiment, processing cluster array 2712 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2712 is configured to perform general parallel computing operations. For example, in at least one embodiment, processing cluster array 2712 may include logic to perform processing tasks including filtering video and/or audio data, performing modeling operations, including physical operations, and performing data transformations.

In at least one embodiment, processing cluster array 2712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2712 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2712 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2702 may transfer data from system memory for processing via I/O unit 2704. In at least one embodiment, during processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 2722) during processing and then written back to system memory.

In at least one embodiment, when parallel processing unit 2702 is used to perform graphics processing, scheduler 2710 may be configured to divide the processing workload into approximately equal sized tasks to better allocate graphics processing operations to the multiple clusters 2714A-2714N of processing cluster array 2712. In at least one embodiment, portions of processing cluster array 2712 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2714A-2714N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 2714A-2714N for further processing.

In at least one embodiment, the processing cluster array 2712 can receive processing tasks to be performed via a scheduler 2710, which scheduler 2710 receives commands defining the processing tasks from the front end 2708. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and/or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, the scheduler 2710 may be configured to obtain an index corresponding to a task or may receive an index from the front end 2708. In at least one embodiment, front end 2708 may be configured to ensure that processing cluster array 2712 is configured to a valid state prior to launching a workload specified by an incoming command buffer (e.g., batch-buffer, push buffer, etc.).

In at least one embodiment, each of the one or more instances of parallel processing unit 2702 can be coupled with parallel processor memory 2722. In at least one embodiment, parallel processor memory 2722 may be accessed via memory crossbar 2716, which memory crossbar 2716 may receive memory requests from processing cluster array 2712 and I/O unit 2704. In at least one embodiment, memory crossbar 2716 can access parallel processor memory 2722 via memory interface 2718. In at least one embodiment, memory interface 2718 may include multiple partition units (e.g., partition unit 2720A, partition unit 2720B through partition unit 2720N), which may each be coupled to a portion of parallel processor memory 2722 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2720A-2720N are configured to be equal to the number of memory units such that a first partition unit 2720A has a corresponding first memory unit 2724A, a second partition unit 2720B has a corresponding memory unit 2724B, and an nth partition unit 2720N has a corresponding nth memory unit 2724N. In at least one embodiment, the number of partition units 2720A-2720N may not be equal to the number of memory devices.

In at least one embodiment, memory units 2724A-2724N may include various types of memory devices including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory. In at least one embodiment, memory units 2724A-2724N may also include 3D stacked memory, including but not limited to High Bandwidth Memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory units 2724A-2724N, allowing partition units 2720A-2720N to write portions of each rendering target in parallel to efficiently use the available bandwidth of parallel processor memory 2722. In at least one embodiment, local instances of parallel processor memory 2722 may be eliminated to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

In at least one embodiment, any of clusters 2714A-2714N of processing cluster array 2712 may process data to be written to any of memory cells 2724A-2724N within parallel processor memory 2722. In at least one embodiment, the memory crossbar 2716 may be configured to transmit the output of each cluster 2714A-2714N to any of the partition units 2720A-2720N or another cluster 2714A-2714N, and the clusters 2714A-2714N may perform other processing operations on the output. In at least one embodiment, each cluster 2714A-2714N may communicate with memory interface 2718 through memory crossbar 2716 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 2716 has a connection to memory interface 2718 to communicate with I/O unit 2704 and a connection to a local instance of parallel processor memory 2722 to enable processing units within different processing clusters 2714A-2714N to communicate with system memory or other memory that is not local to parallel processing unit 2702. In at least one embodiment, memory crossbar 2716 may use virtual channels to split traffic between clusters 2714A-2714N and partition units 2720A-2720N.

In at least one embodiment, multiple instances of parallel processing unit 2702 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2702 may be configured to interoperate even though the different instances have different numbers of processing cores, different numbers of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2702 may include a higher precision floating point unit relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2702 or parallel processor 2700 may be implemented in a variety of configurations and form factors, including, but not limited to, a desktop, laptop or handheld personal computer, server, workstation, gaming machine, and/or embedded system.

Fig. 27B is a block diagram of a partition unit 2720 according to at least one embodiment. In at least one embodiment, partition unit 2720 is an example of one of partition units 2720A-2720N of fig. 27A. In at least one embodiment, partition unit 2720 includes an L2 cache 2721, a frame buffer interface 2725, and a ROP 2726 (raster operations unit). L2 cache 2721 is a read/write cache configured to perform load and store operations received from memory crossbar 2716 and ROP 2726. In at least one embodiment, the L2 cache 2721 outputs read misses and urgent write-back requests to the frame buffer interface 2725 for processing. In at least one embodiment, the updates may also be sent to the frame buffer for processing via the frame buffer interface 2725. In at least one embodiment, the frame buffer interface 2725 interacts with one of the memory units in the parallel processor memory, such as memory units 2724A-2724N of fig. 27A (e.g., within parallel processor memory 2722).

In at least one embodiment, ROP2726 is a processing unit that performs raster operations, such as templates, z-tests, blending, and the like. In at least one embodiment, ROP2726 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, ROP2726 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP2726 may vary based on the statistical properties of the data to be compressed. For example, in at least one embodiment, delta color compression is performed based on depth and color data on a per tile basis.

In at least one embodiment, ROP2726 is included within each processing cluster (e.g., clusters 2714A-2714N of FIG. 27A) rather than within partition unit 2720. In at least one embodiment, read and write requests for pixel data are transmitted through memory crossbar 2716 instead of pixel segment data. In at least one embodiment, the processed graphics data may be displayed on a display device (such as one of the one or more display devices 2110 of fig. 21), routed by the processor 2102 for further processing, or routed by one of the processing entities within the parallel processor 2700 of fig. 27A for further processing.

FIG. 27C is a block diagram of a processing cluster 2714 within a parallel processing unit in accordance with at least one embodiment. In at least one embodiment, the processing clusters are examples of one of processing clusters 2714A-2714N of fig. 27A. In at least one embodiment, processing clusters 2714 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single Instruction Multithreading (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

In at least one embodiment, the operation of processing cluster 2714 may be controlled by pipeline manager 2732, which distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2732 receives instructions from scheduler 2710 of fig. 27A, and manages execution of these instructions through graphics multiprocessor 2734 and/or texture unit 2736. In at least one embodiment, graphics multiprocessor 2734 is an illustrative example of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within processing cluster 2714. In at least one embodiment, one or more instances of graphics multiprocessor 2734 may be included within processing cluster 2714. In at least one embodiment, graphics multiprocessor 2734 may process data, and data crossbar 2740 may be used to distribute the processed data to one of a plurality of possible purposes, including other shader units. In at least one embodiment, pipeline manager 2732 may facilitate distribution of processed data by specifying a destination of the processed data to be distributed via data crossbar 2740.

In at least one embodiment, each graphics multiprocessor 2734 within processing cluster 2714 may include the same set of function execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined fashion, where a new instruction may be issued before a previous instruction completes. In at least one embodiment, the function execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, boolean operations, shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

In at least one embodiment, instructions transferred to the processing cluster 2714 constitute threads. In at least one embodiment, the set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a generic program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within graphics multiprocessor 2734. In at least one embodiment, the thread group may include fewer threads than the plurality of processing engines within the graphics multiprocessor 2734. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than multiple processing engines within graphics multiprocessor 2734. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 2734, processing may be performed in successive clock cycles. In at least one embodiment, multiple thread groups may be concurrently executing on graphics multiprocessor 2734.

In at least one embodiment, graphics multiprocessor 2734 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2734 may relinquish the internal cache and use the cache memory (e.g., L1 cache 2748) within processing cluster 2714. In at least one embodiment, each graphics multiprocessor 2734 may also access an L2 cache within partition units (e.g., partition units 2720A-2720N of FIG. 27A) that are shared among all processing clusters 2714 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2734 may also access off-chip global memory, which may include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit 2702 may be used as global memory. In at least one embodiment, processing cluster 2714 includes multiple instances of graphics multiprocessor 2734, which may share common instructions and data that may be stored in L1 cache 2748.

In at least one embodiment, each processing cluster 2714 may include a memory management unit ("MMU") 2745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2745 can reside within memory interface 2718 of FIG. 27A. In at least one embodiment, MMU 2745 includes a set of Page Table Entries (PTEs) for mapping virtual addresses to physical addresses of blocks (tiles) and optionally to cache line indexes. In at least one embodiment, MMU 2745 may include an address Translation Lookaside Buffer (TLB) or may reside in graphics multiprocessor 2734 or an L1 cache or a cache within processing cluster 2714. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or miss.

In at least one embodiment, processing clusters 2714 may be configured such that each graphics multiprocessor 2734 is coupled to texture unit 2736 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2734, and fetched from an L2 cache, local parallel processor memory, or system memory, as desired. In at least one embodiment, each graphics multiprocessor 2734 outputs processed tasks to data crossbar 2740 for providing the processed tasks to another processing cluster 2714 for further processing or for storing the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2716. In at least one embodiment, preROP 2742 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 2734, direct the data to ROP units, which may be located with partition units described herein (e.g., partition units 2720A-2720N of FIG. 27A). In at least one embodiment, the PreROP 2742 unit may perform optimization for color blending, organize pixel color data, and perform address translation. In at least one embodiment, at least one component shown or described with respect to fig. 27A-27C is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 27D illustrates a graphics multiprocessor 2734 in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor 2734 is coupled with pipeline manager 2732 that processes clusters 2714. In at least one embodiment, graphics multiprocessor 2734 has execution pipelines including, but not limited to, instruction cache 2752, instruction unit 2754, address mapping unit 2756, register file 2758, one or more General Purpose Graphics Processing Unit (GPGPU) cores 2762, and one or more load/store units 2766.GPGPU core 2762 and load/store unit 2766 are coupled to cache memory 2772 and shared memory 2770 via memory and cache interconnect 2768.

In at least one embodiment, instruction cache 2752 receives a stream of instructions to execute from pipeline manager 2732. In at least one embodiment, instructions are cached in instruction cache 2752 and dispatched for execution by instruction unit 2754. In at least one embodiment, the instruction unit 2754 may dispatch instructions as a thread group (e.g., a thread bundle), each thread of the thread group being assigned to a different execution unit within the GPGPU core 2762. In at least one embodiment, an instruction may access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2756 may be used to translate addresses in a unified address space into different memory addresses that may be accessed by load/store unit 2766.

In at least one embodiment, register file 2758 provides a set of registers for the functional units of graphics multiprocessor 2734. In at least one embodiment, register file 2758 provides temporary storage for operands of the data paths of the functional units (e.g., GPGPU core 2762, load/store unit 2766) connected to graphics multiprocessor 2734. In at least one embodiment, the register file 2758 is divided among each functional unit such that a dedicated portion of the register file 2758 is allocated for each functional unit. In at least one embodiment, register file 2758 is divided among different thread bundles being executed by graphics multiprocessor 2734.

In at least one embodiment, the GPGPU cores 2762 may each include a Floating Point Unit (FPU) and/or an integer Arithmetic Logic Unit (ALU) for executing instructions of the graphics multiprocessor 2734. In at least one embodiment, the GPGPU cores 2762 may be similar in architecture or may differ in architecture. In at least one embodiment, the first portion of the GPGPU core 2762 includes a single-precision FPU and integer ALUs, while the second portion of the GPGPU core includes a dual-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating point algorithms or enable variable precision floating point algorithms. In at least one embodiment, graphics multiprocessor 2734 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores 2762 may also include fixed or special function logic.

In at least one embodiment, the GPGPU core 2762 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU core 2762 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for a GPGPU core may be generated by a shader compiler at compile time, or automatically when executing programs written and compiled for Single Program Multiple Data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

In at least one embodiment, memory and cache interconnect 2768 is an interconnect network that connects each functional unit of graphics multiprocessor 2734 to register file 2758 and shared memory 2770. In at least one embodiment, memory and cache interconnect 2768 is a crossbar interconnect that allows load/store unit 2766 to implement load and store operations between shared memory 2770 and register file 2758. In at least one embodiment, the register file 2758 may operate at the same frequency as the GPGPU core 2762, such that the latency of data transfer between the GPGPU core 2762 and the register file 2758 is very low. In at least one embodiment, shared memory 2770 may be used to enable communication between threads executing on functional units within graphics multiprocessor 2734. In at least one embodiment, cache memory 2772 may be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2736. In at least one embodiment, shared memory 2770 may also be used as a program managed cache. In at least one embodiment, threads executing on the GPGPU core 2762 may also programmatically store data in shared memory in addition to automatically cached data stored in the cache memory 2772.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various General Purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor/core via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core through an internal processor bus/interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPUs are connected, the processor core may allocate work to the GPUs in the form of command/instruction sequences contained in the work descriptors. In at least one embodiment, the GPU then uses dedicated circuitry/logic to efficiently process these commands/instructions. In at least one embodiment, at least one component shown or described with respect to fig. 27D is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 28 illustrates a multi-GPU computing system 2800 in accordance with at least one embodiment. In at least one embodiment, a multi-GPU computing system 2800 can include a processor 2802 coupled to a plurality of General Purpose Graphics Processing Units (GPGPUs) 2806A-D via a host interface switch 2804. In at least one embodiment, host interface switch 2804 is a PCI Express switch device that couples processor 2802 to a PCI Express bus, through which processor 2802 may communicate with GPGPGPUs 2806A-D. GPGPUs 2806A-D may be interconnected via a set of high speed P2P GPU-to-GPU links 2816. In at least one embodiment, GPU-to-GPU link 2816 is connected to each of GPGPUs 2806A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 2816 enables direct communication between each GPGPU 2806A-D without communication through a host interface bus 2804 to which the processor 2802 is connected. In at least one embodiment, host interface bus 2804 remains available for system memory access or to communicate with other instances of multi-GPU computing system 2800, e.g., via one or more network devices, with GPU-to-GPU traffic directed to P2P GPU link 2816. While in at least one embodiment GPGPUs 2806A-D are connected to processor 2802 via host interface switch 2804, in at least one embodiment processor 2802 includes direct support for P2P GPU link 2816 and may be connected directly to GPGPUs 2806A-D. In at least one embodiment, at least one component shown or described with respect to fig. 28 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 29 is a block diagram of a graphics processor 2900 according to at least one embodiment. In at least one embodiment, graphics processor 2900 includes ring interconnect 2902, pipeline front end 2904, media engine 2937, and graphics cores 2980A-2980N. In at least one embodiment, ring interconnect 2902 couples graphics processor 2900 to other processing units, including other graphics processors or one or more general purpose processor cores. In at least one embodiment, graphics processor 2900 is one of many processors integrated within a multi-core processing system.

In at least one embodiment, graphics processor 2900 receives multiple batches of commands via ring interconnect 2902. In at least one embodiment, the incoming commands are interpreted by a command stream converter (command stream) 2903 in the pipeline front end 2904. In at least one embodiment, graphics processor 2900 includes extensible execution logic for performing 3D geometry processing and media processing via graphics cores 2980A-2980N. In at least one embodiment, for 3D geometry processing commands, command stream converter 2903 provides commands to geometry pipeline 2936. In at least one embodiment, for at least some media processing commands, command stream converter 2903 provides commands to video front end 2934, which is coupled to media engine 2937. In at least one embodiment, the media engine 2937 includes a Video Quality Engine (VQE) 2930 for video and image post-processing, and a multi-format encoding/decoding (MFX) 2933 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2936 and the media engine 2937 each generate execution threads for thread execution resources provided by at least one graphics core 2980A.

In at least one embodiment, graphics processor 2900 includes extensible thread execution resources having (metering) modular cores 2980A-2980N (sometimes referred to as core slices), each having multiple sub-cores 2950A-550N,2960A-2960N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2900 may have any number of graphics cores 2980A through 2980N. In at least one embodiment, graphics processor 2900 includes a graphics core 2980A having at least a first sub-core 2950A and a second sub-core 2960A. In at least one embodiment, graphics processor 2900 is a low power processor with a single sub-core (e.g., 2950A). In at least one embodiment, graphics processor 2900 includes a plurality of graphics cores 2980A-2980N, each including a set of first sub-cores 2950A-2950N and a set of second sub-cores 2960A-2960N. In at least one embodiment, each of the first sub-cores 2950A-2950N includes at least a first set of execution units 2952A-2952N and media/texture samplers 2954A-2954N. In at least one embodiment, each of the second sub-cores 2960A-2960N includes at least a second set of execution units 2962A-2962N and samplers 2964A-2964N. In at least one embodiment, each sub-core 2950A-2950N,2960A-2960N shares a set of shared resources 2970A-2970N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, at least one component shown or described with respect to fig. 29 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 30 is a block diagram illustrating a microarchitecture for a processor 3000 in accordance with at least one embodiment, the processor 3000 may include logic to execute instructions. In at least one embodiment, processor 3000 may execute instructions, including x86 instructions, ARM instructions, special purpose instructions for an Application Specific Integrated Circuit (ASIC), and the like. In at least one embodiment, the processor 3010 may include registers for storing packaged data, such as a 64-bit wide MMX in a microprocessor enabled with MMX technology as Intel corporation of Santa Clara, calif ^TM A register. In at least one embodiment, MMX registers available in integer and floating point forms may be run with packed data elements accompanying single instruction multiple data ("SIMD") and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher version (commonly referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, the processor 3010 may execute instructions to accelerate machine learning or deep learning algorithms, training, or reasoning.

In at least one embodiment, processor 3000 includes an in-order front end ("front end") 3001 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, the front end 3001 may comprise several units. In at least one embodiment, instruction pre-fetcher 3026 fetches instructions from memory and provides instructions to instruction decoder 3028, which instruction decoder 3028 in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 3028 decodes the received instructions into one or more operations that are machine executable, so-called "micro-instructions" or "micro-operations" (also referred to as "micro-operations" or "micro-instructions"). In at least one embodiment, the instruction decoder 3028 parses the instruction into an opcode and corresponding data and control fields that may be used by the microarchitecture to perform operations in accordance with at least one embodiment. In at least one embodiment, the trace cache 3030 may assemble decoded microinstructions into a program ordered sequence or trace in the microinstruction queue 3034 for execution. In at least one embodiment, when trace cache 3030 encounters a complex instruction, microcode ROM 3032 provides the microinstructions required to complete the operation.

In at least one embodiment, some instructions may be converted to single micro-operations, while other instructions require several micro-operations to complete the entire operation. In at least one embodiment, if more than four microinstructions are required to complete an instruction, instruction decoder 3028 may access microcode ROM3032 to execute the instruction. In at least one embodiment, instructions may be decoded into a small number of microinstructions for processing at instruction decoder 3028. In at least one embodiment, if multiple microinstructions are required to complete the operation, the instructions may be stored in microcode ROM 3032. In at least one embodiment, trace cache 3030 references an entry point programmable logic array ("PLA") to determine a correct microinstruction pointer for reading a microcode sequence from microcode ROM3032 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after microcode ROM3032 completes ordering the micro-operations for the instructions, the front end 3001 of the machine may resume fetching micro-operations from trace cache 3030.

In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 3003 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as instructions descend down the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 3003 includes, but is not limited to, a allocator/register renamer 3040, a memory micro instruction queue 3042, an integer/floating point micro instruction queue 3044, a memory scheduler 3046, a fast scheduler 3002, a slow/general floating point scheduler ("slow/general FP scheduler") 3004, and a simple floating point scheduler ("simple FP scheduler") 3006. In at least one embodiment, the fast scheduler 3002, the slow/general floating point scheduler 3004, and the simple floating point scheduler 3006 are also collectively referred to as "micro instruction schedulers 3002, 3004, 3006". In at least one embodiment, the allocator/register renamer 3040 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, allocator/register renamer 3040 renames logical registers to entries in register files. In at least one embodiment, the allocator/register renamer 3040 also allocates an entry for each of two micro instructions in one of the two micro instruction queues, the memory micro instruction queue 3042 for memory operations and the integer/floating point micro instruction queue 3044 for non-memory operations, ahead of the memory scheduler 3046 and the micro instruction schedulers 3002, 3004, 3006. In at least one embodiment, the micro instruction schedulers 3002, 3004, 3006 determine when to prepare to execute a micro instruction based on the readiness of their dependent input register operand sources and the availability of execution resource micro instructions that need to be completed. The fast scheduler 3002 of at least one embodiment may schedule on each half of the main clock cycle, while the slow/general floating point scheduler 3004 and the simple floating point scheduler 3006 may schedule once per main processor clock cycle. In at least one embodiment, the micro instruction scheduler 3002, 3004, 3006 arbitrates for the scheduling ports to schedule micro instructions for execution.

In at least one embodiment, execution blocks 3011 include, but are not limited to, integer register file/bypass network 3008, floating point register file/bypass network ("FP register file/bypass network") 3010, address generation units ("AGUs") 3012 and 3014, fast arithmetic logic units ("fast ALUs") 3016 and 3018, slow arithmetic logic unit ("slow ALU") 3020, floating point ALU ("FP") 3022, and floating point move unit ("FP move") 3024. In at least one embodiment, the integer register file/bypass network 3008 and floating point register file/bypass network 3010 are also referred to herein as "register files 3008, 3010". In at least one embodiment, the AGUs 3012 and 3014, the fast ALUs 3016 and 3018, the slow ALU 3020, the floating point ALU 3022, and the floating point move unit 3024 are also referred to herein as "execution units 3012, 3014, 3016, 3018, 3020, 3022, and 3024". In at least one embodiment, execution block 3011 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

In at least one embodiment, register files 3008, 3010 may be disposed between microinstruction schedulers 3002, 3004, 3006 and execution units 3012, 3014, 3016, 3018, 3020, 3022, and 3024. In at least one embodiment, the integer register file/bypass network 3008 performs the integer operation. In at least one embodiment, the floating point register file/tributary network 3010 performs floating point operations. In at least one embodiment, each of the register files 3008, 3010 may include, but is not limited to, a bypass network that may bypass or forward the just completed result that has not been written to the register file to a new dependent object. In at least one embodiment, the register files 3008, 3010 may communicate data with each other. In at least one embodiment, the integer/bypass network 3008 may include, but is not limited to, two separate register files, one for low order 32-bit data and a second for high order 32-bit data. In at least one embodiment, the floating point register file/bypass network 3010 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands of width 64 to 128 bits.

In at least one embodiment, execution units 3012, 3014, 3016, 3018, 3020, 3022, 3024 may execute instructions. In at least one embodiment, the register files 3008, 3010 store integer and floating point data operand values that the micro-instructions need to execute. In at least one embodiment, processor 3000 may include, but is not limited to, any number of execution units 3012, 3014, 3016, 3018, 3020, 3022, 3024, and combinations thereof. In at least one embodiment, floating point ALU 3022 and floating point move unit 3024 may perform floating point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 3022 may include, but is not limited to, a 64-bit by 64-bit floating point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating point values may be processed with floating point hardware. In at least one embodiment, ALU operations may be passed to the fast ALUs 3016, 3018. In at least one embodiment, the fast ALUs 3016, 3018 may perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter the slow ALU 3020, as the slow ALU 3020 may include, but is not limited to, integer execution hardware for long delay type operations, such as multipliers, shifts, tag logic, and branch processing. In at least one embodiment, memory load/store operations may be performed by AGUS 3012, 3014. In at least one embodiment, the fast ALU3016, the fast ALU 3018, and the slow ALU 3020 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU3016, fast ALU 3018, and slow ALU 3020 may be implemented to support various data bit sizes including sixteen, thirty-two, 128, 306, etc. In at least one embodiment, the floating point ALU 3022 and floating point move unit 3024 may be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 3022 and floating point move unit 3024 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, the micro instruction schedulers 3002, 3004, 3006 schedule dependent operations before parent loads complete execution. In at least one embodiment, processor 3000 may also include logic to handle memory misses, as micro-instructions may be speculatively scheduled and executed in processor 3000. In at least one embodiment, if a data load in the data cache misses, there may be a dependent operation running in the pipeline that causes the scheduler to temporarily have no correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions using incorrect data. In at least one embodiment, it may be desirable to replay the dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

In at least one embodiment, the term "register" may refer to an on-board processor memory location that may be used as part of an instruction that identifies an operand. In at least one embodiment, the registers may be those that may be used externally to the processor (from a programmer's perspective). In at least one embodiment, the registers may not be limited to a particular type of circuit. Rather, in at least one embodiment, registers may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within a processor using a variety of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and so forth. In at least one embodiment, the integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data. In at least one embodiment, at least one component shown or described with respect to fig. 30 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 31 illustrates a block diagram of a processing system in accordance with at least one embodiment. In at least one embodiment, system 3100 includes one or more processors 3102 and one or more graphics processors 3108, and may be a single processor desktop system, a multiprocessor workstation system, or a server system with a large number of processors 3102 or processor cores 3107. In at least one embodiment, system 3100 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

In at least one embodiment, system 3100 can include or be incorporated into a server-based gaming platform, including a game console, a mobile game console, a handheld game console, or an online game console. In at least one embodiment, system 3100 is a mobile phone, smart phone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 3100 can further include a wearable device coupled with or integrated in the wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 3100 is a television or set-top box device having one or more processors 3102 and a graphical interface generated by one or more graphics processors 3108.

In at least one embodiment, the one or more processors 3102 each include one or more processor cores 3107 to process instructions that, when executed, perform operations for the system and user software. In at least one embodiment, each of the one or more processor cores 3107 is configured to process a particular instruction set 3109. In at least one embodiment, the instruction set 3109 may facilitate Complex Instruction Set Computing (CISC), reduced Instruction Set Computing (RISC), or computing by Very Long Instruction Words (VLIW). In at least one embodiment, the processor cores 3107 may each process a different instruction set 3109, which may include instructions that help emulate other instruction sets. In at least one embodiment, the processor core 3107 may also include other processing devices, such as a Digital Signal Processor (DSP).

In at least one embodiment, the processor 3102 includes a cache memory 3104. In at least one embodiment, the processor 3102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among the various components of processor 3102. In at least one embodiment, the processor 3102 also uses an external cache (e.g., a level three (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among the processor cores 3107 using known cache coherency techniques. In at least one embodiment, a register file 3106 is additionally included in the processor 3102, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 3106 may comprise general purpose registers or other registers.

In at least one embodiment, one or more processors 3102 are coupled with one or more interface buses 3110 to transmit communication signals, such as address, data, or control signals, between the processors 3102 and other components in the system 3100. In at least one embodiment, interface bus 3110 may be a processor bus in one embodiment, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface 3110 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 3102 includes an integrated memory controller 3116 and a platform controller hub 3130. In at least one embodiment, memory controller 3116 facilitates communication between memory devices and other components of processing system 3100, while Platform Controller Hub (PCH) 3130 provides connectivity to input/output (I/O) devices via a local I/O bus.

In at least one embodiment, memory device 3120 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or have suitable capabilities to function as a processor memory. In at least one embodiment, the storage device 3120 may serve as a system memory for the processing system 3100 to store data 3122 and instructions 3121 for use when one or more processors 3102 execute applications or processes. In at least one embodiment, memory controller 3116 is also coupled to an optional external graphics processor 3112, which may communicate with one or more graphics processors 3108 of processors 3102 to perform graphics and media operations. In at least one embodiment, a display device 3111 may be connected to the processor 3102. In at least one embodiment, the display device 3111 may include one or more of internal display devices, such as in a mobile electronic device or a laptop device or an external display device connected through a display interface (e.g., display port (DisplayPort), etc.). In at least one embodiment, the display device 3111 may include a Head Mounted Display (HMD), such as a stereoscopic display device used in a Virtual Reality (VR) application or an Augmented Reality (AR) application.

In at least one embodiment, platform controller hub 3130 enables peripheral devices to connect to storage device 3120 and processor 3102 through a high speed I/O bus. In at least one embodiment, the I/O peripherals include, but are not limited to, an audio controller 3146, a network controller 3134, a firmware interface 3128, a wireless transceiver 3126, a touch sensor 3125, a data storage 3124 (e.g., hard drive, flash memory, etc.). In at least one embodiment, data storage device 3124 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 3125 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 3126 may be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 3128 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 3134 may enable network connections to wired networks. In at least one embodiment, a high performance network controller (not shown) is coupled to interface bus 3110. In at least one embodiment, audio controller 3146 is a multi-channel high definition audio controller. In at least one embodiment, the processing system 3100 includes an optional legacy I/O controller 3140 for coupling legacy (e.g., personal System 2 (PS/2)) devices to the system. In at least one embodiment, the platform controller hub 3130 may also be connected to one or more Universal Serial Bus (USB) controllers 3142 that connect input devices, such as a keyboard and mouse 3143 combination, a camera 3144, or other USB input devices.

In at least one embodiment, the memory controller 3116 and an instance of the platform controller hub 3130 may be integrated into a discrete external graphics processor, such as external graphics processor 3112. In at least one embodiment, the platform controller hub 3130 and/or the memory controller 3116 may be external to the one or more processors 3102. For example, in at least one embodiment, system 3100 may include an external memory controller 3116 and a platform controller hub 3130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset in communication with processor 3102. In at least one embodiment, at least one component shown or described with respect to fig. 31 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 32 is a block diagram of a processor 3200 having one or more processor cores 3202A-3202N, an integrated memory controller 3214, and an integrated graphics processor 3208, in accordance with at least one embodiment. In at least one embodiment, the processor 3200 may contain additional cores, up to and including additional cores 3202N, represented by dashed boxes. In at least one embodiment, each processor core 3202A-3202N includes one or more internal cache molecules 3204A-3204N. In at least one embodiment, each processor core may also access one or more shared cache units 3206.

In at least one embodiment, internal cache units 3204A-3204N and shared cache unit 3206 represent a cache memory hierarchy within processor 3200. In at least one embodiment, cache memory units 3204A-3204N may include at least one level of instruction and data caches within each processor core and one or more levels of cache in a shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, where the highest level of cache preceding external memory is categorized as LLC. In at least one embodiment, the cache coherency logic maintains coherency between the various cache units 3206 and 3204A-3204N.

In at least one embodiment, the processor 3200 may also include a set of one or more bus controller units 3216 and a system agent core 3210. In at least one embodiment, one or more bus controller units 3216 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 3210 provides management functions for the various processor components. In at least one embodiment, the system agent core 3210 includes one or more integrated memory controllers 3214 to manage access to various external memory devices (not shown).

In at least one embodiment, one or more of the processor cores 3202A-3202N include support for simultaneous multithreading. In at least one embodiment, the system agent core 3210 includes components for coordinating and operating the cores 3202A-3202N during multi-threaded processing. In at least one embodiment, the system agent core 3210 may additionally include a Power Control Unit (PCU) that includes logic and components for adjusting one or more power states of the processor cores 3202A-3202N and the graphics processor 3208.

In at least one embodiment, the processor 3200 further comprises a graphics processor 3208 for performing graphics processing operations. In at least one embodiment, graphics processor 3208 is coupled with shared cache unit 3206 and system agent core 3210, which includes one or more integrated memory controllers 3214. In at least one embodiment, the system agent core 3210 also includes a display controller 3211 for driving graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 3211 may also be a separate module coupled with the graphics processor 3208 via at least one interconnect, or may be integrated within the graphics processor 3208.

In at least one embodiment, a ring-based interconnect unit 3212 is used to couple internal components of the processor 3200. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, graphics processor 3208 is coupled with ring interconnect 3212 via I/O link 3213.

In at least one embodiment, the I/O links 3213 represent at least one of a variety of I/O interconnects, including encapsulated I/O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 3218 (e.g., eDRAM modules). In at least one embodiment, each of the processor cores 3202A-3202N and the graphics processor 3208 use the embedded memory module 3218 as the shared last level cache.

In at least one embodiment, processor cores 3202A-3202N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 3202A-3202N are heterogeneous in terms of Instruction Set Architecture (ISA), with one or more processor cores 3202A-3202N executing a common instruction set and one or more other processor cores 3202A-3202N executing a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 3202A-3202N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 3200 may be implemented on one or more chips or as a SoC integrated circuit. In at least one embodiment, at least one component shown or described with respect to fig. 32 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 33 is a block diagram of a graphics processor 3300, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 3300 communicates with registers on the graphics processor 3300 and commands placed in memory via a memory mapped I/O interface. In at least one embodiment, the graphics processor 3300 includes a memory interface 3314 for accessing memory. In at least one embodiment, the memory interface 3314 is an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In at least one embodiment, the graphics processor 3300 also includes a display controller 3302 for driving display output data to the display device 3320. In at least one embodiment, the display controller 3302 includes hardware for one or more overlay planes of the display device 3320 and a combination of multi-layer video or user interface elements. In at least one embodiment, the display device 3320 may be an internal or external display device. In at least one embodiment, the display device 3320 is a head mounted display device, such as a Virtual Reality (VR) display device or an Augmented Reality (AR) display device. In at least one embodiment, the graphics processor 3300 includes a video codec engine 3306 to encode, decode, or transcode media into, from, or between one or more media encoding formats, including, but not limited to, moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), advanced Video Coding (AVC) formats (e.g., h.264/MPEG-4AVC, and american Society of Motion Picture Television Engineers (SMPTE) 421M/VC-1) and Joint Photographic Experts Group (JPEG) formats (e.g., JPEG) and Motion JPEG (MJPEG) formats.

In at least one embodiment, the graphics processor 3300 includes a block image transfer (BLIT) engine 3304 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of a Graphics Processing Engine (GPE) 3310. In at least one embodiment, GPE 3310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In at least one embodiment, the GPE 3310 includes a 3D pipeline 3312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, the 3D pipeline 3312 includes programmable and fixed functional elements that perform various tasks and/or spawn threads of execution to the 3D/media subsystem 3315. Although the 3D pipeline 3312 may be used to perform media operations, in at least one embodiment the GPE 3310 also includes a media pipeline 3316 for performing media operations such as video post-processing and image enhancement.

In at least one embodiment, the media pipeline 3316 includes a fixed function or programmable logic unit for performing one or more specialized media operations such as video decoding acceleration, video de-interlacing and video encoding acceleration in lieu of or on behalf of the video codec engine 3306. In at least one embodiment, the media pipeline 3316 also includes a thread generation unit for generating threads for execution on the 3D/media subsystem 3315. In at least one embodiment, the spawned threads perform computation of media operations on one or more graphics execution units contained in the 3D/media subsystem 3315.

In at least one embodiment, the 3D/media subsystem 3315 includes logic for executing threads spawned by the 3D pipeline 3312 and the media pipeline 3316. In at least one embodiment, the 3D pipeline 3312 and media pipeline 3316 send thread execution requests to the 3D/media subsystem 3315, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D/media subsystem 3315 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 3315 also includes a shared memory including registers and addressable memory to share data between threads and store output data. In at least one embodiment, at least one component shown or described with respect to fig. 33 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 34 is a block diagram of a graphics processing engine 3410 of a graphics processor in accordance with at least one embodiment. In at least one embodiment, graphics Processing Engine (GPE) 3410 is a version of GPE 2810 shown in fig. 28. In at least one embodiment, the media pipeline 3416 is optional and may not be explicitly included in the GPE 3410. In at least one embodiment, a separate media and/or image processor is coupled to the GPE 3410.

In at least one embodiment, the GPE 3410 is coupled to or includes a command stream converter 3403 that provides a command stream to the 3D pipeline 3412 and/or the media pipeline 3416. In at least one embodiment, the command stream translator 3403 is coupled to memory, which may be system memory or one or more of an internal cache memory and a shared cache memory. In at least one embodiment, the command stream transformer 3403 receives commands from memory and sends the commands to the 3D pipeline 3412 and/or the media pipeline 3416. In at least one embodiment, the commands are instructions, primitives, or micro-operations fetched from a ring buffer that stores commands for the 3D pipeline 3412 and the media pipeline 3416. In at least one embodiment, the ring buffer may further include a batch command buffer storing a plurality of commands for each batch. In at least one embodiment, the commands for the 3D pipeline 3412 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 3412 and/or image data and memory objects for the media pipeline 3416. In at least one embodiment, the 3D pipeline 3412 and the media pipeline 3416 process commands and data by performing operations or by dispatching one or more threads of execution to the graphics core array 3414. In at least one embodiment, graphics core array 3414 includes one or more graphics core blocks (e.g., one or more graphics cores 3415A, one or more graphics cores 3415B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources including general purpose and graphics specific execution logic for performing graphics and computing operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

In at least one embodiment, the 3D pipeline 3412 includes fixed functionality and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 3414. In at least one embodiment, the graphics core array 3414 provides uniform execution resource blocks for processing shader programs. In at least one embodiment, multipurpose execution logic (e.g., execution units) within graphics cores 3415A-3415B of graphics core array 3414 includes support for various 3D API shader languages, and may execute multiple simultaneous threads of execution associated with multiple shaders.

In at least one embodiment, the graphics core array 3414 further includes execution logic to perform media functions, such as video and/or image processing. In at least one embodiment, the execution unit includes general logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations.

In at least one embodiment, the output data may output data to memory in a Unified Return Buffer (URB) 3418, the output data generated by threads executing on the graphics core array 3414. In at least one embodiment, the URB 3418 may store data for multiple threads. In at least one embodiment, the URB 3418 may be used to send data between different threads executing on the graphics core array 3414. In at least one embodiment, the URB 3418 can also be used for synchronization between threads on the graphics core array 3414 and fixed function logic within the shared function logic 3420.

In at least one embodiment, the graphics core array 3414 is scalable such that the graphics core array 3414 includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 3410. In at least one embodiment, the execution resources are dynamically scalable such that the execution resources may be enabled or disabled as desired.

In at least one embodiment, graphics core array 3414 is coupled to shared function logic 3420, which includes a plurality of resources shared between graphics cores in graphics core array 3414. In at least one embodiment, the shared functionality performed by shared functionality logic 3420 is embodied in hardware logic units that provide dedicated supplemental functionality to graphics core array 3414. In at least one embodiment, shared functional logic 3420 includes, but is not limited to, sampler 3421, math 3422, and inter-thread communication (ITC) logic 3423. In at least one embodiment, one or more caches 3425 are included in or coupled to shared function logic 3420.

In at least one embodiment, shared functionality is used if the need for dedicated functionality is not sufficient for inclusion in graphics core array 3414. In at least one embodiment, a single instance of a dedicated function is used in shared function logic 3420 and shared among other execution resources within graphics core array 3414. In at least one embodiment, specific sharing functions may be included within the sharing function logic 3416 within the graphics core array 3414, the specific sharing functions being within the sharing function logic 3420 that is widely used by the graphics core array 3414. In at least one embodiment, shared function logic 3416 within graphics core array 3414 may include some or all of the logic within shared function logic 3420. In at least one embodiment, all logic elements within shared function logic 3420 may be replicated within shared function logic 3416 of graphics core array 3414. In at least one embodiment, shared function logic 3420 is excluded to support shared function logic 3416 within graphics core array 3414. In at least one embodiment, at least one component shown or described with respect to fig. 34 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 35 is a block diagram of hardware logic of a graphics processor core 3500 in accordance with at least one embodiment described herein. In at least one embodiment, graphics processor core 3500 is included within a graphics core array. In at least one embodiment, graphics processor cores 3500 (sometimes referred to as core slices) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 3500 is an example of one graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelope. In at least one embodiment, each graphics core 3500 can include a fixed function block 3530 coupled with a plurality of sub-cores 3501A-3501F, also referred to as sub-slices, which include modules of general purpose and fixed function logic.

In at least one embodiment, the fixed function block 3530 includes a geometry and fixed function pipeline 3536, e.g., in a lower performance and/or lower power graphics processor implementation, the geometry and fixed function pipeline 3536 may be shared by all sub-cores in the graphics processor 3500. In at least one embodiment, the geometry and fixed function pipeline 3536 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages unified return buffers.

In at least one embodiment of the fixation, the fixation block 3530 further comprises a graphics SoC interface 3537, a graphics microcontroller 3538, and a media pipeline 3539. In at least one embodiment, the graphics SoC interface 3537 provides an interface between the graphics core 3500 and other processor cores in the integrated circuit system on chip. In at least one embodiment, graphics microcontroller 3538 is a programmable sub-processor that can be configured to manage various functions of graphics processor 3500, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 3539 includes logic that facilitates decoding, encoding, preprocessing, and/or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 3539 implements media operations via requests to compute or sample logic within the sub-cores 3501-3501F.

In at least one embodiment, the SoC interface 3537 enables the graphics core 3500 to communicate with a general-purpose application processor core (e.g., CPU) and/or other components within the SoC, including memory hierarchy elements such as shared last-level cache, system RAM, and/or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 3537 can also enable communication with fixed function devices (e.g., camera imaging pipelines) within the SoC, and enable the use and/or implementation of global memory atoms that can be shared between the graphics core 3500 and the CPU inside the SoC. In at least one embodiment, soC interface 3537 may also implement power management control for graphics core 3500 and enable interfaces between the clock domains of graphics core 3500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 3537 enables receipt of command buffers from the command stream transformer and the global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 3539 when media operations are to be performed, or may be assigned to geometry and fixed-function pipelines (e.g., geometry and fixed-function pipeline 3536, and/or geometry and fixed-function pipeline 3514) when graphics processing operations are to be performed.

In at least one embodiment, graphics microcontroller 3538 can be configured to perform various scheduling and management tasks for graphics core 3500. In at least one embodiment, graphics microcontroller 3538 can perform graphics and/or compute workload scheduling on various graphics parallel engines within Execution Unit (EU) arrays 3502A-3502F, 3504A-3504F in sub-cores 3501A-3501F. In at least one embodiment, host software executing on a CPU core of the SoC including graphics core 3500 can submit a workload of one of a plurality of graphics processor doorbell that invokes a scheduling operation on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload to run next, submitting the workload to a command stream transformer, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, graphics microcontroller 3538 can also facilitate low power or idle states of graphics core 3500, thereby providing graphics core 3500 with the ability to save and restore registers within graphics core 3500 independent of operating system and/or graphics driver software on the system across low power state transitions.

In at least one embodiment, graphics core 3500 may have up to N modular sub-cores greater or fewer than sub-cores 3501A-3501F as shown. For each set of N sub-cores, in at least one embodiment, graphics core 3500 may also include shared function logic 3510, shared and/or cache memory 3512, geometry/fixed function pipeline 3514, and additional fixed function logic 3516 to accelerate various graphics and computing processing operations. In at least one embodiment, shared function logic 3510 may include logic units (e.g., samplers, mathematical and/or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 3500. The shared and/or cache memory 3512 may be the last level cache of the N sub-cores 3501A-3501F within the graphics core 3500 and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, a geometry/fixed function pipeline 3514 may be included in place of the geometry/fixed function pipeline 3536 within the fixed function block 3530 and may include similar logic units.

In at least one embodiment, graphics core 3500 includes additional fixed-function logic 3516, which may include various fixed-function acceleration logic for use by graphics core 3500. In at least one embodiment, the additional fixed-function logic 3516 includes additional geometry pipelines for use in location-only shading. In location-only coloring, there are at least two geometry pipelines, while in the complete geometry pipelines and culling pipelines within the geometry and fixed-function pipelines 3514, 3536, it is an additional geometry pipeline that may be included in additional fixed-function logic 3516. In at least one embodiment, the culling line is a trimmed version of the full geometry line. In at least one embodiment, the full pipeline and the culling pipeline may execute different instances of an application, each instance having a separate environment. In at least one embodiment, only location shading may hide the long culling runs of discarded triangles, so that shading may be done earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 3516 may execute the position shader in parallel with the host application and generally generate key results faster than a full pipeline because the culling pipeline acquires and masks the position attributes of vertices without performing rasterization and rendering pixels to a frame buffer. In at least one embodiment, the culling pipeline may use the generated critical results to calculate visibility information for all triangles, regardless of whether the triangles are culled. In at least one embodiment, a full pipeline (which may be referred to as a replay pipeline in this case) may consume visibility information to skip through the culled triangles to mask only the visible triangles that are ultimately passed to the rasterization stage.

In at least one embodiment, the additional fixed-function logic 3516 can further comprise machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementing optimizations including for machine learning training or reasoning.

In at least one embodiment, a set of execution resources are included within each graphics sub-core 3501A-3501F that can be used to perform graphics, media, and computing operations in response to requests by a graphics pipeline, media pipeline, or shader program. In at least one embodiment, graphics sub-cores 3501A-3501F include a plurality of EU arrays 3502A-3502F, 3504A-3504F, thread dispatch and inter-thread communication (TD/IC) logic 3503A-3503F,3D (e.g., texture) samplers 3505A-3505F, media samplers 3506A-3506F, shader processors 3507A-3507F, and Shared Local Memory (SLM) 3508A-3508F. The EU arrays 3502A-3502F, 3504A-3504F each contain a plurality of execution units, which are general purpose graphics processing units capable of servicing graphics, media, or computing operations, performing floating point and integer/fixed point logical operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD/IC logic 3503A-3503F performs local thread dispatch and thread control operations for execution units within the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. In at least one embodiment, 3D samplers 3505A-3505F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D sampler may read texture data differently based on the sampling state and texture format of the configuration associated with a given texture. In at least one embodiment, media samplers 3506A-3506F may perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 3501A-3501F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 3501A-3501F can utilize shared local memory 3508A-3508F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory. In at least one embodiment, at least one component shown or described with respect to fig. 35 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

36A-36B illustrate thread execution logic 3600 of an array of processing elements including a graphics processor core in accordance with at least one embodiment. FIG. 36A illustrates at least one embodiment in which thread execution logic 3600 is utilized. FIG. 36B illustrates exemplary internal details of an execution unit in accordance with at least one embodiment.

As shown in fig. 36A, in at least one embodiment, thread execution logic 3600 includes a shader processor 3602, a thread dispatcher 3604, an instruction cache 3606, a scalable execution unit array including a plurality of execution units 3608A-3608N, a sampler 3610, a data cache 3612, and a data port 3614. In at least one embodiment, the scalable execution unit array may be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 3608A, 3608B, 3608C, 3608D-3608N-1, and 3608N), e.g., based on the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected by an interconnect structure that links to each execution unit. In at least one embodiment, thread execution logic 3600 includes one or more connections to memory (such as system memory or cache memory) through one or more of instruction cache 3606, data port 3614, sampler 3610, and execution units 3608A-3608N. In at least one embodiment, each execution unit (e.g., 3608A) is a separate programmable general purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 3608A-3608N is scalable to include any number of individual execution units.

In at least one embodiment, execution units 3608A-3608N are primarily used to execute shader programs. In at least one embodiment, the shader processor 3602 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 3604. In at least one embodiment, the thread dispatcher 3604 includes logic for arbitrating thread-initiated celebrations from the graphics and media pipelines and instantiating requested threads on one or more of the execution units 3608A-3608N. For example, in at least one embodiment, a geometry pipeline may dispatch vertices, tessellations, or geometry shaders to thread execution logic for processing. In at least one embodiment, the thread dispatcher 3604 may also process runtime thread generation requests from an execution shader program.

In at least one embodiment, the execution units 3608A-3608N support an instruction set that includes native support for many standard 3D graphics shader instructions such that shader programs in a graphics library (e.g., direct 3D and OpenGL) can execute with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, and/or vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general purpose processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 3608A-3608N includes one or more Arithmetic Logic Units (ALUs) capable of executing multiple issue Single Instruction Multiple Data (SIMD) and multi-threaded operation enables an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issues per clock to the pipeline, which is capable of integer, single and double precision floating point operations, SIMD branching functions, logical operations, a priori operations, and other miscellaneous operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, the dependency logic within the execution units 3608A-3608N sleeps the waiting threads until the requested data is returned. In at least one embodiment, the hardware resources may be dedicated to processing other threads while the waiting thread is sleeping. For example, in at least one embodiment, the execution unit may perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader) during a delay associated with vertex shader operations.

In at least one embodiment, each of the execution units 3608A-3608N operates on an array of data elements. In at least one embodiment, the plurality of data elements is an "execution size" or number of channels of instructions. In at least one embodiment, an execution channel is a logical unit for data element access, masking, and execution of flow control within an instruction. In at least one embodiment, the multiple channels may be independent of multiple physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In at least one embodiment, execution units 3608A-3608N support integer and floating point data types.

In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, the various data elements may be stored in registers as packed data types, and the execution unit will process the various elements based on the data sizes of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad-word (QW) sized data elements), eight separate 32-bit packed data elements (double-word (DW) sized data elements), sixteen separate 16-bit packed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

In at least one embodiment, one or more execution units can be combined into a fused execution unit 3609A-3609N with thread control logic (3607A-3607N) executing for fused EUs. In at least one embodiment, multiple EUs may be combined into one EU group. In at least one embodiment, the number of EUs in the converged EU group can be configured to execute separate SIMD hardware threads. The number of EUs in the fused EU group may vary according to various embodiments. In at least one embodiment, each EU may execute a variety of SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 3609A-3609N includes at least two execution units. For example, in at least one embodiment, the fusion execution unit 3609A includes a first EU 3608A, a second EU 3608B, and thread control logic 3607A that is common to the first EU 3608A and the second EU 3608B. In at least one embodiment, the thread control logic 3607A controls threads executing on the fused graphics execution unit 3609A, allowing each EU within the fused execution units 3609A-3609N to execute using a common instruction pointer register.

In at least one embodiment, one or more internal instruction caches (e.g., 3606) are included in the thread execution logic 3600 to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g., 3612) are included to cache thread data during thread execution. In at least one embodiment, sampler 3610 is included to provide texture samples for 3D operations and media samples for media operations. In at least one embodiment, sampler 3610 includes specialized texture or media sampling functions to process texture or media data during sampling before providing the sampled data to an execution unit.

During execution, in at least one embodiment, the graphics and media pipeline sends a thread initiation request to thread execution logic 3600 through thread generation and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 3602 is invoked to further calculate output information and cause the results to be written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader calculates values of various vertex attributes to be interpolated on the rasterized object. In at least one embodiment, pixel processor logic within shader processor 3602 then executes a pixel or fragment shader program provided by an Application Program Interface (API). In at least one embodiment, to execute a shader program, shader processor 3602 dispatches threads to execution units (e.g., 3608A) via thread dispatcher 3604. In at least one embodiment, shader processor 3602 uses texture sampling logic in sampler 3610 to access texture data in texture maps stored in memory. In at least one embodiment, arithmetic operations on texture data and input geometry data calculate pixel color data for each geometry segment, or discard one or more pixels for further processing.

In at least one embodiment, data port 3614 provides a memory access mechanism for thread execution logic 3600 to output processed data to memory for further processing on a graphics processor output pipeline. In at least one embodiment, the data port 3614 includes or is coupled to one or more cache memories (e.g., data cache 3612) to cache data for memory access via the data port.

As shown in FIG. 36B, in at least one embodiment, the graphics execution unit 3608 may include an instruction fetch unit 3637, a general purpose register file array (GRF) 3624, an architectural register file Array (ARF) 3626, a thread arbiter 3622, a issue unit 3630, a branch unit 3632, a set of SIMD Floating Point Units (FPUs) 3634, and in at least one embodiment, a set of special purpose integer SIMD ALUs 3635. In at least one embodiment, GRF 3624 and ARF 3626 include a set of general purpose register files and architectural register files associated with each simultaneous hardware thread that can be active in graphics execution unit 3608. In at least one embodiment, each thread architecture state is maintained in ARF 3626, while data used during thread execution is stored in GRF 3624. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be saved in a thread-specific register in ARF 3626.

In at least one embodiment, the graphics execution unit 3608 has an architecture that is a combination of Simultaneous Multithreading (SMT) and fine-grained Interleaved Multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and a number of registers per execution unit, where execution unit resources are logically allocated for executing multiple simultaneous threads.

In at least one embodiment, the graphics execution unit 3608 may issue multiple instructions together, each of which may be a different instruction. In at least one embodiment, the thread arbiter 3622 of the graphics execution unit thread 3608 may dispatch instructions to one of the issue unit 3630, branch unit 3642, or SIMD FPU 3634 for execution. In at least one embodiment, each thread of execution may access 128 general purpose registers in GRF 3624, where each register may store 32 bytes, accessible as a SIMD 8 element vector of 32-bit data elements. In at least one embodiment, each execution unit thread may access 4KB in GRF 3624, although embodiments are not so limited and in other embodiments more or less register resources may be provided. In at least one embodiment, a maximum of seven threads may be executing simultaneously, although the number of threads per execution unit may also vary depending on the embodiment. In at least one embodiment, where seven threads may access 4KB, GRF 3624 can store a total of 28KB. In at least one embodiment, a flexible addressing scheme may allow registers to be addressed together to effectively build wider registers or rectangular block data structures representing strides.

In at least one embodiment, memory operations, sampler operations, and other longer-delay system communications are scheduled via "send" instructions executed by messaging sending unit 3630. In at least one embodiment, dispatching branch instructions to specialized branch units 3632 facilitates SIMD divergence and ultimately convergence.

In at least one embodiment, the graphics execution unit 3608 includes one or more SIMD Floating Point Units (FPUs) 3634 to perform floating point operations. In at least one embodiment, one or more FPUs 3634 also support integer computing. In at least one embodiment, one or more FPUs 3634 may SIMD perform up to M32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In at least one embodiment, at least one FPU provides extended mathematical capabilities to support high throughput a priori mathematical functions and double precision 64-bit floating points. In at least one embodiment, there is also a set of 8-bit integer SIMD ALUs 3635, and may be specifically optimized to perform operations related to machine learning computations.

In at least one embodiment, an array of multiple instances of the graphics execution unit 3608 may be instantiated in a graphics sub-core grouping (e.g., sub-slice). In at least one embodiment, the execution unit 3608 may execute instructions across multiple execution channels. In at least one embodiment, each thread executing on graphics execution unit 3608 executes on a different channel. In at least one embodiment, at least one component shown or described with respect to fig. 36A-36B is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 37 illustrates a parallel processing unit ("PPU") 3700 in accordance with at least one embodiment. In at least one embodiment, PPU 3700 is configured with machine-readable code, which if executed by PPU 3700, causes PPU 3700 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, PPU 3700 is a multithreaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a delay hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instance of a set of instructions configured to be executed by PPU 3700. In at least one embodiment, PPU 3700 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data in order to generate two-dimensional ("2D") image data for display on a display device, such as a liquid crystal display ("LCD") device. In at least one embodiment, PPU 3700 is used to perform computations, such as linear algebraic operations and machine learning operations. Fig. 37 shows an example parallel processor for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture contemplated within the scope of the present disclosure, and any suitable processor may be employed in addition to and/or in lieu thereof.

In at least one embodiment, one or more PPUs 3700 are configured to accelerate high performance computing ("HPCs"), data centers, and machine learning applications. In at least one embodiment, PPU3700 is configured to accelerate deep learning systems and applications, including the following non-limiting examples: automatic driving automobile platform, deep learning, high-precision voice, image, text recognition system, intelligent video analysis, molecular simulation, drug discovery, disease diagnosis, weather forecast, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language conversion, online search optimization, personalized user recommendation and the like.

In at least one embodiment, PPU3700 includes, but is not limited to, an input/output ("I/O") unit 3706, a front end unit 3710, a scheduler unit 3712, a work distribution unit 3714, a hub 3716, a crossbar ("Xbar") 3720, one or more general processing clusters ("GPCs") 3718, and one or more partition units ("memory partition units") 3722. In at least one embodiment, PPU3700 is connected to a host processor or other PPU3700 through one or more high-speed GPU interconnects ("GPU interconnects") 3708. In at least one embodiment, PPU3700 is connected to a host processor or other peripheral device through interconnect 3702. In one embodiment, PPU3700 is connected to a local memory comprising one or more memory devices ("memories") 3704. In at least one embodiment, memory device 3704 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as a high bandwidth memory ("HBM") subsystem, and multiple DRAM dies are stacked within each device.

In at least one embodiment, the high-speed GPU interconnect 3708 may refer to a line-based multi-channel communication link that the system uses to scale and includes one or more PPUs 3700 ("CPUs") in conjunction with one or more central processing units, supporting cache coherence between PPUs 3700 and CPUs, and CPU hosting. In at least one embodiment, the high-speed GPU interconnect 3708 transmits data and/or commands to and from other units of the PPU3700 via the hub 3716, such as one or more replication engines, video encoders, video decoders, power management units, and/or other components that may not be explicitly shown in fig. 37.

In at least one embodiment, I/O unit 3706 is configured to send and receive communications (e.g., commands, data) from a host processor (not shown in fig. 37) over system bus 3702. In at least one embodiment, the I/O unit 3706 communicates with the host processor directly through the system bus 3702 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, I/O unit 3706 may communicate with one or more other processors (e.g., one or more PPUs 3700) via system bus 3702. In at least one embodiment, I/O unit 3706 implements a peripheral component interconnect Express ("PCIe") interface for communicating over a PCIe bus. In at least one embodiment, I/O unit 3706 implements an interface for communicating with external devices.

In at least one embodiment, I/O unit 3706 decodes packets received via system bus 3702. In at least one embodiment, at least some of the packets represent commands configured to cause PPU3700 to perform various operations. In at least one embodiment, I/O unit 3706 sends the decoded command to various other units of PPU3700 as specified by the command. In at least one embodiment, the commands are sent to the front end unit 3710 and/or to other units of the hub 3716 or PPU3700, such as one or more replication engines, video encoders, video decoders, power management units, etc. (not explicitly shown in fig. 37). In at least one embodiment, I/O unit 3706 is configured to route communications between the various logic units of PPU 3700.

In at least one embodiment, programs executed by the host processor encode the command stream in a buffer that provides the workload to the PPU3700 for processing. In at least one embodiment, a workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffers are regions in memory that are accessible (e.g., read/write) by both the host processor and the PPU 3700-the host interface unit may be configured to access buffers in system memory that are connected to the system bus 3702 via memory requests transmitted by the I/O unit 3706 over the system bus 3702. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to PPU3700 indicating the start of the command stream, such that front end unit 3710 receives the pointer to the one or more command stream and manages the one or more command streams, reads the command from the command stream and forwards the command to the various units of PPU 3700.

In at least one embodiment, the front end unit 3710 is coupled to a scheduler unit 3712, which scheduler unit 3712 configures the various GPCs 3718 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 3712 is configured to track status information regarding various tasks managed by the scheduler unit 3712, wherein the status information may indicate to which GPC3718 a task is assigned, whether a task is active or inactive, priorities associated with a task, and so forth. In at least one embodiment, the scheduler unit 3712 manages a plurality of tasks executing on one or more GPCs 3718.

In at least one embodiment, the scheduler unit 3712 is coupled to a work distribution unit 3714, the work distribution unit 3714 being configured to dispatch tasks for execution on the GPCs 3718. In at least one embodiment, the work distribution unit 3714 tracks the plurality of scheduled tasks received from the scheduler unit 3712 and the work distribution unit 3714 manages the pending and active task pools for each GPC 3718. In at least one embodiment, the pool of tasks to be processed includes a plurality of time slots (e.g., 37 time slots) containing tasks assigned to be processed by a particular GPC 3718; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks that are actively processed by GPCs 3718 such that as one of GPCs 3718 completes execution of a task, that task will be evicted from the active task pool of GPCs 3718 and another task is selected from the pending task pool and scheduled for execution on GPCs 3718. In at least one embodiment, if an active task is in an idle state on the GPC3718, such as while waiting for a data dependency to resolve, the active task is evicted from the GPC3718 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC 3718.

In at least one embodiment, the work distribution unit 3714 communicates with one or more GPCs 3718 via XBar 3720. In at least one embodiment, the XBar 3720 is an interconnection network that couples many of the units of the PPU 3700 to other units of the PPU 3700 and may be configured to couple the work allocation unit 3714 to a particular GPC 3718. In at least one embodiment, one or more other units of PPU 3700 can also be connected to XBar 3720 through hub 3716.

In at least one embodiment, tasks are managed by the scheduler unit 3712 and assigned to one of the GPCs 3718 by the work assignment unit 3714. In at least one embodiment, the GPC 3718 is configured to process tasks and produce results. In at least one embodiment, the results may be consumed by other tasks in the GPC 3718, routed through XBar 3720 to a different GPC 3718 or stored in memory 3704. In at least one embodiment, the results may be written to memory 3704 by partition unit 3722, which implements a memory interface for writing data to memory 3704 or reading data from memory 3704. In at least one embodiment, the results may be transferred to another PPU 3704 or CPU via the high-speed GPU interconnect 3708. In at least one embodiment, PPU 3700 includes, but is not limited to, U partition units 3722, which are equal to the number of separate and distinct memory devices 3704 coupled to PPU 3700, described in more detail herein in connection with fig. 34.

In at least one embodiment, the host processor executes a driver core that implements an Application Programming Interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on PPU 3700. In one embodiment, multiple computing applications are executed simultaneously by PPU 3700, and PPU 3700 provides isolation, quality of service ("QoS"), and independent address space for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by PPU 3700, and the driver core outputs the tasks to one or more streams processed by PPU 3700. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as thread bundles (warp). In at least one embodiment, the thread bundle includes a plurality of related threads (e.g., 37 threads) that may be executed in parallel. In at least one embodiment, a collaboration thread may refer to multiple threads, including instructions for performing tasks and exchanging data through shared memory, the threads and collaboration threads being described in more detail in connection with FIG. 39 in accordance with at least one embodiment. In at least one embodiment, at least one component shown or described with respect to fig. 37 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 38 illustrates a general processing cluster ("GPC") 3800 in accordance with at least one embodiment. In at least one embodiment, GPC 3800 is GPC 2818 of fig. 32. In at least one embodiment, each GPC 3800 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 3800 includes, but is not limited to, a pipeline manager 3802, a pre-raster operations unit ("prog") 3804, a raster engine 3808, a work distribution crossbar ("WDX") 3816, a memory management unit ("MMU") 3818, one or more data processing clusters ("DPC") 3806, and any suitable combination of components.

In at least one embodiment, the operation of the GPC 3800 is controlled by the pipeline manager 3802. In at least one embodiment, the pipeline manager 3802 manages the configuration of one or more DPCs 3806 to handle tasks allocated to GPCs 3800. In at least one embodiment, the pipeline manager 3802 configures at least one of the one or more DPCs 3806 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 3806 is configured to execute a vertex shader program on programmable streaming multiprocessor ("SM") 3814. In at least one embodiment, the pipeline manager 3802 is configured to route data packets received from the work distribution unit to appropriate logic units within the GPC 3800, and in at least one embodiment, some data packets may be routed to fixed function hardware units in the pro 3804 and/or raster engine 3808, while other data packets may be routed to the DPC 3806 for processing by the primitive engine 3812 or SM 3814. In at least one embodiment, the pipeline manager 3802 configures at least one of the DPCs 3806 to implement a neural network model and/or a computational pipeline.

In at least one embodiment, the PROP unit 3804 is configured to route data generated by the raster engines 3808 and DPC 3806 to a raster operations ("ROP") unit in the partition unit 3222 in at least one embodiment, described in more detail above in connection with FIG. 32. In at least one embodiment, the PROP unit 3804 is configured to perform optimization for color blending, organize pixel data, perform address translation, and so forth. In at least one embodiment, the raster engine 3808 includes, but is not limited to, a plurality of fixed function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 3808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregate engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information (e.g., x, y coverage masks for tiles) for the base primitives; the output of the coarse raster engine will be transmitted to the culling engine where the segments associated with the primitives that failed the z-test will be culled and transmitted to the clipping engine where the segments outside the cone range are clipped. In at least one embodiment, the clipped and culled segments are passed to a fine raster engine to generate attributes of pixel segments based on a plane equation generated by a setup engine. In at least one embodiment, the output of the raster engine 3808 includes fragments to be processed by any suitable entity (e.g., by a fragment shader implemented within DPC 3806).

In at least one embodiment, each DPC3806 included in GPC 3800 includes, but is not limited to, an M-pipeline controller ("MPC") 3810; primitive engine 3812; one or more SMs 3814; and any suitable combination thereof. In at least one embodiment, MPC 3810 controls the operation of DPC3806, routing packets received from pipeline manager 3802 to appropriate units in DPC 3806. In at least one embodiment, the packets associated with the vertex are routed to primitive engine 3812, primitive engine 3812 configured to retrieve vertex attributes associated with the vertex from memory; instead, data packets associated with the shader program may be sent to the SM 3814.

In at least one embodiment, SM3814 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM3814 is multi-threaded and configured to concurrently execute multiple threads (e.g., 32 threads) from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture in which each thread of a set of threads (e.g., a thread bundle) is configured to process a different set of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, the SM3814 implements a single instruction, multithreading ("SIMT") architecture in which each thread in a set of threads is configured to process a different set of data based on the same instruction set, but in which individual threads in the set of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundles and serial execution within the thread bundles when threads in the thread bundles diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread such that there is equal concurrency between all threads within and between thread bundles. In at least one embodiment, the execution state is maintained for each individual thread, and threads executing the same instructions may be converged and executed in parallel to improve efficiency. At least one embodiment of SM3814 is described in more detail herein.

In at least one embodiment, the MMU 3818 provides an interface between the GPC 3800 and a memory partition unit (e.g., partition unit 3722 of fig. 37), and the MMU 3818 provides virtual-to-physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 3818 provides one or more translation lookaside buffers ("TLB") for performing translations of virtual addresses to physical addresses in memory. In at least one embodiment, at least one component shown or described with respect to fig. 38 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 39 illustrates a memory partition unit 3900 of a parallel processing unit ("PPU") in accordance with at least one embodiment. In at least one embodiment, memory partition unit 3900 includes, but is not limited to, a raster operations ("ROP") unit 3902; a level two ("L2") cache 3904; a memory interface 3906; and any suitable combination thereof. In at least one embodiment, a memory interface 3906 is coupled to the memory. In at least one embodiment, the memory interface 3906 may implement 39, 64, 128, 1024 bit data buses, or similar implementations for high speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 3906, one memory interface 3906 for each pair of partition units 3900, wherein each pair of partition units 3900 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high bandwidth memory stack or graphics dual data rate version 5 synchronous dynamic random access memory ("GDDR 5 SDRAM").

In at least one embodiment, memory interface 3906 implements a high bandwidth memory second generation ("HBM 2") memory interface and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack is located on the same physical package as the PPU, providing a significant amount of power and saving area compared to conventional GDDR5SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and y=4, each HBM2 stack includes two 128-bit lanes per die for a total of 8 lanes and 1024-bit data bus width. In at least one embodiment, the memory supports single error correction double error detection ("SECDED") error correction code ("ECC") to protect data. ECC may provide higher reliability for computing applications that are sensitive to data corruption.

In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, memory partition unit 3900 supports unified memory to provide a single unified virtual address space for central processing units ("CPUs") and PPU memory to enable data sharing between virtual memory systems. In at least one embodiment, the frequency of access of the PPU to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses the pages more frequently. In at least one embodiment, the high-speed GPU interconnect 3708 supports an address translation service that allows the PPU to directly access the CPU's page tables and provide full access to the CPU memory through the PPU.

In at least one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the replication engine may generate a page fault for an address that is not mapped into the page table, and the memory partition unit 3900 then services the page fault, maps the address into the page table, and then the replication engine performs the transfer. In at least one embodiment, fixed (i.e., non-pageable) memory is operated for multiple replication engines between multiple processors, thereby substantially reducing available memory. In at least one embodiment, in the event of a hardware page fault, the address may be passed to the replication engine regardless of whether the memory page resides or not, and the replication process is transparent.

In accordance with at least one embodiment, data from memory 3704 of fig. 37 or other system memory is fetched by memory partition unit 3900 and stored in L2 cache 3904, with L2 cache 3904 located on-chip and shared among various GPCs. In at least one embodiment, each memory partition unit 3900 includes, but is not limited to, at least a portion of an L2 cache associated with a corresponding memory device. In at least one embodiment, a lower level cache is implemented in each unit within the GPC. In at least one embodiment, each SM 3314 may implement a level one ("L1") cache, where the L1 cache is private memory dedicated to a particular SM 3314, and data is fetched from the L2 cache 3904 and stored in each L1 cache for processing in the functional units of SM 3814. In at least one embodiment, L2 cache 3904 is coupled to memory interface 3906 and XBar 3720.

In at least one embodiment, ROP unit 3902 performs graphics raster operations related to pixel colors, such as color compression, pixel blending, and the like. In at least one embodiment, ROP unit 3902 implements a depth test in conjunction with raster engine 3808, receiving the depth of the sample locations associated with the pixel fragments from the culling engine of raster engine 3808. In at least one embodiment, the depth is tested for a respective depth in a depth buffer of sample locations associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample location, ROP unit 3902 updates the depth buffer and sends the results of the depth test to raster engine 3808. It will be appreciated that the number of partition units 3900 may be different than the number of GPCs, and thus, each ROP unit 3902 may be coupled to each GPC in at least one embodiment. In at least one embodiment, ROP unit 3902 tracks packets received from different GPCs and determines to which result generated by ROP unit 3902 is routed through XBar 3720.

Figure 40 illustrates a streaming multiprocessor ("SM") 4000 in accordance with at least one embodiment. In at least one embodiment, SM 4000 is the SM of fig. 38. In at least one embodiment, SM 4000 includes, but is not limited to, an instruction cache 4002; one or more scheduler units 4004; register file 4008; one or more processing cores ("cores") 4010; one or more special function units ("SFUs") 4012; one or more load/store units ("LSUs") 4014; an interconnection network 4016; a shared memory/level one ("L1") cache 4018; and/or any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks to execute on a common processing cluster ("GPC") of parallel processing units ("PPU"), and each task is assigned to a particular data processing cluster ("DPC") inside the GPC, and if a task is associated with a shader program, the task is assigned to one of the SMs 4000. In at least one embodiment, the scheduler unit 4004 receives tasks from the work allocation unit and manages instruction scheduling of one or more thread blocks assigned to the SM 4000. In at least one embodiment, the scheduler unit 4004 schedules thread blocks to execute as thread bundles of parallel threads, where each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes threads. In at least one embodiment, the scheduler unit 4004 manages a plurality of different thread blocks, assigns thread bundles to different thread blocks, and then assigns instructions from a plurality of different collaboration groups to various functional units (e.g., processing cores 4010, SFU 4012, and LSU 4014) in each clock cycle.

In at least one embodiment, a collaboration group may refer to a programming model for organizing groups of communication threads that allows a developer to express the granularity at which threads are communicating, thereby enabling a richer, more efficient parallel decomposition to be expressed. In at least one embodiment, the collaboration initiation API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the application of the conventional programming model provides a single, simple construct for synchronizing collaborative threads: a barrier (e.g., syncthreads () function) across all threads of a thread block. However, in at least one embodiment, a programmer may define groups of threads with less than thread block granularity and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set-wide functional interface. In at least one embodiment, the collaboration group enables a programmer to explicitly define a thread group at sub-block (i.e., as small as a single thread) and multi-block granularity and perform aggregate operations, such as synchronizing threads in the collaboration group. In at least one embodiment, the programming model supports clean combinations across software boundaries so that library and utility functions can be securely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the collaboration group primitives enable new patterns of collaboration parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across a thread block grid.

In at least one embodiment, the dispatch unit 4006 is configured to send instructions to one or more of the functional units, and the scheduler unit 4004 includes, but is not limited to, two dispatch units 4006, the two dispatch units 4006 enabling two different instructions from the same thread bundle to be dispatched each clock cycle. In at least one embodiment, each scheduler unit 4004 includes a single scheduler unit 4006 or additional scheduler units 4006.

In at least one embodiment, each SM 4000 includes, in at least one embodiment, but is not limited to, a register file 4008, the register file 4008 providing a set of registers for the functional units of the SM 4000. In at least one embodiment, register file 4008 is divided between each functional unit such that each functional unit is assigned a dedicated portion of register file 4008. In at least one embodiment, register file 4008 is divided between different bundles of threads executed by SM 4000, and register file 4008 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 4000 includes, but is not limited to, a plurality L of processing cores 4010. In at least one embodiment, SM 4000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 4010. In at least one embodiment, each processing core 4010 includes, but is not limited to, full pipeline, single precision, double precision, and/or mixed precision processing units including, but not limited to, floating point arithmetic logic units and integer arithmetic logic units. In at least one embodiment, the floating point arithmetic logic unit implements the IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores 4010 include, but are not limited to, 64 single precision (32-bit) floating point cores, 64 integer cores, 32 double precision (64-bit) floating point cores, and 8 tensor cores.

According to at least one embodiment, the tensor core is configured to perform a matrix operation. In at least one embodiment, one or more tensor cores are included in the processing core 4010. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation d=a×b+c, where A, B, C and D are 4×4 matrices.

In at least one embodiment, matrix multiplication inputs a and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating point accumulation operation on 16-bit floating point input data. In at least one embodiment, a 16-bit floating-point multiply uses 64 operations and results in a full-precision product, which is then accumulated with other intermediate products using a 32-bit floating-point addition to perform a 4x4x4 matrix multiply. In at least one embodiment, the tensor core is used to perform a larger two-dimensional or higher-dimensional matrix operation made up of these smaller elements. In at least one embodiment, an API (such as the CUDA 9C++ API) exposes specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations to effectively use tensor cores from the CUDA-C++ program. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16×16 sized matrix spanning all 32 thread bundle threads.

In at least one embodiment, each SM 4000 includes, but is not limited to, M SFUs 4012 that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, SFU 4012 includes, but is not limited to, a tree traversal unit configured to traverse hierarchical tree data structures. In at least one embodiment, SFU 4012 includes, but is not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texels) and sample the texture map from memory to generate sampled texture values for use by a shader program executed by SM 4000. In at least one embodiment, the texture map is stored in the shared memory/L1 cache 4018. In at least one embodiment, according to at least one embodiment, texture units implement texture operations (such as filtering operations) using mipmaps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 4000 includes, but is not limited to, two texture units.

In at least one embodiment, each SM 4000 includes, but is not limited to, N LSUs 4014 that implement load and store operations between shared memory/L1 cache 4018 and register file 4008. In at least one embodiment, each SM 4000 includes, but is not limited to, an interconnection network 4016 that connects each functional unit to a register file 4008 and LSU4014 to register file 4008 and shared memory/L1 cache 4018. In at least one embodiment, the interconnection network 4016 is a crossbar that can be configured to connect any functional unit to any register in the register file 4008 and connect the LSU4014 to the register file 4008 and memory locations in the shared memory/L1 cache 4018.

In at least one embodiment, the shared memory/L1 cache 4018 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between SM4000 and primitive engines and between threads in SM 4000. In at least one embodiment, the shared memory/L1 cache 4018 includes, but is not limited to, 128KB of storage and is located in the path from SM4000 to the partition units. In at least one embodiment, the shared memory/L1 cache 4018 is used in at least one embodiment to cache reads and writes. In at least one embodiment, one or more of the shared memory/L1 cache 4018, L2 cache, and memory is a backing store.

In at least one embodiment, combining data caching and shared memory functions into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use shared memory or as a cache, e.g., if the shared memory is configured to use half the capacity, and texture and load/store operations may use the remaining capacity. In accordance with at least one embodiment, integration within the shared memory/L1 cache 4018 enables the shared memory/L1 cache 4018 to function as a high throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration may be used than graphics processing. In at least one embodiment, the fixed function graphics processing unit is bypassed, creating a simpler programming model. In at least one embodiment, in a general parallel computing configuration, the work allocation unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, the threads in the block execute a general purpose program, use unique thread IDs in the computation to ensure that each thread generates a unique result, use SM4000 to execute the program and perform the computation, use shared memory/L1 cache 4018 to communicate between threads, and use LSU 4014 to read and write global memory through shared memory/L1 cache 4018 and memory partition units. In at least one embodiment, when configured for general parallel computing, SM4000 writes commands to scheduler unit 4004 that can be used to initiate new work on DPC.

In at least one embodiment, the PPU is included in or coupled with a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head mounted display, a handheld electronic device, and the like. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on a chip ("SoC") along with one or more other devices (e.g., additional PPU, memory, reduced instruction set computer ("RISC") CPU, one or more memory management units ("MMU"), digital-to-analog converter ("DAC"), etc.).

In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. In at least one embodiment, the graphics card may be configured to connect with a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit ("iGPU") included in a chipset of a motherboard. In at least one embodiment, at least one component shown or described with respect to fig. 40 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

In at least one embodiment, a single semiconductor platform may refer to a unique single semiconductor-based integrated circuit or chip. In at least one embodiment, a multi-chip module with increased connectivity may be used that simulates on-chip operation and is a substantial improvement over utilizing conventional central processing unit ("CPU") and bus implementations. In at least one embodiment, the various modules may also be placed separately or in various combinations of semiconductor platforms, depending on the needs of the user.

In at least one embodiment, a computer program in the form of machine-readable executable code or computer control logic algorithms is stored in the main memory 2004 and/or secondary storage. In accordance with at least one embodiment, the computer program, if executed by one or more processors, enables the system 2000 to perform various functions. In at least one embodiment, memory 2004, storage, and/or any other storage are possible examples of computer-readable media. In at least one embodiment, secondary storage may refer to any suitable storage device or system, such as a hard disk drive and/or a removable storage drive, representing a floppy diskette drive, a magnetic tape drive, an optical disk drive, a digital versatile disk ("DVD") drive, a recording device, a universal serial bus ("USB") flash memory, and so forth. In at least one embodiment, the architecture and/or functionality of each of the preceding figures is found in the CPU 2002; a parallel processing system 2012; an integrated circuit capable of having at least part of the capabilities of two CPUs 2002; a parallel processing system 2012; a chipset (e.g., a set of integrated circuits designed to operate and sell as a unit to perform related functions, etc.); and in the context of any suitable combination of integrated circuits.

In at least one embodiment, the architecture and/or functionality of the various previous figures is implemented in the context of a general purpose computer system, circuit board system, game console system dedicated for entertainment purposes, dedicated system, and the like. In at least one embodiment, computer system 2000 may take the form of a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., wireless, handheld), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head mounted display, a handheld electronic device, a mobile telephone device, a television, a workstation, a gaming machine, an embedded system, and/or any other type of logic.

In at least one embodiment, parallel processing system 2012 includes, but is not limited to, a plurality of parallel processing units ("PPUs") 2014 and associated memory 2016. In at least one embodiment, PPU2014 is connected to a host processor or other peripheral device via interconnect 2018 and switch 2020 or a multiplexer. In at least one embodiment, the parallel processing system 2012 distributes computing tasks over the parallelizable PPUs 2014, e.g., as part of a distribution of computing tasks across multiple graphics processing unit ("GPU") thread blocks. In at least one embodiment, memory (e.g., for read and/or write access) is shared and accessed among some or all of PPUs 2014, although such shared memory may incur performance penalty relative to using local memory and registers residing on PPUs 2014. In at least one embodiment, the operation of PPUs 2014 is synchronized through the use of commands (such as __ syncthreads ()) where all threads in a block (e.g., executing across multiple PPUs 2014) reach a certain code execution point before proceeding.

Network system

Fig. 41 illustrates a network 4100 for communicating data within a 5G wireless communication network in accordance with at least one embodiment. In at least one embodiment, the network 4100 includes a base station 4106 having a coverage area 4104, a plurality of mobile devices 4108, and a backhaul network 4102. In at least one embodiment, as shown, the base station 4106 establishes an uplink and/or downlink connection with the mobile device 4108 for communicating data from the mobile device 4108 to the base station 4106 and vice versa. In at least one embodiment, the data carried over the uplink/downlink connection may include data communicated between the mobile devices 4108, as well as data communicated to/from a remote end (not shown) by way of the backhaul network 4102. In at least one embodiment, the term "base station" refers to any component (or collection of components) configured to provide wireless access to a network, such as an enhanced base station (eNB), macrocell, femtocell, wi-Fi Access Point (AP), or other wireless-enabled device. In at least one embodiment, a base station may provide wireless access according to one or more wireless communication protocols, such as Long Term Evolution (LTE), LTE-advanced (LTE-A), high Speed Packet Access (HSPA), wi-Fi 802.11a/b/g/n/ac, and so on. In at least one embodiment, the term "mobile device" refers to any component (or collection of components) capable of establishing a wireless connection with a base station, such as User Equipment (UE), mobile Stations (STA), and other wireless-enabled devices. In some embodiments, network 4100 can include various other wireless devices, such as relays, low power nodes, and the like. In at least one embodiment, at least one component shown or described with respect to fig. 41 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 42 illustrates a network architecture 4200 for a 5G wireless network in accordance with at least one embodiment. In at least one embodiment, as shown, the network architecture 4200 includes a Radio Access Network (RAN) 4204, an Evolved Packet Core (EPC) 4202, which may be referred to as a core network, and a home network 4216 of a UE 4208 attempting to access the RAN 4204. In at least one embodiment, RAN4204 and EPC 4202 form a serving wireless network. In at least one embodiment, the RAN4204 includes a base station 4206, and the EPC 4202 includes a Mobility Management Entity (MME) 4212, a Serving Gateway (SGW) 4210, and a Packet Data Network (PDN) gateway (PGW) 4214. In at least one embodiment, the home network 4216 comprises an application server 4218 and a Home Subscriber Server (HSS) 4220. In at least one embodiment, the HSS 4220 may be part of the home network 4216, EPC 4202, and/or variants thereof.

In at least one embodiment, the MME 4212 is a termination point in the network for ciphering/integrity protection of NAS signaling and handles security key management. In at least one embodiment, it should be understood that the term "MME" is used in a 4G LTE network and a 5G LTE network may include a secure anchor node (sea) or a secure access function (SEAF) that performs similar functions. In at least one embodiment, the terms "MME", "sea" and "SEAF" may be used interchangeably. In at least one embodiment, the MME 4212 also provides control plane functionality for mobility between LTE and 2G/3G access networks, and an interface to the home network of the roaming UE. In at least one embodiment, the SGW 4210 routes and forwards user data packets while also acting as a mobility anchor for the user plane during handoff. In at least one embodiment, PGW 4214 provides connectivity from the UE to external packet data networks by being the egress and ingress points for UE traffic. In at least one embodiment, the HSS 4220 is a central database containing user related and subscription related information. In at least one embodiment, the application server 4218 is a central database containing user-related information about various applications that may utilize the network architecture 4200 and communicate via the network architecture 4200. In at least one embodiment, at least one component shown or described with respect to fig. 42 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 43 is a diagram illustrating some basic functions of a mobile telecommunications network/system operating in accordance with LTE and 5G principles in accordance with at least one embodiment. In at least one embodiment, the mobile telecommunications system includes an infrastructure equipment including a base station 4314 connected to a core network 4302, the core network 4302 operating according to a conventional arrangement as will be appreciated by those familiar with communication technology. In at least one embodiment, the infrastructure equipment 4314 may also be referred to as, for example, a base station, a network element, an enhanced node B (eNodeB), or a coordinating entity, and provides a wireless access interface or cell represented by the dashed line 4304, which may be referred to as a radio access network, to one or more communication devices within a coverage area. In at least one embodiment, one or more mobile communication devices 4306 may transmit data via transmission and reception of signals representing the data using a wireless access interface. In at least one embodiment, the core network 4302 may also provide functionality including authentication, mobility management, charging, and the like for communication devices served by network entities.

In at least one embodiment, the mobile communication device of fig. 43 may also be referred to as a communication terminal, user Equipment (UE), terminal device, or the like, and is configured to communicate with one or more other communication devices served by the same or different coverage areas via a network entity. In at least one embodiment, these communications may be performed by sending and receiving signals representing data over a bi-directional communication link using a wireless access interface.

In at least one embodiment, as shown in fig. 43, one of the enodebs 4314a is shown in greater detail to include a transmitter 4312 for transmitting signals to one or more communication devices or UEs 4306 via a wireless access interface and a receiver 4310 for receiving signals from one or more UEs within the coverage area 4304. In at least one embodiment, the controller 4308 controls the transmitter 4312 and the receiver 4310 to transmit and receive signals over a wireless access interface. In at least one embodiment, the controller 4308 may perform the function of controlling the allocation of communication resource elements of the wireless access interface and may include, in some examples, a scheduler for scheduling transmissions for uplink and downlink via the wireless access interface.

In at least one embodiment, the example UE 4306a is shown in more detail as including a transmitter 4320 for transmitting signals to the eNodeB 4314 on an uplink of a wireless access interface and a receiver 4318 for receiving signals transmitted by the eNodeB 4314 on a downlink via the wireless access interface. In at least one embodiment, the transmitter 4320 and the receiver 4318 are controlled by a controller 4316. In at least one embodiment, at least one component shown or described with respect to fig. 43 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 44 illustrates a radio access network 4400 that may be part of a 5G network architecture in accordance with at least one embodiment. In at least one embodiment, the radio access network 4400 covers a geographic area divided into a plurality of cellular areas (cells) that are uniquely identified by User Equipment (UE) based on an identification broadcast over the geographic area from one access point or base station. In at least one embodiment, macro cells 4440, 4428 and 4416 and small cell 4430 may include one or more sectors. In at least one embodiment, a sector is a sub-region of a cell and all sectors within a cell are served by the same base station. In at least one embodiment, a single logical identification belonging to the sector may identify a radio link within the sector. In at least one embodiment, multiple sectors within a cell may be formed by groups of antennas each responsible for communication with UEs in a portion of the cell.

In at least one embodiment, each cell is served by a Base Station (BS). In at least one embodiment, the base station is a network element in a radio access network responsible for radio transmission and reception to or from UEs in one or more cells. In at least one embodiment, a base station may also be referred to as a Base Transceiver Station (BTS), a radio base station, a radio transceiver, a transceiving function, a Basic Service Set (BSS), an Extended Service Set (ESS), an Access Point (AP), a Node B (NB), an eNodeB (eNB), a gNodeB (gNB), or some other suitable terminology. In at least one embodiment, a base station may include a backhaul interface for communicating with a backhaul portion of a network. In at least one embodiment, the base station has an integrated antenna or is connected to an antenna or Remote Radio Head (RRH) through a feeder cable.

In at least one embodiment, the backhaul may provide links between the base stations and the core network, and in some examples, the backhaul may provide interconnections between the various base stations. In at least one embodiment, the core network is part of a wireless communication system that is generally independent of the radio access technology used in the radio access network. In at least one embodiment, various types of backhaul interfaces may be employed, such as direct physical connections using any suitable transport network, virtual networks, and the like. In at least one embodiment, some base stations may be configured as Integrated Access and Backhaul (IAB) nodes, where the wireless spectrum may be used for both access links (i.e., wireless links with UEs) and backhaul links, sometimes referred to as wireless self-backhaul. In at least one embodiment, the wireless spectrum used for communication between the base station and the UE may be used for backhaul communication by wireless self-backhaul, enabling fast and easy deployment of high-density small cell networks, rather than requiring each new base station deployment to be equipped with its own hard-wired backhaul connection.

In at least one embodiment, high power base stations 4436 and 4420 are shown in cells 4440 and 4428, and high power base station 4410 is shown to control Remote Radio Heads (RRHs) 4412 in cell 4416. In at least one embodiment, cells 4440, 4428 and 4416 may be referred to as large size cells or macro cells. In at least one embodiment, the low power base station 4434 is shown in a small cell 4430 (e.g., a micro cell, pico cell, femto cell, home base station, home node B, home eNodeB, etc.), which may overlap with one or more macro cells, and may be referred to as a small cell or small-sized cell. In at least one embodiment, cell size may be determined based on system design and component constraints. In at least one embodiment, relay nodes may be deployed to extend the size or coverage area of a given cell. In at least one embodiment, the radio access network 4400 may include any number of wireless base stations and cells. In at least one embodiment, the base stations 4436, 4420, 4410, 4434 provide wireless access points to the core network for any number of mobile devices.

In at least one embodiment, the four-axis aircraft or drone 4442 may be configured to function as a base station. In at least one embodiment, the cells are not necessarily stationary and the geographic area of the cells may move according to the location of a mobile base station (such as a four-axis aircraft 4442).

In at least one embodiment, the radio access network 4400 supports wireless communication for a plurality of mobile devices. In AT least one embodiment, a mobile device is commonly referred to as a User Equipment (UE), but may also be referred to as a Mobile Station (MS), subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless communication device, remote device, mobile subscriber station, access Terminal (AT), mobile terminal, wireless terminal, remote terminal, handset, terminal, user agent, mobile client, or some other suitable terminology. In at least one embodiment, the UE may be a device that provides a user with access to a network service.

In at least one embodiment, the "mobile" device need not have the capability to move, and may be stationary. In at least one embodiment, a mobile device or mobile apparatus generally refers to a variety of different devices and technologies. In at least one embodiment, the mobile device may be a cell phone, a cellular (cell) phone, a smart phone, a Session Initiation Protocol (SIP) phone, a laptop, a Personal Computer (PC), a notebook, a netbook, a smart book, a tablet, a Personal Digital Assistant (PDA), a wide range of embedded systems, e.g., corresponding to "internet of things" (IoT), an automobile or other vehicle, a remote sensor or actuator, a robot or robotic device, a satellite radio, a Global Positioning System (GPS) device, an object tracking device, an unmanned aerial vehicle, a multi-rotor aircraft, a quad-rotor aircraft, a remote control device, a consumer and/or wearable device, e.g., glasses, a wearable camera, a virtual reality device, a smart watch, a health or fitness tracker, a digital audio player (e.g., MP3 player), a camera, a game console, a digital home or smart home device (e.g., home) audio, video and/or multimedia device, an appliance, an automatic vending machine, smart lighting, a home security system, a smart home or solar panel, a security device, a solar panel, a control lighting (e.g., a military), an automatic power grid, an industrial infrastructure, an aircraft, a water controller, a water craft, a defense device, a marine vehicle, and the like. In at least one embodiment, the mobile device may provide connected medical or telemedicine support, i.e., remote healthcare. In at least one embodiment, the telemedicine devices may include telemedicine monitoring devices and telemedicine management devices whose communications may be given priority or access over other types of information, e.g., in terms of priority access for critical service data transmissions, and/or associated QoS for transmission of critical service data.

In at least one embodiment, a cell of the radio access network 4400 may include UEs that may communicate with one or more sectors of each cell. In at least one embodiment, UEs 4414 and 4408 may communicate with base station 4410 through RRH 4412; UEs 4422 and 4426 may communicate with base station 4420; the UE 4432 may communicate with a low power base station 4434; UEs 4438 and 4418 may communicate with a base station 4436; the UE 4444 may be in communication with a mobile base station 4442. In at least one embodiment, each base station 4410, 4420, 4434, 4436, and 4442 may be configured to provide access points to all core networks (not shown) for all UEs in the respective cells and transmissions from the base station (e.g., base station 4436) to one or more UEs (e.g., UEs 4438 and 4418) may be referred to as Downlink (DL) transmissions, while transmissions from the UEs (e.g., UE 4438) to the base station may be referred to as Uplink (UL) transmissions. In at least one embodiment, the downlink may refer to a point-to-multipoint transmission, which may be referred to as broadcast channel multiplexing. In at least one embodiment, the uplink may refer to a point-to-point transmission.

In at least one embodiment, the four-axis craft 4442, which may be referred to as a mobile network node, may be configured to act as a UE within the cell 4440 by communicating with the base station 4436. In at least one embodiment, multiple UEs (e.g., UEs 4422 and 4426) may communicate with each other using peer-to-peer (P2P) or sidelink signals 4424, which may bypass a base station (such as base station 4420).

In at least one embodiment, the ability of a UE to communicate independent of its location while moving is referred to as mobility. In at least one embodiment, a Mobility Management Entity (MME) establishes, maintains, and releases various physical channels between a UE and a radio access network. In at least one embodiment, the radio access network 4400 may utilize DL-based mobility or UL-based mobility to enable mobility and handover (i.e., transfer a UE's connection from one radio channel to another). In at least one embodiment, a UE may monitor various parameters of signals from its serving cell and various parameters of neighboring cells in a network configured for DL-based mobility, and depending on the quality of these parameters, the UE may maintain communication with one or more neighboring cells. In at least one embodiment, the UE may perform a handover or handoff from the serving cell to a neighboring (or target) cell if the signal quality from the neighboring cell exceeds the signal quality from the serving cell within a given amount of time, or if the UE moves from one cell to another. In at least one embodiment, the UE 4418 (illustrated as a vehicle, although any suitable form of UE may be used) may move from a geographic region corresponding to a cell (e.g., serving cell 4440) to a geographic region corresponding to a neighboring cell (e.g., neighboring cell 4416). In at least one embodiment, the UE 4418 may send a report message to its serving base station 4436 indicating its condition when the signal strength or quality from the neighboring cell 4416 exceeds the signal strength or quality of its serving cell 4440 within a given time. In at least one embodiment, the UE 4418 may receive a handover command and may experience a handover to the cell 4416.

In at least one embodiment, the UL reference signal from each UE may be configured for use by a network of UL-based mobility to select a serving cell for each UE. In at least one embodiment, the base stations 4436, 4420 and 4410/4412 may broadcast unified synchronization signals (e.g., unified Primary Synchronization Signal (PSS), unified Secondary Synchronization Signal (SSS) and unified Physical Broadcast Channel (PBCH)). In at least one embodiment, the UEs 4438, 4418, 4422, 4426, 4414, and 4408 may receive a unified synchronization signal, derive carrier frequencies and slot timing from the synchronization signal, and transmit uplink pilot or reference signals in response to the derived timing. In at least one embodiment, two or more cells (e.g., base stations 4436 and 4410/4412) within radio access network 4400 may simultaneously receive uplink pilot signals transmitted by UEs (e.g., UE 4418). In at least one embodiment, the cell may measure the strength of the pilot signal and the radio access network (e.g., one or more of the base stations 4436 and 4410/4412 and/or a central node within the core network) may determine the serving cell of the UE 4418. In at least one embodiment, as the UE 4418 moves through the radio access network 4400, the network may continue to monitor uplink pilot signals transmitted by the UE 4418. In at least one embodiment, the network 4400 may switch the UE 4418 from the serving cell to the neighbor cell with or without notification to the UE 4418 when the signal strength or quality of the pilot signal measured by the neighbor cell exceeds the signal strength or quality measured by the serving cell.

In at least one embodiment, the synchronization signals transmitted by the base stations 4436, 4420 and 4410/4412 may be uniform, but may not identify a particular cell, but may identify areas of multiple cells operating at the same frequency and/or at the same time. In at least one embodiment, areas in a 5G network or other next generation communication network enable an uplink-based mobility framework and improve the efficiency of the UE and the network, as the number of mobility messages that need to be exchanged between the UE and the network may be reduced.

In at least one embodiment, the air interface in the radio access network 4400 may utilize unlicensed spectrum, licensed spectrum, or shared spectrum. In at least one embodiment, the unlicensed spectrum provides shared use of a portion of spectrum without government granted permissions, however, while some technical rules still generally need to be complied with to access the unlicensed spectrum, generally, any operator or device may gain access. In at least one embodiment, licensed spectrum provides exclusive use of a portion of spectrum, typically relying on a mobile network operator to purchase a license from a government regulatory agency. In at least one embodiment, the shared spectrum may be intermediate between licensed and unlicensed spectrum, where technical rules or restrictions may be required to access the spectrum, but the spectrum may still be shared by multiple operators and/or more RATs. For example, in at least one embodiment, a holder of a license that grants a portion of the spectrum may provide License Sharing Access (LSA) to share the spectrum with other parties, e.g., to obtain access with appropriate license determination conditions. In at least one embodiment, at least one component shown or described with respect to fig. 44 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 45 provides an example illustration of a 5G mobile communication system in which a plurality of different types of devices are used in accordance with at least one embodiment. In at least one embodiment, as shown in fig. 45, the first base station 4518 may be provided to a large cell or macrocell that transmits signals over several kilometers. However, in at least one embodiment, the system may also support transmissions via very small cells, such as by the second infrastructure device 4516, the second infrastructure device 4516 sending and receiving signals over a distance of hundreds of meters, forming a so-called "Pico" cell. In at least one embodiment, the third type of infrastructure equipment 4512 may transmit and receive signals over distances of tens of meters and thus may be used to form so-called "femto" cells.

In at least one embodiment, also shown in fig. 45, different types of communication devices may be used to transmit and receive signals via different types of infrastructure devices 4512, 4516, 4518, and data communications may be adapted according to different types of infrastructure devices using different communication parameters. In at least one embodiment, conventionally, a mobile communications device may be configured to communicate data to and from a mobile communications network via available communications resources of the network. In at least one embodiment, the wireless access system is configured to provide the highest data rate to devices such as smart phone 4506. In at least one embodiment, an "internet of things" may be provided in which low power machine type communication devices transmit and receive data at very low power, low bandwidth, and possibly with low complexity. In at least one embodiment, an example of such a machine type communication device 4514 may communicate via a pico cell 4516. In at least one embodiment, very high data rates and low mobility may be a feature in communication with, for example, television 4504, which may communicate via Pico cells. In at least one embodiment, the virtual reality headset 4508 may require very high data rates and low latency. In at least one embodiment, the relay device 4510 may be deployed to extend the size or coverage area of a given cell or network. In at least one embodiment, at least one component shown or described with respect to fig. 45 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 46 illustrates an example advanced system 4600, wherein at least one embodiment may be utilized. In at least one embodiment, the high-level system 4600 includes an application 4602, a system software+library 4604, framework software 4606, and a data center infrastructure+resource coordinator 4608. In at least one embodiment, the advanced system 4600 can be implemented as a cloud service, a physical service, a virtual service, a web service, and/or variants thereof.

In at least one embodiment, as shown in fig. 46, the data center infrastructure+resource coordinator 4608 can include a 5G radio resource coordinator 4610, GPU packet processing and I/O4612, and node computing resources ("node c.r.") 4616 (1) -4616 (N), where "N" represents any integer, positive integer. In at least one embodiment, nodes c.r.4616 (1) -4616 (N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field Programmable Gate Arrays (FPGAs), graphics processors ("GPUs"), etc.), memory devices (e.g., dynamic read only memory), storage devices (e.g., solid state or disk drives), network input/output ("NW I/O") devices, network switches, virtual machines ("VMs"), power modules, cooling modules, and the like. In at least one embodiment, one or more of nodes c.r.4616 (1) -4616 (N) CR may be a server having one or more of the computing resources described above.

In at least one embodiment, the 5G radio resource coordinator 4610 may configure or otherwise control one or more nodes c.r.4616 (1) -4616 (N) and/or other various components and resources that the 5G network architecture may include. In at least one embodiment, the 5G radio resource coordinator 4610 may include a software design infrastructure ("SDI") management entity for the advanced system 4600. In at least one embodiment, the 5G radio resource coordinator 4610 may include hardware, software, or some combination thereof. In at least one embodiment, the 5G radio resource coordinator 4610 may be used to configure or otherwise control various medium access control sublayers, radio access networks, physical layers or sublayers, and/or variations thereof, which may be part of a 5G network architecture. In at least one embodiment, the 5G radio resource coordinator 4610 may configure or allocate computing, network, memory, or storage resources of the packet to support one or more workloads that may be performed as part of the 5G network architecture.

In at least one embodiment, GPU packet processing and I/O4612 may configure or otherwise process various inputs and outputs, as well as packets such as data packets, which may be transmitted/received as part of a 5G network architecture, may be implemented by high level system 4600. In at least one embodiment, the packets may be data formatted to be provided by the network, and may be generally divided into control information and payloads (i.e., user data). In at least one embodiment, the types of data packets may include internet protocol version 4 (IPv 4) data packets, internet protocol version 6 (IPv 6) packets, and ethernet II frame packets. In at least one embodiment, control data of a data packet may be divided into a data integrity field and a semantic field. In at least one embodiment, the network connection over which the data packet may be received includes a local area network, a wide area network, a virtual private network, the Internet, an intranet, an extranet, a public switched telephone network, an infrared network, a wireless network, a satellite network, and any combination thereof.

In at least one embodiment, framework software 4606 includes AI model architecture+training+use case 4622. In at least one embodiment, the AI model framework + training + use cases 4622 may include tools, services, software, or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models in accordance with one or more embodiments. For example, in at least one embodiment, the machine learning model may be trained by computing weight parameters from a neural network architecture using the software and computing resources described above with respect to the high-level system 4600. In at least one embodiment, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to advanced system 4600, using weight parameters calculated by one or more training techniques. In at least one embodiment, the framework software 4606 can include a framework supporting the system software+libraries 4604 and applications 4602.

In at least one embodiment, the system software+library 4604 or application 4602 may include web-based service software or applications, such as those provided by amazon web services, google cloud, and microsoft Azure, respectively. In at least one embodiment, framework software 4606 may include, but is not limited to, one type of free and open source software web application framework, such as Apache Spark (hereinafter "Spark"). In at least one embodiment, the system software +library 4604 can include software used by at least part of the nodes c.r.4616 (1) -4616 (N). In at least one embodiment, the one or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

In at least one embodiment, PHY 4618 is a set of system software and libraries configured to provide an interface with a physical layer of wireless technology, which may be a physical layer such as a 5G New Radio (NR) physical layer. In at least one embodiment, the NR physical layer utilizes a flexible and scalable design and may include various components and techniques such as modulation schemes, waveform structures, frame structures, reference signals, multi-antenna transmissions, and channel coding.

In at least one embodiment, the NR physical layer supports Quadrature Phase Shift Keying (QPSK), 16 Quadrature Amplitude Modulation (QAM), 64QAM, and 256QAM modulation formats. In at least one embodiment, different modulation schemes for different User Entity (UE) categories may also be included in the NR physical layer. In at least one embodiment, the NR physical layer can be utilized in the Uplink (UL) and Downlink (DL) with scalable digital (subcarrier spacing, cyclic prefix) cyclic prefix orthogonal frequency division multiplexing (CP-OFDM) up to at least 52.6 gigahertz. In at least one embodiment, the NR physical layer can support discrete fourier transform spread orthogonal frequency division multiplexing (DFT-SOFDM) in the UL for coverage limited scenarios with single stream transmission (i.e., without spatial multiplexing).

In at least one embodiment, NR frames support Time Division Duplex (TDD) and Frequency Division Duplex (FDD) transmissions and operation in licensed and unlicensed spectrum, which enables very low latency, fast hybrid automatic repeat request (HARQ) acknowledgements, dynamic TDD, short duration with LTE coexistence and variable length transmissions (e.g., ultra-reliable low delay communications (URLLC), and long duration of enhanced mobile broadband (eMBB). In at least one embodiment, the NR frame structure follows three key design principles to enhance forward compatibility and reduce interactions between different features.

In at least one embodiment, the first principle is that the transmission is self-contained, which may refer to a scheme in which data in time slots and beams can be decoded independently of other time slots and beams. In at least one embodiment, this means that the reference signals required for data demodulation are included in a given slot and a given beam. In at least one embodiment, the second principle is that the transmission is well limited in time and frequency, which results in a scheme that can introduce new types of transmissions in parallel with traditional transmissions. In at least one embodiment, a third principle is to avoid static and/or strict timing relationships across time slots and across different transmission directions. In at least one embodiment, the use of the third principle may entail utilizing asynchronous hybrid automatic repeat request (HARQ) rather than a predefined retransmission time.

In at least one embodiment, the NR frame structure also allows for fast HARQ acknowledgements, where decoding is performed during reception of DL data and HARQ acknowledgements are prepared by the UE during a guard period when switching from DL reception to UL transmission. In at least one embodiment, to obtain low latency, a slot (or a group of slots in the case of a set of slots) is pre-loaded with a control signal and a reference signal at the beginning of the slot (or group of slots).

In at least one embodiment, the NR has a super-thin design that minimizes always-on transmissions to improve network energy efficiency and ensure forward compatibility. In at least one embodiment, the reference signal in NR is transmitted only when necessary. In at least one embodiment, the four primary reference signals are demodulation reference signals (DMRS), phase Tracking Reference Signals (PTRS), sounding Reference Signals (SRS), and channel state information reference signals (CSI-RS).

In at least one embodiment, the DMRS is used to estimate a radio channel for demodulation. In at least one embodiment, the DMRS is UE-specific, may be beamformed, restricted in scheduling resources, and transmitted in DL and UL only when necessary. In at least one embodiment, to support multi-layer Multiple Input Multiple Output (MIMO) transmission, multiple orthogonal DMRS ports may be scheduled, one for each layer. In at least one embodiment, the basic DMRS pattern is pre-amble because DMRS design takes into account early decoding requirements to support low latency applications. In at least one embodiment, for low speed scenarios, the DMRS uses low density in the time domain. However, in at least one embodiment, for high speed scenarios, the time density of DMRS is increased to track rapid changes in the radio channel.

In at least one embodiment, PTRS is introduced in the NR to achieve compensation of oscillator phase noise. In at least one embodiment, the phase noise typically increases as a function of the oscillator carrier frequency. In at least one embodiment, PTRS may therefore be utilized at high carrier frequencies (e.g., millimeter waves) to mitigate phase noise. In at least one embodiment, PTRS is UE-specific, is limited in scheduled resources and can be beamformed. In at least one embodiment, PTRS may be configured according to the quality of the oscillator, carrier frequency, OFDM subcarrier spacing, and modulation and coding scheme used for transmission.

In at least one embodiment, SRS is transmitted in the UL to perform Channel State Information (CSI) measurements primarily for scheduling and link adaptation. In at least one embodiment, SRS is also used for reciprocity-based precoder design for massive MIMO and UL beam management for NR. In at least one embodiment, the SRS has a modular and flexible design to support different procedures and UE capabilities. In at least one embodiment, the method of channel state information reference signals (CSI-RS) is similar.

In at least one embodiment, the NR employs different antenna solutions and techniques depending on which portion of the spectrum is used for its operation. In at least one embodiment, for lower frequencies, a low to medium number of active antennas (in some cases, up to about 32 transmitter chains) is assumed and FDD operation is common. In at least one embodiment, acquisition of CSI requires transmission of CSI-RS in DL and CSI reporting in UL. In at least one embodiment, the limited bandwidth available in this frequency region requires high spectral efficiency achieved through multi-user MIMO (MU-MIMO) and higher order spatial multiplexing, which is achieved through higher resolution CSI reporting compared to LTE.

In at least one embodiment, for higher frequencies, a greater number of antennas may be employed in a given aperture, which increases the capacity of beamforming and multi-user (MU) -MIMO. In at least one embodiment, herein, spectrum allocation is of the TDD type and is assumed to be based on reciprocal operation. In at least one embodiment, high resolution CSI in the form of explicit channel estimation is obtained by UL channel sounding. In at least one embodiment, such high resolution CSI enables complex precoding algorithms to be employed at a Base Station (BS). In at least one embodiment, analog beamforming implementations are currently generally required for higher frequencies (in the millimeter wave range), which limits transmission to a single beam direction per time unit and radio chain. In at least one embodiment, the isotropic antenna element is very small in this frequency region due to the short carrier wavelength, so a large number of antenna elements are required to maintain coverage. In at least one embodiment, beamforming needs to be applied at the transmitter and receiver ends to combat the increased path loss, even for control channel transmissions.

In at least one embodiment, to support these different use cases, NR has a highly flexible but unified CSI framework, where the coupling between CSI measurements, CSI reports and actual DL transmissions is reduced in NR compared to LTE. In at least one embodiment, the NR also supports more advanced schemes such as multipoint transmission and coordination. In at least one embodiment, control and data transmission follow a self-contained principle, wherein all information (e.g., accompanying DMRS) required for decoding the transmission is contained within the transmission itself. In at least one embodiment, the network may thus seamlessly change transmission points or beams as the UE moves in the network.

In at least one embodiment, the MAC 4620 is a set of system software and libraries configured to provide an interface with a Media Access Control (MAC) layer, which may be part of a 5G network architecture. In at least one embodiment, the MAC layer controls hardware responsible for interacting with a wired, optical, or wireless transmission medium. In at least one embodiment, the MAC provides flow control and multiplexing for the transmission medium.

In at least one embodiment, the MAC sublayer provides an abstraction of the physical layer such that the complexity of physical link control is not visible to the upper layers of the Logical Link Control (LLC) and network stack. In at least one embodiment, any LLC sub-layer (and higher layers) may be used with any MAC. In at least one embodiment, any MAC may be used with any physical layer, regardless of the transmission medium. In at least one embodiment, the MAC sublayer encapsulates higher layer frames into frames suitable for the transmission medium when transmitting data to another device on the network, adds a frame check sequence to identify transmission errors, and then forwards the data to the physical layer when appropriate channel access methods allow. In at least one embodiment, the MAC is also responsible for compensating for collisions if a congestion signal is detected, wherein the MAC may initiate retransmissions.

In at least one embodiment, the applications 4602 can include one or more types of applications used by at least portions of the nodes c.r.4616 (1) -4616 (N) and/or the framework software 4606. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or reasoning software, machine learning framework software (e.g., pyTorch, tensorFlow, caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

In at least one embodiment, the RAN API 4614 may be a set of subroutine definitions, communication protocols, and/or software tools that provide a method of communicating with components of a Radio Access Network (RAN), which may be part of a 5G network architecture. In at least one embodiment, the radio access network is part of a network communication system and may implement a radio access technology. In at least one embodiment, the radio access network functions are typically provided by silicon chips located in both the core network and the user equipment. More information about the radio access network can be found in the description of fig. 44.

In at least one embodiment, the high-level system 4600 can use a CPU, application Specific Integrated Circuit (ASIC), GPU, FPGA, or other hardware to perform training, reasoning, and/or other various processes using the above-described resources. Further, in at least one embodiment, the one or more software and/or hardware resources described above may be configured as services that allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services, as well as other services, such as services that allow users to configure and implement aspects of the 5G network architecture. In at least one embodiment, at least one component shown or described with respect to fig. 46 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 47 illustrates an architecture of a network system 4700 in accordance with at least one embodiment. In at least one embodiment, system 4700 is shown to include User Equipment (UE) 4702 and UE 4704. In at least one embodiment, UEs 4702 and 4704 are shown as smartphones (e.g., handheld touch screen mobile computing devices connectable to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as a Personal Data Assistant (PDA), pager, laptop computer, desktop computer, wireless handset, or any computing device that includes a wireless communication interface.

In at least one embodiment, either of UEs 4702 and 4704 may include an internet of things (IoT) UE, which may include a network access layer designed for low power IoT applications that utilize short-lived UE connections. In at least one embodiment, ioT UEs may utilize technologies such as machine-to-machine (M2M) or Machine Type Communication (MTC) to exchange data with MTC servers or devices through Public Land Mobile Networks (PLMNs), proximity services (ProSe) based or device-to-device (D2D) communications, sensor networks, or IoT networks. In at least one embodiment, the M2M or MTC data exchange may be a machine initiated data exchange. In at least one embodiment, the IoT network describes interconnected IoT UEs that may include uniquely identifiable embedded computing devices (within the internet infrastructure) with short-term connections. In at least one embodiment, the IoT UE may execute a background application (e.g., keep alive message, status update, etc.) to facilitate connection of the IoT network.

In at least one embodiment, the UEs 4702 and 4704 may be configured to connect, e.g., communicatively couple, with a Radio Access Network (RAN) 4716. In at least one embodiment, the RAN 4716 may be, for example, an evolved Universal Mobile Telecommunications System (UMTS) terrestrial radio access network (E-UTRAN), a Next Generation RAN (NGRAN), or some other type of RAN. In at least one embodiment, UEs 4702 and 4704 utilize connections 4712 and 4714, respectively, each of which includes a physical communication interface or layer. In at least one embodiment, connections 4712 and 4714 are shown as air interfaces to achieve communicative coupling, and may be consistent with cellular communication protocols, such as the Global System for Mobile communications (GSM) protocol, code Division Multiple Access (CDMA) network protocol, push-to-talk (PTT) protocol, PTT Over Cellular (POC) protocol, universal Mobile Telecommunications System (UMTS) protocol, 3GPP Long Term Evolution (LTE) protocol, fifth generation (5G) protocol, new Radio (NR) protocol, and variants thereof.

In at least one embodiment, the UEs 4702 and 4704 may further exchange communication data directly via the ProSe interface 4706. In at least one embodiment, proSe interface 4706 may alternatively be referred to as a side-chain interface including one or more logical channels, including, but not limited to, a physical side-chain control channel (PSCCH), a physical side-chain shared channel (PSSCH), a physical side-chain discovery channel (PSDCH), and a physical side-chain broadcast channel (PSBCH).

In at least one embodiment, the UE 4704 is shown configured to access an Access Point (AP) 4710 via a connection 4708. In at least one embodiment, connection 4708 may comprise a local wireless connection, such as with any IEEE 802.11 protocol, where AP 4710 would include wireless fidelityAnd a router. In at least one embodiment, the AP 4710 is shown connected to the Internet rather than to the core network of a wireless systemAnd (5) collaterals.

In at least one embodiment, RAN 4716 may include one or more access nodes that enable connections 4712 and 4714. In at least one embodiment, these Access Nodes (ANs) may be referred to as Base Stations (BS), nodebs, evolved nodebs (enbs), next generation nodebs (gnbs), RAN nodes, etc., and may include ground stations (e.g., terrestrial access points) or satellite stations that provide coverage within a geographic area (e.g., cell). In at least one embodiment, the RAN 4716 may include one or more RAN nodes for providing macro cells, such as macro RAN node 4718, and one or more RAN nodes for providing femto cells or pico cells (e.g., having a smaller coverage area, smaller user capacity, or higher bandwidth than macro cells), such as Low Power (LP) RAN node 4720.

In at least one embodiment, either of the RAN nodes 4718 and 4720 may terminate the air interface protocol and may be the first point of contact for the UEs 4702 and 4704. In at least one embodiment, either of RAN nodes 4718 and 4720 may implement various logic functions of RAN 4716 including, but not limited to, radio Network Controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management, and data packet scheduling, as well as mobility management.

In at least one embodiment, UEs 4702 and 4704 may be configured to communicate with each other or any of RAN nodes 4718 and 4720 over multicarrier communication channels using orthogonal frequency division multiplexing ("OFDM") communication signals in accordance with various communication techniques, such as, but not limited to, orthogonal Frequency Division Multiple Access (OFDMA) communication techniques (e.g., for downlink communications) or single carrier frequency division multiple access (SC-FDMA) communication techniques (e.g., for uplink and ProSe or side-chain communications), and/or variants thereof. In at least one embodiment, the OFDM signal may include a plurality of orthogonal subcarriers.

In at least one embodiment, a downlink resource grid may be used for downlink transmissions from either of the RAN nodes 4718 and 4720 to the UEs 4702 and 4704, while uplink transmissions may utilize similar techniques. In at least one embodiment, the grid may be a time-frequency grid, referred to as a resource grid or time-frequency resource grid, which is a physical resource in the downlink of each slot. In at least one embodiment, such a time-frequency plane representation is a common practice for OFDM systems, which makes radio resource allocation intuitive. In at least one embodiment, each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one slot in a radio frame. In at least one embodiment, the smallest time-frequency unit in the resource grid is denoted as a resource element. In at least one embodiment, each resource grid includes a plurality of resource blocks that describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block includes a set of resource elements. In at least one embodiment, in the frequency domain, this may represent the minimum amount of resources that can be currently allocated. In at least one embodiment, there are several different physical downlink channels transmitted using such resource blocks.

In at least one embodiment, a Physical Downlink Shared Channel (PDSCH) may carry user data and higher layer signaling to UEs 4702 and 4704. In at least one embodiment, a Physical Downlink Control Channel (PDCCH) may carry information about transport formats and resource allocations related to PDSCH channels and the like. In at least one embodiment, it may also inform UEs 4702 and 4704 of transport format, resource allocation, and HARQ (hybrid automatic repeat request) information related to the uplink shared channel. In at least one embodiment, downlink scheduling (allocation of control and shared channel resource blocks to UEs 4702 within a cell) may typically be performed at either of the RAN nodes 4718 and 4720 based on channel quality information fed back from either of the UEs 4702 and 4704. In at least one embodiment, the downlink resource allocation information may be transmitted on a PDCCH for (e.g., allocated to) each of the UEs 4702 and 4704.

In at least one embodiment, the PDCCH may use Control Channel Elements (CCEs) to convey control information. In at least one embodiment, the PDCCH complex-valued symbols may first be organized into quadruples before being mapped to resource elements, which may then be permuted using a sub-block interleaver for rate matching. In at least one embodiment, each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements referred to as Resource Element Groups (REGs). In at least one embodiment, four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to each REG. In at least one embodiment, the PDCCH may be transmitted using one or more CCEs depending on a size of Downlink Control Information (DCI) and channel conditions. In at least one embodiment, four or more different PDCCH formats with different numbers of CCEs (e.g., aggregation level, l=1, 2, 4, or 8) may be defined in LTE.

In at least one embodiment, an Enhanced Physical Downlink Control Channel (EPDCCH) using PDSCH resources may be used for control information transmission. In at least one embodiment, the EPDCCH may be transmitted using one or more Enhanced Control Channel Elements (ECCEs). In at least one embodiment, each ECCE may correspond to nine sets of four physical resource elements referred to as Enhanced Resource Element Groups (EREGs). In at least one embodiment, ECCEs may have other amounts of EREGs in some cases.

In at least one embodiment, RAN 4716 is shown communicatively coupled to a Core Network (CN) 4738 via an S1 interface 4722. In at least one embodiment, the CN 4738 may be an Evolved Packet Core (EPC) network, a NextGen Packet Core (NPC) network, or some other type of CN. In at least one embodiment, the S1 interface 4722 is split into two parts: an S1-U interface 4726 that carries traffic data between the RAN nodes 4718 and 4720 and a serving gateway (S-GW) 4730, and an S1-Mobility Management Entity (MME) interface 4724 that is a signaling interface between the RAN nodes 4718 and 4720 and the MME 4728.

In at least one embodiment, the CN 4738 includes an MME 4728, an S-GW 4730, a Packet Data Network (PDN) gateway (P-GW) 4734, and a Home Subscriber Server (HSS) 4732. In at least one embodiment, the MME 4728 may be similar in function to a control plane of a legacy serving General Packet Radio Service (GPRS) support node (SGSN). In at least one embodiment, MME 4728 may manage mobility aspects in access, such as gateway selection and tracking area list management. In at least one embodiment, HSS 4732 may include a database for network users including subscription-related information to support the processing of communication sessions by network entities. In at least one embodiment, the CN 4738 may include one or more HSS 4732 depending on the number of mobile users, the capacity of the device, the organization of the network, etc. In at least one embodiment, HSS 4732 may provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependence, and the like.

In at least one embodiment, the S-GW 4730 may terminate the S1 interface 4722 to the RAN 4716 and route data packets between the RAN 4716 and the CN 4738. In at least one embodiment, the S-GW 4730 may be a local mobility anchor inter-RAN node handoff point or may provide an anchor point for inter-3 GPP mobility. In at least one embodiment, other responsibilities may include lawful interception, charging, and some policy enforcement.

In at least one embodiment, the P-GW 4734 may terminate the SGi interface towards the PDN. In at least one embodiment, the P-GW 4734 may route data packets between the EPC network 4738 and an external network, such as including an application server 4740 (otherwise referred to as an Application Function (AF)) via an Internet Protocol (IP) interface 4742, in at least one embodiment, the application server 4740 may be an element (e.g., UMTS Packet Service (PS) domain, LTEPS data service, etc.) that provides applications that use IP bearer resources with a core network.

In at least one embodiment, the P-GW 4734 may also be a node for policy enforcement and charging data collection. In at least one embodiment, the policy and charging enforcement function (PCRF) 4736 is a policy and charging control element of the CN 4738. In at least one embodiment, in a non-roaming scenario, there may be a single PCRF associated with an internet protocol connection access network (IP-CAN) session of the UE in a Home Public Land Mobile Network (HPLMN). In at least one embodiment, in a roaming scenario with local traffic disruption, there may be two PCRFs associated with the IP-CAN session of the UE: a home PCRF (H-PCRF) within the HPLMN and a visited PCRF (V-PCRF) within the Visited Public Land Mobile Network (VPLMN). In at least one embodiment, PCRF4736 may be communicatively coupled to application server 4740 through P-GW 4734. In at least one embodiment, the application server 4740 may signal the PCRF4736 to indicate a new service flow and select an appropriate quality of service (QoS) and charging parameters. In at least one embodiment, PCRF4736 may provide the rules into a Policy and Charging Enforcement Function (PCEF) (not shown) and have a QoS Class (QCI) of the appropriate Traffic Flow Template (TFT) and identifier, the starting QoS and charging of which are specified by application server 4740. In at least one embodiment, at least one component shown or described with respect to fig. 47 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

FIG. 48 illustrates example components of a device 4800 according to at least one embodiment. In at least one embodiment, the device 4800 can include an application circuit 4804, a baseband circuit 4808, a Radio Frequency (RF) circuit 4810, a Front End Module (FEM) circuit 4812, one or more antennas 4812, and a Power Management Circuit (PMC) 4806 coupled together at least as shown. In at least one embodiment, the components of the illustrated device 4800 can be included in a UE or RAN node. In at least one embodiment, the device 4800 may include fewer elements (e.g., the RAN node may not utilize the application circuitry 4804, but instead include a processor/controller to process IP data received from the EPC). In at least one embodiment, device 4800 can include additional elements such as memory/storage, displays, cameras, sensors, or input/output (I/O) interfaces. In at least one embodiment, the components described below may be included in more than one device (e.g., for a cloud-RAN (C-RAN) implementation, the circuitry may be included separately in more than one device).

In at least one embodiment, the application circuitry 4804 can include one or more application processors. In at least one embodiment, the application circuitry 4804 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. In at least one embodiment, the processor may comprise any combination of general-purpose and special-purpose processors (e.g., graphics processors, application processors, etc.). In at least one embodiment, the processor may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the device 4800. In at least one embodiment, the processor application circuitry 4804 can process IP data packets received from the EPC.

In at least one embodiment, baseband circuitry 4808 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. In at least one embodiment, baseband circuitry 4818 may include one or more baseband processors or control logic to process baseband signals received from the receive signal path of RF circuitry 4810 and generate baseband signals for the transmit signal path of RF circuitry 4810. In at least one embodiment, baseband processing circuit 4808 can interface with application circuit 4804 for generating and processing baseband signals and for controlling the operation of RF circuit 4810. In at least one embodiment, the baseband circuitry 4808 may include a third generation (3G) baseband processor 4808A, a fourth generation (4G) baseband processor 4808B, a fifth generation (5G) baseband processor 4808C, or other baseband processor 4808D for other existing generations, for a generation being developed or to be developed (e.g., second generation (2G), sixth generation (6G), etc.). In at least one embodiment, baseband circuitry 4808 (e.g., one or more of baseband processors 4808A-D) can handle various radio control functions that enable communication with one or more radio networks through RF circuitry 4810. In at least one embodiment, some or all of the functionality of baseband processors 4808A-D may be included in modules stored in memory 4808G and executed via Central Processing Unit (CPU) 4808E. In at least one embodiment, the radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, and the like. In at least one embodiment, the modulation/demodulation circuitry of baseband circuitry 4808 may include Fast Fourier Transform (FFT), precoding, or constellation mapping/demapping functions. In at least one embodiment, the encoding/decoding circuitry of baseband circuitry 4808 may include convolution, tail biting convolution, turbo, viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality.

In at least one embodiment, the baseband circuitry 4808 may include one or more audio Digital Signal Processors (DSPs) 4808F. In at least one embodiment, the audio DSP 4808F may include elements for compression/decompression and echo cancellation, and may include other suitable processing elements in other embodiments. In at least one embodiment, components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or, in some embodiments, disposed on the same circuit board. In at least one embodiment, some or all of the constituent components of baseband circuitry 4808 and application circuitry 4804 may be implemented together, such as on a system on a chip (SOC).

In at least one embodiment, baseband circuitry 4808 may provide communication compatible with one or more radio technologies. In at least one embodiment, baseband circuitry 4808 may support communication with an Evolved Universal Terrestrial Radio Access Network (EUTRAN) or other Wireless Metropolitan Area Network (WMAN), wireless Local Area Network (WLAN), wireless Personal Area Network (WPAN). In at least one embodiment, baseband circuitry 4808 is configured to support radio communications for more than one wireless protocol and may be referred to as multi-mode baseband circuitry.

In at least one embodiment, the RF circuit 4810 may enable communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In at least one embodiment, the RF circuitry 4810 can include switches, filters, amplifiers, and the like to facilitate communication with a wireless network. In at least one embodiment, the RF circuitry 4810 can include a receive signal path that can include circuitry to down-convert an RF signal received from the FEM circuitry 4802 and provide a baseband signal to the baseband circuitry 4808. In at least one embodiment, the RF circuitry 4810 may also include a transmit signal path, which may include circuitry for up-converting the baseband signal provided by the baseband circuitry 4808 and providing an RF output signal to the FEM circuitry 4802 for transmission.

In at least one embodiment, the receive signal path of the RF circuit 4810 may include a mixer circuit 4810a, an amplifier circuit 4810b, and a filter circuit 4810c. In at least one embodiment, the transmit signal path of the RF circuit 4810 may include a filter circuit 4810c and a mixer circuit 4810a. In at least one embodiment, the RF circuit 4810 may also include a synthesizer circuit 4810d for synthesizing frequencies for use by the mixer circuit 4810a of the receive signal path and the transmit signal path. In at least one embodiment, the mixer circuit 4810a of the receive signal path may be configured to down-convert the RF signal received from the FEM circuit 4812 based on the synthesized frequency provided by the synthesizer circuit 4810d. In at least one embodiment, the amplifier circuit 4810b can be configured to amplify the down-converted signal and the filter circuit 4810c can be a Low Pass Filter (LPF) or a Band Pass Filter (BPF) configured to remove unwanted signals from the down-converted signal to produce an output baseband signal. In at least one embodiment, the output baseband signal may be provided to baseband circuitry 4808 for further processing. In at least one embodiment, the output baseband signal may be a zero frequency baseband signal, although this is not required. In at least one embodiment, the mixer circuit 4810a of the receive signal path may comprise a passive mixer.

In at least one embodiment, the mixer circuit 4810a of the transmit signal path may be configured to upconvert the input baseband signal based on a synthesized frequency provided by the synthesizer circuit 4810d to generate an RF output signal for the FEM circuit 4812. In one embodiment, the baseband signal may be provided by baseband circuitry 4808 and may be filtered by filter circuitry 4810 c.

In at least one embodiment, the mixer circuit 4810a of the receive signal path and the mixer circuit 4810a of the transmit signal path may comprise two or more mixers and may be arranged for quadrature down-conversion and up-conversion, respectively. In at least one embodiment, the mixer circuit 4810a of the receive signal path and the mixer circuit 4810a of the transmit signal path may comprise two or more mixers and may be arranged for image rejection (e.g., hartley image rejection). In at least one embodiment, the mixer circuit 4810a and the mixer circuit 4810a of the receive signal path may be arranged for direct down-conversion and direct up-conversion, respectively. In at least one embodiment, the mixer circuit 4810a of the receive signal path and the mixer circuit 4810a of the transmit signal path may be configured for superheterodyne operation.

In at least one embodiment, the output baseband signal and the input baseband signal may be analog baseband signals. In at least one embodiment, the output baseband signal and the input baseband signal may be digital baseband signals. In at least one embodiment, the RF circuitry 4810 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and the baseband circuitry 4818 may include a digital baseband interface in communication with the RF circuitry 4810.

In at least one embodiment, separate radio IC circuits may be provided to process the signals for each spectrum. In at least one embodiment, synthesizer circuit 4810d can be a fractional-N synthesizer or a fractional-N/N+1 synthesizer. In at least one embodiment, the synthesizer circuit 4810d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase locked loop with a frequency divider.

In at least one embodiment, the synthesizer circuit 4810d can be configured to synthesize an output frequency for use by the mixer circuit 4810a of the RF circuit 4810 based on the frequency input and the divider control input. In at least one embodiment, synthesizer circuit 4810d can be a fractional N/n+1 synthesizer.

In at least one embodiment, the frequency input may be provided by a Voltage Controlled Oscillator (VCO). In at least one embodiment, the divider control input may be provided by the baseband circuitry 4808 or the application processor 4804 depending on the desired output frequency. In at least one embodiment, the divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the application processor 4804.

In at least one embodiment, the synthesizer circuit 4810d of the RF circuit 4810 may include a frequency divider, a Delay Locked Loop (DLL), a multiplexer, and a phase accumulator. In at least one embodiment, the frequency divider may be a dual-mode frequency divider (DMD) and the phase accumulator may be a Digital Phase Accumulator (DPA). In at least one embodiment, the DMD may be configured to divide the input signal by N or n+1 (e.g., based on a carry) to provide a fractional division ratio. In at least one embodiment, the DLL may include a set of cascaded adjustable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In at least one embodiment, the delay elements may be configured to divide the VCO period into Nd equal phase packets, where Nd is the number of delay elements in the delay line. In at least one embodiment, in this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO period.

In at least one embodiment, synthesizer circuit 4810d may be configured to generate a carrier frequency as the output frequency, while in other embodiments the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with a quadrature generator and divider circuit to generate a plurality of signals at the carrier frequency, the signals having a plurality of different phases relative to each other. In at least one embodiment, the output frequency may be an LO frequency (fLO). In at least one embodiment, the RF circuit 4810 can include an IQ/polarity converter.

In at least one embodiment, FEM circuitry 4812 may include a receive signal path that may include circuitry configured to operate on RF signals received from one or more antennas 4812, amplify the received signals, and provide an amplified version of the received signals to RF circuitry 4810 for further processing. In at least one embodiment, FEM circuitry 4812 may also include a transmit signal path, which may include circuitry configured to amplify signals provided by RF circuitry 4810 for transmission by one or more of the one or more antennas 4812. In at least one embodiment, amplification by the transmit or receive signal paths may be done in the RF circuit 4810 alone, in the FEM 4812 alone, or in both the RF circuit 4810 and FEM 4812.

In at least one embodiment, FEM circuitry 4802 may include a TX/RX switch to switch between transmit and receive mode operation. In at least one embodiment, the FEM circuitry may include a receive signal path and a transmit signal path. In at least one embodiment, the receive signal path of the FEM circuitry may include an LNA to amplify the received RF signal and provide an amplified received RF signal as an output (e.g., to the RF circuitry 4810). In at least one embodiment, the transmit signal path of FEM circuitry 4812 may include a Power Amplifier (PA) to amplify an input RF signal (e.g., provided by RF circuitry 4810), and one or more filters to generate an RF signal for subsequent transmission (e.g., through one or more of one or more antennas 4812).

In at least one embodiment, the PMC 4806 may manage the power provided to the baseband circuitry 4808. In at least one embodiment, the PMC 4806 may control power supply selection, voltage scaling, battery charging, or DC-DC conversion. In at least one embodiment, PMC 4806 may often be included when device 4800 is capable of being powered by a battery, for example, when the device is included in a UE. In at least one embodiment, PMC 4806 can improve power conversion efficiency while providing desired implementation size and heat dissipation characteristics.

In at least one embodiment, the PMC 4806 may additionally or alternatively be coupled to and perform similar power management operations for other components (e.g., without limitation, application circuitry 4814, RF circuitry 4810, or FEM 4802).

In at least one embodiment, PMC 4806 may control or otherwise be part of various power saving mechanisms of device 4800. In at least one embodiment, if the device 4800 is in an RRC connected state, it is still connected to the RAN node and is expected to receive traffic soon, and then it may enter a state called discontinuous reception mode (DRX) after a period of inactivity. In at least one embodiment, during this state, the device 4800 can be powered down for a brief interval, thereby conserving power.

In at least one embodiment, if there is no data traffic activity for an extended period of time, the device 4800 can transition to an RRC idle state where it disconnects from the network and does not perform operations (such as channel quality feedback, handover, etc.). In at least one embodiment, device 4800 enters a very low power state and it performs paging where it wakes up again periodically to listen to the network and then powers down again. In at least one embodiment, the device 4800 may not receive data in this state and must transition back to the RRC connected state in order to receive data.

In at least one embodiment, the additional power saving mode may allow the device to be unavailable to the network for a period of time longer than the paging interval (ranging from a few seconds to a few hours). In at least one embodiment, during this time the device is completely inaccessible to the network and may be completely powered off. In at least one embodiment, any data transmitted during this period causes a large delay and the delay is assumed to be acceptable.

In at least one embodiment, the processor of the application circuitry 4804 and the processor of the baseband circuitry 4808 may be used to execute elements of one or more instances of a protocol stack. In at least one embodiment, the processor of baseband circuitry 4808 may be used to perform layer 3, layer 2, or layer 1 functions, alone or in combination, while the processor of application circuitry 4808 may utilize the layers of data (e.g., packet data) received from these and further perform layer 4 functions (e.g., transmission Communication Protocol (TCP) and User Datagram Protocol (UDP) layers). In at least one embodiment, layer 3 may include a Radio Resource Control (RRC) layer. In at least one embodiment, layer 2 may include a Medium Access Control (MAC) layer, a Radio Link Control (RLC) layer, and a Packet Data Convergence Protocol (PDCP) layer. In at least one embodiment, layer 1 may include a Physical (PHY) layer of the UE/RAN node. In at least one embodiment, at least one component shown or described with respect to fig. 48 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 49 illustrates an example interface of a baseband circuit in accordance with at least one embodiment. In at least one embodiment, the baseband circuitry 4808 of fig. 48 can include processors 4808A-4808E and memory 4808G used by the processors as described above. In at least one embodiment, each of the processors 4808A-4808E can include a memory interface 4902A-4902E, respectively, to send and receive data to and from the memory 4808G.

In at least one embodiment, baseband circuitry 4808 may also include one or more interfaces to communicatively couple to other circuits/devices, such as memory interface 4904 (e.g., an interface to send/receive data to/from memory external to baseband circuitry 4808), application circuitry interface 4906 (e.g., an interface to send/receive data to/from application circuitry 4804 of fig. 48), RF circuitry interface 4908 (e.g., an interface to send/receive data to/from RF circuitry 4810 of fig. 48), wireless hardware connection interface 4910 (e.g., an interface to/from Near Field Communication (NFC) component, a wireless hardware connection interface 4910 (e.g., a wireless communication interface between a wireless communication device and a wireless communication device),Assembly (e.g.)>Low Energy)、/>Components and other communication components), and a power management interface 4912 (e.g., an interface that transmits/receives power or control signals to/from PMC 4806). In at least one embodiment, at least one component shown or described with respect to fig. 49 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 50 illustrates an example of an uplink channel in accordance with at least one embodiment. In at least one embodiment, fig. 50 illustrates transmitting and receiving data within a Physical Uplink Shared Channel (PUSCH) in a 5G NR, which may be part of the physical layer of a mobile device network.

In at least one embodiment, a Physical Uplink Shared Channel (PUSCH) in the 5G NR is designated to carry multiplexing control information and user application data. In at least one embodiment, the 5G NR provides more flexibility and reliability than its predecessor, which may be referred to as 4GLTE in some examples, including more flexible pilot arrangement and support for Cyclic Prefix (CP) -OFDM and discrete fourier transform spread (DFT-s) -OFDM waveforms. In at least one embodiment, standard-introduced filtered OFDM (f-OFDM) techniques are used to add additional filtering to reduce out-of-band emissions and improve the performance of higher modulation orders. In at least one embodiment, modifications in Forward Error Correction (FEC) are imposed on replacing the Turbo code used in 4GLTE with a quasi-cyclic low density parity check (QC-LDPC) code, which proves to enable better transmission rates and provide opportunities for more efficient hardware implementation.

In at least one embodiment, the transmission of 5G NR downlink and uplink data is organized into frames of duration 10 milliseconds, each frame being divided into 10 subframes of 1 millisecond each. In at least one embodiment, a subframe consists of a variable number of slots, depending on the selected subcarrier spacing parameterized in the 5G NR. In at least one embodiment, the slot is constructed from 14 OFDMA symbols, each symbol carrying a cyclic prefix. In at least one embodiment, the subcarriers that are located within the passband and designated for transmission are referred to as Resource Elements (REs). In at least one embodiment, a group of 12 adjacent REs in the same symbol form a Physical Resource Block (PRB).

In at least one embodiment, the 5G NR standard defines two types of reference signals associated with transmissions within a PUSCH channel. In at least one embodiment, the demodulation reference signal (DMRS) is a user specific reference signal with high frequency density. In at least one embodiment, the DMRS is transmitted only within dedicated Orthogonal Frequency Division Multiple Access (OFDMA) symbols and is designated for frequency selective channel estimation. In at least one embodiment, the number of DMRS symbols within a slot may vary between 1 and 4 depending on the configuration, with denser DMRS symbol time intervals being designated for fast time-varying channels to obtain more accurate estimates within the coherence time of the channel. In at least one embodiment, in the frequency domain, DMRS PRBs are mapped within the entire transmission allocation. In at least one embodiment, the spacing between DMRS Resource Elements (REs) allocated to the same Antenna Port (AP) may be selected between 2 and 3. In at least one embodiment, the standard allows for orthogonal allocation of REs among APs in the case of 2-2 Multiple Input Multiple Output (MIMO). In at least one embodiment, the receiver may perform partial single-input multiple-output (SIMO) channel estimation based on the DMRS REs prior to MIMO equalization, ignoring spatial correlation.

In at least one embodiment, the second type of reference signal is a Phase Tracking Reference Signal (PTRS). In at least one embodiment, PTRS subcarriers are arranged in a comb structure having a high density in the time domain. In at least one embodiment, it is primarily used in the millimeter wave band to track and correct for phase noise, which is an important source of performance loss. In at least one embodiment, the use of PTRS is optional because it may reduce the overall spectral efficiency of the transmission when the effect of phase noise is negligible.

In at least one embodiment, for the transmission of data, transport blocks may be generated from the MAC layer and provided to the physical layer. In at least one embodiment, the transport block may be data to be transmitted. In at least one embodiment, the transmission in the physical layer begins with packetized resource data, which may be referred to as transport blocks. In at least one embodiment, the transport block is received by a Cyclic Redundancy Check (CRC) 5002. In at least one embodiment, a cyclic redundancy check is appended to each transport block for error detection. In at least one embodiment, cyclic redundancy check is used for error detection in a transport block. In at least one embodiment, the entire transport block is used to calculate the CRC parity bits, which are then appended to the end of the transport block. In at least one embodiment, the minimum and maximum code block sizes are specified so that the block sizes are compatible with further processing. In at least one embodiment, the input block is segmented when the input block is greater than a maximum code block size.

In at least one embodiment, the transport blocks are received and encoded by Low Density Parity Check (LDPC) encoding 5004. In at least one embodiment, NR employs Low Density Parity Check (LDPC) codes for the polarity codes of the data channel and the control channel. In at least one embodiment, LDPC codes are defined by their parity check matrices, each column representing one encoded bit, and each row representing one parity check equation. In at least one embodiment, the LDPC code is decoded by exchanging messages between variables and parity check in an iterative manner. In at least one embodiment, the proposed LDPC code for NR uses a quasi-cyclic structure, wherein the parity check matrix is defined by a smaller base matrix. In at least one embodiment, each entry of the base matrix represents a ZxZ zero matrix or a shifted ZxZ identity matrix.

In at least one embodiment, the encoded transport block is received by rate matching 5006. In at least one embodiment, the encoding block is used to create an output bitstream having a desired code rate. In at least one embodiment, rate matching 5006 is used to create an output bitstream to be transmitted at a desired code rate. In at least one embodiment, bits are selected and pruned from the buffer to create an output bitstream having a desired code rate. In at least one embodiment, a hybrid automatic repeat request (HARQ) error correction scheme is incorporated.

In at least one embodiment, in scrambling 5008, the output bits are scrambled, which may aid in privacy. In at least one embodiment, the codeword is multiplied bit by bit with the orthogonal sequence and the UE-specific scrambling sequence. In at least one embodiment, the output of scrambling 5008 can be input into modulation/mapping/precoding and other processes 5010. In at least one embodiment, various modulation, mapping, and precoding processes are performed.

In at least one embodiment, the bits output from scrambling 5008 are modulated with a modulation scheme, producing a block of modulation symbols. In at least one embodiment, the scrambled codeword is modulated using one of the modulation schemes QPSK, 16QAM, 64QAM, resulting in a block of modulation symbols. In at least one embodiment, a first time mapping of modulation symbols to transmit waveforms may be implemented using a channel interleaver process while ensuring that HARQ information is present on both slots. In at least one embodiment, modulation symbols are mapped to various layers based on the transmit antennas. In at least one embodiment, the symbols may be precoded, where they are divided into groups, and an inverse fast fourier transform may be performed. In at least one embodiment, transmission data and control multiplexing may be performed such that HARQ Acknowledgement (ACK) information exists in two slots and is mapped to resources around demodulation reference signals. In at least one embodiment, various precoding procedures are performed.

In at least one embodiment, the symbols are mapped to physical resource elements allocated in resource element mapping 5012. In at least one embodiment, the allocation size may be limited to a value of a prime factor of 2, 3, and 5. In at least one embodiment, the symbols are mapped in increasing order starting from the subcarriers. In at least one embodiment, the subcarrier mapped modulation symbol data is Orthogonal Frequency Division Multiple Access (OFDMA) modulated by IFFT operation in OFDMA modulation 5014. In at least one embodiment, the time domain representation of each symbol is concatenated and filtered using a transmit FIR filter to attenuate unwanted out-of-band emissions of adjacent bands due to phase discontinuities and the use of different numerologies. In at least one embodiment, the output of OFDMA modulation 5014 may be transmitted for receipt and processing by another system.

In at least one embodiment, the transmission may be received by OFDMA demodulation 5016. In at least one embodiment, the transmission may be initiated from the user mobile device over the cellular network, although other scenarios may exist. In at least one embodiment, the transmission may be demodulated by IFFT processing. In at least one embodiment, estimation and correction of residual Sampling Time Offset (STO) and Carrier Frequency Offset (CFO) may be performed once OFDMA demodulation by IFFT processing is completed. In at least one embodiment, both CFO and STO correction must be performed in the frequency domain, since the received signal may be a superposition of transmissions from multiple UEs multiplexed in frequency, each UE suffering from a particular residual synchronization error. In at least one embodiment, the residual CFO is estimated as a phase rotation between pilot subcarriers belonging to different OFDM symbols and corrected by a cyclic convolution operation in the frequency domain.

In at least one embodiment, the output of OFDMA demodulation 5016 can be received by resource element demapping 5018. In at least one embodiment, the resource element demapping 5018 can determine a symbol and demapping the symbol from the allocated physical resource elements. In at least one embodiment, channel estimation and equalization is performed in channel estimation 5020 to compensate for the effects of multipath propagation. In at least one embodiment, channel estimation 5020 may be utilized to minimize the effects of noise originating from various transmission layers and antennas. In at least one embodiment, the channel estimate 5020 can generate equalized symbols from the output of the resource element demapping 5018. In at least one embodiment, demodulation/demapping 5022 can receive equalized symbols from channel estimates 5020. In at least one embodiment, the equalized symbols are demapped and permuted by a layer demapping operation. In at least one embodiment, a maximum a posteriori probability (MAP) demodulation method may be used to generate a value representing a confidence level of 0 or 1 for a received bit, expressed in the form of a Log Likelihood Ratio (LLR).

In at least one embodiment, the soft demodulated bits are processed using various operations including descrambling using a circular buffer prior to LDPC decoding, deinterleaving, and rate mismatch with the soft LLR combination. In at least one embodiment, the descrambling 5024 may involve reversing the process of one or more processes of the scrambling 5008. In at least one embodiment, rate mismatch 5026 can involve reversing the process of one or more of the processes of rate matching 5006. In at least one embodiment, the descrambler 5024 may receive the output from the demodulation/demapping 5022 and descramble the received bits. In at least one embodiment, rate mismatch 5026 may receive the descrambled bits and utilize soft combining of the LLRs with a circular buffer prior to LDPC decoding 5028.

In at least one embodiment, decoding of the LDPC code in practical applications is accomplished based on an iterative belief propagation algorithm. In at least one embodiment, the LDPC code may be represented in the form of a bipartite graph in which a parity check matrix H of size mxn is a double adjacency matrix defining connections between graph nodes. In at least one embodiment, M rows of matrix H correspond to parity check nodes and N columns correspond to variable nodes, i.e., received codeword bits. In at least one embodiment, the principles of the belief propagation algorithm are based on iterative message exchanges in which posterior probabilities between variables and check nodes are updated until a valid codeword is obtained. In at least one embodiment, the LDPC decoding 5028 may output a transport block including data.

In at least one embodiment, CRC check 5030 may determine errors and perform one or more actions based on parity bits appended to the received transport block. In at least one embodiment, CRC check 5030 may analyze and process parity bits appended to the received transport block, or any information associated with the CRC. In at least one embodiment, CRC check 5030 may send the processed transport block to the MAC layer for further processing.

It should be noted that in various embodiments, the sending and receiving of data, which may be transport blocks or other variations thereof, may include various processes not depicted in fig. 50. In at least one embodiment, the process depicted in fig. 50 is not intended to be exhaustive, and further processing (such as additional modulation, mapping, multiplexing, precoding, constellation mapping/demapping, MIMO detection, decoding, and variants thereof) may be utilized in transmitting and receiving data as part of a network. In at least one embodiment, at least one component shown or described with respect to fig. 50 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 51 illustrates an architecture of a system 5100 of a network according to some embodiments. In at least one embodiment, the system 5100 is shown as including a UE 5102, a 5G access node or RAN node (shown as (R) AN node 5108), user plane functionality (shown as UPF 5104), a data network (DN 5106), which may be, for example, AN operator service, internet access, or a 3 rd party service, and a 5G core network (5 GC) (shown as CN 5110).

In at least one embodiment, the CN 5110 includes an authentication server function (AUSF 5114); core access and mobility management functions (AMF 5112); session management function (SMF 5118); network exposure function (NEF 5116); policy control function (PCF 5122); a Network Function (NF) repository function (NRF 5120); unified data management (UDM 5124); and an application function (AF 5126). In at least one embodiment, the CN 5110 may also include other elements not shown, such as structured data storage network functions (SDSFs), unstructured data storage network functions (UDSFs), and variants thereof.

In at least one embodiment, UPF 5104 may act as an anchor point for intra-RAT and inter-RAT mobility, an external PDU session point interconnected with DN 5106, and a branching point supporting multi-homed PDU sessions. In at least one embodiment, the UPF 5104 may also perform packet routing and forwarding, packet inspection, user plane part of enforcing policy rules, lawful interception packets (UP collection); traffic usage reporting, performing QoS processing (e.g., data packet filtering, gating, UL/DL rate execution) for the user plane, performing uplink traffic verification (e.g., SDF to QoS flow mapping), transport level data packet tagging in uplink and downlink, and downlink data packet buffering and downlink data notification triggering. In at least one embodiment, the UPF 5104 may include an uplink classifier to support routing traffic flows to a data network. In at least one embodiment, DN 5106 may represent various network operator services, internet access, or third party services.

In at least one embodiment, the AUSF 5114 may store data for authentication of the UE 5102 and process authentication related functions. In at least one embodiment, the AUSF 5114 can facilitate a generic authentication framework for various access types.

In at least one embodiment, the AMF5112 may be responsible for registration management (e.g., for registering the UE 5102, etc.), connection management, reachability management, mobility management, and lawful interception of AMF related events, as well as access authentication and authorization. In at least one embodiment, the AMF5112 can provide transport for SM messages of the SMF 5118 and act as a transparent proxy for routing SM messages. In at least one embodiment, the AMF5112 may also provide for transmission of a Short Message Service (SMS) message between the UE 5102 and an SMS function (SMSF) (not shown in fig. 51). In at least one embodiment, the AMF5112 may act as a secure anchor function (SEA), which may include the interaction with the AUSF 5114 and the UE 5102, and the receipt of an intermediate key established as a result of the UE 5102 authentication procedure. In at least one embodiment using USIM-based authentication, the AMF5112 may retrieve the security material from the AUSF 5114. In at least one embodiment, the AMF5112 may further comprise a Security Context Management (SCM) function that receives a key from the SEA that is used to derive access network specific keys. Furthermore, in at least one embodiment, the AMF5112 may be a termination point (N2 reference point) of the RANCP interface, a termination point of NAS (NI) signaling, and perform NAS ciphering and integrity protection.

In at least one embodiment, the AMF 5112 may also support NAS signaling with the UE 5102 over an N3 interworking function (IWF) interface. In at least one embodiment, the N3IWF may be used to provide access to untrusted entities. In at least one embodiment, the N3IWF may be the termination point for the N2 and N3 interfaces of the control plane and user plane, respectively, and thus may handle N2 signaling from the SMF and AMF for PDU sessions and QoS, encapsulating/decapsulating packets for IPSec and N3 tunnels, marking the N3 user plane data packets in the uplink, and enforcing QoS corresponding to the N3 data packet marking taking into account QoS requirements associated with such marking received over N2. In at least one embodiment, the N3IWF may also relay uplink and downlink control plane NAS (NI) signaling between the UE 5102 and the AMF 5112, and relay uplink and downlink user plane packets between the UE 5102 and the UPF 5104. In at least one embodiment, the N3IWF also provides a mechanism to establish an IPsec tunnel with the UE 5102.

In at least one embodiment, the SMF 5118 may be responsible for session management (e.g., session establishment, modification, and release, including tunnel maintenance between UPF and AN nodes); ue ip address allocation and management (including optional authorization); selecting and controlling an UP function; configuring traffic steering at the UPF to route traffic to the correct destination; terminating the interface to the policy control function; controlling part policy enforcement and QoS; lawful interception (for SM events and LI system interfaces); terminating the SM portion of the NAS message; notifying downlink data; the initiator of the AN specific SM information is sent to the AN through the AMF on N2; the SSC pattern of the session is determined. In at least one embodiment, the SMF 5118 can include the following roaming functions: processing the native implementation to apply QoSSLAB (VPLMN); a billing data collection and billing interface (VPLMN); lawful interception (for SM events and interfaces to LI systems in VPLMN); interactions with the external DN are supported to transmit PDU session grant/authentication signaling for the external DN.

In at least one embodiment, the NEF5116 may provide means for securely exposing services and capabilities provided by 3GPP network functions for third parties, internal exposure/re-exposure, application functions (e.g., AF 5126), edge computing or fog computing systems, and the like. In at least one embodiment, the NEF5116 can authenticate, authorize, and/or throttle the AF. In at least one embodiment, the NEF5116 may also translate information exchanged with the AF 5126 and information exchanged with internal network functions. In at least one embodiment, the NEF5116 may translate between AF-service-identifiers and internal 5GC information. In at least one embodiment, the NEF5116 may also receive information from other Network Functions (NFs) based on the exposed capabilities of the other network functions. In at least one embodiment, this information may be stored in NEF5116 as structured data, or in data store NF using a standardized interface. In at least one embodiment, the stored information may then be re-exposed to other NFs and AFs by the NEF5116 and/or used for other purposes, such as analysis.

In at least one embodiment, NRF 5120 may support a service discovery function, receive NF discovery requests from NF instances, and provide information of the discovered NF instances to the NF instances. In at least one embodiment, NRF 5120 also maintains information of available NF instances and services supported thereby.

In at least one embodiment, PCF5122 may provide policy rules to control plane functions to implement them and may also support a unified policy framework to manage network behavior. In at least one embodiment, PCF5122 can also implement a Front End (FE) to access subscription information related to policy decisions in the UDR of UDM 5124.

In at least one embodiment, the UDM 5124 may process subscription related information to support the processing of communication sessions by network entities and may store subscription data for the UE 5102. In at least one embodiment, the UDM 5124 can include two parts, an application FE and a User Data Repository (UDR). In at least one embodiment, the UDM may include UDMFE, responsible for the processing of credentials, location management, subscription management, and the like. In at least one embodiment, several different front ends may serve the same user in different transactions. In at least one embodiment, the UDM-FE accesses subscription information stored in the UDR and performs authentication credential processing; user identity processing; access authorization; registration/mobility management; subscription management. In at least one embodiment, the UDR may interact with the PCF 5122. In at least one embodiment, the UDM 5124 may also support SMS management, where SMS-FE implements similar application logic as previously discussed.

In at least one embodiment, the AF 5126 can provide application impact on flow routing, access to Network Capability Exposure (NCE), and interact with a policy framework for policy control. In at least one embodiment, NCE may be a mechanism that allows 5GC and AF 5126 to provide information to each other through NEF 5116, which may be used for edge computing implementations. In at least one embodiment, network operators and third party services may be hosted near the UE 5102 access point to enable efficient service delivery by reducing end-to-end delay and load on the transport network. In at least one embodiment, for edge computing implementations, the 5GC may select a UPF 5104 near the UE 5102 and perform traffic steering from the UPF 5104 to the DN 5106 over the N6 interface. In at least one embodiment, this may be based on UE subscription data, UE location, and information provided by AF 5126. In at least one embodiment, the AF 5126 can affect UPF (re) selection and traffic routing. In at least one embodiment, based on the operator deployment, the network operator may allow the AF 5126 to interact directly with the associated NF when the AF 5126 is considered a trusted entity.

In at least one embodiment, the CN 5110 may include an SMSF that may be responsible for SMS subscription checking and authentication, and relaying SM messages to/from the UE 5102 to/from other entities, such as SMS-GMSC/IWMSC/SMS-router. In at least one embodiment, SMS may also interact with AMF 5112 and UDM 5124 for informing the process that UE 5102 is available for SMS transmission (e.g., setting a UE unreachable flag and informing UDM 5124 when UE 5102 is available for SMS).

In at least one embodiment, the system 5100 can include the following service-based interfaces: namf: the AMF shows a service-based interface; nsmf: the SMF shows a service-based interface; nnef: the NEF shows a service-based interface; npcf: a service-based interface shown by the PCF; nudm: a service-based interface shown by UDM; naf: the service-based interface shown by AF; nnrf: NRF shows service-based interfaces; nausf: the AUSF shows a service-based interface.

In at least one embodiment, the system 5100 can include the following reference points: n1: a reference point between the UE and the AMF; n2: (R) a reference point between AN and AMF; and N3: (R) a reference point between AN and UPF; n4: a reference point between SMF and UPF; and N6: reference points between UPF and data network. In at least one embodiment, there may be more reference points and/or service-based interfaces between NF services in the NF, however, these interfaces and reference points are omitted for clarity. In at least one embodiment, the NS reference point may be between the PCF and the AF; the N7 reference point may be between PCF and SMF; the N11 reference point is between AMF and SMF; etc. In at least one embodiment, the CN 5110 may include an Nx interface, which is an inter-CN interface between the MME and the AMF 5112, to enable interworking between the CN 5110 and the CN 7251.

In at least one embodiment, the system 5100 can include a plurality of RAN nodes (e.g., R) AN nodes 5108), wherein AN Xn interface is defined between two or more (R) AN nodes 5108 (e.g., gnbs) connected to the 5gc 5110, between a (R) AN node 5108 (e.g., gNB) connected to the CN 5110 and AN eNB (e.g., macro RAN node), and/or between two enbs connected to the CN 5110.

In at least one embodiment, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, an Xn-U may provide for the non-guaranteed delivery of user plane PDUs and support/provide data forwarding and flow control functions. In at least one embodiment, the Xn-C may provide management and error handling functions, functions to manage the Xn-C interface; mobility support of the UE 5102 in a CONNECTED mode (e.g., CM-CONNECTED) includes functionality to manage UE mobility in a CONNECTED mode between one or more (R) AN nodes 5108. In at least one embodiment, mobility support may include a context transfer from AN old (source) service (R) AN node 5108 to a new (target) service (R) AN node 5108; and controls the user plane tunnel between the old (source) serving (R) AN node 5108 to the new (target) serving (R) AN node 5108.

In at least one embodiment, the protocol stack of the Xn-U may include a transport network layer built on top of an Internet Protocol (IP) transport layer, and a GTP-U layer above the UDP and/or IP layer for carrying user plane PDUs. In at least one embodiment, the Xn-C protocol stack may include an application layer signaling protocol, referred to as Xn application protocol (Xn-AP), and a transport network layer built upon the SCTP layer. In at least one embodiment, the SCTP layer may be above the IP layer. In at least one embodiment, the SCTP layer provides for the guaranteed delivery of application layer messages. In at least one embodiment, signaling PDUs are conveyed in the transport IP layer using point-to-point transport. In at least one embodiment, the Xn-U protocol stack and/or the Xn-C protocol stack may be the same or similar to the user plane and/or control plane protocol stacks shown and described herein. In at least one embodiment, at least one component shown or described with respect to fig. 51 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 52 is an illustration of a control plane protocol stack according to some embodiments. In at least one embodiment, control plane 5200 is shown as a communication protocol stack between UE 4202 (or alternatively, UE 4204), RAN 4216, and MME 4228.

In at least one embodiment, the PHY layer 5202 may transmit or receive information used by the MAC layer 5204 over one or more air interfaces. In at least one embodiment, the PHY layer 5202 may further perform link adaptation or Adaptive Modulation and Coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers, such as the RRC layer 5210. In at least one embodiment, PHY layer 5202 may further perform error detection for the transport channel, forward Error Correction (FEC) encoding/decoding of the transport channel, modulation/demodulation of the physical channel, interleaving, rate matching, mapping to the physical channel, and multiple-input multiple-output (MIMO) antenna processing.

In at least one embodiment, the MAC layer 5204 may perform mapping between logical channels and transport channels, multiplexing MAC Service Data Units (SDUs) from one or more logical channels onto Transport Blocks (TBs) for transmission to a PHY via the transport channels, demultiplexing MAC SDUs from Transport Blocks (TBs) transmitted from the PHY over the transport channels to one or more logical channels, multiplexing MAC SDUs onto TBs, scheduling information reporting, error correction by hybrid automatic repeat request (HARD), and logical channel prioritization.

In at least one embodiment, the RLC layer 5206 can operate in a variety of modes of operation, including: transparent Mode (TM), unacknowledged Mode (UM), and Acknowledged Mode (AM). In at least one embodiment, the RLC layer 5206 may perform transmission of upper layer Protocol Data Units (PDUs), error correction by automatic repeat request (ARQ) for AM data transmission, and concatenation, segmentation, and reassembly transfer of RLC SDUs for UM and AM data. In at least one embodiment, the RLC layer 5206 may also perform re-segmentation of RLC data PDUs for AM data transmissions, re-ordering RLC data PDUs for UM and AM data transmissions, detecting duplicate data for UM and AM data transmissions, discarding RLC SDUs for UM and AM data transmissions, detecting protocol errors for AM data transmissions, and performing RLC re-establishment.

In at least one embodiment, the PDCP layer 5208 can perform header compression and decompression of IP data, maintain PDCP Sequence Numbers (SNs), perform sequential delivery of upper layer PDUs when reconstructing lower layers, eliminate duplicate re-establishment of lower layer SDUs of radio bearers mapped on RLCAM, encrypt and decrypt control plane data, perform integrity protection and integrity verification of control plane data, control timer-based data dropping, and perform security operations (e.g., ciphering, deciphering, integrity protection, integrity verification, etc.).

In at least one embodiment, the primary services and functions of the RRC layer 5210 may include broadcasting of system information (e.g., included in a Master Information Block (MIB) or System Information Block (SIB) associated with a non-access stratum (NAS)), broadcasting of system information associated with an Access Stratum (AS), paging, establishment, maintenance and release of RRC connections between a UE and an E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance and release of point-to-point radio bearers, security functions including key management, inter-Radio Access Technology (RAT) mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, the MIB and SIB may include one or more Information Elements (IEs), each of which may include a separate data field or data structure.

In at least one embodiment, UE 4202 and RAN 4216 may exchange control plane data via a protocol stack comprising PHY layer 5202, MAC layer 5204, RLC layer 5206, PDCP layer 5208, and RRC layer 5210 using a Uu interface (e.g., an LTE-Uu interface).

In at least one embodiment, the non-access stratum (NAS) protocol (NAS protocol 5212) forms the highest layer of the control plane between UE 4202 and MME 4228. In at least one embodiment, NAS protocol 5212 supports mobility and session management procedures for UE 4202 to establish and maintain an IP connection between UE 4202 and P-GW 4234.

In at least one embodiment, the Si application protocol (S1-AP) layer (Si-AP layer 5222) can support the functionality of the Si interface and include basic procedures (EP). In at least one embodiment, the EP is an interworking unit between the RAN 4216 and the CN 4228. In at least one embodiment, the S1-AP layer services may include two groups: UE-related services and non-UE-related services. In at least one embodiment, the functions performed by these services include, but are not limited to: E-UTRAN radio access bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transport, RAN Information Management (RIM), and configuration transport.

In at least one embodiment, a Stream Control Transmission Protocol (SCTP) layer (alternatively referred to as a stream control transmission protocol/internet protocol (SCTP/IP) layer) (SCTP layer 5220) may ensure that signaling messages are reliably transported over the IP protocol at the RAN 4216 and MME 4228, supported by IP layer 5218. In at least one embodiment, the L2 layer 5216 and the L1 layer 5214 can refer to communication links (e.g., wired or wireless) used by the RAN node and MME to exchange information.

In at least one embodiment, the RAN 4216 and MME 4228 may exchange control plane data via a protocol stack comprising an L1 layer 5214, an L2 layer 5216, an IP layer 5218, an SCTP layer 5220, and a Si-AP layer 5222 using an S1-MME interface. In at least one embodiment, at least one component shown or described with respect to fig. 52 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 53 is an illustration of a user plane protocol stack in accordance with at least one embodiment. In at least one embodiment, the user plane 5300 is shown as a communication protocol stack between the UE 4702, RAN 4716, S-GW4730 and P-GW 4734. In at least one embodiment, the user plane 5300 may use the same protocol layer as the control plane 5200. For example, in at least one embodiment, the UE 4702 and the RAN 4716 may utilize a Uu interface (e.g., an LTE-Uu interface) to exchange user plane data via a protocol stack including a PHY layer 5202, a MAC layer 5204, an RLC layer 5206, a PDCP layer 5208.

In at least one embodiment, a General Packet Radio Service (GPRS) tunneling protocol for the user plane (GTP-U) layer (GTP-U layer 5304) may be used to carry user data within a GPRS core network and between a radio access network and the core network. In at least one embodiment, the transmitted user data may be packets in any of, for example, IPv4, IPv6, or PPP formats. In at least one embodiment, the UDP and IP security (UDP/IP) layer (UDP/IP layer 5302) may provide a checksum for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication of selected data streams. In at least one embodiment, RAN 4716 and S-GW4730 may utilize the S1-U interface to exchange user plane data via a protocol stack that includes L1 layer 5214, L2 layer 5216, UDP/IP layer 5302, and GTP-U layer 5304. In at least one embodiment, the S-GW4730 and the P-GW4734 may utilize the S5/S8a interface to exchange user plane data via a protocol stack comprising L1 layer 5214, L2 layer 5216, UDP/IP layer 5302 and GTP-U layer 5304. In at least one embodiment, as discussed above with respect to fig. 52, the NAS protocol supports mobility and session management procedures for UE 4702 to establish and maintain IP connectivity between UE 4702 and P-GW 4734. In at least one embodiment, at least one component shown or described with respect to fig. 53 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 54 illustrates components 5400 of a core network in accordance with at least one embodiment. In at least one embodiment, the components of the CN 4738 may be implemented in one physical node or in a separate physical node, including components that read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, network Function Virtualization (NFV) is used to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). In at least one embodiment, a logical instance of CN 4738 may be referred to as network slice 5402 (e.g., network slice 5402 is shown as including HSS 4732, MME 4728, and S-GW 4730). In at least one embodiment, a logical instance of a portion of CN 4738 may be referred to as network sub-slice 5404 (e.g., network sub-slice 5404 is shown as including P-GW 4734 and PCRF 4736).

In at least one embodiment, the NFV architecture and infrastructure can be used to virtualize one or more network functions or be performed by proprietary hardware onto physical resources including industry standard server hardware, storage hardware, or a combination of switches. In at least one embodiment, the NFV system may be used to perform virtual or reconfigurable implementations of one or more EPC components/functions. In at least one embodiment, at least one component shown or described with respect to fig. 54 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

Fig. 55 is a block diagram illustrating components of a system 5500 supporting Network Function Virtualization (NFV) in accordance with at least one embodiment. In at least one embodiment, system 5500 is shown to include a virtualized infrastructure manager (shown as VIM 5502), a network function virtualized infrastructure (shown as NFVI 5504), a VNF manager (shown as VNFM 5506), a virtualized network function (shown as VNF 5508), an element manager (shown as EM 5510), a NFVO coordinator (shown as NFVO 5512), and a network manager (shown as NM 5514).

In at least one embodiment, VIM 5502 manages the resources of NFVI 5504. In at least one embodiment, NFVI 5504 may include physical or virtual resources and applications (including hypervisors) for executing system 5500. In at least one embodiment, VIM 5502 may use NFVI 5504 to manage the lifecycle of virtual resources (e.g., creation, maintenance, and tear down of Virtual Machines (VMs) associated with one or more physical resources), track VM instances, track performance, failure, and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

In at least one embodiment, the VNFM 5506 may manage the VNF 5508. In at least one embodiment, VNF 5508 may be used to perform EPC components/functions. In at least one embodiment, VNFM 5506 may manage the life cycle of VNF 5508 and track performance, faults, and security of the virtual aspects of VNF 5508. In at least one embodiment, the EM 5510 may track performance, faults, and security in the functional aspects of the VNF 5508. In at least one embodiment, the tracking data from VNFM 5506 and EM 5510 may include, for example, performance Measurement (PM) data used by VIM 5502 or NFVI 5504. In at least one embodiment, both VNFM 5506 and EM 5510 may extend the number of VNFs of upper/lower system 5500.

In at least one embodiment, NFVO 5512 may coordinate, authorize, release, and use the resources of NFVI5504 to provide the requested service (e.g., perform EPC functions, components, or slices). In at least one embodiment, NM 5514 may provide an end user function package responsible for managing the network, which may include network elements with VNFs, non-virtualized network functions, or both (management of VNFs may be through EM 5510).

In at least one embodiment, one or more components of the systems and/or processors disclosed above may be in communication with one or more CPU, ASIC, GPU, FPGA or other hardware, circuits, or integrated circuit components including, for example, an amplifier or upsampler to amplify an image, a sampler to sample an image (e.g., as part of a DSP), a neural network circuit configured to perform an amplifier to amplify an image (e.g., from a low resolution image to a high resolution image), or other hardware to modify or generate an image, frame, or video to adjust its resolution, size, or pixels; one or more components of the systems and/or processors disclosed above may perform the methods, operations, or instructions of generating or modifying images using the components described in this disclosure. In at least one embodiment, at least one component shown or described with respect to fig. 55 is used to implement the techniques and/or functions described in connection with fig. 1-15B.

At least one embodiment of the present disclosure may be described according to the following clauses:

1. a processor, comprising:

one or more circuits for executing the application programming interface API such that the data is stored in a selected store to be used for transferring information between the plurality of fifth generation new radio 5G-NR computing resources.

2. The processor of clause 1, wherein execution of the API causes one of the plurality of 5G-NR computing resources to:

transmitting the data stored in the store to another 5G-NR computing resource of the plurality of 5G-NR computing resources; and

the reference counter indicating when to release the selected store is decremented.

3. The processor of any of clauses 1-2, wherein the information is to be transmitted between one of the plurality of 5G-NR computing resources associated with a first information transmission type and another of the plurality of 5G-NR computing resources associated with a second information transmission type.

4. The processor of any of clauses 1-3, wherein the one or more circuits are further to execute the API without information about a transmission type associated with one or more of the 5G-NR computing resources.

5. The processor of any one of clauses 1-4, wherein executing the API further causes one or more 5G-NR computing resources of the plurality of 5G-NR computing resources to perform one or more operations associated with a plurality of information transfer types associated with one or more 5G-NR computing resources of the plurality of 5G-NR computing resources.

6. The processor of any of clauses 1-5, wherein the API is based at least in part on information identifying an information transmission type associated with one or more 5G-NR computing resources of the plurality of 5G-NR computing resources.

7. The processor of any one of clauses 1-6, wherein executing the API further causes one or more 5G-NR computing resources of the plurality of 5G-NR computing resources to perform an operation related to a first information transmission type based at least in part on a corresponding operation related to a second information transmission type.

8. The processor of any of clauses 1-7, wherein:

the plurality of 5G-NR computing resources are associated with a 5G-NR network protocol stack comprising a first layer, a second layer, and a third layer;

a first 5G-NR computing resource of the plurality of 5G-NR computing resources is associated with the first layer;

A second 5G-NR computing resource of the plurality of 5G-NR computing resources is associated with the second layer;

the API is associated with the third layer; and

the third layer is located between the first layer and the second layer.

9. The processor of any of clauses 1-8, wherein:

the API is further for transferring information between a first layer and a second layer corresponding to a 5G-NR network protocol, wherein one or more 5G-NR computing resources of the plurality of 5G-NR computing resources associated with the second layer requests an operation associated with a first information transfer type; and

execution of the API causes one or more 5G-NR computing resources of the plurality of 5G-NR computing resources associated with the first layer to perform an operation associated with a second transport type.

10. A system comprising a memory to store instructions that, as a result of execution by one or more processors, cause the system to:

the application programming interface API is executed such that the data is stored in a selected store to be used for transferring information between the plurality of fifth generation new radio 5G-NR computing resources.

11. The system of clause 10, wherein execution of the API is based at least in part on a transport protocol associated with one 5G-NR computing resource of the plurality of 5G-NR computing resources.

12. The system of any of clauses 10-11, wherein:

the information is to be transmitted between a first layer and a second layer of a 5G-NR network protocol stack; and

the first layer and the second layer are each associated with a different transport protocol.

13. The system of any of clauses 10-12, wherein an application associated with one of the plurality of 5G-NR computing resources invokes the API and does not have information about any transport protocols supported by one or more of the plurality of 5G-NR computing resources.

14. The system of any of clauses 10-13, wherein the API is embedded in another API.

15. The system of any of clauses 10-14, wherein the information is transmitted using an application that causes a call from one layer associated with one transport protocol to perform an operation in a second layer associated with a second transport protocol.

16. The system of any of clauses 10-15, further comprising:

a network coordinator configured to identify one or more transmission profiles supported by one 5G-NR computing resource of the plurality of 5G-NR computing resources, and to deploy a second 5G-NR computing resource of the plurality of 5G-NR computing resources with the one 5G-NR computing resource, the one 5G-NR computing resource configured with a transmission profile supported by the second 5G-NR computing resource.

17. The system of any of clauses 10-16, wherein one or more 5G-NR computing resources of the plurality of 5G-NR computing resources are virtual devices.

18. A machine-readable medium having one or more instructions stored thereon that, if executed by one or more processors, cause the one or more processors to at least:

19. The machine-readable medium of clause 18, wherein the execution of the API is based at least in part on a transmission configuration associated with one of the plurality of 5G-NR computing resources.

20. The machine readable medium of any of clauses 18-19, wherein:

the information is transmitted between a first layer and a second layer of a 5G-NR network protocol stack using a third layer between the first layer and the second layer, the third layer based at least in part on a plurality of transmission protocols.

21. The machine-readable medium of any of clauses 18-20, wherein the one or more circuits are further to execute the API without information associated with a transmission type associated with one or more of the 5G-NR computing resources.

22. The machine readable medium of any of clauses 18-21, wherein the one or more processors are one or more Graphics Processing Units (GPUs).

23. The machine readable medium of any of clauses 18-22, wherein:

one 5G-NR computing resource of the plurality of 5G-NR computing resources is to invoke the API; and

execution of the API causes, at least in part, the one 5G-NR computing resource to transmit information to one or more other 5G-NR computing resources of the plurality of 5G-NR computing resources supporting a different transmission protocol without modifying the one 5G-NR computing resource.

24. The machine readable medium of any of clauses 18-23, wherein:

the selected store is an allocated buffer; and

the API is further for decrementing a reference counter associated with the allocated buffer; and

if the decremented reference counter remains at a value of zero, the allocated buffer is deselected.

25. The machine-readable medium of any of clauses 18-24, wherein one 5G-NR computing resource of the plurality of 5G-NR computing resources has been configured with a transmission profile supported by a second 5G-NR computing resource of the plurality of 5G-NR computing resources.

26. A method, comprising:

27. The method of clause 26, wherein the execution of the API is based at least in part on a transmission profile associated with one of the plurality of 5G-NR computing resources.

28. The method of any of clauses 26-27, further comprising: one or more transmission profiles supported by one or more 5G-NR computing resources of the plurality of 5G-NR computing resources are identified.

29. The method of any of clauses 26-28, further comprising:

configuring said one 5G-NR computing resource of said plurality of 5G-NR computing resources using a transmission profile supported by said one 5G-NR computing resource; and

the one configured 5G-NR computing resource is deployed with a second 5G-NR computing resource.

30. The method of any of clauses 26-29, wherein the API is invoked by one 5G-NR computing resource of the plurality of 5G-NR computing resources, the one 5G-NR computing resource being deployed with a second 5G-NR computing resource of the plurality of 5G-NR computing resources, wherein the second 5G-NR computing resource is configured with one or more transmission profiles.

31. The method of any of clauses 26-30, further comprising: the information is transmitted using an application that maps the API to an operation related to a transmission protocol, wherein the application is at least partially implemented on a hardware accelerator.

32. The method of any of clauses 26-31, wherein the API is embedded in another API.

33. The method of any of clauses 26-32, wherein:

the information is transmitted between two layers of a 5G-NR network protocol stack, wherein each layer is associated with a different transmission protocol; and

the API is located in a third layer.

34. The method of any one of clauses 26-33, wherein:

execution of the API does not decrement the reference counter;

the reference counter is associated with the selected store; and

the selected storage is further used as part of a zero copy buffer method.

35. The method of any of clauses 26-34, wherein the information comprises different messages each associated with a different information transmission type; and

the information is transmitted between two 5G-NR computing resources of the plurality of 5G-NR computing resources using one transmission.

Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the specific forms or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure as defined in the appended claims.

The use of the terms "a" and "an" and "the" and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of terms. Unless otherwise indicated, the terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (meaning "including, but not limited to"). The term "coupled," when unmodified and referring to a physical connection, is to be interpreted as including in part or in whole, being connected or linked together, even if something intervenes. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, unless otherwise indicated or contradicted by context, the use of the term "set" (e.g., "a set of items") or "subset" is to be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily denote a proper subset of the corresponding set, but the subset and the corresponding set may be equal.

Conjunctive language, such as a phrase in the form of "at least one of A, B and C" or "at least one of A, B and C", is understood in this context to mean generally any non-empty subset of items, terms, etc., that may be a or B or C, or a set of a and B and C, unless otherwise explicitly stated or clearly contradicted by context. For example, in the illustrative example of a set of three members, the conjunctive phrases "at least one of A, B and C" and "at least one of A, B and C" refer to any of the following sets: { A }, { B }, { C }, { A, B }, { A, C }, { B, C }, { A, B, C }. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B, and at least one of C to each be present. Further, unless otherwise indicated herein or otherwise clearly contradicted by context, the term "plurality" refers to the state of a plurality (e.g., "a plurality of items" refers to a plurality of items). In at least one embodiment, the number of items is at least two, but may be more when indicated explicitly or by context. Furthermore, unless stated otherwise or otherwise clear from the context, the phrase "based on" means "based at least in part on" rather than "based only on".

The operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, processes such as those described herein (or variations and/or combinations thereof) are performed under control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that is jointly executed on one or more processors via hardware or combinations thereof. In at least one embodiment, the code is stored on a computer readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include a transient signal (e.g., a propagated transient electrical or electromagnetic transmission) but includes non-transient data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of the transient signal. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory storing executable instructions) that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause the computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer readable storage media includes a plurality of non-transitory computer readable storage media and one or more individual non-transitory storage media of the plurality of non-transitory computer readable storage media lack all code and the plurality of non-transitory computer readable storage media collectively store all code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors-e.g., a non-transitory computer readable storage medium stores instructions and a main central processing unit ("CPU") executes some instructions and a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors and different processors execute different subsets of instructions.

Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such computer system is configured with suitable hardware and/or software capable of performing the operations. Further, a computer system implementing at least one embodiment of the present disclosure is a single device and, in another embodiment, a distributed computer system comprising multiple devices operating in different manners such that the distributed computer system performs the operations described herein and such that a single device does not perform all of the operations.

The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the disclosed embodiments and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in particular examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

Unless specifically stated otherwise, it is appreciated that throughout the description, terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical quantities (e.g., electronic quantities) within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system memories, registers or other such information storage, transmission or display devices.

In a similar manner, the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory and converts the electronic data into other electronic data that may be stored in registers and/or memory. As a non-limiting example, a "processor" may be a CPU or GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and/or hardware entities, such as tasks, threads, and intelligent agents, that perform work over time. Furthermore, each process may refer to a plurality of processes for executing instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" are used interchangeably herein as long as the system can embody one or more methods and the methods can be considered a system.

In at least one embodiment, the arithmetic logic unit is a set of combinational logic circuits that employ one or more inputs to produce a result. In at least one embodiment, the processor uses arithmetic logic units to implement mathematical operations, such as addition, subtraction, or multiplication. In at least one embodiment, an arithmetic logic unit is used to implement a logical operation, such as a logical AND/OR OR XOR. In at least one embodiment, the arithmetic logic unit is stateless and is made of physical switching components (such as semiconductor transistors) arranged to form logic gates. In at least one embodiment, the arithmetic logic unit may operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, the arithmetic logic unit may be configured as an asynchronous logic circuit having internal states that are not maintained in the associated register set. In at least one embodiment, an arithmetic logic unit is used by a processor to combine operands stored in one or more registers of the processor and produce an output that can be stored by the processor in another register or memory location.

In at least one embodiment, as a result of processing an instruction retrieved by the processor, the processor presents one or more inputs or operands to an arithmetic logic unit, thereby causing the arithmetic logic unit to produce a result based at least in part on instruction code provided to the inputs of the arithmetic logic unit. In at least one embodiment, the instruction code provided by the processor to the ALU is based at least in part on instructions executed by the processor. In at least one embodiment, combinational logic in the ALU processes the inputs and produces outputs that are placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on the output bus such that clocking the processor causes the results produced by the ALU to be sent to the desired location.

Within the scope of the present application, the term arithmetic logic unit or ALU is used to refer to any computational logic circuit that processes operands to produce a result. For example, in this document, the term ALU may refer to a floating point unit, DSP, tensor core, shader core, coprocessor, or CPU.

Reference herein may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, computer system or computer-implemented machine. The process of obtaining, acquiring, receiving or inputting analog and digital data may be accomplished in a variety of ways, such as by receiving the data as a parameter of a function call or a call to an application programming interface. In some embodiments, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data via a serial or parallel interface. In another embodiment, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting the data from the providing entity to the acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data may be implemented by taking the data as input or output parameters for a function call, parameters for an application programming interface, or inter-process communication mechanism.

While the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of the present disclosure. Furthermore, while specific assignments of responsibilities are defined above for purposes of discussion, various functions and responsibilities may be assigned and divided in different ways depending on the circumstances.

Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A processor, comprising:

2. The processor of claim 1, wherein execution of the API causes one 5G-NR computing resource of the plurality of 5G-NR computing resources to:

3. The processor of claim 1, wherein the information is to be transmitted between one of the plurality of 5G-NR computing resources associated with a first information transmission type and another of the plurality of 5G-NR computing resources associated with a second information transmission type.

4. The processor of claim 1, wherein the one or more circuits are further to execute the API without information regarding a type of transmission associated with one or more of the 5G-NR computing resources.

5. The processor of claim 1, wherein executing the API further causes one or more 5G-NR computing resources of the plurality of 5G-NR computing resources to perform one or more operations associated with a plurality of information transfer types associated with one or more 5G-NR computing resources of the plurality of 5G-NR computing resources.

6. The processor of claim 1, wherein the API is based at least in part on information identifying an information transmission type associated with one or more 5G-NR computing resources of the plurality of 5G-NR computing resources.

7. The processor of claim 1, wherein executing the API further causes one or more 5G-NR computing resources of the plurality of 5G-NR computing resources to perform operations related to a first information transfer type based at least in part on corresponding operations related to a second information transfer type.

8. The processor of claim 1, wherein:

the API is associated with the third layer; and

the third layer is located between the first layer and the second layer.

9. The processor of claim 1, wherein:

11. The system of claim 10, wherein execution of the API is based at least in part on a transport protocol associated with one 5G-NR computing resource of the plurality of 5G-NR computing resources.

12. The system of claim 10, wherein:

13. The system of claim 10, wherein an application associated with one of the plurality of 5G-NR computing resources invokes the API and does not have information about any transport protocols supported by one or more of the plurality of 5G-NR computing resources.

14. The system of claim 10, wherein the APII is embedded within another API.

15. The system of claim 10, wherein the information is transmitted using an application that causes a call from one layer associated with one transport protocol to perform an operation in a second layer associated with a second transport protocol.

16. The system of claim 10, further comprising:

17. The system of claim 10, wherein one or more 5G-NR computing resources of the plurality of 5G-NR computing resources are virtual devices.

19. The machine-readable medium of claim 18, wherein execution of the API is based at least in part on a transmission configuration associated with one of the plurality of 5G-NR computing resources.

20. The machine-readable medium of claim 18, wherein:

21. The machine-readable medium of claim 18, wherein the one or more circuits are further to execute the API without information associated with a transmission type associated with one or more of the 5G-NR computing resources.

22. The machine readable medium of claim 18, wherein the one or more processors are one or more graphics processing units, GPUs.

23. The machine-readable medium of claim 18, wherein:

24. The machine-readable medium of claim 18, wherein:

the selected store is an allocated buffer; and

25. The machine-readable medium of claim 18, wherein one 5G-NR computing resource of the plurality of 5G-NR computing resources has been configured with a transmission profile supported by a second 5G-NR computing resource of the plurality of 5G-NR computing resources.

26. A method, comprising:

27. The method of claim 26, wherein execution of the API is based at least in part on a transmission profile associated with one of the plurality of 5G-NR computing resources.

28. The method of claim 26, further comprising: one or more transmission profiles supported by one or more 5G-NR computing resources of the plurality of 5G-NR computing resources are identified.

29. The method of claim 26, further comprising:

30. The method of claim 26, wherein the API is invoked by one of the plurality of 5G-NR computing resources, the one 5G-NR computing resource deployed with a second 5G-NR computing resource of the plurality of 5G-NR computing resources, wherein the second 5G-NR computing resource is configured with one or more transmission profiles.

31. The method of claim 26, further comprising: the information is transmitted using an application that maps the API to an operation related to a transmission protocol, wherein the application is at least partially implemented on a hardware accelerator.

32. The method of claim 26, wherein the API is embedded within another API.

33. The method of claim 26, wherein:

the API is located in a third layer.

34. The method of claim 26, wherein:

execution of the API does not decrement the reference counter;

the reference counter is associated with the selected store; and

the selected storage is further used as part of a zero copy buffer method.

35. The method of claim 26, wherein the information comprises different messages each associated with a different information transmission type; and