CN116774806B

CN116774806B - Dynamic voltage frequency adjustment method and system and electronic equipment

Info

Publication number: CN116774806B
Application number: CN202311075415.0A
Authority: CN
Inventors: 李垒
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-08-25
Filing date: 2023-08-25
Publication date: 2023-11-17
Anticipated expiration: 2043-08-25
Also published as: CN116774806A

Abstract

The application discloses a dynamic voltage frequency adjustment method, a system and electronic equipment, which relate to the technical field of integrated circuits and are applied to a voltage dynamic adjustment device comprising an instruction operation unit, wherein the method can comprise the following steps: one or more instructions are executed at a first operating frequency and a first operating voltage by an instruction arithmetic unit. Based on the executed instruction output by the instruction operation unit from the first time to the second time and the instruction which is not executed by the buffer memory at the second time, whether the first working frequency needs to be reduced to the second working frequency is determined. When it is determined that the first operating frequency needs to be reduced to the second operating frequency, the operating frequency of the instruction arithmetic unit is reduced from the first operating frequency to the second operating frequency.

Description

Dynamic voltage frequency adjustment method and system and electronic equipment

Technical Field

The present application relates to the field of integrated circuits, and in particular, to a dynamic voltage frequency adjustment method, system and electronic device.

Background

In the technical field of integrated circuits, the power consumption of a chip is closely related to the operating voltage and operating frequency of the chip. The greater the operating frequency of the chip, the greater the operating voltage of the chip and therefore the greater the power consumption of the chip. The minimum operating voltage required by the chip can be determined by factors such as process deviation, operating temperature, operating frequency, chip aging index and the like of the chip. If a fixed operating voltage is used for the chip, unnecessary power consumption is caused to the chip when the minimum operating voltage required for the chip is small. Therefore, how to adjust the working voltage and the working frequency of the chip according to the actual requirement of the chip, reduce the power consumption of the chip, and maintain the working stability of the chip becomes a technical problem to be solved in the present day.

Disclosure of Invention

The application provides a dynamic voltage frequency adjustment method, a system and electronic equipment, which are used for predicting the working voltage change condition of an instruction operation unit according to the operation condition of an instruction, and adjusting the working frequency of the instruction operation unit in advance before the working voltage drop of the instruction operation unit occurs, so that the problem that the working voltage is not matched with the working frequency due to time delay caused by the adjustment of the working frequency, and the system operation is failed is solved.

In a first aspect, the present application provides a voltage dynamic adjustment device, comprising an instruction operation unit, an instruction analysis unit, a clock generation unit, a power supply unit, and an adaptive voltage adjustment AVS control unit, wherein: the clock generating unit is used for outputting a clock signal to the instruction operation unit, wherein the clock signal is used for controlling the working frequency of the instruction operation unit. The power supply unit is used for outputting a voltage signal to the instruction operation unit, wherein the voltage signal is used for controlling the working voltage of the instruction operation unit. The instruction operation unit is used for operating one or more instructions at a first operating frequency and a first operating voltage. The instruction analysis unit is used for determining whether to output a high-level instruction signal to the AVS control unit based on the instruction which is operated between the first time and the second time and the instruction which is cached at the second time and is not operated. The high level indication signal is used for indicating that the working voltage of the instruction operation unit is reduced at a third moment, and the third moment is later than the second moment. The AVS control unit is used for reducing the working frequency of the instruction operation unit from a first working frequency to a second working frequency through the clock generation unit when receiving the high-level instruction signal output by the instruction analysis unit. Wherein the second operating frequency is less than the first operating frequency.

In one possible implementation, the voltage dynamic adjustment device further includes a performance detection unit, where the performance detection unit is configured to detect an operating voltage of the instruction operation unit. The AVS control unit is also used for acquiring the working voltage of the instruction operation unit through the performance detection unit. The AVS control unit is also used for adjusting the working frequency of the instruction operation unit through the clock generation unit based on the change rate of the working voltage.

In one possible implementation, the AVS control unit is specifically configured to: the operating voltage of the instruction operation unit is acquired by the performance detection unit at every specified detection frequency.

In one possible implementation, the instructions that have been operated on between the first time and the second time include N1 instructions, and the instructions that have been cached at the second time and that have not been operated on include N2 instructions. The instruction analysis unit is specifically configured to: based on the first record table, a first average current consumed during the N1 instruction operations and a second average current consumed during the N2 instruction operations are determined. The first record table is used for current consumed in operation of each instruction. When the second average current is larger than the first average current and the difference value between the first average current and the second average current is larger than a first specified threshold value, the high level indication signal is output to the AVS control unit.

In one possible implementation, the AVS control unit is further configured to: when receiving the low level indication signal output by the instruction analysis unit, determining that the instruction operation unit keeps the first operating frequency unchanged.

In one possible implementation, the instructions that have been operated on between the first time and the second time include N1 instructions, and the instructions that have been cached at the second time and that have not been operated on include N2 instructions. The instruction analysis unit is specifically configured to: based on the first record table, a first average current consumed during the N1 instruction operations and a second average current consumed during the N2 instruction operations are determined. The first record table is used for current consumed in operation of each instruction. And outputting the low-level indication signal to the AVS control unit when a difference between the second average current and the second average current is smaller than a first specified threshold or when the second average current is smaller than the first average current and a difference between the first average current and the second average current is larger than the first specified threshold.

In one possible implementation, the AVS control unit is further configured to: when the high level indication signal is received, the detection frequency is set to a first detection frequency.

In one possible implementation, the AVS control unit is further configured to: when the low level indication signal is received, the detection frequency is set to a second detection frequency.

In one possible implementation, the AVS control unit is specifically configured to: when the falling slope or the rising slope of the working voltage is determined to be larger than a second designated threshold value, the current working frequency of the instruction operation unit is kept unchanged. When it is determined that the falling slope of the operating voltage is smaller than the second specified threshold and larger than a third specified threshold, the operating frequency of the instruction operation unit is reduced by a first percentage by the clock generation unit. When it is determined that the falling slope of the operating voltage is smaller than the third specified threshold and larger than the fourth specified threshold, the operating frequency of the instruction operation unit is reduced by a second percentage by the clock generation unit. When the rising slope of the working voltage is smaller than the second specified threshold and larger than the third specified threshold, the current working frequency of the instruction operation unit is kept unchanged. When it is determined that the rising slope of the operating voltage is smaller than the third specified threshold and larger than the fourth specified threshold, the operating frequency of the instruction arithmetic unit is raised by a third percentage by the clock generating unit.

In a second aspect, the present application provides a dynamic voltage frequency adjustment method applied to a voltage dynamic adjustment device including an instruction operation unit, the method including: one or more commands are operated at a first operating frequency and a first operating voltage by the command operation unit. Based on the instruction which is operated between the first time and the second time and the instruction which is cached at the second time and is not operated, which is output by the instruction operation unit, whether the first working frequency needs to be reduced to the second working frequency is determined. When it is determined that the first operating frequency needs to be reduced to the second operating frequency, the operating frequency of the instruction arithmetic unit is reduced from the first operating frequency to the second operating frequency.

In one possible implementation, the method further includes: the operating voltage of the instruction arithmetic unit is detected. Based on the change rate of the operating voltage, the operating frequency of the instruction arithmetic unit is adjusted.

In one possible implementation manner, detecting the operating voltage of the instruction operation unit specifically includes: the operating voltage of the instruction arithmetic unit is detected every prescribed detection frequency.

In one possible implementation, the instructions that have been operated on between the first time and the second time include N1 instructions, and the instructions that have been cached at the second time and that have not been operated on include N2 instructions. Based on the operated instruction and the instruction which is not operated and is cached during the second time from the first time to the second time output by the instruction operation unit, the method for determining whether the first working frequency needs to be reduced to the second working frequency specifically comprises the following steps: based on the first record table, a first average current consumed during the N1 instruction operations and a second average current consumed during the N2 instruction operations are determined. The first record table is used for current consumed in operation of each instruction. When the second average current is greater than the first average current and the difference between the first average current and the second average current is greater than a first specified threshold, it is determined that the first operating frequency needs to be reduced to the second operating frequency.

In one possible implementation, the method further includes: when it is determined that the first operating frequency does not need to be reduced to the second operating frequency, the first operating frequency of the instruction arithmetic unit is kept unchanged.

In one possible implementation, the method further includes: when it is determined that the first operating frequency does not need to be reduced to the second operating frequency, the detection frequency is set to the second detection frequency.

In one possible implementation, the method further includes: when it is determined that the first operating frequency needs to be reduced to the second operating frequency, the detection frequency is set to a first detection frequency. In one possible implementation manner, the adjusting the operating frequency of the instruction arithmetic unit based on the rate of change of the operating voltage specifically includes: when the falling slope or the rising slope of the working voltage is determined to be larger than a second designated threshold value, the current working frequency of the instruction operation unit is kept unchanged. When it is determined that the falling slope of the operating voltage is smaller than the second specified threshold and larger than a third specified threshold, the operating frequency of the instruction operation unit is reduced by a first percentage by the clock generation unit. When it is determined that the falling slope of the operating voltage is smaller than the third specified threshold and larger than the fourth specified threshold, the operating frequency of the instruction operation unit is reduced by a second percentage by the clock generation unit. When the rising slope of the working voltage is smaller than the second specified threshold and larger than the third specified threshold, the current working frequency of the instruction operation unit is kept unchanged. When it is determined that the rising slope of the operating voltage is smaller than the third specified threshold and larger than the fourth specified threshold, the operating frequency of the instruction arithmetic unit is raised by a third percentage by the clock generating unit.

In a third aspect, the present application provides an electronic device, comprising: one or more processors, one or more memories. The one or more memories are coupled to the one or more processors, the one or more memories being for storing computer program code comprising computer instructions which, when executed by the one or more processors, cause the terminal to perform the method as in any of the possible implementations of the second aspect described above.

In a fourth aspect, the present application provides a chip system comprising processing circuitry and interface circuitry for receiving code instructions and transmitting to the processing circuitry, the processing circuitry being operable to execute the code instructions to cause the chip system to perform a method as in any one of the possible implementations of the second aspect described above.

In a fifth aspect, the application provides a computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform a method as in any one of the possible implementations of the second aspect described above.

Drawings

FIG. 1A is a schematic diagram of an adaptive voltage regulation system 10 according to an embodiment of the present application;

Fig. 1B is a schematic diagram of an adaptive voltage adjustment system 20 according to an embodiment of the present application;

FIG. 1C is a schematic diagram of data signal acquisition according to an embodiment of the present application;

FIG. 1D is a schematic diagram of a clock signal transmission delay according to an embodiment of the present application;

FIG. 1E is a schematic diagram of a clock signal delay according to an embodiment of the present application;

fig. 2A is a schematic diagram of a voltage dynamic adjustment system 30 according to an embodiment of the application;

FIG. 2B is a schematic diagram of the working voltage and the working frequency according to the embodiment of the present application;

FIG. 2C is a schematic diagram of computing total computing power resources according to an embodiment of the present application;

fig. 2D is a schematic diagram of a low level indication signal/high level indication signal determining method according to an embodiment of the present application;

fig. 2E is a schematic diagram of an adjustment method for operating voltage and operating frequency according to an embodiment of the present application;

FIG. 2F is a schematic diagram of a method for adjusting a detection frequency of a performance detection unit according to an embodiment of the present application;

FIG. 2G is a schematic diagram of a method for adjusting an operating frequency according to a voltage change rate according to an embodiment of the present application;

FIG. 2H is a schematic diagram of a frequency domain impedance curve according to an embodiment of the present application;

FIG. 2I is a schematic diagram of a transient voltage according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a dynamic voltage frequency adjustment method according to an embodiment of the present application;

fig. 4 is a schematic hardware structure of an electronic device according to an embodiment of the present application.

Detailed Description

The terminology used in the following embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates to the contrary. It should also be understood that the term "and/or" as used in this disclosure is meant to encompass any or all possible combinations of one or more of the listed items. In embodiments of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as implying relative importance or as implying an order of magnitude of the indicated technical features. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature, and in the description of embodiments of the application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Fig. 1A schematically illustrates an adaptive voltage regulation system 10 provided in an embodiment of the present application.

As shown in fig. 1A, the adaptive voltage regulation system 10 may include: a clock module 11, a performance detection module 12, a voltage regulation direction judgment module 13, an adaptive voltage regulation (adaptive voltage scaling, AVS) module 14, a power supply module 15, a target function module 16, and the like. Wherein:

the clock module 11 may be used to generate a clock signal that may be output to the target function module 16 and the performance detection module 12. The target functional module 16 may process a target task based on an operating frequency corresponding to the clock signal, and the performance detecting module 12 may detect, based on the clock signal, whether the voltage output by the current power module 15 matches the operating frequency of the target functional module 16.

The performance detection module 12 may receive the clock signal output by the clock module 11 and the voltage signal output by the power module 15. The performance detection module 12 may detect whether the voltage output by the current power module 15 matches the operating frequency of the target function module 16 based on the received clock signal and voltage signal.

The voltage regulation direction judging module 13 may be configured to receive the detection result signal of the performance detecting module 12, and determine whether the voltage should be increased or decreased by comparing the difference between the voltage output by the current power module 15 and the minimum operating voltage corresponding to the clock signal. When the voltage output by the power supply module 15 is smaller than the minimum operating voltage corresponding to the clock signal, the voltage regulation direction judging module 13 may determine that the voltage should be increased; when the voltage output from the power supply module 15 is greater than the minimum operating voltage corresponding to the clock signal, the voltage regulation direction determination module 13 may determine that the voltage should be reduced.

The AVS module 14 may be configured to receive the voltage adjustment signal output from the voltage adjustment direction determination module 13 and output a voltage setting signal to the power supply module 15 based on the voltage adjustment signal.

The power module 15 may receive the voltage setting signal output by the AVS module 14, and adjust the output voltage to the minimum operating voltage corresponding to the current clock signal based on the voltage setting signal. The power module 15 may then output a voltage signal to the target function module 16. The voltage signal may be used to energize the target function module 16 to process the target task at the operating frequency corresponding to the current clock signal. The power module 15 may also output a voltage signal to the performance detection module 12 for the performance detection module 12 to detect whether the voltage currently output by the power module 15 matches the operating frequency of the target function module 16 based on the voltage signal.

The target function module 16 may be configured to receive the voltage signal output by the power module 15 and the clock signal output by the clock module 11, and process the target task at the operating frequency corresponding to the current clock signal based on the voltage signal.

However, the adaptive voltage adjustment system 10 shown in fig. 1A is suitable for a direct current-direct current (DC-DC) circuit, the voltage adjustment rate is relatively slow, and for the ripple voltage caused by the clock edge pulse above gigahertz (GHz), the speed of adjusting the voltage by the adaptive voltage adjustment system 10 cannot meet the rate of change of the clock signal. Therefore, to ensure that the target functional module 16 operates normally in a severe scenario, a protection voltage is typically added to the normal operating voltage, and this implementation results in energy waste.

Wherein the ripple voltage refers to an alternating current component superimposed on the direct current output voltage. Ripple voltages are typically caused by the inability of filters in the power supply circuit to completely remove the ac component. Such an alternating current component will form a periodic ripple on the direct current voltage and may therefore be referred to as a ripple voltage.

Fig. 1B schematically illustrates an adaptive voltage regulation system 20 provided by an embodiment of the present application.

As shown in fig. 1B, the adaptive voltage regulation system 20 may include: a clock generation module 21, a performance detection module 22, a voltage regulation direction judgment module 23, an AVS module 24, a power supply module 25, a target function module 26, a clock adjustment module 27, and the like. Wherein:

the clock generation module 21 may be used to generate a reference clock signal that may be output to the clock adjustment module 27 and the performance detection module 22. The clock adjustment module 27 may generate a system clock signal based on the reference clock signal, and the performance detection module 22 may detect whether the voltage output by the current power module 25 meets the performance requirement or the power consumption requirement of the target functional module 26 based on the reference clock signal.

The performance detection module 22 may receive the reference clock signal output by the clock generation module 21 and the system clock signal output by the clock adjustment module 27. The performance detection module 22 may detect whether the voltage output by the current power module 25 meets the performance requirement or the power consumption requirement of the target function module 26 based on the reference clock signal and the system clock signal.

The voltage regulation direction judgment module 23 may receive the detection result signal of the performance detection module 22, thereby determining whether the voltage should be increased or decreased. When the voltage output from the power supply module 25 does not meet the performance requirement of the target function module 26, the voltage regulation direction judgment module 23 may determine that the voltage should be increased; when the voltage output from the power supply module 25 does not meet the power consumption requirement of the target function module 26, the voltage regulation direction judgment module 23 may determine that the voltage should be reduced.

The AVS module 24 may be configured to receive the voltage adjustment signal output from the voltage adjustment direction determination module 23 and output a voltage setting signal to the power supply module 25 based on the voltage adjustment signal.

The power supply module 25 may receive the voltage setting signal output from the AVS module 24 and adjust the output voltage of the power supply module 25 based on the voltage setting signal. The power module 25 may then output a voltage signal to the target function module 26 and the clock adjustment module 27. The voltage signal may be used by the clock adjustment module 27 to adjust the system clock signal and, at the same time, to excite the target functional module 26 to process the target task at the operating frequency corresponding to the current system clock signal.

The target function module 26 may be configured to receive the voltage signal output by the power module 25 and the system clock signal output by the clock adjustment module 27, and process the target task based on the voltage signal and the system clock signal.

The clock adjustment module 27 may receive the reference clock signal output by the clock generation module 21 and the voltage signal output by the power supply module 25, and generate a system clock signal based on the received reference clock signal and voltage signal, where the frequency of the system clock signal is the operating frequency of the target functional module 26. Wherein, when the voltage output by the power module 25 decreases, the clock adjustment module 27 adjusts the operating frequency of the target function module 26 to decrease; when the voltage output from the power supply module 25 increases, the clock adjustment module 27 adjusts the operating frequency of the target function module 26 to increase. The clock adjustment module 27 may output the system clock signal to the target function module 26 and the performance detection module 22, so that the target function module 26 processes the target task at the operating frequency corresponding to the system clock signal, and the performance detection module 22 detects whether the voltage output by the current power module 25 meets the performance requirement or the power consumption requirement of the target function module 26.

In the adaptive voltage regulating system 20 shown in fig. 1B, the operating frequency of the target function module 26 is no longer fixed, but changes with the voltage output from the power supply module 25. When the voltage output from the power supply module 25 decreases, the operating frequency of the target function module 26 also decreases, thereby ensuring that the clock margin satisfies the requirements.

The adaptive voltage regulating system 20 shown in fig. 1B can provide a clock margin for a rapidly varying ripple voltage, and can solve the problem of a part of the clock margin (e.g., a setup clock margin/a hold clock margin) being insufficient by a method of lowering an operating frequency on the basis of satisfying voltage regulation.

Some descriptions are made here of the above "build clock margin" and "hold clock margin":

the parallel signals in the target function 26 may be divided into "data signals" and "clock signals". The clock signal edge is a parameter criterion for the sampling of the data signal, which is recognized by the target function 26 at the discretion of the clock signal. For the data signal to be normally collected, the data signal needs to be stable for a constant period of time before the rising edge of the clock signal arrives, which may be referred to as the setup time, that is, the data signal should arrive at the target functional module 26 in advance of the rising edge T1 of the clock signal, and this period T1 is the setup time; also, the data signal needs to be stable for a period of time after the rising edge of the clock signal, which may be referred to as a hold time, that is, the data signal must also be held for a period of time T2 after the rising edge of the clock is triggered so as to be able to be stably collected, this period of time T2 is the hold time. Thus, if the duration of the data signal before the clock rising edge is triggered is greater than the setup time, then the excess time is the "setup clock margin"; if the steady-state time of the data signal after the clock rising edge is triggered is greater than the hold time, then the excess time is the "hold clock margin". If both the setup and hold clock margins are positive, then the data signal may be collected normally.

As shown in fig. 1C, the ripple voltage may vary as shown in a Q1 curve, the original operating frequency that is constant may be as shown in a Q2 curve, the operating frequency that varies with voltage may be as shown in a Q3 curve, and the data signal may be as shown in a Q4 curve. It can be seen that at a fixed original operating frequency, the data signals of the D3 segment and the D4 segment are erroneous in acquisition due to insufficient established clock margin. However, at the operating frequency that varies with the voltage, the setup clock margin of the data signals of the D3 segment and the D4 segment is sufficient, so that the data signals of the D3 segment and the D4 segment can be correctly collected.

However, in the adaptive voltage adjustment system 20 shown in fig. 1B, the adjustment of the system clock signal is passive, that is, the adjustment of the system clock signal is controlled by the trend of the voltage signal, the voltage signal changes first, and the system clock signal changes later. As shown in fig. 1D, there is a delay in the transmission path of the clock signal (CLK) between the clock adjustment module 27 and the target functional module 26, so, as shown in fig. 1E, when the system clock signal output from the clock adjustment module 27 is output to the target functional module 26, there is a certain delay, that is, the adjustment of the operating frequency of the target functional module 26 is always delayed for a certain time.

Therefore, when frequent voltage fluctuations are faced, the time when the voltage input to the target function module 26 is lower than the minimum operating voltage required by the target function module 26 is prolonged with the increase of the occurrence number of ripple voltages, and the probability that the voltage of the target function module 26 cannot match the operating frequency of the target function module 26 after the decrease is further increased, so that the operation error of the target function module 26 is also increased, thereby causing instability of the target function module 26. Therefore, when the voltage input to the target functional module 26 decreases, after the clock adjustment module 27 is triggered to adjust the system clock signal, the protection voltage needs to be superimposed on the target functional module 26 until the system clock signal reaches the target functional module 26, so that the target functional module 26 can work normally, and the existence of the protection voltage also has a certain waste of power consumption.

Therefore, the present application provides a voltage dynamic adjustment system that can predict the change situation of the operating voltage of the instruction operation unit in the voltage dynamic adjustment system based on N1 instructions that have been operated in the past specified time period L1 and N2 instructions that are about to be operated in the future specified time period L2. If the working voltage of the instruction operation unit is about to be reduced, the voltage dynamic adjustment system can reduce the working frequency of the instruction operation unit in advance. Then, the voltage dynamic adjustment system can detect the working voltage of the instruction operation unit at intervals of specified detection frequency, and adjust the working frequency of the instruction operation unit according to the actual change trend of the working voltage of the instruction operation unit.

Therefore, the voltage dynamic adjustment system can predict the working voltage change condition of the instruction operation unit according to the operation condition of the instruction, and adjust the working frequency of the instruction operation unit in advance before the working voltage drop of the instruction operation unit occurs, so that the problem that the working voltage is not matched with the working frequency due to time delay caused by the adjustment of the working frequency, and the system operation is failed is avoided. Meanwhile, the voltage dynamic adjustment system provided by the application can detect the working voltage change condition of the command operation unit at intervals of the command detection frequency, and judge the falling stage of the working voltage according to the change rate of the working voltage, so that the corresponding working frequency is accurately adjusted, the performance loss of the system is reduced, and the running power consumption of the system is also reduced.

Fig. 2A schematically illustrates a voltage dynamics adjustment system 30 provided by an embodiment of the present application.

In the embodiment of the application, the voltage dynamic adjustment system 30 can be applied to a voltage dynamic adjustment device.

As shown in fig. 2A, the voltage dynamics adjustment system 30 may be applied to an electronic device.

The voltage dynamic adjustment system 30 may include: an instruction arithmetic unit 31, a workload prediction unit 32 (optional), a temperature management unit 33 (optional), a frequency decision unit 34 (optional), an AVS control unit 35, a power supply unit 36, a frequency voltage mapping unit 37 (optional), a performance detection unit 38, an instruction analysis unit 39, a chip temperature sensor 311 (optional), a clock generation unit 312, and the like. Wherein:

1. Instruction arithmetic unit 31

The instruction operation unit 31 may be configured to perform operations of one or more instructions at a specified operating frequency and a specified operating voltage.

The inputs to the instruction arithmetic unit 31 may be: the clock signal output from the clock generation unit 312, the voltage signal output from the power supply unit 36, and the stop operation instruction (optional) output from the temperature management unit 33. The voltage signal may be used to control the operating voltage of the instruction arithmetic unit 31, and the clock signal may be used to control the operating frequency of the instruction arithmetic unit 31. The stop instruction may trigger the instruction operation unit 31 to stop operation to protect the internal circuit when the temperature of the instruction operation unit 31 reaches a high Wen Guanji threshold. The instruction operation unit 31 may be a central processing unit (central processing unit, CPU), a graphics processor (graphics processing unit, GPU), a digital signal processor (Digital Signal Processing, DSP), or the like in an integrated circuit.

The output of the instruction arithmetic unit 31 may be: one or more processes being operated at the present time and one or more processes to be operated at the next time, which are outputted to the workload prediction unit 32; n1 instructions that have been operated for the past specified period L1 and N2 instructions that are about to be operated for the future specified period L2, which are output to the instruction analysis unit 39. The duration of L1 and the duration of L2 can be the same or different; n1 and N2 may be the same or different.

The instruction operation unit 31 generally performs operations of one or more instructions at a specified operating frequency. The magnitude of this operating frequency is directly related to the operation performance of the instruction arithmetic unit 31. And the instruction arithmetic unit 31 has an approximately linear positive correlation between the minimum operating voltage required for normal operation and its operating frequency. That is, the higher the operating frequency of the instruction arithmetic unit 31, the higher the minimum operating voltage required when the instruction arithmetic unit 31 operates normally; the lower the operating frequency of the instruction arithmetic unit 31, the lower the minimum operating voltage required when the instruction arithmetic unit 31 operates normally.

The relationship between the operating frequency of the instruction arithmetic unit 31 and the minimum operating voltage required for its normal operation may be as shown in fig. 2B. In fig. 2B, the operating frequency F1< F2< F3 of the instruction arithmetic unit 31, the minimum operating voltage V1< V2< V3 required when the instruction arithmetic unit 31 is operating normally.

In fig. 2A and the following embodiments, the operating voltage and the operating frequency described refer to the operating voltage and the operating frequency of the instruction arithmetic unit 31.

2. Workload prediction unit 32

The inputs to the workload prediction unit 32 may be: the instruction operation unit 31 outputs one or more processes being operated at the present time and one or more processes to be operated at the next time. One or more instructions may be included in a process.

The output of the workload prediction unit 32 may be: control signal 3 output to frequency decision unit 34. The control signal 3 may be used to indicate the computational power resources (which may be simply referred to as computational power resources) required by the instruction arithmetic unit 31 at the next time.

The workload prediction unit 32 may be configured to: the required computational power resources of the instruction arithmetic unit 31 at the next time are determined based on the one or more processes being operated at the present time and the one or more processes to be operated at the next time. Among them, the computing power resource may refer to a resource for executing instruction operations in the instruction operation unit 31.

Specifically, fig. 2C exemplarily shows a calculation manner of the calculation force resources required by the instruction arithmetic unit 31 at the next time.

As shown in fig. 2C, the workload prediction unit 32 may obtain the computational force resource occupancy history from a storage unit (not shown in fig. 2A). The computing power resource occupation history record may include computing power resources occupied by each process when the instruction operation unit 31 executes one or more processes in the history time. The workload prediction unit 32 may determine, according to the historical records of the occupation of computing power resources, computing power resources occupied by one or more processes that are currently operating and computing power resources required by one or more processes that are to be operated at a next time, and then superimpose the two computing power resources to determine the total computing power resources required at the next time.

For example, the workload prediction unit 32 may determine, from the historical records of the occupation of the computing power resources, that the computing power resources occupied by the one or more processes currently being operated are A1, and that the computing power resources occupied by the one or more processes to be operated at the next time are A2, so the workload prediction unit 32 may determine that the total computing power resources required at the next time are a1+a2.

3. Frequency decision unit 34

The inputs to the frequency decision unit 34 may be: the control signal 3 output by the workload prediction unit 32. Reference is made to the foregoing description for the description of the control signal 3, which is not repeated here.

The output of the frequency decision unit 34 may be: control signal 2 output to AVS control section 35, and frequency instruction information output to frequency-voltage mapping section 37. The control signal 2 may be used to instruct the instruction arithmetic unit 31 to operate at a frequency point (may be referred to as a target operating frequency) at the next time. The higher the operating frequency point is, the higher the frequency level is, and the stronger the instruction computing capability of the instruction computing unit 31 to instructions is.

The frequency decision unit 34 may be configured to: based on the control signal 3, it is determined whether to adjust the operating frequency point of the instruction arithmetic unit 31.

In some embodiments, the input to the frequency decision unit 34 may also be: the control signal 4 outputted from the temperature management unit 33. The control signal 4 may be used to trigger the frequency decision unit 34 to adjust the operating frequency of the instruction arithmetic unit 31 according to the temperature of the instruction arithmetic unit 31. The output of the frequency decision unit 34 may also be: a control signal 5 output to the AVS control unit 35, the control signal 5 being used to trigger the AVS control unit 35 to adjust the operating frequency of the command operation unit 31 in accordance with the temperature of the command operation unit 31. Therefore, in this embodiment, the frequency decision unit 34 may be configured to trigger the AVS control unit 35 to adjust the operating frequency of the instruction arithmetic unit 31 by the control signal 5 according to the temperature of the instruction arithmetic unit 31.

In the following embodiment, the description will be given taking as an example that the frequency decision unit 34 outputs the control signal 2 to the AVS control unit 35, and the operating frequency of the adjustment instruction arithmetic unit 31 is the target operating frequency.

Specifically, the power consumption of the instruction operation unit 31 and the operating frequency of the instruction operation unit 31 are in a linear positive correlation, and the operating voltage of the instruction operation unit 31 is in a square positive correlation, so that, in the case of meeting the instruction operation requirement, the frequency decision unit 34 will first set the target operating frequency for the instruction operation unit 31 to meet the current instruction operation requirement. When the frequency decision unit 34 receives the total power resource required by the instruction operation unit 31 at the next time (referred to as the next time total power resource for short), the frequency decision unit 34 may compare the next time total power resource with the power resource intervals [ a, B ] corresponding to the operating frequency point of the instruction operation unit 31 at the current time, to determine whether to modify the operating frequency point. If the total computing power resource at the next moment is greater than the maximum computing power resource B corresponding to the working frequency point at the current moment, the frequency decision unit 34 determines to raise the working frequency point by one step; if the total computing power resource at the next moment is smaller than the minimum computing power resource A corresponding to the working frequency point at the current moment, the frequency decision unit 34 determines to reduce the working frequency point by one step.

For example, if the operating frequency points of the instruction operation unit 31, the frequency shift division corresponding to each operating frequency point, and the computing power resource interval corresponding to each operating frequency point are as follows in table 1:

TABLE 1

As shown in Table 1, the working frequency point Fa is a first gear, and the corresponding computing power resource interval is A1-B1; the working frequency point Fc is a second gear, and the corresponding computing power resource interval is A2-B2; the working frequency point Fe is the third gear, and the corresponding computing power resource interval is A3-B3.

If the working frequency point at the current moment is the second gear Fc, the corresponding computing power resource interval is A2-B2. When the total calculation force resource is larger than B2 at the next moment, the frequency decision unit 34 determines to raise the working frequency point by one grade, namely, raise the working frequency point Fc of the second grade to the working frequency point Fe of the third grade; when the total calculation force resource is smaller than A2 at the next moment, the frequency decision unit 34 determines to decrease the operating frequency point by one gear, that is, decrease the operating frequency point Fc of the second gear to the operating frequency point Fa of the first gear.

4. Temperature management unit 33 (optional)

The inputs to the temperature management unit 33 may be: the chip temperature sensor 311 outputs the temperature of the instruction arithmetic unit 31.

The output of the temperature management unit 33 may be: a stop instruction output to the instruction operation unit 31, or a control signal 4 output to the frequency decision unit.

The temperature management unit 33 may be configured to: one or more temperature thresholds are preset, and the temperature of the instruction arithmetic unit 31 is monitored in real time by the chip temperature sensor 311. When the temperature of the instruction arithmetic unit 31 exceeds a certain preset temperature threshold, the temperature management unit 33 may perform a corresponding operation (for example, output a stop operation instruction to the instruction arithmetic unit 31, or output the control signal 4 to the frequency decision unit 34).

For example, since the field effect transistor (i.e., the MOS transistor) in the instruction arithmetic unit 31 needs to operate at a proper temperature, the MOS transistor may be thermally broken down due to the excessive temperature. Therefore, in order to protect the instruction arithmetic unit 31 from high temperatures, the temperature management unit 33 may preset three temperature thresholds, which may be respectively: temperature threshold 1 (which may be referred to as a high temperature warning threshold), temperature threshold 2 (which may be referred to as a high Wen Guanji threshold), and temperature threshold 3 (which may be referred to as a high Wen Huidiao threshold).

When the temperature management unit 33 monitors that the temperature of the instruction operation unit 31 reaches the high-temperature early warning threshold value through the chip temperature sensor 311, the temperature management unit 33 can output a control signal 4 to the frequency decision unit 34 for reducing the working frequency of the instruction operation unit 31 through the frequency decision unit 34; when the temperature management unit 33 monitors that the temperature of the instruction operation unit 31 reaches the high Wen Guanji threshold value through the chip temperature sensor 311, the temperature management unit 33 can output a stop operation instruction to the instruction operation unit 31, and trigger the instruction operation unit 31 to stop operation so as to prevent the instruction operation unit 31 from thermal damage risk; when the temperature management unit 33 monitors that the temperature of the instruction arithmetic unit 31 falls from the temperature above the temperature threshold 1/temperature threshold 2 to the temperature threshold 3 (may be referred to as a high Wen Huidiao threshold) and below by the chip temperature sensor 311, the temperature management unit 33 may output the control signal 4 to the frequency decision unit 34 for increasing the operating frequency of the instruction arithmetic unit 31 by the frequency decision unit 34.

5. Frequency voltage mapping unit 37

The inputs to the frequency voltage mapping unit 37 may be: the frequency indication information output by the frequency decision unit 34. The frequency indication information may be used to indicate the operating frequency (e.g., the aforementioned operating frequency point, etc.) of the instruction arithmetic unit 31 determined by the frequency decision unit 34.

The output of the frequency-voltage mapping unit 37 may be: voltage instruction information output to the AVS control unit 35. The voltage indication information may be used to indicate the operating voltage (which may be referred to as a base voltage) of the instruction operation unit 31 corresponding to the target operating frequency determined by the frequency decision unit 34 when the instruction operation unit 31 is in the ideal operating environment (i.e., the instruction operation unit 31 has no process deviation, no aging condition, is in a suitable temperature state, etc.).

The frequency-voltage mapping unit 37 may be configured to read the frequency-base voltage mapping relationship from a storage unit (not shown in fig. 2A), and determine the base voltage corresponding to the target operating frequency based on the frequency-base voltage mapping relationship. Wherein the frequency-voltage mapping may be used to record a mapping between one or more frequencies and one or more base voltages.

The frequency-to-base voltage mapping may be as shown in table 2:

TABLE 2

As can be seen from table 2, if the target operating frequency is F1, the corresponding basic voltage is 1.0; the target working frequency is F2, and the corresponding basic voltage is 2.0; if the target operating frequency is F3, the corresponding base voltage is 3.0, etc. Table 2 is only for exemplary explanation of the present application and does not constitute any limitation of the present application.

If the frequency decision unit 34 determines that the target operating frequency is F1, the frequency-voltage mapping unit 37 may determine that the basic voltage corresponding to F1 is 1.0 based on the frequency-basic voltage mapping relationship.

The frequency-voltage mapping unit 37 may be an open loop system, and in some embodiments, the frequency-voltage mapping unit 37 may determine the initial operating voltage based on the initial operating frequency before the command operation unit 31 is initially powered up and directly control the command operation unit 31 to operate at the initial operating voltage through the power supply unit 36 before the AVS control unit 35 is not activated.

6. Performance detection Unit 38

The inputs to the performance detection unit 38 may be: the clock signal output by the clock generation unit 312, the voltage signal output by the power supply unit 36, and the setting information output by the AVS control unit 35. Wherein the setting information may be used to set the detection frequency at which the performance detection unit 38 detects the operating voltage.

The output of the performance detection unit 38 may be: voltage information and voltage regulation signal 1 outputted to AVS control section 35.

The performance detection unit 38 may be configured to:

1) Based on the clock signal and the voltage signal, determining whether the current operating voltage matches the operating frequency by detecting a delay signal of the critical path. If the current operating voltage does not match the current operating frequency, the performance detecting unit 38 may determine the voltage adjustment direction and output the voltage adjustment signal 1 to the AVS control unit 35, and trigger the AVS control unit 35 to adjust the operating voltage of the instruction calculating unit 31 through the power supply unit 36 so that the operating voltage matches the operating frequency. Here, the "operating voltage matching operating frequency" means that the operating voltage of the instruction operation unit 31 can support the operation of the instruction operation unit 31 to execute an instruction at the current operating frequency.

2) The operating voltage of the instruction arithmetic unit 31 is detected based on the critical path, and operating voltage information (which may be simply referred to as voltage information, or may be referred to as a delay detection result) which may be used to indicate the current operating voltage of the instruction arithmetic unit 31 may be output to the AVS control unit 35 in real time.

The critical path refers to a delay link that matches the maximum delay path executed by the instruction arithmetic unit 31. The critical path may accurately reflect delay information of related circuits inside the instruction arithmetic unit 31, so the performance detecting unit 38 may determine the current operating voltage of the instruction arithmetic unit 31 according to the delay signal for detecting the critical path.

In some embodiments, the performance detecting unit 38 may directly send the voltage adjustment value to the AVS control unit 35 according to the instruction of the instruction operation unit 31, and trigger the AVS control unit 35 to directly control the operating voltage of the instruction operation unit 31 through the power supply unit 36.

7. Instruction analysis unit 39

The inputs to instruction analysis unit 39 may be: n1 instructions that have been operated for the past specified period L1 and N2 instructions that are to be operated for the future specified period L2, which are output from the instruction operation unit 31. The duration of L1 and the duration of L2 can be the same or different; n1 and N2 may be the same or different.

The output of instruction analysis unit 39 may be: a high level instruction signal/a low level instruction signal output to the AVS control unit 35.

The instruction analysis unit 39 may be configured to: the average current 1 consumed during N1 instruction operations and the average current 2 consumed during N2 instruction operations are calculated, and the average current 1 and the average current 2 are judged. When the average current 2 is less than or equal to the average current 1, the instruction analysis unit 39 may determine that the operating frequency of the instruction operation unit 31 does not have to be changed, and thus output a low level instruction signal to the AVS control unit 35; when the average current 2 is greater than the average current 1, the instruction analysis unit 39 determines that the operating frequency of the instruction operation unit 31 needs to be reduced from the current operating frequency to the guard frequency, and thus outputs a high-level instruction signal to the AVS control unit 35. Wherein the high level indication signal may be used to indicate that the operating voltage of the instruction arithmetic unit 31 will decrease at the next time.

In one example, the "past specified period L1" may refer to a period between a first time and a second time, and the "N2 instructions to be operated on by the future specified period L2" may refer to N2 instructions to be operated on by a third time, that is, N2 instructions that are cached and not operated on at the second time, the third time being later than the second time. The high level indication signal may be used to indicate that the operating voltage of the instruction arithmetic unit will decrease at the third instant.

Here, since the impedance voltage increases and the operating voltage of the instruction arithmetic unit 31 decreases when the current increases based on ohm's law, the operating voltage of the instruction arithmetic unit 31 decreases when the average current 2 is larger than the average current 1, and the decreasing operating voltage cannot support the instruction arithmetic unit 31 to operate the instruction at the current operating frequency, so that it is necessary to decrease the operating frequency of the instruction arithmetic unit 31. The average current 2 is smaller than the average current 1, the impedance voltage is reduced, the operating voltage of the instruction operation unit 31 is increased, and the increased operating voltage can support the instruction operation unit 31 to operate the instruction at the current operating frequency, so that the operating frequency of the instruction operation unit 31 does not need to be changed.

In particular, instruction analysis unit 39 may have a plurality of data registers that may be used to store a plurality of instructions. Wherein N1 data registers may be used to store N1 instructions that have been operated on for a specified time period L1 in the past, and N2 data registers may be used to store N2 instructions that are to be operated on for a specified time period L2 in the future. As shown in fig. 2D, a specific calculation procedure may be as follows:

1) The instruction analysis unit 39 may calculate the average current 1 consumed at the time of N1 instruction operations and the average current 2 consumed at the time of N2 instruction operations based on the record table 1 stored in advance in the instruction current consumption database (not shown in fig. 2A). The record table 1 can be used to record the current consumed in each instruction operation.

2) The command analysis unit 39 may compare the magnitudes of the average current 1 and the average current 2.

3) If the average current 1 and the average current 2 are the same or the difference between them is smaller than the specified threshold 1, the instruction analysis unit 39 determines that the operating frequency is not changed, and outputs a low-level instruction signal to the AVS control unit 35.

4) If the average current 2 is smaller than the average current 1 and the difference between the two is larger than the specified threshold 1, the instruction analysis unit 39 determines that the operating frequency is not changed, and outputs a low-level instruction signal to the AVS control unit 35.

5) If the average current 2 is greater than the average current 1 and the difference between the two is greater than the specified threshold 1, the instruction analysis unit 39 determines to lower the current operating frequency to the guard frequency and outputs a high level instruction signal to the AVS control unit 35.

6) The instruction analysis unit 39 waits for the instruction operation unit 31 to refresh the instruction into the data register, and loops the flow shown in fig. 2D.

The current consumed in the calculation of each instruction in table 1 is recorded as shown in table 3 below:

TABLE 3 Table 3

Table 3 is only for exemplary explanation of the present application and does not constitute any limitation of the present application.

The acquisition mode of the record table 1 can be as follows: the command operation unit 31 repeatedly performs the operation of each command in advance, and finally obtains the average current data consumed at the time of operation of each command, and records the average current data in the record table 1, and then stores the record table 1 in the command current consumption database.

8. AVS control unit 35

The inputs to AVS control unit 35 may be: the control signal 2 output by the frequency decision unit 34, the voltage instruction information output by the frequency voltage mapping unit 37, the voltage adjustment signal 1 and the voltage information output by the performance detection unit 38, the high level instruction signal/low level instruction signal output by the instruction analysis unit 39, and the voltage adjustment signal 2 output by the clock generation unit 312.

The output of the AVS control unit 35 may be: the frequency control signal output to the clock generation unit 312, the voltage control signal output to the power supply unit 36, and the setting information output to the performance detection unit 38. Wherein the setting information may be used to set the detection frequency at which the performance detection unit 38 detects the operating voltage.

The AVS control unit 35 may function as follows:

function 1, based on the control signal 2 output from the frequency decision unit 34, outputs the frequency control signal 1 to the clock generation unit 312, and triggers the clock generation unit 312 to adjust the operating frequency of the instruction operation unit 31 to the target operating frequency determined by the frequency decision unit 34.

Function 2, based on the voltage information output by the frequency voltage mapping unit 37, determines a target operating voltage corresponding to the target operating frequency according to the basic voltage. Then, the voltage control signal 1 is sent to the power supply unit 36, triggering the power supply unit 36 to adjust the operating voltage of the operation unit 31 to the target operating voltage.

The target operating voltage may be understood as an initial operating voltage when the command operation unit 31 switches the operating frequency to the target operating frequency, and when the command operation unit 31 is actually operating, the operating voltage of the command operation unit 31 may fluctuate between the surrounding regions of the target operating voltage due to the influence of the self temperature, the external environment, and the like.

Specifically, the AVS control unit 35 may read the temperature-voltage deviation map, the process deviation-voltage deviation map, the aging condition-voltage deviation map, and the like from the memory unit (not shown in fig. 2A). The AVS control unit may superimpose the voltage deviation values corresponding to the target operating frequency in the one or more mapping relationships on the basis of the basic voltage, and finally determine the target operating voltage. The temperature-voltage deviation mapping relationship may be used to indicate a mapping relationship between each temperature and voltage deviation at each frequency, the process deviation-voltage deviation mapping relationship may be used to indicate a mapping relationship between process deviation and voltage deviation at each frequency, and the aging condition-voltage deviation mapping relationship may be used to indicate a mapping relationship between hardware aging condition and voltage deviation at each frequency.

Exemplary aging conditions-voltage deviation maps may be shown in table 4 below:

TABLE 4 Table 4

Exemplary, process bias-voltage bias mappings may be as shown in table 5:

TABLE 5

Exemplary, temperature-voltage deviation maps may be as shown in table 6:

TABLE 6

If the current target working frequency is F1 and the temperature is 2, the value of the target working voltage may be:

V=basic voltage+voltage deviation value corresponding to aging condition+voltage deviation value corresponding to process deviation+voltage deviation value corresponding to temperature 2=1.0+0.11+0.022+0.01= 1.142.

The above tables 4, 5 and 6 are only for exemplary explanation of the present application, and do not constitute any limitation.

The frequency-basic voltage mapping relation, the process deviation-voltage deviation mapping relation, the temperature-voltage deviation mapping relation and the aging condition-voltage deviation mapping relation can be obtained by selecting typical hardware samples in a hardware design verification stage and performing batch test.

As shown in fig. 2E, a flow of the AVS control unit 35 adjusting the operation voltage and the operation frequency is described here:

s201: comparing the new operating frequency with the current operating frequency.

S202: when the new operating frequency is greater than the current operating frequency, the AVS control unit 35 controls the power supply unit 36 to adjust the operating voltage of the instruction arithmetic unit 31 to a new operating voltage corresponding to the new operating frequency.

S203: the AVS control unit 35 controls the clock generation unit 312 to adjust the operating frequency of the instruction arithmetic unit 31 to the new operating frequency.

S204: when the new operating frequency is smaller than the current operating frequency, the AVS control unit 35 controls the clock generating unit 312 to adjust the operating frequency of the instruction arithmetic unit 31 to the new operating frequency.

S205: the AVS control unit 35 controls the power supply unit 36 to adjust the operating voltage of the instruction arithmetic unit 31 to a new operating voltage corresponding to the new operating frequency.

S206: when the new operating frequency is the same as the current operating frequency, the AVS control unit 35 controls the operating frequency and the operating voltage of the instruction arithmetic unit 31 to be unchanged.

Function 3, based on the low level instruction signal/high level instruction signal outputted from instruction analysis section 39, determines whether or not to adjust the detection frequency at which performance detection section 38 detects the operating voltage. When receiving the high-level instruction signal output from the instruction analysis unit 39, the AVS control unit 35 determines the guard frequency from the current operating frequency based on the interrupt instruction from the instruction analysis unit 39, and outputs the frequency control signal 2 (may also be referred to as a guard frequency control code) to the clock generation unit 312, thereby triggering the clock generation unit 312 to reduce the operating frequency of the instruction operation unit 31 from the current operating frequency to the guard frequency.

Specifically, as shown in fig. 2F, the flow of the AVS control unit 35 performing the corresponding operation based on the low level instruction signal/the high level instruction signal may be as follows:

s210: when the AVS control unit 35 receives the low-level instruction signal, the AVS control unit 35 sets the frequency at which the performance detecting unit 38 detects the operation voltage to the detection frequency 1.

S211: when the AVS control unit 35 receives the high-level indication signal, the AVS control unit 35 calculates the guard frequency based on the current operating frequency.

In one possible implementation manner, the calculation formula of the protection frequency may be:

guard frequency = current operating frequencyE%/>

In the above formula, E may be a preset value. The formula is only used to exemplarily explain the present application and does not limit the present application in any way, and in other implementations, the guard frequency may be calculated in other ways.

S212: AVS control unit 35 outputs a guard frequency control code to clock generation unit 312, and controls clock generation unit 312 to lower the operating frequency of instruction arithmetic unit 31 from the current operating frequency to the guard frequency.

S213: the AVS control unit 35 sets the frequency at which the performance detection unit 38 detects the operation voltage to the detection frequency 2.

Wherein the detection frequency 2 is higher than the detection frequency 1. That is, when the AVS control unit 35 receives the high-level instruction signal, the AVS control unit 35 may control the performance detecting unit 38 to more frequently detect the operation voltage of the instruction arithmetic unit 31.

Function 4, based on the voltage regulation signal 1 output by the performance detection unit 38, controls the power supply unit 36 to adjust the operating voltage of the instruction operation unit 31 so that the operating voltage matches the current operating frequency.

Function 5, based on the voltage regulation signal 2 output from the clock generation unit 312, controls the power supply unit 36 to adjust the operating voltage of the instruction operation unit 31. This function is described in detail in the subsequent clock generation unit 312 and is not described here in detail.

Function 6 calculates the trend of the operating voltage based on the voltage information output from the performance detecting unit 38, adjusts the operating frequency of the instruction calculating unit 31 according to the trend of the operating voltage (i.e., the rate of change), then outputs the frequency control signal 3 (which may be referred to as a frequency pre-adjustment code) to the clock generating unit 312, and adjusts the operating frequency of the instruction calculating unit 31 by the clock generating unit 312.

Specifically, as shown in fig. 2G, the flow of the AVS control unit 35 for adjusting the operating frequency of the instruction arithmetic unit 31 according to the trend of the operating voltage may be as follows:

s220: the AVS control unit 35 acquires the operating voltage of the instruction arithmetic unit 31 through the performance detection unit 38 every specified detection frequency (for example, detection frequency 1/detection frequency 2).

S221: the AVS control unit 35 calculates a slope of the operation voltage (may be simply referred to as a voltage slope) based on the operation voltage acquired this time and the operation voltage acquired last time.

In the embodiment of the application, the slope of the working voltage can be used for representing the change trend of the working voltage.

S222: the AVS control unit 35 determines whether the current acquired operating voltage is lower than the last acquired operating voltage.

S223: when it is determined that the operating voltage drops and the voltage drop slope is greater than the specified threshold V1, the AVS control unit 35 controls the clock generating unit 312 to keep the current operating frequency unchanged.

The voltage drop slope is larger than the specified threshold V1, indicating that the currently changing voltage is a glitch signal that does not affect the operating state of the instruction arithmetic unit 31, and thus the operating frequency does not need to be changed.

S224: when it is determined that the operating voltage drops, and the voltage drop slope is greater than the specified threshold V2 and less than the specified threshold V1, the AVS control unit 35 controls the clock generating unit 312 to down-regulate the current operating frequency by Q1%.

S225: when it is determined that the operating voltage drops, and the voltage drop slope is greater than the specified threshold V3 and less than the specified threshold V2, the AVS control unit 35 controls the clock generating unit 312 to down-regulate the current operating frequency by Q2%.

Wherein, the value of Q2 can be smaller than Q1. Q2 and Q1 may be preset values.

S226: when it is determined that the operating voltage rises and the voltage rising slope is greater than the specified threshold V1, or the voltage rising slope is greater than the specified threshold V2 and less than the specified threshold V1, the AVS control unit 35 controls the clock generating unit 312 to keep the current operating frequency unchanged.

S227: when it is determined that the operating voltage rises, and the voltage rising slope is greater than the specified threshold V3 and less than the specified threshold V2, the AVS control unit 35 controls the clock generating unit 312 to increase the current operating frequency by Q2/2%.

S228: when the voltage falling slope is smaller than the specified threshold V3, or the voltage rising slope is smaller than the specified threshold V3, the AVS control unit 35 determines whether the presently acquired operating voltage matches the current operating frequency.

S229: when it is determined that the currently acquired operating voltage does not match the current operating frequency, the AVS control unit 35 controls the power supply unit 36 to adjust the operating voltage to an operating voltage matching the operating frequency according to the delay detection result of the performance detection unit 38.

S230: when it is determined that the currently acquired operating voltage matches the current operating frequency, the AVS control unit 35 determines whether the current operating frequency is greater than the target operating frequency through the clock generating unit 312.

S231: when it is determined that the current operating frequency is greater than the target operating frequency and the difference between the two is greater than the specified threshold B1, the AVS control unit 35 controls the clock generating unit 312 to adjust the current operating frequency to the target operating frequency.

S232: when it is determined that the current operating frequency is smaller than the target operating frequency and the difference between the current operating frequency and the target operating frequency is larger than the specified threshold B1, the AVS control unit 35 controls the power supply unit 36 to adjust the operating voltage to the target operating voltage corresponding to the target operating frequency.

S233: the AVS control unit 35 controls the clock generation unit 312 to adjust the current operating frequency to the target operating frequency.

When the AVS control unit 35 performs the flow shown in fig. 2G, the operating frequency of the instruction operation unit 31 can be dynamically and precisely adjusted according to the actual change of the voltage during the operation of the instruction operation unit 31.

Fig. 2H shows the frequency domain impedance characteristics of the path of the power supply unit 36 to the capacitive load inside the instruction arithmetic unit 31 in the entire voltage dynamic adjustment system 30. The impedance peaks shown in fig. 2G may be divided into a first resonance peak at a high frequency (e.g., 100 MHz), a second resonance peak at an intermediate frequency (e.g., 20 MHz), and a third resonance peak at a low frequency (e.g., 200 KHz).

Fig. 2I shows the voltage drop corresponding to each resonance peak in fig. 2H. As shown in fig. 2I, the first resonance peak corresponds to a first dip, the voltage change speed is the fastest, the dip amplitude is the largest, and the time span of the whole trough is about 10 nanoseconds; the second resonance peak corresponds to a second dip, the voltage change speed of the second resonance peak is slower than that of the first dip, and the time span of the whole trough is about 30 nanoseconds; the third resonance peak corresponds to a third dip, the voltage change speed is slowest, the dip amplitude is lowest, and the time span of the whole trough is about microsecond.

Therefore, as can be seen from the above-described impedance peaks of different frequencies shown in fig. 2H and the trend of change in voltage drop corresponding to each impedance peak shown in fig. 2I, the AVS control unit 35 dynamically and accurately adjusts the operating frequency of the instruction arithmetic unit 31 for different voltage trends, so that the power consumption of the instruction arithmetic unit 31 can be reduced while ensuring the stability of the instruction arithmetic unit 31. In addition, the AVS control unit 35 sets different operating frequency variation values in advance according to different voltage variation rates and time spans corresponding to different dips, so that a frequency margin (i.e., a frequency margin left when the instruction operation unit 31 operates normally) can be provided for voltage fluctuation in a subsequent period of time, the magnitude of the protection voltage can be reduced, the energy efficiency ratio of the instruction operation unit 31 can be improved, and the operating stability of the instruction operation unit 31 can be improved.

9. Clock generation unit 312

The inputs to the clock generation unit 312 may be: the AVS control unit 35 outputs a frequency control signal.

The output of the clock generation unit 312 may be: the clock signal output to the instruction arithmetic unit 31, the clock signal output to the performance detecting unit 38, and the voltage regulating signal 2 output to the AVS control unit 35.

The clock generation unit 312 may be configured to: 1) Based on the frequency control signal, a clock signal is generated to control the instruction operation unit 31 to perform the operation of the instruction at the operating frequency corresponding to the clock signal. 2) The clock signal is output to the performance detection unit 38 for detection by the performance detection unit 38. 3) The voltage regulating signal 2 is output to the AVS control unit 35, triggering the AVS control unit 35 to regulate the operating voltage through the power supply unit 36.

Specifically, the clock generation unit 312 may receive the frequency control signal output from the AVS control unit 35 through the frequency generation controller, and then the frequency generation controller adjusts the frequency magnitude of the output clock signal by selecting the number of delay units in the voltage controlled oscillator (voltage controlled oscillator, VCO).

Also, the frequency of the clock signal (which may be simply referred to as a clock frequency) may be input to a frequency counter in the clock generation unit 312 so that the frequency counter can detect the clock frequency at specified time intervals. When the frequency counter determines that the difference between the clock frequency and the target operating frequency is greater than the specified threshold B1, the frequency counter may notify the frequency generation controller in the clock generation unit 312, trigger the clock generation unit 312 to output the voltage adjustment signal 2 to the AVS control unit 35, and perform adjustment of the operating voltage and/or adjustment of the operating frequency by the AVS control unit 35.

Wherein the clock frequency and the current operating frequency are the same.

10. Power supply unit 36

The input to the power supply unit 36 may be: the AVS control unit 35 outputs a voltage control signal.

The output of the power supply unit 36 may be: the voltage signal output to the performance detecting unit 38 and the voltage signal output to the instruction calculating unit 31.

The power supply unit 36 may be configured to: 1) The instruction operation unit 31 is activated based on the voltage signal to perform the operation of the instruction. The voltage at which the instruction arithmetic unit 31 operates is referred to as an operating voltage. 2) The voltage signal is output to the performance detection unit 38 for detection by the performance detection unit 38.

In some embodiments, the frequency-voltage mapping unit 37 may also read the frequency-base voltage mapping relationship, the process deviation-voltage deviation mapping relationship, the temperature-voltage deviation mapping relationship, and the aging-condition-voltage deviation mapping relationship from the storage unit (not shown in fig. 2A) when receiving the frequency indication information, and determine the operating voltage of the instruction operation unit 31 based on the frequency-base voltage mapping relationship, the process deviation-voltage deviation mapping relationship, the temperature-voltage deviation mapping relationship, and the aging-condition-voltage deviation mapping relationship. The working voltage is the target working voltage, and the specific calculation method can refer to the foregoing description, which is not repeated here. Then, the frequency voltage mapping unit 37 may output voltage instruction information to the AVS control unit 35, at which time the voltage instruction information is used to trigger the AVS control unit 35 to adjust the operating voltage of the instruction operation unit 31 to the target operating voltage through the power supply unit 36.

Fig. 3 illustrates a specific flow of a dynamic voltage frequency adjustment method according to an embodiment of the present application.

As shown in fig. 3, the specific flow of the dynamic voltage frequency adjustment method may include:

s301: the instruction operation unit 31 performs the operation of the instruction at the operating frequency 1 and the operating voltage 1.

S302: the instruction analysis unit 39 acquires the N1 instructions that have been operated between the first time and the second time and the N2 instructions that have been cached and not operated at the second time from the instruction operation unit 31.

S303: the instruction analysis unit 39 calculates an average current 1 at the time of N1 instruction operations and an average current 2 at the time of N2 instruction operations based on the record table 1.

S304: the instruction analysis unit 39 determines whether to lower the operating frequency of the instruction operation unit 31 from the operating frequency 1 to the guard frequency based on the magnitude of the average current 1 and the average current 2.

S305: when the instruction analyzing unit 39 determines that the average current 1 and the average current 2 are the same, or the difference between the two is smaller than the specified threshold 1, or the average current 2 is smaller than the average current 1 and the difference between the two is larger than the specified threshold 1, the instruction analyzing unit 39 determines that the instruction operating unit 31 keeps the current operating frequency 1 unchanged.

S306: when the instruction analysis unit 39 determines that the average current 2 is greater than the average current 1 and the difference between the two is greater than the specified threshold value 1, the instruction analysis unit 39 controls the instruction operation unit 31 to lower the operating frequency from the operating frequency 1 to the guard frequency through the AVS control unit 35 and the clock generation unit 312.

Specifically, reference may be made to the embodiment of FIG. 2A for the description of S302-S306.

In some embodiments, the instruction analysis unit 39 may also determine whether to reduce the operating frequency of the instruction operation unit 31 from the operating frequency 1 to the protection frequency based on the N1 instructions that have been operated between the first time and the second time and the N2 instructions that are buffered and not operated at the second time.

S307: alternatively, the AVS control unit 35 determines the trend of the operating voltage of the instruction arithmetic unit 31 through the performance detecting unit 38, and adjusts the operating frequency of the instruction arithmetic unit 31 based on the trend of the operating voltage.

The performance detection unit 38 may detect the operating voltage of the instruction arithmetic unit 31. The AVS control unit 35 acquires the operating voltage of the instruction arithmetic unit 31 at every specified detection frequency through the performance detection unit 38.

In particular, this step may be described with reference to the embodiment of fig. 2A described above.

In some examples, when it is determined that the operating frequency 1 needs to be lowered to the guard frequency, the AVS control unit 35 triggers the performance detection unit 38 to detect the operating voltage of the frequency 2 detection instruction operation unit 31; when it is determined that it is not necessary to lower the operating frequency 1 to the guard frequency, the AVS control unit 35 triggers the performance detecting unit 38 to detect the operating voltage of the frequency 1 detection instruction calculating unit 31.

In the embodiment of the application, the method can be used for the electronic equipment or related devices in the electronic equipment.

Fig. 4 illustrates a hardware structure of an electronic device according to an embodiment of the present application.

The electronic device 100 shown in fig. 4 may be the electronic device described in the foregoing description.

As shown in fig. 4, the electronic device 100 may include a processor 401, a memory 402, a wireless communication module 403 (optional), a display 404 (optional), a power module 405, and the like.

It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the application, electronic device 100 may also include more or fewer components than shown in FIG. 4, or may combine certain components, or split certain components, or a different arrangement of components. The components shown in fig. 4 may be implemented in hardware, software, or a combination of software and hardware.

The processor 401 may include one or more processor units, for example, the processor 401 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 401 for storing instructions and data. In some embodiments, the memory in the processor 401 is a cache memory. The memory may hold instructions or data that has just been used or recycled by the processor 401. If the processor 401 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 401 is reduced, thus improving the efficiency of the system.

In some embodiments, the processor 401 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a USB interface, among others.

A memory 402 is coupled to the processor 401 for storing various software programs and/or sets of instructions. In particular implementations, memory 402 may include volatile memory (RAM), such as Random Access Memory (RAM); non-volatile memory (non-volatile memory) such as ROM, flash memory (flash memory), hard Disk Drive (HDD) or solid state Disk (Solid State Drives, SSD) may also be included; memory 402 may also include a combination of the above types of memory. The memory 402 may also store some program code such that the processor 401 invokes the program code stored in the memory 402 to implement a method of implementing an embodiment of the present application in the electronic device 100. The memory 402 may store an operating system, such as an embedded operating system, for example uCOS, vxWorks, RTLinux.

The wireless communication module 403 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc., applied to the electronic device 100. The wireless communication module 403 may be one or more devices integrating at least one communication processing module. The wireless communication module 403 receives electromagnetic waves via an antenna, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 401. The wireless communication module 403 may also receive a signal to be transmitted from the processor 401, frequency modulate and amplify the signal, and convert the signal to electromagnetic waves through an antenna to radiate. In some embodiments, the electronic device 100 may also probe or scan for devices in the vicinity of the electronic device 100 by transmitting signals through a bluetooth module (not shown in fig. 4), a WLAN module (not shown in fig. 4) in the wireless communication module 403, and establish a wireless communication connection with the nearby devices to transmit data. The bluetooth module may provide a solution including one or more bluetooth communications of classical bluetooth (BR/EDR) or bluetooth low energy (bluetooth low energy, BLE), and the WLAN module may provide a solution including one or more WLAN communications of Wi-Fi direct, wi-Fi LAN, or Wi-Fi softAP, among others.

The display 404 may be used to display images, video, etc. The display 404 may include a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED) or an active-matrix organic light-emitting diode (matrix organic light emitting diode), a flexible light-emitting diode (flex), a mini, a Micro led, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, electronic device 100 may include 1 or N displays 404, N being a positive integer greater than 1.

The power module 405 may be used to power various modules on the electronic device 100, such as the processor 401, the memory 402, the wireless communication module 403 (optional), the display screen 404 (optional), and so forth.

In the embodiment of the present application, the electronic device 100 shown in fig. 4 is only used for exemplarily explaining the hardware structure of the electronic device provided by the present application, and does not limit the present application in particular.

As used in the above embodiments, the term "when …" may be interpreted to mean "if …" or "after …" or "in response to determination …" or "in response to detection …" depending on the context. Similarly, the phrase "at the time of determination …" or "if detected (a stated condition or event)" may be interpreted to mean "if determined …" or "in response to determination …" or "at the time of detection (a stated condition or event)" or "in response to detection (a stated condition or event)" depending on the context.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc.

Those of ordinary skill in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by a computer program to instruct related hardware, the program may be stored in a computer readable storage medium, and the program may include the above-described method embodiments when executed. And the aforementioned storage medium includes: ROM or random access memory RAM, magnetic or optical disk, etc.

Claims

1. The utility model provides a voltage dynamic adjustment device, its characterized in that, voltage dynamic adjustment device includes instruction arithmetic unit, instruction analysis unit, clock generation unit, power supply unit, performance detection unit and adaptive voltage adjustment AVS control unit, wherein:

the clock generation unit is used for outputting a clock signal to the instruction operation unit, wherein the clock signal is used for controlling the working frequency of the instruction operation unit;

the power supply unit is used for outputting a voltage signal to the instruction operation unit, wherein the voltage signal is used for controlling the working voltage of the instruction operation unit;

the instruction operation unit is used for operating one or more instructions under a first working frequency and a first working voltage;

The instruction analysis unit is used for determining whether to output a high-level indication signal to the AVS control unit based on the instruction which is operated between the first time and the second time and the instruction which is cached at the second time and is not operated;

the instructions which are operated between the first time and the second time comprise N1 instructions, the instructions which are cached and are not operated at the second time comprise N2 instructions, the high level indication signal is used for indicating that the working voltage of the instruction operation unit is reduced at a third time, the third time is later than the second time, and the instructions which are cached and are not operated at the second time comprise instructions which are operated at the third time;

the AVS control unit is used for receiving the high-level indication signal output by the instruction analysis unit when the instruction analysis unit determines that the second average current consumed during the N2 instruction operations is larger than the first average current consumed during the N1 instruction operations based on a first record table and the difference value between the first average current and the second average current is larger than a first specified threshold value;

the AVS control unit is further configured to reduce, by the clock generation unit, an operating frequency of the instruction operation unit from the first operating frequency to a second operating frequency when the high-level instruction signal is received; wherein the second operating frequency is less than the first operating frequency;

The performance detection unit is used for detecting the working voltage of the instruction operation unit;

the AVS control unit is also used for acquiring the working voltage of the instruction operation unit through the performance detection unit;

the AVS control unit is further used for keeping the current working frequency of the instruction operation unit unchanged when the falling slope or the rising slope of the working voltage is determined to be larger than a second designated threshold value;

the AVS control unit is further configured to reduce, by the clock generation unit, an operating frequency of the instruction operation unit by a first percentage when it is determined that the falling slope of the operating voltage is smaller than the second specified threshold and larger than a third specified threshold;

the AVS control unit is further configured to reduce, by the clock generation unit, an operating frequency of the instruction operation unit by a second percentage when it is determined that the falling slope of the operating voltage is smaller than the third specified threshold and larger than a fourth specified threshold;

the AVS control unit is further used for keeping the current working frequency of the instruction operation unit unchanged when the rising slope of the working voltage is determined to be smaller than the second specified threshold and larger than a third specified threshold;

The AVS control unit is further configured to raise, by a third percentage, an operating frequency of the instruction arithmetic unit by the clock generating unit when it is determined that the rising slope of the operating voltage is smaller than the third specified threshold and larger than a fourth specified threshold.

2. The apparatus according to claim 1, wherein the AVS control unit is specifically configured to:

and acquiring the working voltage of the instruction operation unit through the performance detection unit at intervals of specified detection frequency.

3. The apparatus of claim 2, wherein the AVS control unit is further to:

when receiving the low-level indication signal output by the instruction analysis unit, determining that the first working frequency is unchanged by the instruction operation unit.

4. The apparatus of claim 3, wherein the device comprises a plurality of sensors,

the instruction analysis unit is specifically configured to:

determining a first average current consumed during the operation of the N1 instructions and a second average current consumed during the operation of the N2 instructions based on a first record table; the first record table is used for current consumed in operation of each instruction;

and outputting the low-level indication signal to the AVS control unit when a difference between the second average current and the second average current is smaller than a first specified threshold or when the second average current is smaller than the first average current and a difference between the first average current and the second average current is larger than a first specified threshold.

5. The apparatus of claim 2, wherein the AVS control unit is further to:

when the high level indication signal is received, the detection frequency is set to a first detection frequency.

6. The apparatus of claim 3, wherein the AVS control unit is further to:

when the low level indication signal is received, the detection frequency is set to a second detection frequency.

7. A dynamic voltage frequency adjustment method, applied to a voltage dynamic adjustment device including an instruction operation unit, the method comprising:

operating one or more instructions at a first operating frequency and a first operating voltage by the instruction operation unit;

determining whether the first working frequency needs to be reduced to a second working frequency or not based on an instruction which is operated between a first time and a second time and is not operated and an instruction which is cached at the second time and is output by the instruction operation unit;

the instructions which are cached at the second moment and are not operated comprise instructions which are operated at a third moment, the third moment is later than the second moment, the operated instructions from the first moment to the second moment comprise N1 instructions, and the instructions which are cached at the second moment and are not operated comprise N2 instructions;

When the second average current consumed in the N2 instruction operations is calculated to be larger than the first average current consumed in the N1 instruction operations and the difference value between the first average current and the second average current is larger than a first specified threshold value based on a first record table, and the first working frequency is determined to be reduced to the second working frequency, the working frequency of the instruction operation unit is reduced from the first working frequency to the second working frequency;

detecting the working voltage of the instruction operation unit;

when the falling slope or the rising slope of the working voltage is determined to be larger than a second designated threshold value, keeping the current working frequency of the instruction operation unit unchanged;

when it is determined that the falling slope of the operating voltage is smaller than the second specified threshold and larger than a third specified threshold, decreasing the operating frequency of the instruction arithmetic unit by a first percentage;

when the falling slope of the working voltage is determined to be smaller than the third specified threshold and larger than a fourth specified threshold, reducing the working frequency of the instruction operation unit by a second percentage;

when the rising slope of the working voltage is determined to be smaller than the second specified threshold and larger than a third specified threshold, keeping the current working frequency of the instruction operation unit unchanged;

When it is determined that the rising slope of the operating voltage is smaller than the third specified threshold and larger than a fourth specified threshold, the operating frequency of the instruction arithmetic unit is raised by a third percentage.

8. The method according to claim 7, wherein detecting the operating voltage of the instruction arithmetic unit, in particular, comprises:

and detecting the working voltage of the instruction operation unit at every appointed detection frequency.

9. The method of claim 8, wherein the method further comprises:

when it is determined that the first operating frequency does not need to be reduced to the second operating frequency, the first operating frequency of the instruction arithmetic unit is kept unchanged.

10. The method according to claim 9, wherein the method further comprises:

when it is determined that the first operating frequency does not need to be reduced to the second operating frequency, the detection frequency is set to the second detection frequency.

11. The method of claim 8, wherein the method further comprises:

when it is determined that the first operating frequency needs to be reduced to the second operating frequency, the detection frequency is set to a first detection frequency.

12. An electronic device, comprising: one or more processors, one or more memories; the one or more memories coupled to the one or more processors, the one or more memories to store computer program code comprising computer instructions that, when executed by the one or more processors, cause the electronic device to perform the method of any of claims 7-11.

13. A chip system comprising processing circuitry and interface circuitry, the interface circuitry to receive code instructions and to transmit to the processing circuitry, the processing circuitry to execute the code instructions to cause the chip system to perform the method of any of claims 7-11.

14. A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of claims 7-11.