CN116761502A - Switch memristor and preparation method thereof - Google Patents
Switch memristor and preparation method thereof Download PDFInfo
- Publication number
- CN116761502A CN116761502A CN202210208347.XA CN202210208347A CN116761502A CN 116761502 A CN116761502 A CN 116761502A CN 202210208347 A CN202210208347 A CN 202210208347A CN 116761502 A CN116761502 A CN 116761502A
- Authority
- CN
- China
- Prior art keywords
- layer
- resistive layer
- memristor
- resistive
- voltage signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims description 9
- 230000007547 defect Effects 0.000 claims abstract description 89
- 230000008859 change Effects 0.000 claims abstract description 61
- 230000009471 action Effects 0.000 claims abstract description 18
- 230000005284 excitation Effects 0.000 claims abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 60
- 229910052760 oxygen Inorganic materials 0.000 claims description 60
- 239000001301 oxygen Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 16
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 6
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 19
- 210000002569 neuron Anatomy 0.000 abstract description 16
- 230000036279 refractory period Effects 0.000 abstract description 12
- 230000000295 complement effect Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000004044 response Effects 0.000 description 4
- 230000006399 behavior Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000001537 neural effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005323 electroforming Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000002336 repolarization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000000638 stimulation Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
The application relates to a switch memristor, which comprises a bottom electrode layer; the first resistance change layer is arranged on the bottom electrode layer; the second resistive layer is arranged on the first resistive layer; the top electrode layer is arranged on the second resistance change layer; under the condition that the switch memristor is in a low-resistance state, the vacancy defects in the first resistance change layer and the second resistance change layer directionally move under the action of preset excitation, so that the vacancy defects in one of the first resistance change layer and the second resistance change layer are exhausted, and the other one of the first resistance change layer and the second resistance change layer is in a low-resistance state. The memristor provided by the application has the characteristic of refractory period, can simulate the refractory period of biological neurons, and is suitable for other fields such as pulse time coding methods.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a switch memristor and a preparation method thereof.
Background
Memristors, collectively known as memristors (memristors). It is a circuit device that shows the relationship of magnetic flux to electric charge, having the dimension of resistance, but its resistance value is determined by the electric charge flowing through it. Therefore, by measuring the resistance of memristors, the amount of charge flowing through the memristors can be known, and the effect of memory charge is achieved. In the big data age of information explosion, the demand for ultra-high performance calculation and nonvolatile storage is in explosive growth, and the integration level and the power consumption of the memristor are superior to those of the traditional random access memory, so that the memristor is generally used as an information memory in the field of computers. Memristors have been developed since the advent of the wave, but at present memristors are generally used as memories, and the application field is relatively single.
Disclosure of Invention
Based on this, it is necessary to provide a switch memristor based on the complementary resistance switching principle and a preparation method thereof to address the above-mentioned problems.
To achieve the above object, in one aspect, the present application provides a switching memristor, including:
a bottom electrode layer;
the first resistance change layer is arranged on the bottom electrode layer;
the second resistive layer is arranged on the first resistive layer;
the top electrode layer is arranged on the second resistance change layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
under the condition that the switch memristor is in a low-resistance state, the vacancy defects in the first resistance change layer and the second resistance change layer directionally move under the action of preset excitation, so that the vacancy defects in one of the first resistance change layer and the second resistance change layer are exhausted, and the other one of the first resistance change layer and the second resistance change layer is in a low-resistance state.
In one embodiment, the vacancy defect is an oxygen vacancy defect, the preset stimulus includes a negative voltage signal applied to the bottom electrode layer, the oxygen vacancy defect moves towards the first resistive layer under the action of the negative voltage signal, the oxygen vacancy defect of the second resistive layer is depleted, and the first resistive layer is in a low-resistance state.
In one embodiment, when the oxygen vacancy defect of the second resistive layer is exhausted and the first resistive layer is in a low-resistance state, if the preset stimulus is the negative voltage signal, the resistance state of the switch memristor is unchanged.
In one embodiment, when the oxygen vacancy defect of the second resistive layer is exhausted and the first resistive layer is in a low-resistance state, if the preset stimulus is a forward voltage signal and the forward voltage signal reaches a first threshold, the resistance state of the switch memristor is in a low-resistance state.
In one embodiment, if the resistance state of the switch memristor is a low resistance state, if the preset stimulus is a forward voltage signal, and the forward voltage signal is greater than a second threshold, the oxygen vacancy defect moves toward the second resistive layer under the action of the forward voltage signal, so that the oxygen vacancy defect of the first resistive layer is depleted, and the second resistive layer is in a low resistance state.
In one embodiment, when the oxygen vacancy defect of the first resistive layer is exhausted and the second resistive layer is in a low-resistance state, if the preset stimulus is the forward voltage signal, the resistance state of the switch memristor is unchanged.
In one embodiment, when the oxygen vacancy defect of the first resistive layer is exhausted and the second resistive layer is in a low-resistance state, if the preset stimulus is a negative voltage signal and the negative voltage signal reaches a third threshold, the resistance state of the switch memristor is in a low-resistance state.
In one embodiment, if the preset stimulus is a negative voltage signal and the negative voltage signal reaches a fourth threshold, the oxygen vacancy defect moves toward the first resistive layer under the action of the negative voltage signal, so that the oxygen vacancy defect of the second resistive layer is exhausted, and the first resistive layer is in a low-resistance state.
In one embodiment, the first resistive layer and the second resistive layer are respectively different metal oxide layers.
In one embodiment, the first resistive layer is one of tantalum oxide or tantalum pentoxide and the second resistive layer is the other of tantalum oxide or tantalum pentoxide.
On the other hand, the application also provides a preparation method of the switch memristor, which comprises the following steps:
providing a substrate layer;
forming a bottom electrode layer on the substrate layer;
forming a first resistive layer on the bottom electrode layer;
forming a second resistive layer on the first resistive layer;
forming a top electrode layer on the second resistive layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
under the condition that the switch memristor is in a low-resistance state, the vacancy defects in the first resistance change layer and the second resistance change layer directionally move under the action of preset excitation, so that the vacancy defects in one of the first resistance change layer and the second resistance change layer are exhausted, and the other one of the first resistance change layer and the second resistance change layer is in a low-resistance state.
According to the switch memristor and the preparation method thereof, the bottom electrode layer, the first resistance change layer, the second resistance change layer and the top electrode layer are sequentially formed, and the preset excitation is applied to the bottom electrode layer, so that the vacancy defect in the memristor can be directionally moved to the state that one of the first resistance change layer and the second resistance change layer is in the vacancy defect depletion state, the other one of the first resistance change layer and the second resistance change layer is in the low resistance state, the resistance state of the memristor in the depletion state can not be changed, the characteristics of 'refractory period' are achieved, the refractory period of biological neurons can be simulated, functions of the memristor are diversified, the memristor can be applied to other fields such as pulse time coding, and the application range of the memristor is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a method of fabricating a switching memristor provided in one embodiment;
FIG. 2 is a schematic diagram of a switch memristor provided in an embodiment;
FIG. 3 is a schematic diagram of oxygen vacancy content of an initial state of a switching memristor provided in an embodiment;
FIG. 4 is a low resistance state schematic diagram of a switching memristor provided in an embodiment;
FIG. 5 is a schematic diagram of applying a preset stimulus to a switching memristor provided in one embodiment;
FIG. 6 is a schematic diagram of a resistance state of a switching memristor provided in an embodiment;
FIG. 7 is another schematic diagram of a resistance state of a switching memristor provided in an embodiment;
FIG. 8 is a graph of current response of a complementary resistance switching memristor provided in one embodiment with 1ms pulse width, 5ms interval pulses;
FIG. 9 is a graph of current response of a complementary resistance switching memristor provided in one embodiment with 1ms pulse width, 0.7ms interval pulses;
FIG. 10 is a graph of current response of a complementary resistance switching memristor provided in one embodiment with 0.1ms pulse width, 0.7ms interval pulses;
FIG. 11 is a graph of current response of a complementary resistance switching memristor provided in one embodiment with 1ms pulse width, 0.6ms interval pulses.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an electrode or layer is referred to as being "on," "adjacent to," "connected to" another electrode or layer, it can be directly on, adjacent to, connected to the other electrode or layer, or intervening electrodes or layers may be present. In contrast, when an electrode is said to be "directly on," "directly adjacent to," "directly connected to" another electrode or layer, then there is no intervening electrode or layer. It will be understood that, although the terms first, second, third, etc. may be used to describe various electrodes, components, regions, layers, doping types and/or sections, these electrodes, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one electrode, component, region, layer, doping type or section from another electrode, component, region, layer, doping type or section. Thus, a first resistive layer discussed below may be denoted as a second resistive layer and a second resistive layer may be denoted as a first resistive layer without departing from the teachings of the present application.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one electrode or feature's relationship to another electrode or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other electrodes or features would then be oriented "over" the other electrodes or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques, the regions illustrated in the figures being schematic in nature, and their shapes do not represent actual shapes of regions of a device, and are not intended to limit the scope of the application.
In one embodiment, referring to fig. 1, the present application provides a method for manufacturing a switch memristor, including:
step 100 provides a substrate layer.
The substrate layer may be SiO 2 A Si substrate layer. Specifically, the substrate layer can take a silicon wafer as a substrate, and a certain thickness of SiO is prepared on the surface of the substrate by a plasma chemical vapor deposition method after cleaning 2 A layer of SiO is obtained 2 A Si substrate layer.
And 102, forming a bottom electrode layer on the substrate layer.
The bottom electrode layer may be made of a metal material to form a metal electrode layer, such as Ta or Ti.
Step 104, forming a first resistive layer on the bottom electrode layer.
The first resistive layer is a metal oxide with a small number of oxygen vacancy defects, such as an oxide of Ta or an oxide of Ti, and under practical operating conditions, lattice oxygen in the metal oxide may escape from the lattice due to a certain excitation, so that the number of oxygen vacancy defects increases significantly.
And 106, forming a second resistive layer on the first resistive layer.
The second resistive layer is also a metal oxide with oxygen vacancy defects, and the specific composition of the second resistive layer is different from that of the first resistive layer.
And 108, forming a top electrode layer on the second resistance change layer.
The preparation method of each electrode layer may be, but not limited to, a magnetron sputtering method, a molecular beam epitaxy method, a spin coating method, a chemical vapor deposition method, etc., and the specific preparation process and the thickness of each electrode layer are not limited herein.
Under the condition that the switch memristor is in a low-resistance state, the vacancy defects in the first resistance change layer and the second resistance change layer directionally move under the action of preset excitation, so that the vacancy defects in one of the first resistance change layer and the second resistance change layer are exhausted, and the other one of the first resistance change layer and the second resistance change layer is in a low-resistance state.
Specifically, the top electrode layer may be an inert metal Pt. The vacancy defects are vacancies, typically charged vacancy defects, left by ions in the crystal lattice of the electrode material escaping from the lattice sites. When the number of vacancy defects in the first resistance changing layer and the second resistance changing layer is increased to form conductive filaments which can be communicated with the first resistance changing layer and the second resistance changing layer through certain treatment, the memristor is conducted to be in a low resistance state. At this time, a preset excitation, for example, a voltage signal is applied to the switch memristor, so that the charged vacancy defect therein can move in a certain direction under the action of the electric field, and the moving direction of the vacancy defect can be changed by changing the direction of the voltage signal, so that the resistance states of the first resistance change layer and the second resistance change layer also change accordingly. For example, when the vacancy defects all move toward the first resistive layer, the first resistive layer is in a low-resistance state of conduction, and the second resistive layer is in a high-resistance state of depletion of the vacancy defects.
In this embodiment, by sequentially forming a bottom electrode layer, a first resistive layer, a second resistive layer and a top electrode layer, applying preset excitation on the bottom electrode layer, a vacancy defect in the memristor can be moved to a vacancy defect depletion state in one of the first resistive layer and the second resistive layer, and the other one is in a low-resistance state, so that the resistance state of the depleted memristor is not changed, the characteristics of "refractory period" are provided, the refractory period of a biological neuron can be simulated, the functions of the memristor are diversified, and the memristor can be applied to other fields such as a pulse time coding method.
In one embodiment, as shown in fig. 2, the present application further provides a switching memristor, including: a bottom electrode layer 202, a first resistive layer 204, a second resistive layer 206, and a top electrode layer 208. Wherein, the first resistive layer 204 is disposed on the bottom electrode layer 202; a second resistive layer 206 disposed on the first resistive layer 204; a top electrode layer 208 disposed on the second resistive layer 206. The first resistive layer 204 and the second resistive layer 206 are respectively different metal oxide layers, and the bottom electrode layer 202 is a metal electrode layer, such as metal Ta or Ti.
When the composition of the resistive layer is a metal oxide, the vacancy defect is an oxygen vacancy defect. Optionally, the first resistive layer 204 is tantalum oxide TaO y (y is the number of oxygen vacancy defects) or tantalum pentoxide Ta 2 O 5-x (x is the number of oxygen vacancy defects), and the second resistive layer 206 is the other of tantalum oxide or tantalum pentoxide. In addition, the resistive layer may also be other metal oxides such as oxides of the metal Ti.
In one embodiment, the substrate layer 200 is further included, and the bottom electrode layer 202 is disposed on the substrate layer 200.
In the present application, the substrate layer 200 is SiO 2 The Si substrate, the bottom electrode layer 202 is a Ta electrode layer, and the first resistive layer 204 is TaO y The second resistive layer 206 is Ta 2 O 5-x The top electrode layer 208 is exemplified by metal Pt.
Under the condition that the switch memristor is in a low-resistance state, the vacancy defects in the first resistance change layer and the second resistance change layer directionally move under the action of preset excitation, so that the vacancy defects in one of the first resistance change layer and the second resistance change layer are exhausted, and the other one of the first resistance change layer and the second resistance change layer is in a low-resistance state.
As shown in FIG. 3, the resistance change layer of the initial state of the switching memristor contains a small amount of oxygen vacancy defects, which are insufficient for conduction, and the memristor is initially in a high-resistance state. The oxygen vacancy defect in the resistive layer can be promoted to generate by electroforming, a warm hydrogenation method, a high-energy particle bombardment method, an atmosphere deoxidation method, a chemical reaction method and the like, and conductive filaments which are communicated with the two resistive layers are formed, as shown in fig. 4, and the memristor is in a low-resistance state at the moment.
When a predetermined stimulus, such as a voltage signal stimulus, is applied to the bottom electrode layer 202, referring to fig. 5-7, the oxygen vacancy defects in the first resistive layer 204 and the second resistive layer 206 may move toward one of the resistive layers in a directional manner, so that the resistive states of the first resistive layer and the second resistive layer are different, and the first resistive layer and the second resistive layer are embodied as depletion of the oxygen vacancy defects of one resistive layer, and are in a high resistive state; and the other resistance change layer has more oxygen vacancy defects and is in a low resistance state.
In this embodiment, by sequentially forming a bottom electrode layer, a first resistive layer, a second resistive layer and a top electrode layer, and applying a preset excitation on the bottom electrode layer, a vacancy defect in the memristor can be moved to a state that one of the first resistive layer or the second resistive layer is depleted in vacancy defect, and the other one is in a low-resistance state, so that the resistance state of the memristor in the depleted state is not changed, and the memristor has the characteristic of "refractory period" and can be applied to other fields such as pulse time coding methods.
In one embodiment, referring to fig. 5 and 6, the vacancy defect is an oxygen vacancy defect, the preset stimulus includes a negative voltage signal applied to the bottom electrode layer 202, the oxygen vacancy defect moves toward the first resistive layer 204 under the effect of the negative voltage signal, so that the oxygen vacancy defect of the second resistive layer 206 is depleted, and the first resistive layer 204 is in a low resistance state.
During testing, a voltage signal is applied to the bottom electrode layer 202, and the top electrode layer 208 is grounded. When the preset stimulus is a negative voltage signal, the charged oxygen vacancy defect moves to the first resistive layer 204 under the action of the negative voltage signal, and when the charged oxygen vacancy defect moves to a certain extent, the oxygen vacancy defect of the second resistive layer 206 is exhausted, and the first resistive layer 204 is in a low-resistance state.
In one embodiment, please continue to refer to fig. 6, in which the oxygen vacancy defect of the second resistive layer 206 is depleted and the first resistive layer 204 is in a low resistance state, if the predetermined stimulus is the negative voltage signal, the resistance state of the switch memristor is unchanged.
When the first resistive layer 204 is in a low-resistance state, the oxygen vacancy defect of the second resistive layer 206 is exhausted, if the direction of the preset excitation is unchanged, the negative voltage signal is maintained, and no matter the negative voltage signal is increased or decreased, the moving direction of the oxygen vacancy defect is kept unchanged, so that the resistance state of the switch memristor is unchanged, namely, the switch memristor has the characteristic of "refractory period".
In one embodiment, when the oxygen vacancy defect of the second resistive layer 206 is exhausted and the first resistive layer 204 is in a low-resistance state, if the predetermined stimulus is a forward voltage signal and the forward voltage signal reaches a first threshold, the resistance state of the switch memristor is in a low-resistance state.
When the oxygen vacancy defect of the second resistive layer 206 is exhausted and the first resistive layer 204 is in a low-resistance state, if the signal applied to the bottom electrode layer 202 is a forward scanning voltage signal, the voltage increases to a first threshold value V th1 When the oxygen vacancy defects migrate back to the second resistive layer 206 under the influence of the electric field and reform an oxygen vacancy conductive filament connecting the two electrodes, the device becomes a low resistance state as shown in fig. 4.
In one embodiment, if the resistance state of the switch memristor is a low resistance state, the predetermined stimulus is a forward voltage signal, and the forward voltage signal is greater than a second threshold, the oxygen vacancy defect moves toward the second resistive layer 206 under the effect of the forward voltage signal, so that the oxygen vacancy defect of the first resistive layer 204 is depleted, and the second resistive layer 206 is in a low resistance state, as shown in fig. 7.
When the memristor returns to the low-resistance state as shown in fig. 4, the forward scan voltage signal continues to increase the second threshold V th2 The oxygen vacancy defects continue to move toward the second resistive layer 206 to the depletion of the oxygen vacancy defects of the first resistive layer 204 by the forward voltage signal greater than a second threshold, the second resistive layer 206 being in a low resistance state.
In one embodiment, when the oxygen vacancy defect of the first resistive layer is exhausted and the second resistive layer is in a low-resistance state, if the preset stimulus is the forward voltage signal, the resistance state of the switch memristor is unchanged.
With continued reference to fig. 7, when the oxygen vacancy defect of the first resistive layer 204 is exhausted, the second resistive layer 206 is in a low-resistance state, and if the direction of the preset excitation is unchanged and the forward voltage signal is maintained, the moving direction of the oxygen vacancy defect is unchanged no matter the forward voltage signal is increased or decreased, so that the resistive state of the switch memristor is unchanged, and the switch memristor has the characteristic of "refractory period".
In one embodiment, when the oxygen vacancy defect of the first resistive layer is exhausted and the second resistive layer is in a low-resistance state, if the preset stimulus is a negative voltage signal and the negative voltage signal reaches a third threshold, the resistance state of the switch memristor is in a low-resistance state.
With continued reference to fig. 4 and 7, when the oxygen-vacancy defect of the first resistive layer 204 is exhausted and the second resistive layer 206 is in a low-resistance state, the predetermined stimulus becomes a negative voltage signal and the negative voltage signal reaches a third threshold V th3 The charged oxygen vacancy defects move towards the first resistive layer 204 under the action of the negative voltage signal to form conductive filaments which are communicated with the two poles, and the memristor returns to a low-resistance state.
In one embodiment, if the preset stimulus is a negative voltage signal and the negative voltage signal reaches a fourth threshold, the oxygen vacancy defect moves toward the first resistive layer under the action of the negative voltage signal, so that the oxygen vacancy defect of the second resistive layer is exhausted, and the first resistive layer is in a low-resistance state.
Continuing to apply the negative voltage signal to a fourth threshold V th4 The oxygen vacancy defect continues to move toward the first resistive layer 204, returning the switching memristor to the state shown in fig. 6. And continuing to apply a negative voltage signal at the moment, wherein the resistance state of the switch memristor is not changed in the process of retracing to 0.
Complementary resistive switching memristors have been reported in previous studies, and are commonly used in large-scale memristor arrays, and can be used for inhibiting sneak path currents, and the similarity of the process and neuron discharge behaviors of the complementary resistive switching memristors is discovered for the first time. Specifically, the abrupt increase in current when a memristor switches to a low resistance state is similar to the threshold discharge of a neuron, while the abrupt decrease in current when a memristor switches from a low resistance state to another resistance state is similar to the repolarization process of a neuron.
To further demonstrate that such complementary resistive switching memristors have a biological neuron-like discharge behavior, pulse voltage signals of the same magnitude, different widths and spacings are applied to the memristors, thereby simulating a leakage, integration, firing (LIF) process of neurons. The pulse widths and spacings below are merely illustrative, and pulses at other frequencies may still achieve similar results.
As shown in fig. 8, when using pulses of 1ms width, with a pulse interval of 5ms, the current remains at a low level during the measurement, and even if the number of pulses increases to 20, the switching from the second resistive layer depletion state to the low resistive state cannot be triggered, which simulates the leakage behaviour of the neuron under low frequency stimulation, i.e. the effect of the neuron on each pulse is almost completely attenuated over a longer pulse interval, and thus cannot be integrated to the threshold value.
If the pulse interval is reduced to 0.7ms, a current spike will occur after four pulses as shown in fig. 9. This is similar to the neuronal LIF process: the effects of these pulses accumulate gradually, and leakage effects are insignificant due to the short time intervals. After four pulses, the threshold is reached, triggering the switching from the second resistive layer depletion state to the low resistive state, i.e. the generation of a discharge current.
When shorter pulses are applied (width 0.1ms, pulse interval 0.7 ms), as shown in fig. 10, the number of pulses required for neuron discharge increases because the integration effect is weakened.
When higher frequency pulses are applied (interval 0.6ms, pulse width 1 ms), as shown in fig. 11, the number of pulses required for neuron discharge decreases because leakage at the pulse interval decreases.
In addition, complementary resistive switching memristors have a refractory period after firing, which is also quite similar to that of biological neurons, i.e., neurons do not fire for a period of time after a firing is completed, even if stimulated again. The complementary resistance switch memristor reaches a depletion state after being released under the action of a positive voltage, at the moment, positive voltage signals are applied again, the memristor does not generate discharge current, and the memristor can be switched back to the depletion state to be released next time only by applying negative voltage signals. This neuron property was rarely reported in previous studies and was adapted to a first pulse-time-coded (time-to-first-spike) pulsed neural network. In particular, neurons have long refractory periods to ensure that they will trigger only once when classifying an input pattern. When applied exceeding V th4 The neural component in the refractory period may revert to an excitable state for the next classification task.
Therefore, the application discovers that the switch memristor based on the complementary resistance principle can simulate an LIF neuron model for the first time and is suitable for a pulse neural network of the first pulse time coding.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in more detail and not in detailAnd should therefore be construed as limiting the scope of the claims. It should be noted that the present application uses Pt/Ta alone 2 O 5-x /TaO y The Ta structure is given by way of example for illustrating the principle of resistance change, and it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the inventive concept, all of which fall within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (11)
1. A switching memristor, comprising:
a bottom electrode layer;
the first resistance change layer is arranged on the bottom electrode layer;
the second resistive layer is arranged on the first resistive layer;
the top electrode layer is arranged on the second resistance change layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
under the condition that the switch memristor is in a low-resistance state, the vacancy defects in the first resistance change layer and the second resistance change layer directionally move under the action of preset excitation, so that the vacancy defects in one of the first resistance change layer and the second resistance change layer are exhausted, and the other one of the first resistance change layer and the second resistance change layer is in a low-resistance state.
2. The switching memristor of claim 1, wherein the vacancy defect is an oxygen vacancy defect, the preset stimulus comprises a negative voltage signal applied to the bottom electrode layer, the oxygen vacancy defect moves toward the first resistive layer under the action of the negative voltage signal, the oxygen vacancy defect of the second resistive layer is depleted, and the first resistive layer is in a low-resistance state.
3. The switching memristor of claim 2, wherein, in the case where the oxygen vacancy defect of the second resistive layer is depleted and the first resistive layer is in a low-resistance state, the resistance state of the switching memristor is unchanged if the preset stimulus is the negative voltage signal.
4. The switching memristor of claim 2, wherein, in the case where the oxygen vacancy defect of the second resistive layer is depleted and the first resistive layer is in a low-resistance state, the resistive state of the switching memristor is in a low-resistance state if the preset stimulus is a forward voltage signal and the forward voltage signal reaches a first threshold.
5. The switch memristor of claim 4, wherein if the preset stimulus is a forward voltage signal and the forward voltage signal is greater than a second threshold, the oxygen vacancy defect moves toward the second resistive layer under the action of the forward voltage signal to deplete the oxygen vacancy defect of the first resistive layer and the second resistive layer is in a low-resistance state.
6. The switching memristor of claim 5, wherein, in the case where the oxygen vacancy defect of the first resistive layer is depleted and the second resistive layer is in a low-resistance state, the resistance state of the switching memristor is unchanged if the preset stimulus is the forward voltage signal.
7. The switching memristor of claim 5, wherein, in the case where the oxygen vacancy defect of the first resistive layer is depleted and the second resistive layer is in a low-resistance state, the resistive state of the switching memristor is in a low-resistance state if the preset stimulus is a negative voltage signal and the negative voltage signal reaches a third threshold.
8. The switching memristor of claim 7, wherein if the preset stimulus is a negative voltage signal and the negative voltage signal reaches a fourth threshold, the oxygen vacancy defect moves toward the first resistive layer under the action of the negative voltage signal, depletes the oxygen vacancy defect of the second resistive layer, and the first resistive layer is in a low-resistance state.
9. The switching memristor of claim 1, wherein the first resistive layer and the second resistive layer are each different metal oxide layers.
10. The switching memristor of claim 9, wherein the first resistive layer is one of tantalum oxide or tantalum pentoxide and the second resistive layer is the other of tantalum oxide or tantalum pentoxide.
11. The preparation method of the switch memristor is characterized by comprising the following steps:
providing a substrate layer;
forming a bottom electrode layer on the substrate layer;
forming a first resistive layer on the bottom electrode layer;
forming a second resistive layer on the first resistive layer;
forming a top electrode layer on the second resistive layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
under the condition that the switch memristor is in a low-resistance state, the vacancy defects in the first resistance change layer and the second resistance change layer directionally move under the action of preset excitation, so that the vacancy defects in one of the first resistance change layer and the second resistance change layer are exhausted, and the other one of the first resistance change layer and the second resistance change layer is in a low-resistance state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210208347.XA CN116761502A (en) | 2022-03-03 | 2022-03-03 | Switch memristor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210208347.XA CN116761502A (en) | 2022-03-03 | 2022-03-03 | Switch memristor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116761502A true CN116761502A (en) | 2023-09-15 |
Family
ID=87953864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210208347.XA Pending CN116761502A (en) | 2022-03-03 | 2022-03-03 | Switch memristor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116761502A (en) |
-
2022
- 2022-03-03 CN CN202210208347.XA patent/CN116761502A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Marchewka et al. | Nanoionic resistive switching memories: On the physical nature of the dynamic reset process | |
| Lübben et al. | SET kinetics of electrochemical metallization cells: influence of counter-electrodes in SiO2/Ag based systems | |
| Yu et al. | Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory | |
| Waser et al. | Introduction to new memory paradigms: memristive phenomena and neuromorphic applications | |
| EP0749638B1 (en) | Semiconductor memory devices and methods of producing such | |
| Hur et al. | Modeling for multilevel switching in oxide-based bipolar resistive memory | |
| JP4784960B2 (en) | Memory cell having asymmetric crystal structure and method for manufacturing the same | |
| Li et al. | Coexistence of diode-like volatile and multilevel nonvolatile resistive switching in a ZrO2/TiO2 stack structure | |
| Saleem et al. | Transformation of digital to analog switching in TaOx-based memristor device for neuromorphic applications | |
| Li et al. | NiO-based memristor with three resistive switching modes | |
| EP3602561B1 (en) | A switching resistor and method of making such a device | |
| Wang et al. | Improved resistive switching properties of Ti/ZrO2/Pt memory devices for RRAM application | |
| US11038102B2 (en) | Artificial synapse device and method of manufacturing the same | |
| US9231208B2 (en) | Method for forming memory device | |
| Mahata et al. | Controlled multilevel switching and artificial synapse characteristics in transparent HfAlO-alloy based memristor with embedded TaN nanoparticles | |
| JP2010123989A (en) | Asymmetric memory cell | |
| Qi et al. | Comparisons of switching characteristics between Ti/Al2O3/Pt and TiN/Al2O3/Pt RRAM devices with various compliance currents | |
| Domaradzki et al. | Memristors: a short review on fundamentals, structures, materials and applications | |
| Rubi et al. | Manganite based memristors: Influence of the electroforming polarity on the electrical behavior and radiation hardness | |
| Lim et al. | Electric field effect dominated bipolar resistive switching through interface control in a Pt/TiO 2/TiN structure | |
| US20220013720A1 (en) | Low current rram-based crossbar array circuit implemented with switching oxide engineering technologies | |
| CN116761502A (en) | Switch memristor and preparation method thereof | |
| Nie et al. | Ultrathin SrTiO3-based oxide memristor with both drift and diffusive dynamics as versatile synaptic emulators for neuromorphic computing | |
| CN112614937B (en) | Electrode modification layer, memristor and preparation and control methods thereof | |
| Bousoulas et al. | Experiments and simulation of multilevel resistive switching in forming free Ti/TiO 2− x RRAM devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |