CN116759459B - Power switching tube, voltage conversion circuit and voltage conversion chip - Google Patents

Power switching tube, voltage conversion circuit and voltage conversion chip Download PDF

Info

Publication number
CN116759459B
CN116759459B CN202311040858.6A CN202311040858A CN116759459B CN 116759459 B CN116759459 B CN 116759459B CN 202311040858 A CN202311040858 A CN 202311040858A CN 116759459 B CN116759459 B CN 116759459B
Authority
CN
China
Prior art keywords
grid electrode
gate
power switch
switch tube
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202311040858.6A
Other languages
Chinese (zh)
Other versions
CN116759459A (en
Inventor
樊茂
刘敬东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Yinglian Electronic Technology Co ltd
Original Assignee
Shanghai Yinglian Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Yinglian Electronic Technology Co ltd filed Critical Shanghai Yinglian Electronic Technology Co ltd
Priority to CN202311040858.6A priority Critical patent/CN116759459B/en
Publication of CN116759459A publication Critical patent/CN116759459A/en
Application granted granted Critical
Publication of CN116759459B publication Critical patent/CN116759459B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Abstract

The invention discloses a power switching tube, a voltage conversion circuit and a voltage conversion chip. The power switch tube comprises a deep well layer, a first insulating layer, a first grid electrode, a second grid electrode, a first pole and a second pole; the second grid electrode and the first insulating layer are arranged in the deep well layer, the first insulating layer coats the second grid electrode, the deep well layer further comprises a via hole, and the second grid electrode is electrically connected with the external structure through the via hole; the first grid electrode is arranged on the deep well layer; the first grid electrode and the second grid electrode are partially overlapped along the thickness direction of the deep well layer; the first electrode, the first grid electrode and the second electrode are arranged along a first direction, wherein the first direction is perpendicular to the thickness direction of the deep well layer, and a first insulating layer is wrapped on the periphery of the second grid electrode. The potential of the second grid electrode can be independently controlled to increase the rate of charging the miller capacitance by the first grid electrode, so that the time of the power switching tube in a power consumption stage is effectively shortened, the power consumption of the power switching tube is reduced, and the efficiency of the power switching tube is improved.

Description

Power switching tube, voltage conversion circuit and voltage conversion chip
Technical Field
The embodiment of the invention relates to the field of semiconductor devices, in particular to a power switching tube, a voltage conversion circuit and a voltage conversion chip.
Background
When the metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET, MOS transistor for short) is used as a power switch tube, the metal oxide semiconductor field effect transistor can be applied to a voltage conversion circuit to realize voltage conversion. For example, the MOS transistor can be applied to a BUCK circuit to realize conversion of direct current.
When the MOS tube is applied to the circuit, the power consumption of the MOS tube directly influences the power consumption of the circuit. In the prior art, the MOS tube has serious power consumption, so that the efficiency of the circuit is low when the MOS tube is applied to the circuit, and the full utilization of electric energy is not facilitated.
Disclosure of Invention
The invention provides a power switching tube, a voltage conversion circuit and a voltage conversion chip, which are used for shortening the Miller platform time, reducing the Miller effect of the power switching tube and improving the efficiency of the power switching tube.
In a first aspect, an embodiment of the present invention provides a power switch tube, including a deep well layer, a first insulating layer, a first gate, a second gate, a first pole and a second pole;
the second grid electrode and the first insulating layer are arranged in the deep well layer, the first insulating layer coats the second grid electrode, the deep well layer further comprises a via hole, and the second grid electrode is electrically connected with an external structure through the via hole; the first grid electrode is arranged on the deep well layer; the first gate electrode and the second gate electrode partially overlap in a thickness direction of the deep well layer; the first electrode, the first grid electrode and the second electrode are arranged along a first direction, wherein the first direction is perpendicular to the thickness direction of the deep well layer, and a first insulating layer is wrapped on the periphery of the second grid electrode.
Further, the second grid electrode comprises at least two, and the deep well layer comprises at least two through holes; each second grid electrode is overlapped with the first grid electrode in a part along the thickness direction of the deep well layer, and each second grid electrode is electrically connected with the external structure through one through hole.
Further, the second gates include at least two second gates, and each second gate is partially overlapped with the first gate along the thickness direction of the deep well layer, and is electrically connected with the external structure through the via hole after being electrically connected.
Further, the power switch tube further comprises a substrate, a well layer, a second insulating layer and an active layer;
the deep well layer is arranged on the substrate, the well layer is arranged in the deep well layer, the active layer is arranged in the well layer, the second insulating layer is arranged on the active layer, and the first grid electrode is arranged on the second insulating layer;
the active layer includes a first region and a second region; along the first direction, a vertical projection of the first electrode region on the substrate is at least partially located on one side of a vertical projection of the first gate electrode on the substrate, and a vertical projection of the second electrode region on the substrate is at least partially located on the other side of the vertical projection of the first gate electrode on the substrate; the first electrode region is in contact with the first pole, and the second electrode region is in contact with the second pole.
Further, the first gate electrode includes a first connection terminal, the second electrode includes a second connection terminal, and an overall thickness of the second insulating layer in a first range is greater than an overall thickness of the second insulating layer in a second range between the first connection terminal and the second connection terminal; wherein the first range is a midpoint between the first connection terminal and the second connection terminal, and the second range is a midpoint between the second connection terminal and the first connection terminal and the second connection terminal.
In a second aspect, an embodiment of the present invention further provides a voltage conversion circuit, including a driving unit and the power switch tube described above; the first output end of the driving unit is connected with the first grid electrode of the power switch tube, the second output end of the driving unit is connected with the second grid electrode of the power switch tube, the first input end of the driving unit is used for accessing a control signal, and the reference signal input end of the driving unit is used for accessing a reference voltage signal; the driving unit is used for controlling the potential of the first grid electrode according to the control signal so as to enable the power switch tube to be conducted through the first grid electrode; and controlling the potential of the second grid electrode when the voltage of the first grid electrode is larger than the reference voltage signal so as to enable the power switch tube to be conducted through the second grid electrode.
Further, the driving unit comprises a first driving module, a second driving module and a comparison module;
the input end of the first driving module is used for accessing the control signal, the output end of the first driving module is connected with the first grid electrode and the positive input end of the comparison module, and the first driving module is used for controlling the potential of the first grid electrode according to the control signal; the negative input end of the comparison module is used for accessing the reference voltage signal, the output end of the comparison module is connected with the input end of the second driving module, and the output end of the second driving module is connected with the second grid electrode; the comparison module is used for forming a comparison signal according to the potential of the first grid electrode and the reference voltage signal, and the second driving module is used for controlling the potential of the second grid electrode according to the comparison signal.
Further, the reference voltage signal satisfies:
V p ＞V ref ≥V th ；
wherein V is th Is the threshold voltage of the power switch tube, V p Is the Miller platform voltage, V of the power switch tube ref Is the reference voltage signal.
Further, the voltage conversion circuit further comprises an input switching tube and an energy storage unit, the grid electrode of the input switching tube is connected with the third output end of the driving unit, the first electrode of the input switching tube is connected with the power input end, the second electrode of the input switching tube is connected with the second electrode of the power switching tube and the first input end of the energy storage unit, the first electrode of the power switching tube and the second input end of the energy storage unit are connected with the fixed potential end, the output end of the energy storage unit serves as the output end of the voltage conversion circuit, the driving unit is further used for controlling the time-sharing conduction of the input switching tube and the power switching tube, and the energy storage unit is used for storing and releasing electric energy.
In a third aspect, an embodiment of the present invention further provides a voltage conversion chip, including the voltage conversion circuit described above.
According to the technical scheme, the second grid electrode is arranged in the deep well layer of the power switch tube, and the first grid electrode and the second grid electrode are partially overlapped along the thickness direction of the deep well layer; so that a capacitive structure is formed between the overlapping portions of the first gate and the second gate. And the second grid electrode is electrically connected with the external structure through the through hole, so that voltage can be supplied to the second grid electrode. When the potential jump of the first grid electrode is an effective level, a first capacitance between the first electrode of the power switch tube and the first grid electrode is larger than a threshold voltage, and the power switch tube is in a conducting state. The miller capacitance between the first gate and the second pole of the power switch tube is charged through the first gate. Meanwhile, the second grid electrode can be electrically connected with an external structure through the through hole to independently control the potential of the second grid electrode, and charge is coupled to the Miller capacitor through the middle capacitor between the second grid electrode and the first grid electrode, so that the rate of charging the Miller capacitor by the first grid electrode is increased, the time that the power switching tube is in a power consumption stage is effectively shortened, the power consumption of the power switching tube is reduced, and the efficiency of the power switching tube is improved. And the power switch tube has simple structure and low production cost, and is favorable for large-scale popularization and application. In addition, the second grid electrode is arranged in the deep well layer, so that the second grid electrode can be prevented from releasing stress on the first grid electrode, and the stability and the service life of the first grid electrode are ensured.
Drawings
Fig. 1 is a schematic cross-sectional view of a MOS transistor in the prior art.
Fig. 2 is a schematic diagram of an equivalent model of a MOS transistor in the prior art.
Fig. 3 is a graph of voltage and current curves of a MOS transistor in different states in the prior art.
Fig. 4 is a schematic cross-sectional view of a power switch tube according to an embodiment of the present invention.
Fig. 5 is a schematic top view of a power switch tube according to an embodiment of the present invention.
Fig. 6 is a graph of voltage and current of a power switch tube in different states according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of another power switch tube according to an embodiment of the present invention.
Fig. 8 is a schematic top view of another power switch tube according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of another power switch tube according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of another power switch tube according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of another power switch tube according to an embodiment of the present invention.
Fig. 12 is a schematic diagram of a voltage conversion circuit according to an embodiment of the invention.
Fig. 13 is a schematic diagram of another voltage conversion circuit according to an embodiment of the invention.
Fig. 14 is a schematic diagram of another voltage conversion circuit according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic cross-sectional view of a MOS transistor in the prior art, fig. 2 is a schematic diagram of an equivalent model of the MOS transistor in the prior art, and fig. 3 is a graph of voltage and current of the MOS transistor in different states in the prior art. As shown in fig. 1 to 3, the MOS transistor includes a gate, a source, and a drain, and parasitic capacitance C exists between the poles of the MOS transistor gd 、C gs And C ds Wherein C gd Is MOS transistor gate-drain capacitance, also called Miller capacitance, C gs Is MOS transistor gate-source capacitance, C ds Is the source-drain capacitance of the MOS tube. When the gate-source voltage V of the MOS transistor gs Less than threshold voltage V gs (th) when the MOS tube is in the off state, the drain-source voltage V ds Drain current I of MOS tube is kept unchanged d Is 0. When the gate-source voltage V of the MOS transistor gs Greater than threshold voltage V gs (th) when the MOS tube is in the on state, the drain-source voltage V ds Drop, drain current I d Rising. At this time, power consumption exists between the source electrode and the drain electrode of the MOS transistor, and the power consumption is P=V gs *I d Up to drain-source voltage V ds The drop is 0. In addition, because the MOS tube has the Miller effect, the MOS tube has the drain-source voltage V ds The descending stage is provided with a Miller platform, and the drain-source voltage V of the MOS tube is increased ds The time of the falling stage is increased, so that the time for generating power consumption of the MOS tube is increased, and M is increasedAnd the power consumption of the OS tube reduces the efficiency of the MOS tube.
Based on the above problems, the embodiment of the invention provides a power switch tube, which is used for shortening the miller platform time and reducing the miller effect of the power switch tube.
Fig. 4 is a schematic cross-sectional view of a power switch tube provided by an embodiment of the present invention, fig. 5 is a schematic top plan view of the power switch tube provided by the embodiment of the present invention, as shown in fig. 4 and 5, the power switch tube includes a deep well layer 105, a first insulating layer 106, a first gate 101, a second gate 104, a first pole 102 and a second pole 103, the second gate 104 and the first insulating layer 106 are disposed in the deep well layer 105, the first insulating layer 106 wraps the second gate 104, the deep well layer 105 further includes a via 1051, and the second gate 104 is electrically connected with an external structure through the via 1051; the first gate 101 is disposed on the deep well layer 105; the first gate 101 and the second gate 104 partially overlap in the thickness direction Y of the deep well layer 105; the first pole 102, the first gate 101 and the second pole 103 are arranged along a first direction X, wherein the first direction X is perpendicular to a thickness direction Y of the deep well layer 105.
Specifically, the first direction X may be a horizontal direction, the thickness direction Y of the deep well layer 105 may be a vertical direction, and the Z direction is a direction in which the first gate 101 and the second gate 104 partially overlap, as shown in fig. 5, the first insulating layer 106 wraps the periphery of the second gate 104, and may be used as a capacitance medium between the first gate 101 and the second gate 104 on the one hand, and may isolate the deep well layer 105, be insulated from the deep well layer 105, and the first insulating layer 106 may be a gate oxide layer on the other hand; the first electrode 102, the first gate 101 and the second electrode 103 are arranged in a horizontal direction, the second gate 104 and the first gate 101 are partially overlapped in a thickness direction Y of the deep well layer 105, and compared with the second gate 104 arranged above the first gate 101, the second gate 104 arranged below the first gate 101 can reduce stress applied to the first gate 101, and stability and service life of the first gate 101 are increased. The material of the second gate 104 may be the same as that of the first gate 101, and the first gate 101 and the second gate 104 may be used as two plates of a capacitor to form electricity between overlapping portions of the second gate 104 and the first gate 101Capacitance structure, which may be referred to as intermediate capacitance C g12 . In addition, the potential of the first gate 101 and the potential of the second gate 104 can be controlled independently, the via 1051 penetrates the first insulating layer 106 and the deep well layer 105, and the second gate 104 is electrically connected to an external structure through the via 1051, so that the potential of the second gate 104 is controlled independently. When the potential of the first gate 101 is at the inactive level, a first capacitance C is provided between the first electrode 102 of the power switch and the first gate 101 gs And the power switch tube is in a cut-off state when the voltage is smaller than the threshold voltage. When the potential of the first gate 101 jumps to an effective level, a first capacitance C between the first electrode 102 of the power switch and the first gate 101 gs And the power switch tube is in a conducting state and is larger than the threshold voltage. At this time, the first gate 101 is the miller capacitance C between the first gate 101 and the second pole 103 of the power switch tube gd And (5) charging. At the same time, the potential of the second gate 104 can be independently controlled and the intermediate capacitance C between the second gate 104 and the first gate 101 g12 Coupling charge to Miller capacitance C gd To increase the first gate 101 to the miller capacitance C gd The charging speed effectively shortens the time of the power switching tube in the power consumption stage, reduces the power consumption of the power switching tube and improves the efficiency of the power switching tube. In addition, the second grid electrode is arranged in the deep well layer, so that the second grid electrode can be prevented from releasing stress on the first grid electrode, and the stability and the service life of the first grid electrode are ensured.
When the power switch tube is an N-type MOS tube, fig. 6 is a graph of voltage and current of the power switch tube in different states according to the embodiment of the present invention. Wherein, the abscissa is time, and the ordinate is voltage and current (V, I) of different poles of the power switch tube. Referring to FIG. 6, at Q gs1 Stage, voltage V between first gate 101 and first pole 102 of power switch tube gs Less than threshold voltage V th The power switch tube is in a non-conducting state, and the second pole 103 current I of the power switch tube d 0, at this time, the power switch tube has no power consumption; at Q gs2 Stage, voltage V between first gate 101 and first pole 102 of power switch tube gs Greater than a threshold valueVoltage V th The power switch is in a conductive state, the voltage V between the first pole 102 and the second pole 103 ds Falling, second pole 103 current I d Rising, the power switch tube has power consumption. At this time, a part of the charge of the first gate 101 is the miller capacitance C gd Charging while controlling the potential jump of the second gate 104 to an effective level by an intermediate capacitance C between the second gate 104 and the first gate 101 in the power switch tube g12 Coupling charge to Miller capacitance C gd Thereby increasing the first gate 101 to charge the miller capacitance C gd Reducing the rate at which the power switch tube is at Q gs2 The time of the stage can be reduced, so that the Q of the power switch tube can be reduced gs2 The power consumption of the stage improves the efficiency of the power switch tube; similarly, at Q gd Stage, voltage V between first gate 101 and first pole 102 of power switch tube gs At the Miller stage, a voltage V between the first pole 102 and the second pole 103 ds Continuing to drop, the second pole 103 current I d The maximum value is reached, and the power switch tube also has power consumption. At this time, a part of the charge of the first gate 101 continues to be the miller capacitance C gd Charging while controlling the potential of the second gate 104 and passing through the intermediate capacitance C between the second gate 104 and the first gate 101 g12 Coupling charge to Miller capacitance C gd To increase the first gate 101 to the miller capacitance C gd The charging speed effectively shortens the time of the power switch tube in the Miller platform, reduces the power consumption of the power switch tube and improves the efficiency of the power switch tube. Illustratively, as shown in FIGS. 3 and 6, the second gate 104 may be disposed at Q for the power switch tube gd The potential of the second gate 104 is controlled during the stage and is controlled by the intermediate capacitance C between the second gate 104 and the first gate 101 g12 Coupling charge to Miller capacitance C gd To increase the first gate 101 to the miller capacitance C gd Rate of charge. Specifically, the time of the power switch tube in the miller platform is smaller than that of the power switch tube in the miller platform provided by the prior art, so that the time of the power switch tube in the miller platform is shortened, and the position of the power switch tube is effectively shortenedAnd in the time with the power consumption stage, the power consumption of the power switching tube is reduced, and the efficiency of the power switching tube is improved. Finally at Q godr Stage, voltage V between first gate 101 and first pole 102 gs Continuing to rise, the voltage V between the first pole 102 and the second pole 103 ds 0, second pole 103 current I d The power switch tube is unchanged, and no power consumption exists.
According to the technical scheme, the second grid electrode of the power switch tube is arranged in the deep well layer, and the first grid electrode and the second grid electrode are partially overlapped along the thickness direction of the deep well layer; a capacitive structure is formed between overlapping portions of the first gate and the second gate. And the second grid electrode is electrically connected with the external structure through the through hole, so that voltage can be supplied to the second grid electrode. When the potential jump of the first grid electrode is an effective level, a first capacitance between the first electrode of the power switch tube and the first grid electrode is larger than a threshold voltage, and the power switch tube is in a conducting state. The miller capacitance between the first gate and the second pole of the power switch tube is charged through the first gate. Meanwhile, the second grid electrode can be electrically connected with an external structure through the through hole to independently control the potential of the second grid electrode, and charge is coupled to the Miller capacitor through the middle capacitor between the second grid electrode and the first grid electrode, so that the rate of charging the Miller capacitor by the first grid electrode is increased, the time that the power switching tube is in a power consumption stage is effectively shortened, the power consumption of the power switching tube is reduced, and the efficiency of the power switching tube is improved. And the power switch tube has simple structure and low production cost, and is favorable for large-scale popularization and application. In addition, the second grid electrode is arranged in the deep well layer, so that the second grid electrode can be prevented from releasing stress on the first grid electrode, and the stability and the service life of the first grid electrode are ensured.
Further, fig. 7 is a schematic cross-sectional view of another power switch tube provided by the embodiment of the present invention, and fig. 8 is a schematic top plan view of another power switch tube provided by the embodiment of the present invention, where, as shown in fig. 7 and fig. 8, the second gate 104 includes at least two, and the deep well layer 105 includes at least two vias 1051; along the thickness direction Y of the deep well layer 105, each second gate 104 partially overlaps the first gate 101, and each second gate 104 is electrically connected to the external structure through a via 1051.
Specifically, the periphery of each second gate 104 is wrapped with a first insulating layer 106, and the first insulating layer 106 serves as a capacitance medium between the first gate 101 and the second gate 104, and may isolate the deep well layer 105. The overlapped part between each second gate 104 and the first gate 101 can form a capacitance structure, the potential of each second gate 104 can be controlled by arranging a plurality of second gates 104 and electrically connecting with the external structure through a via 1051, and charges are coupled to the Miller capacitance C through the capacitance between the plurality of second gates 104 and the first gate 101 gd Further increasing the first gate 101 to be the miller capacitance C gd The rate of charging further shortens the time that the power switch is in the phase with power consumption. In addition, by arranging at least two second gates 104 in the deep well layer 105, the at least two second gates 104 can be sequentially arranged, so that the local stress concentration phenomenon of the deep well layer 105 caused by the second gates 104 can be improved, and the service life of the power switch tube is further prolonged.
Alternatively, in other embodiments, the second gate 104 includes at least two second gates 104, and the at least two second gates 104 are electrically connected to the external structure through the via 1051, and the first gate 101 and the second gate 104 partially overlap along the thickness direction Y of the deep well layer 105.
Specifically, the plurality of second gates 104 may be electrically connected first, and then electrically connected to the external structure through a via 1051 to control the potential of the second gates 104, where the potential of each second gate 104 is the same, and the overlapping portion between the plurality of second gates 104 and the first gate 101 may still form a capacitance structure, and still be capable of coupling charges to the miller capacitance C through the capacitance between the plurality of second gates 104 and the first gate 101 gd Effectively increasing the first gate 101 to a miller capacitance C gd The charging speed effectively shortens the time of the power switch tube in the power consumption stage, reduces the via 1051 and simplifies the manufacturing process of the power tube. Meanwhile, the local stress concentration phenomenon of the deep well layer 105 caused by the second grid electrode 104 can be improved, and the service life of the power switch tube is further prolonged.
Further, fig. 9 is a schematic cross-sectional view of another power switch tube according to an embodiment of the present invention, as shown in fig. 9, the power switch tube further includes a substrate 107, a well layer 1051, a second insulating layer 106, and an active layer 108;
the deep well layer 105 is disposed on the substrate 107, the well layer 1051 is disposed in the deep well layer 105, the active layer 10510 is disposed in the well layer 1051, the second insulating layer 108 is disposed on the active layer 10510, and the first gate 101 is disposed on the second insulating layer 108;
the active layer 10510 includes a first region 10511 and a second region 10512; along the first direction X, the vertical projection of the first region 10511 onto the substrate 107 is at least partially on one side of the vertical projection of the first gate 101 onto the substrate 107, and the vertical projection of the second region 10512 onto the substrate 107 is at least partially on the other side of the vertical projection of the first gate 101 onto the substrate 107; the first pole region 10511 is in contact with the first pole 102 and the second pole region 10512 is in contact with the second pole 103.
Specifically, an intermediate capacitance C between the second gate 104 and the first gate 101 g12 Is formed by the second electrode region 10512, the first insulating layer 106 and the second gate 104, the first insulating layer 106 serves as a capacitance medium between the second electrode region 10512 and the second gate 104, thereby forming an intermediate capacitance C g12 When the potential of the second gate 104 is changed, the charge is coupled to the second electrode region 10512. The deep well layer 105 can reduce coupling noise of the substrate 107. The first gate 101, the second pole region 10512 and the second insulating layer 108 form a miller capacitance C gd During the power switch tube conduction, the voltage V between the first grid electrode 101 and the first pole 102 gs Increasing to Miller plateau voltage V p At the same time, the potential of the second gate 104 is controlled and the intermediate capacitance C between the second gate 104 and the first gate 101 is used for g12 Coupling charge to Miller capacitance C gd To increase the first gate 101 to the miller capacitance C gd The charging speed effectively shortens the time of the power switch tube in the Miller platform, reduces the power consumption of the power switch tube and improves the efficiency of the power switch tube.
Further, fig. 10 is a schematic cross-sectional view of another power switch tube provided in the embodiment of the present invention, and fig. 11 is a schematic cross-sectional view of another power switch tube provided in the embodiment of the present invention, where, as shown in fig. 10 and 11, the first gate 101 includes a first connection terminal 1011, the second pole 103 includes a second connection terminal 1031, and an overall thickness of the second insulating layer 108 in a first range is greater than an overall thickness of the second insulating layer 108 in a second range between the first connection terminal 1011 and the second connection terminal 1031; the first range is the midpoint between the first connection terminal 1011 and the second connection terminal 1031, and the second range is the midpoint between the second connection terminal 1031 and the first connection terminal 1011 and the second connection terminal 1031.
Specifically, the first connection terminal 1011 and the second connection terminal 1031 may be used for establishing electrical connection with the outside of the first gate electrode 101 and the second gate electrode 103, respectively, and the first electrode 102 and the second gate electrode 104 also have corresponding connection terminals, not shown in the drawing, for establishing electrical connection with the outside. By providing the second insulating layer 108 to have an overall thickness in the first range greater than the overall thickness of the second insulating layer 108 in the second range, as shown in fig. 10, the first gate 101 is integrally curved, as shown in fig. 11, and the first gate 101 is integrally curved, such that the thickness of the second insulating layer 108 is thinner in the region near the second stage 103, the miller capacitance C formed by the first gate 101, the second electrode region 10512, and the second insulating layer 108 can be reduced without degrading the performance of the power switch gd Further speeding up the miller capacitance C of the first gate 101 gd The charging speed effectively shortens the time of the power switch tube in the Miller platform, reduces the power consumption of the power switch tube and improves the efficiency of the power switch tube.
Fig. 12 is a schematic diagram of a voltage conversion circuit according to an embodiment of the present invention, including a driving unit 201 and a power switch tube in the above embodiment, where, as shown in fig. 12, a first output end of the driving unit 201 is connected to a first gate 101 of the power switch tube, a second output end of the driving unit 201 is connected to a second gate 104 of the power switch tube, and a first input end of the driving unit 201 is used for accessing a control signal V c Reference signal of driving unit 201Input end for accessing reference voltage signal V ref The method comprises the steps of carrying out a first treatment on the surface of the The driving unit 201 is used for driving the driving unit according to the control signal V c Controlling the potential of the first grid electrode 101 to enable the power switch tube to be conducted through the first grid electrode 101; and the voltage at the first gate 101 is greater than the reference voltage signal V ref The potential of the second gate 104 is controlled to accelerate the turn-on of the power switch through the second gate 104.
Specifically, the driving unit 201 may be configured to control the driving unit according to the control signal V c Controlling the potential of the first gate 101 of the power switch tube, and then according to the potential of the first gate 101 and the reference voltage signal V ref The potential of the second gate 104 is controlled so that the state of the power switch can be controlled. Illustratively, the power switching tube may be an N-type MOS tube. The driving unit 201 can be controlled according to the control signal V c Controlling the voltage V between the first gate 101 and the first pole 102 gs Less than threshold voltage V th At this time, the power switch tube is in a cut-off state; when the driving unit 201 can be controlled according to the control signal V c Controlling the voltage V between the first gate 101 and the first pole 102 gs Greater than threshold voltage V th At this time, the power switch tube is turned on by the first gate 101, and the second current I d Above 0, the power switch has power consumption before the voltage between the first pole 102 and the second pole 103 decreases to 0. A portion of the charge of the first gate 101 is miller capacitance C gd And (5) charging. At Miller capacitance C gd During the charging process, the driving unit 201 can generate a voltage signal V according to the potential of the first gate 101 and the reference voltage ref Controlling the potential jump of the second gate 104 to be high level to pass through the intermediate capacitance C between the second gate 104 and the first gate 101 g12 Coupling charge to Miller capacitance C gd To increase the first gate 101 to the miller capacitance C gd The charging speed is reduced, so that the time of the power switching tube in a power consumption stage can be shortened, the power consumption of the power switching tube is reduced, and the efficiency of the power switching tube is improved. Therefore, the power consumption of the voltage conversion circuit can be further reduced, and the efficiency of the voltage conversion circuit is improved.
The embodiment provides a voltage conversion circuit, which comprises a driving unit and the power switch tube in the embodiment, wherein in the working process of the voltage conversion circuit, when the driving unit controls the power switch tube to be conducted according to a control signal and a reference voltage signal, the power of the power switch tube can be reduced, so that the power consumption of the voltage conversion circuit can be reduced, and the efficiency of the voltage conversion circuit is improved.
Fig. 13 is a schematic diagram of another voltage conversion circuit provided in an embodiment of the present invention, as shown in fig. 13, a driving unit 201 includes a first driving module 2011, a second driving module 2012, and a comparing module 2013;
the input end of the first driving module 2011 is used for accessing the control signal V c The output end of the first driving module 2011 is connected with the first gate 101 and the positive input end of the comparing module 2013, and the first driving module 2011 is configured to c Controlling the potential of the first gate 101; the input end of the comparison module 2013 is used for accessing the reference voltage signal V ref An output end of the comparison module 2013 is connected with an input end of the second driving module 2012, and an output end of the second driving module 2012 is connected with the second gate 104; the comparing module 2013 is configured to form a comparison signal according to the potential of the first gate 101 and the reference voltage signal, and the second driving module 2012 is configured to control the potential of the second gate 104 according to the comparison signal.
Specifically, the first driving module 2011 is configured to control the driving module according to the control signal V c The potential of the first gate 101 is controlled. In the first driving module 2011, according to the control signal V c When the potential of the first grid electrode 101 is controlled to jump from the invalid level to the valid level, the power switch tube is in a conducting state through the first grid electrode 101, and the voltage V between the first pole 102 and the second pole 103 of the power switch tube ds Falling, second pole 103 current I d Rising, the power switch begins to have power consumption. At this time, a part of the charge of the first gate 101 is the miller capacitance C gd And (5) charging. The range of the reference voltage signal can be set according to the requirement, so that the comparison module 2013 forms an effective comparison signal according to the potential of the first gate 101 and the reference voltage signal when the power switch tube has the power consumption stage, and the second driving module 2012 controls the potential of the second gate 104 to jump from the invalid level to the valid comparison signalAn effective level such that an intermediate capacitance C between the second gate 104 and the first gate 101 g12 Coupling charge to Miller capacitance C gd To increase the first gate 101 to the miller capacitance C gd The charging speed effectively shortens the time of the power switching tube in the power consumption stage, reduces the power consumption of the power switching tube and improves the efficiency of the power switching tube. Therefore, the power consumption of the voltage conversion circuit can be further reduced, and the efficiency of the voltage conversion circuit is improved.
Illustratively, the power switching tube may be an N-type MOS tube. The comparison module 2013 may be a comparator, and a negative input terminal of the comparator is connected to the reference voltage signal V ref The positive input terminal is connected to the first gate 101, and the potential of the first gate 101 is obtained. The comparator compares the potential of the first gate 101 with the reference voltage signal V ref Is greater than the reference voltage signal V at the comparator ref When the comparator outputs a high level signal to the second driving module 2012, the second driving module 2012 controls the potential transition of the second gate 104 to be high level according to the high level signal provided by the comparator to pass through the intermediate capacitor C between the second gate 104 and the first gate 101 g12 Coupling charge to Miller capacitance C gd To increase the first gate 101 to the miller capacitance C gd The charging speed effectively shortens the time of the power switching tube in a power consumption stage, reduces the power consumption of the power switching tube, and improves the efficiency of the power switching tube, so that the efficiency of the voltage conversion circuit can be further improved; the voltage at the first gate 101 is less than the reference voltage signal V ref When the comparator outputs a low level signal to the second driving module 2012, the second driving module 2012 controls the potential of the second gate 104 to be maintained at a low level, and the intermediate capacitor C between the second gate 104 and the first gate 101 g12 The charge cannot be coupled to the first gate 101.
Optionally, the reference voltage signal satisfies: v (V) p ＞V ref ≥V th The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is th Is the threshold voltage of the power switch tube, V p Is the miller platform voltage of the power switch tube, V ref Is a reference voltage signal.
In particular, with reference to FIGS. 6 and 12, V th Is Q gs2 Start point of stage V p Is Q gd End of stage. When the reference voltage signal satisfies: v (V) p ＞V ref ≥V th At the time of Q gs2 Stage or Q gd The stage control power switch tube is conducted through the second grid electrode 104, and at the moment, the intermediate capacitor C between the second grid electrode 104 and the first grid electrode 101 can be used for g12 Coupling charge to the first gate 101 to increase the first gate 101 to a miller capacitance C gd The charging speed effectively shortens the time of the power switch tube in the Miller platform, reduces the power consumption of the power switch tube, and improves the efficiency of the power switch tube, thereby further improving the power consumption of the voltage conversion circuit. When the reference voltage signal V ref For Miller platform voltage V p When the power switch tube is in the miller platform, the time for the power switch tube to be in the miller platform can be shortened. In other embodiments, the reference voltage signal V may also be set ref At a threshold voltage V th Can furthest reduce the Miller capacitance C gd Further reducing the power consumption of the power switch tube.
Optionally, fig. 14 is a schematic diagram of another voltage conversion circuit provided in the embodiment of the present invention, as shown in fig. 14, where the power switch tube 100 is a power switch tube described in the foregoing embodiment, the voltage conversion circuit further includes an input switch tube 301 and an energy storage unit 401, a gate of the input switch tube 301 is connected to a third output end of the driving unit 201, a first pole of the input switch tube 301 is connected to a power input end VDD, a second pole of the input switch tube 301 is connected to a second pole of the power switch tube 100 and a first input end of the energy storage unit 401, a first pole of the power switch tube 100 and a second input end of the energy storage unit 401 are connected to a fixed potential end V1, an output end of the energy storage unit 401 is used as an output end VOUT of the voltage conversion circuit, the driving unit 201 is further used to control the input switch tube 301 and the power switch tube 100 to conduct in a time-sharing manner, and the energy storage unit 401 is used to store and release electric energy.
Specifically, the input switching tube 301 and the power switching tube 100 are controlled to conduct in a time-sharing manner by the pulse width modulator in the driving unit 201 unit, so that electric energy is stored in the energy storage unit 401 through the input switching tube 301, and voltage conversion is achieved through the power switching tube 100. When the input switching tube 301 is turned on and the power switching tube 100 is turned off, the input switching tube 301 stores electric energy of the power supply input end VDD into the energy storage unit 401, when the power switching tube 100 is turned on and the input switching tube 301 is turned off, the power switching tube 100 and the energy storage unit 401 form a loop, and the energy storage unit 401 supplies electric energy to the output end VOUT of the voltage conversion circuit to supply power to a load.
It should be noted that, as shown in fig. 14, the energy storage unit 401 exemplarily includes an inductor and a capacitor, one end of the inductor is used as a first input end of the energy storage unit 401, the other end of the inductor is connected to one end of the capacitor and is used as an output end of the energy storage unit 401, and the other end of the capacitor is used as a second input end of the energy storage unit 401. By providing the energy storage unit 401 comprising an inductance and a capacitance, the storage and release of electrical energy can be achieved while having a filtering effect.
With continued reference to fig. 14, the voltage conversion circuit further includes an over-temperature protection unit 501, where the over-temperature protection unit 501 is connected to the driving unit 201, and the over-temperature protection unit 501 is configured to output an over-temperature control signal to the driving unit 201 when the temperature of the power switching tube 100 and/or the input switching tube 301 exceeds a preset temperature, and the driving unit 201 is further configured to control the power switching tube 100 and the input switching tube 301 to be turned off according to the over-temperature control signal.
Specifically, when the power switch tube 100 and the input switch tube 301 have power loss in the opening process to generate heat, when the temperature of the power switch tube 100 and/or the input switch tube 301 exceeds a preset temperature, the over-temperature protection unit 501 may output an over-temperature control signal to the driving unit 201, and the driving unit 201 controls the power switch tube 100 and the input switch tube 301 to be turned off simultaneously according to the over-temperature control signal, so as to avoid damage to the power switch tube 100 and the input switch tube 301 caused by overhigh temperature of the power switch tube 100 and the input switch tube 301 in the opening process.
In addition, the embodiment of the invention also provides a voltage conversion chip which comprises the voltage conversion circuit in the embodiment.
Specifically, the voltage conversion chip can realize the same function as that of the voltage conversion circuit in the above embodiment, and has the corresponding beneficial effects of the voltage conversion circuit in the above embodiment.
It should be understood that the above detailed description is not intended to limit the scope of the invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
The foregoing description is only of the preferred embodiments of the invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (10)

1. The power switch tube is characterized by comprising a deep well layer, a first insulating layer, a first grid electrode, a second grid electrode, a first pole and a second pole;
the second grid electrode and the first insulating layer are arranged in the deep well layer, the first insulating layer coats the second grid electrode, the deep well layer further comprises a via hole, and the second grid electrode is electrically connected with an external structure through the via hole; the first grid electrode is arranged on the deep well layer; the first gate electrode and the second gate electrode partially overlap in a thickness direction of the deep well layer; the first electrode, the first grid electrode and the second electrode are arranged along a first direction, wherein the first direction is perpendicular to the thickness direction of the deep well layer.
2. The power switch tube of claim 1, wherein said second gate comprises at least two and said deep well layer comprises at least two of said vias; each second grid electrode is overlapped with the first grid electrode in a part along the thickness direction of the deep well layer, and each second grid electrode is electrically connected with the external structure through one through hole.
3. The power switch tube as claimed in claim 1, wherein the second gate electrode includes at least two, and at least two of the second gate electrodes are electrically connected to the external structure through the via holes after being electrically connected, and each of the second gate electrodes partially overlaps the first gate electrode in a thickness direction of the deep well layer.
4. The power switch tube of claim 1, further comprising a substrate, a well layer, a second insulating layer, and an active layer;
the deep well layer is arranged on the substrate, the well layer is arranged in the deep well layer, the active layer is arranged in the well layer, the second insulating layer is arranged on the active layer, and the first grid electrode is arranged on the second insulating layer;
the active layer includes a first region and a second region; along the first direction, a vertical projection of the first electrode region on the substrate is at least partially located on one side of a vertical projection of the first gate electrode on the substrate, and a vertical projection of the second electrode region on the substrate is at least partially located on the other side of the vertical projection of the first gate electrode on the substrate; the first electrode region is in contact with the first pole, and the second electrode region is in contact with the second pole.
5. The power switch tube of claim 4, wherein said first gate includes a first connection terminal and said second gate includes a second connection terminal, and wherein an overall thickness of said second insulating layer in a first range is greater than an overall thickness of said second insulating layer in a second range between said first connection terminal and said second connection terminal; wherein the first range is a midpoint between the first connection terminal and the second connection terminal, and the second range is a midpoint between the second connection terminal and the first connection terminal and the second connection terminal.
6. A voltage conversion circuit comprising a drive unit and the power switching tube of any one of claims 1-5; the first output end of the driving unit is connected with the first grid electrode of the power switch tube, the second output end of the driving unit is connected with the second grid electrode of the power switch tube, the first input end of the driving unit is used for accessing a control signal, and the reference signal input end of the driving unit is used for accessing a reference voltage signal; the driving unit is used for controlling the potential of the first grid electrode according to the control signal so as to enable the power switch tube to be conducted through the first grid electrode; and controlling the potential of the second grid electrode when the voltage of the first grid electrode is larger than the reference voltage signal so as to enable the power switch tube to be conducted through the second grid electrode.
7. The voltage conversion circuit of claim 6, wherein the drive unit comprises a first drive module, a second drive module, and a comparison module;
the input end of the first driving module is used for accessing the control signal, the output end of the first driving module is connected with the first grid electrode and the positive input end of the comparison module, and the first driving module is used for controlling the potential of the first grid electrode according to the control signal; the negative input end of the comparison module is used for accessing the reference voltage signal, the output end of the comparison module is connected with the input end of the second driving module, and the output end of the second driving module is connected with the second grid electrode; the comparison module is used for forming a comparison signal according to the potential of the first grid electrode and the reference voltage signal, and the second driving module is used for controlling the potential of the second grid electrode according to the comparison signal.
8. The voltage conversion circuit of claim 6, wherein the reference voltage signal satisfies: v (V) p ＞V ref ≥V th The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is th Is the threshold voltage of the power switch tube, V p Is the Miller platform voltage, V of the power switch tube ref Is the reference voltage signal.
9. The voltage conversion circuit according to claim 6, further comprising an input switching tube and an energy storage unit, wherein a gate of the input switching tube is connected to the third output terminal of the driving unit, a first pole of the input switching tube is connected to a power input terminal, a second pole of the input switching tube is connected to the second pole of the power switching tube and a first input terminal of the energy storage unit, the first pole of the power switching tube and the second input terminal of the energy storage unit are connected to a fixed potential terminal, an output terminal of the energy storage unit serves as an output terminal of the voltage conversion circuit, the driving unit is further configured to control the input switching tube and the power switching tube to conduct in a time-sharing manner, and the energy storage unit is configured to store and release electric energy.
10. A voltage conversion chip comprising a voltage conversion circuit according to any one of claims 6-9.
CN202311040858.6A 2023-08-18 2023-08-18 Power switching tube, voltage conversion circuit and voltage conversion chip Active CN116759459B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311040858.6A CN116759459B (en) 2023-08-18 2023-08-18 Power switching tube, voltage conversion circuit and voltage conversion chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311040858.6A CN116759459B (en) 2023-08-18 2023-08-18 Power switching tube, voltage conversion circuit and voltage conversion chip

Publications (2)

Publication Number Publication Date
CN116759459A CN116759459A (en) 2023-09-15
CN116759459B true CN116759459B (en) 2023-12-05

Family

ID=87953662

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311040858.6A Active CN116759459B (en) 2023-08-18 2023-08-18 Power switching tube, voltage conversion circuit and voltage conversion chip

Country Status (1)

Country Link
CN (1) CN116759459B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085625A (en) * 1999-09-13 2001-03-30 Hitachi Ltd Semiconductor integrated circuit device and fabrication method thereof
CN101505055A (en) * 2008-12-30 2009-08-12 上海英联电子系统有限公司 Active surge current control circuit
CN115332338A (en) * 2022-08-08 2022-11-11 上海功成半导体科技有限公司 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN116137292A (en) * 2021-11-17 2023-05-19 无锡华润上华科技有限公司 LDMOS device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101526555B1 (en) * 2014-08-22 2015-06-09 서울대학교산학협력단 Reconfigurable electronic devices and operation method thereof
JP2021180297A (en) * 2020-05-15 2021-11-18 富士電機株式会社 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085625A (en) * 1999-09-13 2001-03-30 Hitachi Ltd Semiconductor integrated circuit device and fabrication method thereof
CN101505055A (en) * 2008-12-30 2009-08-12 上海英联电子系统有限公司 Active surge current control circuit
CN116137292A (en) * 2021-11-17 2023-05-19 无锡华润上华科技有限公司 LDMOS device and manufacturing method thereof
CN115332338A (en) * 2022-08-08 2022-11-11 上海功成半导体科技有限公司 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof

Also Published As

Publication number Publication date
CN116759459A (en) 2023-09-15

Similar Documents

Publication Publication Date Title
US8941356B2 (en) Battery heating circuits and methods with resonance components in series using energy transfer
CN101064468B (en) Dc-to-dc converter and electric motor drive system using the same
US8941358B2 (en) Heating circuits and methods based on battery discharging and charging using resonance components in series and freewheeling circuit components
US9209793B2 (en) Bootstrap circuitry for an IGBT
US9007099B2 (en) Semiconductor device with a current sampler and a start-up structure
Seidel et al. A fully integrated three-level 11.6 nC gate driver supporting GaN gate injection transistors
CN101552554A (en) Control circuit of cascade type buck-boost converter and control method thereof
WO2019184442A1 (en) Three-level bidirectional dc/dc circuit
US11894762B2 (en) Direct current-direct current conversion circuit
CN110957923A (en) High-frequency isolation bidirectional direct current converter based on phase-shifted full bridge and grid-connected energy storage system
CN110034681B (en) Staggered parallel ZVZCS high-boost DC/DC converter
CN109309448B (en) Wide-input wide-output Cuk DC-DC converter
RU2691959C1 (en) Electric power conversion circuit
CN116759459B (en) Power switching tube, voltage conversion circuit and voltage conversion chip
Jin et al. 30.6 A 98.6%-peak-efficiency 1.47 A/mm2-current-density buck-boost converter with always reduced conduction loss
CN209896911U (en) DC-DC converter for fuel cell
KR101030776B1 (en) Boost dc/dc converter
CN103532382A (en) Switching power supply circuit
CN114172374B (en) Cross flying capacitor hybrid boost-buck DC-DC converter based on double inductors
Abdulslam et al. 17.5 A 98.2%-efficiency reciprocal direct charge recycling inductor-first DC-DC converter
CN109217449A (en) Power supply device operation method, power supply device and power supply device management system
CN216625581U (en) Synchronous rectification circuit, maximum power point tracking controller and photovoltaic optimizer
US20230057337A1 (en) Series stacked phase dc-dc converters with stable operation
CN216751538U (en) Soft switch boost chopper circuit
CN211209582U (en) Slope compensation circuit and voltage converter

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant