CN116757143A - Thermal mechanical reliability layout optimization method and device for TSV array, electronic equipment and storage medium - Google Patents

Thermal mechanical reliability layout optimization method and device for TSV array, electronic equipment and storage medium Download PDF

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CN116757143A
CN116757143A CN202310803493.1A CN202310803493A CN116757143A CN 116757143 A CN116757143 A CN 116757143A CN 202310803493 A CN202310803493 A CN 202310803493A CN 116757143 A CN116757143 A CN 116757143A
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layout
tsv array
tsv
thermal
mechanical reliability
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刘建云
徐勤志
曹鹤
李志强
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/08—Thermal analysis or thermal optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/14—Force analysis or force optimisation, e.g. static or dynamic forces

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Abstract

The application provides a thermal mechanical reliability layout optimization method and device of a TSV array, electronic equipment and a storage medium, wherein the method comprises the following steps: according to TSV array arrangement, solving a thermal stress distribution result of a structure, optimizing the thermal mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result to obtain a TSV array layout with optimal thermal mechanical reliability, and finding possible stress hot spots in the structure in a design stage to improve array arrangement and increase process yield; in addition, the thermal mechanical reliability result of the TSV array can be predicted, analysis is performed, so that the process flow is optimized, more reliable structural layout is obtained, the influence on the subsequent process is reduced, and the period from design to manufacture is shortened.

Description

Thermal mechanical reliability layout optimization method and device for TSV array, electronic equipment and storage medium
Technical Field
The application relates to the technical field of data processing, in particular to a thermal mechanical reliability layout optimization method and device of a TSV array, electronic equipment and a storage medium.
Background
Through silicon vias (Through Silicon Via, TSVs) are a vertical channel etched in the middle of a silicon wafer that enables the chips to be vertically interconnected to one another by filling with a metal material. Currently, copper filled TSVs are a popular application. Copper has high feasibility for use in TSVs due to its good electrical conductivity, but copper filling still has some thermal stress issues. The thermal expansion coefficient of the silicon substrate is generally 2.6x10 < -6 >/DEG C, the thermal expansion coefficient of the silicon dioxide is 0.4x10 < -6 >/DEG C, the thermal expansion coefficient of the filled copper metal is 16.5x10 < -6 >/DEG C, a larger temperature difference can be generated in the annealing process of TSV processing, and the problem of thermal stress mismatch between the filling material and the silicon substrate is more remarkable.
The TSV metal introduces thermal mechanical stress in the surrounding silicon substrate, the light causes a change in carrier mobility in the surrounding silicon substrate, which leads to degradation of device performance, and the heavy causes spalling and faults of the silicon substrate, which leads to damage and failure of the chip. Due to process and structural particularities, thermal reliability issues faced by TSVs include cracking of the TSV due to copper-silicon thermal mismatch in the event of periodic temperature changes in copper-filled TSVs; the TSV and the bump are connected with the fracture of the intermetallic compound under the stress. Particularly for TSV arrays, it is therefore highly desirable to evaluate the thermo-mechanical reliability of the array during the design phase, and to propose an optimization scheme.
Disclosure of Invention
In view of the above, embodiments of the present application provide a method, an apparatus, an electronic device, and a storage medium for optimizing a thermal mechanical reliability layout of a TSV array, which can discover stress hot spots possibly existing in a structure in a design stage, and improve array arrangement.
In order to achieve the above object, the embodiment of the present application provides the following technical solutions:
the first aspect of the embodiment of the application discloses a thermal mechanical reliability layout optimization method for a TSV array, which comprises the following steps:
according to the arrangement of the TSV array, solving a structural thermal stress distribution result;
and optimizing the thermal mechanical reliability of the TSV array by utilizing a preset algorithm based on the thermal stress distribution result to obtain the TSV array layout with optimal thermal mechanical reliability.
Optionally, in the above method for optimizing the thermal mechanical reliability layout of a TSV array, according to the TSV array arrangement, solving a thermal stress distribution result of a structure includes:
determining a thermal stress field of each TSV in the TSV array;
and superposing the thermal stress fields of each TSV in the TSV array to obtain the thermal stress distribution result.
Optionally, in the method for optimizing the thermal mechanical reliability layout of the TSV array, based on the thermal stress distribution result, the thermal mechanical reliability of the TSV array is optimized by using a preset algorithm, so as to obtain a TSV array layout with optimal thermal mechanical reliability, including:
in each optimizing process, comparing the maximum value of the layout stress of the current optimizing with the maximum value of the stress of the last optimizing to obtain a comparison result, and judging that the comparison result meets the stress solution convergence condition; the maximum layout stress value is obtained based on the preset algorithm, the thermal stress distribution result and a preset layout constraint condition;
and taking the TSV array layout corresponding to the stress solution convergence condition as the TSV array layout with the optimal thermal mechanical reliability.
Optionally, in the above method for optimizing the layout of the thermal mechanical reliability of the TSV array, before determining that the comparison result meets the stress solution convergence condition, the method further includes:
determining the layout of the TSV array according to the specification of the circuit layout; and if the circuit layout specification is not met, reserving the current TSV array layout for the last layout.
The second aspect of the embodiment of the application discloses a thermal mechanical reliability layout optimization device for a TSV array, which comprises the following components:
the solving unit is used for solving the thermal stress distribution result of the structure according to the TSV array arrangement;
and the optimizing unit is used for optimizing the thermal mechanical reliability of the TSV array by utilizing a preset algorithm based on the thermal stress distribution result to obtain the TSV array layout with the optimal thermal mechanical reliability.
Optionally, in the above-mentioned arrangement optimizing device for thermal mechanical reliability of TSV array, the solving unit is specifically configured to, when configured to solve a thermal stress distribution result of a structure according to the arrangement of the TSV array:
determining a thermal stress field of each TSV in the TSV array;
and superposing the thermal stress fields of each TSV in the TSV array to obtain the thermal stress distribution result.
Optionally, in the above-mentioned apparatus for optimizing a thermal-mechanical reliability layout of a TSV array, the optimizing unit is configured to, when performing optimizing on the thermal-mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result, obtain a TSV array layout with optimal thermal-mechanical reliability, specifically configured to:
in each optimizing process, comparing the maximum value of the layout stress of the current optimizing with the maximum value of the stress of the last optimizing to obtain a comparison result, and judging that the comparison result meets the stress solution convergence condition; the maximum layout stress value is obtained based on the preset algorithm, the thermal stress distribution result and a preset layout constraint condition;
and taking the TSV array layout corresponding to the stress solution convergence condition as the TSV array layout with the optimal thermal mechanical reliability.
Optionally, the above-mentioned thermal mechanical reliability layout optimizing device for TSV array further includes:
the determining unit is used for determining the TSV array layout according to the circuit layout specification before judging that the comparison result meets the stress solution convergence condition; and if the circuit layout specification is not met, reserving the current TSV array layout for the last layout.
In a third aspect, an embodiment of the present application discloses an electronic device, including a memory and a processor;
the memory is used for storing a computer program;
the processor is configured to execute the computer program, and in particular, to implement a method for optimizing a thermal mechanical reliability layout of a TSV array according to any one of the first aspect disclosed.
A fourth aspect of the embodiment of the present application discloses a computer storage medium, configured to store a computer program, where the computer program is specifically configured to implement the method for optimizing the thermal mechanical reliability layout of the TSV array according to any one of the first aspect disclosed.
The thermal mechanical reliability layout optimization method for the TSV array provided by the embodiment of the application comprises the following steps: according to TSV array arrangement, solving a thermal stress distribution result of a structure, optimizing the thermal mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result to obtain a TSV array layout with optimal thermal mechanical reliability, and finding possible stress hot spots in the structure in a design stage to improve array arrangement and increase process yield; in addition, the thermal mechanical reliability result of the TSV array can be predicted, analysis is performed, so that the process flow is optimized, more reliable structural layout is obtained, the influence on the subsequent process is reduced, and the period from design to manufacture is shortened.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a thermal mechanical reliability layout optimization method for a TSV array provided by the present application;
FIG. 2 is a flow chart of determining a thermal stress field for each TSV in a TSV array according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a cylindrical TSV structure according to an embodiment of the present application;
fig. 4 is a flowchart of a layout of a TSV array with optimal thermo-mechanical reliability according to an embodiment of the present application;
FIG. 5 is a flowchart of another embodiment of the present application for providing a layout of a TSV array with optimal thermal mechanical reliability;
fig. 6 is a schematic structural diagram of a thermal mechanical reliability layout optimizing device for TSV arrays according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
TSVs are a vertical channel etched in the middle of a silicon wafer that enables a chip to be vertically interconnected to another chip by filling with a metal material. TSVs are high density, low capacity interconnects that enable more interconnects between stacked chips and which can operate at higher speeds and lower power consumption than conventional wire bonding. Even in the era where traditional feature size scaling has become increasingly difficult and expensive, TSV-based 3D technologies can create new generation "superchips" by opening up new architectures that allow the semiconductor industry to continue to pursue more functions, bandwidth and performance in terms of smaller size, power consumption and cost.
TSV technology is a key technology for realizing inter-chip connection, however, three-dimensional integration still faces some problems and technical challenges in terms of reliability due to the introduction of new materials, new processes and new structures. In TSV three-dimensional stacked packaging technology, heterogeneous integration, structural diversification and cost requirements are involved, and new challenges that may be caused include: chip-package collaborative design and thermal management of a complex system, TSV interconnection technology and testing tools and methods of an integrated system are used for meeting the requirements of novel material development of system integration electricity, heat and force heat. The reliability of the three-dimensional integrated micro system is an important breakthrough point, and particularly, the thermodynamic performance research and the thermo-mechanical reliability evaluation of the system are realized.
Based on the above, the embodiment of the application provides a thermal mechanical reliability layout optimization method for a TSV array, which can discover stress hot spots possibly existing in a structure in a design stage and improve array arrangement.
Referring to fig. 1, the method for optimizing the thermal mechanical reliability layout of the TSV array mainly includes the following steps:
s101, according to TSV array arrangement, solving a thermal stress distribution result of the structure.
In practical application, step S101 is executed, and according to the TSV array arrangement, the thermal stress distribution result of the solving structure is mainly used to determine the thermal stress distribution result of the TSV array, and the specific process may be as shown in fig. 2, and may include steps S201 and S202:
s201, determining a thermal stress field of each TSV in the TSV array.
The TSV array is generally formed by combining a plurality of TSVs. The thermal stress field of a single TSV structure in a TSV array can be solved using classical theory of elastomechanics.
Taking a cylindrical TSV structure as an example, the cylindrical TSV structure may be as shown in fig. 3, a conventional TSV includes a dielectric isolation layer, a diffusion barrier layer, and a filler metal. A common dielectric barrier layer is silicon dioxide and diffusion barriers are nitrides of titanium and tantalum. In general, the thickness of the diffusion barrier layer is nano-scale and is far smaller than that of the dielectric isolation layer, so that the diffusion barrier layer has little influence on thermal stress and can be treated according to the dielectric isolation layer.
In practical application, the thermal stress data of any position in the TSV structure can be determined by utilizing the three-dimensional theoretical analysis solution of the TSV structure, and a specific formula can be as follows:
wherein sigma z Is longitudinal stress, sigma r Is radial stress, sigma θ Is the axial stress, sigma zr The other stress component is zero for shear stress. The coordinate value of any point is (r, z), r is the distance from the TSV center, z is the vertical height, a is the TSV radius, P is the surface pressure caused by temperature, v is the Poisson's ratio,β＝tan -1 [ρsinθ/(r-ρcosθ)]。
it should be noted that the thermal stress data of the TSV structure in this embodiment is equivalent to the thermal stress field of the TSV structure.
S202, superposing the thermal stress fields of each TSV in the TSV array to obtain a thermal stress distribution result.
In practical application, the thermal stress distribution result of the TSV can be determined by utilizing the superposition principle based on the thermal stress data of any position in the TSV structure. The specific process can be as follows: and calculating the thermal stress of each TSV in the TSV array by considering the superposition principle calculation, and obtaining the thermal stress distribution result of the TSV array. The superposition principle refers to that when a plurality of forces act on a certain point at the same time, the actual stress condition of the point is the sum of all the forces and the stress vector of the point.
It should be noted that, the thermal stress data of any position in the TSV structure can be determined by using the three-dimensional theoretical analysis solution of the TSV structure, and then the thermal stress distribution result of the TSV is determined by using the superposition principle based on the thermal stress data of any position in the TSV structure, so as to be used for analyzing the thermal reliability of the three-dimensional integrated circuit.
S102, optimizing the thermal mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result to obtain the TSV array layout with the optimal thermal mechanical reliability.
In practical application, the layout of the TSV array can be optimized by introducing a simulated annealing algorithm. For the TSV array, in order to shorten the calculation time and save the calculation resources, the simulation annealing algorithm is considered to be introduced to optimize the layout of the TSV array, so that the optimal layout of the chip on the premise of key indexes is obtained, and stress hot spots are eliminated.
Specifically, the simulated annealing algorithm and the constraint condition of the TSV array can be combined to obtain the improved TSV array layout optimization simulated annealing algorithm.
Based on the above, the specific process of performing step S102 to obtain the TSV array layout with optimal thermal mechanical reliability by optimizing the thermal mechanical reliability of the TSV array by using the preset algorithm based on the thermal stress distribution result may be as shown in fig. 4, and mainly includes steps S301 and S302:
s301, comparing the maximum value of the layout stress of the current optimizing with the maximum value of the stress of the last optimizing in each optimizing process to obtain a comparison result, and judging that the comparison result meets the stress solution convergence condition.
The maximum layout stress value is obtained based on a preset algorithm, a thermal stress distribution result and a preset layout constraint condition.
Specifically, the preset algorithm may be a simulated annealing algorithm or other existing algorithms, which are not specifically limited by the present application, and are all within the scope of the present application.
Similarly, the preset layout constraint condition can be determined according to the specific application environment and the user requirement, and the application is not particularly limited and is within the protection scope of the application.
It should be noted that, the optimizing is a process of continuously and circularly executing, and in conjunction with fig. 5, the specific process may be as follows:
step 1: initializing all parameters, carrying out thermal stress solving by the initial layout, taking the maximum value of the layout stress (the maximum thermal stress value) as an objective function, and storing the initial solution as the current solution.
In other words, all parameters may be initialized at the time of the initial execution, the thermal stress solution is performed by the initial layout, the maximum value of the layout stress (the maximum thermal stress value) is taken as an objective function, and the initial solution is saved as the current solution.
It should be noted that, all parameters may be parameters required for the layout of the TSV array, such as geometric dimensions, material parameters in the initial random layout, such as chip area, length, width, TSV number, diameter, pitch, geometric position, and material parameters of the related materials, such as elastic modulus, poisson ratio, thermal expansion coefficient, etc.; the stress solving process can specifically refer to step S101, and the thermal stress distribution result of the solving structure is obtained according to the TSV array arrangement, which is not described herein.
Step 2: a new layout is created by changing the TSV locations. The TSVs within the constraint conditions do not participate in the handover, and if the constraint conditions are not satisfied, a new solution needs to be regenerated.
The constraint condition mainly refers to constraint of circuit layout specifications, such as constraint and limiting condition of TSV geometric positions. The TSV locations within the constraints not participating in the shift may be that the TSV locations within the circuit layout condition definition cannot be changed.
It should be noted that, in practical application, the TSV positions may be changed to generate a new layout. Specifically, the method for generating the new layout is not particularly limited, and the method can be manually modified or can be modified through an algorithm, and is within the protection scope of the application.
Step 3: the new solution generated in the step 2 can be solved according to the method of the first step to obtain the objective function value of the new solution, and the objective function value difference between the two solutions is obtained by comparing the objective function value with the current objective function value.
Step 4: judging whether the calculation reaches the termination condition, if the calculation is carried out for several times, the new solution and the current solution are unchanged in form, namely judging that the calculation of the algorithm is finished, keeping the current solution and outputting the current solution as the global optimal layout, and if not, jumping to the second step, generating the new solution and continuously executing the algorithm.
The termination condition may be that the calculated maximum stress does not generate a new minimum value under different layout conditions, and it can be understood that the optimal solution of the stress in the non-layout is found.
That is, the stress solution convergence condition may be satisfied as the termination condition, and the difference in objective function value between the two solutions may be used as the comparison result.
S302, taking the TSV array layout corresponding to the stress solution convergence condition as the TSV array layout with optimal thermal mechanical reliability.
In practical application, after the comparison result is judged to meet the stress solution convergence condition, the TSV array layout corresponding to the stress solution convergence condition is used as the TSV array layout with optimal thermal mechanical reliability.
In some embodiments, before the comparison result is determined to meet the stress solution convergence condition in step S301, the method for optimizing the thermal mechanical reliability layout of the TSV array may further include S401:
s401, determining the current TSV array layout according to the circuit layout specification.
If the circuit layout specification is met, the TSV array layout is a new layout corresponding to the comparison result, and if the circuit layout specification is not met, the TSV array layout keeps the last layout.
In practical application, the layout receiving result can be determined according to the circuit layout specification, and then the TSV array layout can be determined according to the layout receiving result. If the layout receiving result is acceptable, the TSV array layout is a new layout corresponding to the comparison result, and if the layout receiving result is not acceptable, the TSV array layout reserves the last layout; of course, the layout of the TSV array is not limited thereto, and the present TSV array layout can be determined according to the application environment and the user requirements, which is not particularly limited by the present application, and is within the scope of the present application.
Based on the above principle, the thermal mechanical reliability layout optimization method for the TSV array provided by the embodiment includes: according to TSV array arrangement, solving a thermal stress distribution result of a structure, optimizing the thermal mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result to obtain a TSV array layout with optimal thermal mechanical reliability, and finding possible stress hot spots in the structure in a design stage to improve array arrangement and increase process yield; in addition, the thermal mechanical reliability result of the TSV array can be predicted, analysis is performed, so that the process flow is optimized, more reliable structural layout is obtained, the influence on the subsequent process is reduced, and the period from design to manufacture is shortened.
Based on the method for optimizing the thermal mechanical reliability layout of the TSV array provided in the above embodiment, correspondingly, another embodiment of the present application further provides a device for optimizing the thermal mechanical reliability layout of the TSV array, referring to fig. 6, which mainly includes:
the solving unit 101 is configured to solve a thermal stress distribution result of the structure according to TSV array arrangement.
And the optimizing unit 102 is configured to optimize the thermal mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result, so as to obtain a TSV array layout with optimal thermal mechanical reliability.
In some embodiments, the solving unit 101 is specifically configured to, when used for solving a thermal stress distribution result of a structure according to TSV array arrangement:
determining a thermal stress field of each TSV in the TSV array; and superposing the thermal stress fields of each TSV in the TSV array to obtain a thermal stress distribution result.
In some embodiments, the optimizing unit 102 is configured to, when performing optimization on the thermo-mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result of the TSV array, obtain a TSV array layout with optimal thermo-mechanical reliability, specifically configured to:
in each optimizing process, comparing the maximum value of the layout stress of the current optimizing with the maximum value of the stress of the last optimizing to obtain a comparison result, and judging that the comparison result meets the stress solution convergence condition; the maximum value of the layout stress is obtained based on a preset algorithm, a thermal stress distribution result of the TSV array and layout constraint conditions.
And taking the TSV array layout corresponding to the stress solution convergence condition as the TSV array layout with optimal thermal mechanical reliability.
In some embodiments, the thermal mechanical reliability layout optimization apparatus of the TSV array further includes:
the determining unit is used for determining the TSV array layout according to the circuit layout specification before judging that the comparison result meets the stress solution convergence condition; if the circuit layout specification is met, the TSV array layout is a new layout corresponding to the comparison result, and if the circuit layout specification is not met, the TSV array layout keeps the last layout.
In the thermal mechanical reliability layout optimization device for the TSV array provided in this embodiment, the solution unit 101 may be used to solve the thermal stress distribution result of the structure according to the TSV array arrangement; the optimizing unit 102 is configured to optimize the thermo-mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result of the TSV array, so as to obtain a TSV array layout with optimal thermo-mechanical reliability, and find possible stress hot spots in the structure in the design stage, so as to improve the array arrangement and increase the process yield; in addition, the thermal mechanical reliability result of the TSV array can be predicted, analysis is performed, so that the process flow is optimized, more reliable structural layout is obtained, the influence on the subsequent process is reduced, and the period from design to manufacture is shortened.
It should be noted that, for the description of each unit of the thermal mechanical reliability layout optimization device of the TSV array, reference may be made to the corresponding embodiment of the above method, and the description is omitted here.
Optionally, another embodiment of the present application further provides an electronic device, please refer to fig. 7, including a memory 601 and a processor 602;
the memory 601 is for storing a computer program;
the processor 602 is configured to execute a computer program, and is specifically configured to implement a method for optimizing a thermal mechanical reliability layout of a TSV array according to any embodiment of the present application.
It should be noted that, for the description of the method for optimizing the layout of the thermal mechanical reliability of the TSV array, reference is made to the above embodiment, and the description thereof is omitted here.
Optionally, the embodiment of the present application further provides a computer storage medium, where the computer storage medium is used to store a computer program, and the computer program is specifically used to implement the method for optimizing the thermal mechanical reliability layout of the TSV array provided by any embodiment of the present application.
It should be noted that, for the description of the method for optimizing the layout of the thermal mechanical reliability of the TSV array, reference is made to the above embodiment, and the description thereof is omitted here.
In the context of this disclosure, a computer storage medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The systems and system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The thermal mechanical reliability layout optimization method for the TSV array is characterized by comprising the following steps of:
according to the TSV array arrangement, solving a thermal stress distribution result of the structure;
and optimizing the thermal mechanical reliability of the TSV array by utilizing a preset algorithm based on the thermal stress distribution result to obtain the TSV array layout with optimal thermal mechanical reliability.
2. The method for optimizing the thermal mechanical reliability layout of a TSV array according to claim 1, wherein solving the thermal stress distribution result of the structure according to the TSV array arrangement includes:
determining a thermal stress field of each TSV in the TSV array;
and superposing the thermal stress fields of each TSV in the TSV array to obtain the thermal stress distribution result.
3. The method for optimizing the thermal mechanical reliability layout of the TSV array according to claim 1, wherein optimizing the thermal mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result to obtain the TSV array layout with the optimal thermal mechanical reliability comprises:
in each optimizing process, comparing the maximum value of the layout stress of the current optimizing with the maximum value of the stress of the last optimizing to obtain a comparison result, and judging that the comparison result meets the stress solution convergence condition; the maximum layout stress value is obtained based on the preset algorithm, the thermal stress distribution result and a preset layout constraint condition;
and taking the TSV array layout corresponding to the stress solution convergence condition as the TSV array layout with the optimal thermal mechanical reliability.
4. The method for optimizing the thermal mechanical reliability layout of a TSV array according to claim 3, further comprising, before determining that the comparison result satisfies a stress solution convergence condition:
determining the layout of the TSV array according to the specification of the circuit layout; and if the circuit layout specification is not met, reserving the current TSV array layout for the last layout.
5. A thermal mechanical reliability layout optimization device for a TSV array, comprising:
the solving unit is used for solving the thermal stress distribution result of the structure according to the TSV array arrangement;
and the optimizing unit is used for optimizing the thermal mechanical reliability of the TSV array by utilizing a preset algorithm based on the thermal stress distribution result to obtain the TSV array layout with the optimal thermal mechanical reliability.
6. The arrangement optimizing apparatus for thermal mechanical reliability of TSV array according to claim 5, wherein the solving unit is specifically configured to, when configured to solve a thermal stress distribution result of a structure according to the TSV array arrangement:
determining a thermal stress field of each TSV in the TSV array;
and superposing the thermal stress fields of each TSV in the TSV array to obtain the thermal stress distribution result.
7. The apparatus for optimizing a thermal-mechanical reliability layout of a TSV array according to claim 5, wherein the optimizing unit is configured to, when performing optimizing the thermal-mechanical reliability of the TSV array by using a preset algorithm based on the thermal stress distribution result, obtain a TSV array layout with optimal thermal-mechanical reliability, specifically:
in each optimizing process, comparing the maximum value of the layout stress of the current optimizing with the maximum value of the stress of the last optimizing to obtain a comparison result, and judging that the comparison result meets the stress solution convergence condition; the maximum layout stress value is obtained based on the preset algorithm, the thermal stress distribution result and a preset layout constraint condition;
and taking the TSV array layout corresponding to the stress solution convergence condition as the TSV array layout with the optimal thermal mechanical reliability.
8. The apparatus for optimizing the thermal mechanical reliability layout of a TSV array according to claim 7 further comprising:
the determining unit is used for determining the TSV array layout according to the circuit layout specification before judging that the comparison result meets the stress solution convergence condition; and if the circuit layout specification is not met, reserving the current TSV array layout for the last layout.
9. An electronic device comprising a memory and a processor;
the memory is used for storing a computer program;
the processor is configured to execute the computer program, in particular to implement a thermo-mechanical reliability layout optimization method of a TSV array according to any of claims 1 to 4.
10. A computer storage medium, characterized by storing a computer program, which, when executed, is in particular adapted to implement a thermo-mechanical reliability layout optimization method of a TSV array according to any of claims 1 to 4.
CN202310803493.1A 2023-07-03 2023-07-03 Thermal mechanical reliability layout optimization method and device for TSV array, electronic equipment and storage medium Pending CN116757143A (en)

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