CN116757142A

CN116757142A - Quantum chip layout simulation method, device, equipment and storage medium

Info

Publication number: CN116757142A
Application number: CN202310716338.6A
Authority: CN
Inventors: 王宇轩; 晋力京
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2023-06-15
Filing date: 2023-06-15
Publication date: 2023-09-15

Abstract

The disclosure provides a simulation method, a device, equipment and a storage medium of a quantum chip layout, relates to the technical field of computers, and particularly relates to the technical fields of quantum computation, quantum simulation and the like. The specific implementation scheme is as follows: determining a target association relation corresponding to a target coupler architecture in a quantum chip layout, wherein the target coupler architecture at least comprises two quantum bits and a coupler; the coupler is used for coupling the two qubits; the target association relation characterizes the association relation between the intrinsic frequency difference between two quantum bits and the actual frequency of the coupler; under the condition that a target point exists in the target association relation, a first simulation result is obtained, and the first simulation result characterizes the target coupler architecture to meet the preset architecture requirement; and the equivalent coupling strength between the two quantum bits at the target point meets the coupling requirement.

Description

Quantum chip layout simulation method, device, equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to the technical fields of quantum computing, quantum simulation, and the like.

Background

The superconducting quantum chip is the core of the technical scheme of the superconducting quantum circuit, along with the progress of micro-nano processing technology, the number of the quantum bits which can be integrated on the superconducting quantum chip is continuously increased, and the aim in the future is to realize the integration of tens of thousands of quantum bits from a few, tens of thousands to hundreds of different. As the number of qubits continues to grow, the quantum chip layout design of superconducting quantum chips becomes increasingly urgent and important. After the quantum chip layout is designed, a problem is how to verify the validity of the quantum chip layout, and the problem is to be solved currently.

Disclosure of Invention

The disclosure provides a simulation method, device and equipment of a quantum chip layout and a storage medium.

According to one aspect of the present disclosure, a method for simulating a quantum chip layout is provided, including:

determining a target association relation corresponding to a target coupler architecture in a quantum chip layout, wherein the target coupler architecture at least comprises two quantum bits and a coupler; wherein the coupler is used for coupling the two qubits; the target association relation characterizes the association relation between the intrinsic frequency difference between two quantum bits and the actual frequency of the coupler; and

Under the condition that a target point exists in the target association relation, a first simulation result is obtained, and the first simulation result characterizes the target coupler architecture to meet the preset architecture requirement; and the equivalent coupling strength between the two quantum bits at the target point meets the coupling requirement.

According to another aspect of the present disclosure, there is provided a simulation apparatus of a quantum chip layout, including:

the first processing unit is used for determining a target association relation corresponding to a target coupler architecture in the quantum chip layout, wherein the target coupler architecture at least comprises two quantum bits and a coupler; wherein the coupler is used for coupling the two qubits; the target association relation characterizes the association relation between the intrinsic frequency difference between two quantum bits and the actual frequency of the coupler; and

the second processing unit is used for obtaining a first simulation result under the condition that a target point exists in the target association relation, and the first simulation result represents that the target coupler architecture meets the preset architecture requirement; and the equivalent coupling strength between the two quantum bits at the target point meets the coupling requirement.

According to yet another aspect of the present disclosure, there is provided a computing device comprising:

At least one quantum processing unit QPU;

a memory coupled to the at least one QPU and configured to store executable instructions,

the instructions are executed by the at least one QPU to enable the at least one QPU to perform the method described above;

alternatively, it includes:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method described above.

According to yet another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above;

alternatively, the computer instructions are for causing the computer to perform the method described above.

According to a further aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by at least one quantum processing unit, implements the method described above;

Or which when executed by a processor implements the method described above.

In this way, the scheme of the present disclosure passes through a specific scheme for verifying the validity and rationality of the target coupler architecture, and further verifies the design rationality of the quantum chip layout containing the target coupler architecture; therefore, the method has important guiding significance for the design, simulation and verification of the subsequent quantum chip; in addition, the scheme disclosed by the invention is simple and convenient, is easy to implement, and has low use threshold, thus having practicability.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of an implementation flow of a simulation method of a quantum chip layout according to an embodiment of the present disclosure;

FIG. 2 is a second schematic implementation flow diagram of a simulation method of a quantum chip layout according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram III of an implementation flow of a simulation method of a quantum chip layout according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a flow chart for implementing a simulation method of a quantum chip layout according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an implementation flow of a simulation method of a quantum chip layout in a specific example according to an embodiment of the disclosure;

FIG. 6 (a) is a schematic diagram of a quantum chip layout of a superconducting quantum chip according to an embodiment of the present disclosure;

FIG. 6 (b) is a graphical illustration of the difference in eigenfrequency versus the actual frequency of the coupler in one example in accordance with the disclosed scheme;

FIG. 6 (c) is a graph of equivalent coupling strength between qubits versus actual frequency of a coupler for a prior art scheme;

FIG. 7 is a schematic diagram of a simulation apparatus of a quantum chip layout according to an embodiment of the present disclosure;

FIG. 8 is a block diagram of a computing device used to implement a simulation method of a quantum chip layout of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. The term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, e.g., including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C. The terms "first" and "second" herein mean a plurality of similar technical terms and distinguishes them, and does not limit the meaning of the order, or only two, for example, a first feature and a second feature, which means that there are two types/classes of features, the first feature may be one or more, and the second feature may be one or more.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be appreciated by one skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Quantum computation is one of the landmark technologies in the post-molar age, and is attracting attention from academia and industry. Compared with traditional calculation, quantum calculation has obvious advantages in solving problems such as large number decomposition, and provides new ideas for front-end research such as quantum multi-body systems, quantum chemical simulation and the like. These potential quantum applications greatly drive the development of quantum hardware, and in hardware implementation, such as superconducting quantum circuits, ion traps, diamond NV color centers, nuclear magnetic resonance, optical quantum systems, etc., are all candidates for quantum computing hardware, wherein superconducting quantum circuits are considered as the most promising candidates for quantum computing hardware in industry due to their advantages of long decoherence time, easy operation/reading, and high scalability.

Based on the above, the scheme of the disclosure provides a simulation method of a quantum chip layout, which is used for verifying the validity of the quantum chip layout.

Specifically, fig. 1 is a schematic diagram of an implementation flow of a simulation method of a quantum chip layout according to an embodiment of the present disclosure; the method is optionally applied to a quantum computing device with classical computing capability, and also can be applied to a classical computing device with classical computing capability, or directly applied to an electronic device with classical computing capability, such as a personal computer, a server cluster, and the like, or directly applied to a quantum computer, and the scheme of the disclosure is not limited to this.

Further, the method includes at least part of the following. As shown in fig. 1, includes:

step S101: and determining a target association relationship corresponding to the target coupler architecture in the quantum chip layout.

Here, the target coupler architecture includes at least two qubits and a coupler; the coupler is used for coupling the two qubits, for example, the coupler is arranged between the two qubits so as to couple two adjacent qubits.

Further, the target association represents an association between an intrinsic frequency difference between two qubits and an actual frequency of the coupler. For example, in one example, the target relationship may be represented by a relationship, such as an intrinsic frequency difference versus the actual frequency of the coupler.

Step S102: under the condition that a target point exists in the target association relation, a first simulation result is obtained, and the first simulation result characterizes that the target coupler architecture meets the preset architecture requirement.

Here, the equivalent coupling strength between the two qubits at the target point satisfies the coupling requirement.

In a specific example, the equivalent coupling strength between the two qubits at the target point is less than an strength threshold; further, the target point may be specifically coupling Guan Duandian, where the equivalent coupling strength between the two qubits at the coupling-off point is approximately 0, so that the rationality and effectiveness of the quantum chip layout including the target coupler architecture are verified based on whether the coupling-off point exists in the target coupler architecture.

In a specific example, the target point may be represented by a two-dimensional real pair, for example, in the case where the target association relationship is represented by a curve, the target point may be represented by a coordinate point, for example, by a coordinate point (an actual frequency of a coupler at the target point, an intrinsic frequency difference at the target point). Alternatively, the target point may be represented by a real number, e.g., by the actual frequency of the coupler at the target point.

In a specific example of the scheme of the disclosure, the quantum chip layout is a quantum chip layout of a superconducting quantum chip; further, the superconducting quantum chip refers to a quantum chip prepared from superconducting materials. For example, all components (such as qubits, coupling devices, etc.) in the superconducting quantum chip are made of superconducting materials. Therefore, the scheme disclosed by the invention can be applied to the superconducting quantum chip, enriches the use scene of the scheme disclosed by the invention, and has important guiding significance for the design, simulation and verification of the superconducting quantum chip.

In a specific example of the solution of the present disclosure, fig. 2 is a second implementation flow diagram of a simulation method of a quantum chip layout according to an embodiment of the present disclosure; the method is optionally applied to a quantum computing device with classical computing capability, and also can be applied to a classical computing device with classical computing capability, or directly applied to an electronic device with classical computing capability, such as a personal computer, a server cluster, and the like, or directly applied to a quantum computer, and the scheme of the disclosure is not limited to this. It will be appreciated that the relevant content of the method shown in fig. 1 above may also be applied to this example, and this example will not be repeated for the relevant content.

Further, the method includes at least part of the following. As shown in fig. 2, includes:

step S201: and determining a target association relationship corresponding to the target coupler architecture in the quantum chip layout.

Here, the target coupler architecture includes at least two qubits and a coupler; the coupler is used for coupling the two qubits; the target association represents an association between an intrinsic frequency difference between two qubits and an actual frequency of the coupler.

Step S202: judging whether a target point exists in the target association relation; if yes, go to step S203; otherwise, step S204 is performed.

Step S203: under the condition that a target point exists in the target association relation, a first simulation result is obtained, and the first simulation result characterizes that the target coupler architecture meets the preset architecture requirement.

Step S204: and under the condition that the target point does not exist in the target association relationship, obtaining a second simulation result, wherein the second simulation result characterizes that the target coupler architecture does not meet the preset architecture requirement.

In this way, the scheme of the disclosure passes through a refinement scheme for verifying the effectiveness and rationality of the target coupler architecture, and further verifies the design rationality of the quantum chip layout containing the target coupler architecture; therefore, the method has important guiding significance for the design, simulation and verification of the subsequent quantum chip. Moreover, the verification scheme is simple, convenient and efficient, can quickly verify the effectiveness of the target coupler architecture, does not need complex calculation, has higher practicability, and is convenient for engineering popularization.

In a specific example of the scheme of the present disclosure, the following manner may be used to quickly obtain the equivalent coupling strength between qubits; specifically, fig. 3 is a schematic diagram of an implementation flow chart of a simulation method of a quantum chip layout according to an embodiment of the disclosure; the method is optionally applied to a quantum computing device with classical computing capability, and also can be applied to a classical computing device with classical computing capability, or directly applied to an electronic device with classical computing capability, such as a personal computer, a server cluster, and the like, or directly applied to a quantum computer, and the scheme of the disclosure is not limited to this. It will be appreciated that the relevant content of the method shown in fig. 1 above may also be applied to this example, and this example will not be repeated for the relevant content.

Further, the method includes at least part of the following. As shown in fig. 3, includes:

step S301: and determining a target association relationship corresponding to the target coupler architecture in the quantum chip layout.

Step S302: under the condition that a target point exists in the target association relation, a first simulation result is obtained, and the first simulation result characterizes that the target coupler architecture meets the preset architecture requirement.

Step S303: and under the condition that the target point exists in the target association relation, acquiring the target bare frequency difference of the two quantum bits.

Step S304: based on the target association relationship, obtaining an intrinsic frequency difference at a first point; the first point is any point except the target point in the target association relation.

Step S305: and obtaining the target equivalent coupling strength between the two quantum bits at the first point based on the target bare frequency difference of the two quantum bits and the intrinsic frequency difference at the first point.

That is, in the case that the target point exists in the target association relationship, that is, in the case that the target coupler architecture meets the preset architecture requirement, the target equivalent coupling strength between two qubits at any point other than the target point can be obtained quickly by using the target association relationship.

Further, in a specific example, the target equivalent coupling strength between two qubits at the first point is noted as g _eff Recording the target bare frequency difference of the two quantum bits as delta ₀ Recording the firstThe difference in intrinsic frequency between the two qubits at the point isThe target equivalent coupling strength g between the two qubits at the first point _eff Can be obtained by the following formula:

in this way, under the condition that the verification target coupler architecture meets the preset architecture requirement, the target association relation required by the verification process can be fully utilized, and the target equivalent coupling strength between two quantum bits at any non-target point can be rapidly obtained, so that a feasible scheme is provided for efficiently obtaining the coupling strength between two quantum bits. In addition, the process does not need to carry out complex calculation, reduces the calculation complexity of equivalent coupling strength, saves a great amount of calculation resources and time, and has more practicability.

In a specific example of the disclosed scheme, the target bare frequency difference of two qubits may be obtained in the following manner; specifically, when the target point exists in the target association relationship, the method acquires the target bare frequency difference of the two qubits (i.e. step S303 described above), which specifically includes:

step S303-1: and under the condition that a target point exists in the target association relationship, acquiring an intrinsic frequency difference at the target point based on the target association relationship.

Step S303-2: and obtaining the target bare frequency difference of the two quantum bits based on the intrinsic frequency difference at the target point.

In a specific example, the difference in eigenfrequency at the target point can be directly taken as the difference in target bare frequency of two qubits, i.e., as Δ in the above equation ₀ Further, the target association relation required by the verification process is fully utilized, and any non-target is rapidly obtained on the basis of effectively ensuring the accuracy of the obtained equivalent coupling strengthTarget equivalent coupling strength between two qubits at a point.

In this way, under the condition that the verification target coupler architecture meets the preset architecture requirement, the target association relation required by the verification process is further fully utilized, and the target equivalent coupling strength between two quantum bits at any non-target point is rapidly obtained, so that a feasible scheme is further provided for efficiently obtaining the coupling strength between two quantum bits. In addition, the process does not need to carry out complex calculation, reduces the calculation complexity of equivalent coupling strength, saves a great amount of calculation resources and time, and has more practicability.

FIG. 4 is a schematic diagram of a flow chart for implementing a simulation method of a quantum chip layout according to an embodiment of the present disclosure; the method is optionally applied to a quantum computing device with classical computing capability, and also can be applied to a classical computing device with classical computing capability, or directly applied to an electronic device with classical computing capability, such as a personal computer, a server cluster, and the like, or directly applied to a quantum computer, and the scheme of the disclosure is not limited to this. It will be appreciated that the relevant content of the method shown in fig. 1 above may also be applied to this example, and this example will not be repeated for the relevant content.

Further, the method includes at least part of the following. As shown in fig. 4, includes:

step S401: and under the condition that the two quantum bits are in a target resonance state, determining a target association relation corresponding to a target coupler architecture in the quantum chip layout.

In a specific example, the difference of the intrinsic frequencies of the two quantum bits in the target resonance state is smaller than a preset threshold, for example, smaller than a verification value, for example, 10MHz, so that the problem that the target point cannot be found due to other reasons is effectively avoided, and further, a foundation is laid for further improving the validity of the verification result.

Step S402: under the condition that a target point exists in the target association relation, a first simulation result is obtained, and the first simulation result characterizes that the target coupler architecture meets the preset architecture requirement.

It should be noted that, in the coupler architecture, the coupling strength between the qubits is typically around 5-20MHz, and the bare frequency difference between the two qubits may be on the order of tens to hundreds of megahertz. In addition, considering the simulation error of simulating the quantum chip layout, under the condition of a certain bare frequency difference, a target point in the target association relation between the intrinsic frequency difference of two quantum bits and the actual frequency of the coupler may be submerged in the bare frequency difference and the simulation error, so that in order to avoid the problem, the two quantum bits are in the target resonance state in advance, and the target association relation between the intrinsic frequency difference and the frequency of the coupler is obtained by using simulation data, so that the effectiveness of the result is effectively improved.

In this way, the scheme of the present disclosure provides a refinement scheme for verifying the validity and rationality of the target coupler architecture in the target resonance state, so as to improve the accuracy of the verification result. Moreover, the verification scheme is simple, convenient and efficient, can quickly verify the effectiveness of the target coupler architecture, does not need complex calculation, has higher practicability, and is convenient for engineering popularization.

In a specific example of the solution of the present disclosure, before determining the target association relationship corresponding to the target coupler architecture in the quantum chip layout (i.e., before the step S401 described above) in the case where the two qubits are in the target resonance state, the method further includes:

determining a first target inductance and a second target inductance capable of bringing the two qubits into the target resonance state; the first target inductance is an equivalent inductance of a first qubit of the two qubits; the second target inductance is an equivalent inductance of a second qubit of the two qubits;

it is noted that in the case where the equivalent inductance of a first qubit of the two qubits is a first target inductance and the equivalent inductance of a second qubit is a second target inductance, the two qubits are in a target resonance state.

Further, in the case that the two qubits are in the target resonance state, determining the target association relationship corresponding to the target coupler architecture in the quantum chip layout (i.e. the step S401 described above) specifically includes:

and determining a target association relation corresponding to a target coupler architecture in the quantum chip layout under the condition that the first quantum bit is in the first target inductance and the second quantum bit is in the second target inductance.

That is, the mode of adjusting the equivalent inductance of the qubit is used for enabling the two qubits to be in the target resonance state, so that a specific mode for enabling the two qubits to be in the target resonance state is provided, and a foundation is laid for the follow-up effective verification of the design rationality of the target coupler architecture.

In a specific example of the disclosed solution, the first target inductance and the second target inductance may be obtained in the following manner; specifically, the determining the first target inductance and the second target inductance that enable the two qubits to be in the target resonance state specifically includes:

determining a target frequency of the coupler that is capable of decoupling the coupler from the first qubit and decoupling the coupler from the second qubit;

A first target inductance and a second target inductance capable of bringing the two qubits into the target resonance state are determined with the coupler at a target frequency.

That is, before determining the first target inductance and the second target inductance that enable the two qubits to be in the target resonance state, it is necessary to further decouple the coupler from the first qubit and decouple the coupler from the second qubit, and then de-confirm the first target inductance and the second target inductance that enable the two qubits to be in the target resonance state.

For example, in an example, where the actual frequency of the coupler is fixed at the target frequency, adjusting the equivalent inductance of the first qubit and/or the equivalent inductance of the second qubit, such as adjusting the equivalent inductance of the first qubit to a first value and the equivalent inductance of the second qubit to a second value; at this time, the eigenfrequency of the first quantum bit and the eigenfrequency of the second quantum bit are obtained through simulation, and then the eigenfrequency difference of the first quantum bit and the eigenfrequency difference of the second quantum bit are obtained; under the condition that the difference of the intrinsic frequencies of the two quantum bits is smaller than a preset threshold value, the two quantum bits can be determined to be in a target resonance state, at the moment, the first value is the first target inductance, and the second value is the second target inductance.

Or under the condition that the difference of the intrinsic frequencies of the two is larger than or equal to a preset threshold value, the equivalent inductance of at least one quantum bit in the two quantum bits can be continuously adjusted, and the difference of the intrinsic frequencies is obtained through re-simulation until the difference of the intrinsic frequencies is smaller than the preset threshold value.

Therefore, the scheme of the present disclosure provides a method for rapidly obtaining the first target inductance and the second target inductance, so that the two qubits are in a target resonance state, and a foundation is laid for improving the accuracy of the verification result. Moreover, the scheme is simple, convenient and efficient, does not need complex calculation, has higher practicability and is convenient for engineering popularization.

In a specific example of the disclosed solution, the target frequency of the coupler may be obtained in the following manner; specifically, the determining the target frequency of the coupler that enables the coupler to be in a decoupled state from the first qubit and enables the coupler to be in a decoupled state from the second qubit specifically includes:

a target equivalent inductance of the coupler is determined that is capable of decoupling the coupler from the first qubit and decoupling the coupler from the second qubit.

Here, the actual frequency of the coupler is the target frequency at the target equivalent inductance.

In a specific example, the target equivalent inductance is smaller than a preset inductance value, for example, an inductance value smaller than or equal to 0.5nH, so that the actual frequency of the coupler reaches a larger value (corresponding to the target frequency described above), and at this time, the coupler and each qubit are in a decoupled state, so that the first qubit Q1 and the second qubit Q2 are in an approximately direct coupling state. And further, a foundation is laid for rapidly enabling two qubits to be in a target resonance state, and meanwhile, a foundation is laid for effectively improving the accuracy of a verification result.

That is, in this example, the purpose of adjusting the actual frequency of the coupler can be achieved by adjusting the equivalent inductance of the coupler, so that the target frequency of the coupler is obtained quickly, and a foundation is laid for effectively improving the accuracy of the verification result in the following process. Moreover, the scheme is simple, convenient and efficient, does not need complex calculation, has higher practicability and is convenient for engineering popularization.

In a specific example of the solution of the present disclosure, the target association relationship may be obtained as follows; specifically, determining the target association relationship corresponding to the target coupler architecture in the quantum chip layout when the first qubit is in the first target inductance and the second qubit is in the second target inductance specifically includes:

Executing the following simulation steps for a plurality of times under the condition that the first qubit is in the first target inductance and the second qubit is in the second target inductance, namely, under the condition that two qubits are in a target resonance state, so as to obtain the intrinsic frequency difference of the two qubits, wherein the coupler is in different actual frequencies; here, the actual frequencies of the couplers are different in the different simulation steps;

obtaining the target association relation based on the intrinsic frequency difference of the two quantum bits of the coupler under different actual frequencies;

the current simulation steps comprise:

simulating to obtain the eigenfrequency of each quantum bit in the two quantum bits when the coupler is at the current actual frequency;

and obtaining the intrinsic frequency difference of the two quantum bits under the current actual frequency of the coupler based on the intrinsic frequency of each quantum bit in the two quantum bits.

In this way, the scheme disclosed by the disclosure provides a specific simulation scheme for obtaining the target association relationship, and the scheme can verify the effectiveness and rationality of the target coupler architecture in the target resonance state, so that the accuracy of a verification result is improved. Moreover, the scheme is simple, convenient and efficient, can rapidly verify the effectiveness of the target coupler architecture, does not need complex calculation, has higher practicability, and is convenient for engineering popularization.

Further, in a specific example, after deriving the difference in the intrinsic frequencies of the two qubits for which the coupler is at the current actual frequency, the method further includes:

adjusting the actual frequency of the coupler within a preset frequency range;

after the actual frequency adjustment of the coupler is completed, the next simulation step is entered.

That is, with the first qubit at the first target inductance and the second qubit at the second target inductance, performing the following steps to obtain an intrinsic frequency difference of the two qubits with the coupler at different actual frequencies; the method comprises the following specific steps:

step one: simulating to obtain the eigenfrequency of each quantum bit in the two quantum bits when the coupler is at the current actual frequency;

step two: based on the intrinsic frequency of each quantum bit in the two quantum bits, obtaining the intrinsic frequency difference of the two quantum bits of the coupler under the current actual frequency;

step three: adjusting the actual frequency of the coupler within a preset frequency range;

step four: after the actual frequency adjustment of the coupler is completed, i.e. the process returns to the first step to perform the next simulation step and is repeated a plurality of times.

Thus, the intrinsic frequency difference of the two quantum bits of the coupler under different actual frequencies, namely, multiple groups of data, can be obtained, and then the target association relationship is obtained based on the multiple groups of data, for example, the target association relationship is obtained based on fitting of the multiple groups of data.

In summary, the scheme disclosed by the invention can verify the validity of the coupler architecture through the simulation and the data post-processing of the quantum chip layout, and further verify the validity of the quantum chip layout containing the coupler architecture. Moreover, the application range of the scheme disclosed by the invention is wide, namely the scheme has universality, for example, the scheme disclosed by the invention is suitable for a coupler framework with symmetrical quantum bits (such as electromagnetic environment symmetry of the quantum bits), and is also suitable for a coupler framework with asymmetrical quantum bits (such as electromagnetic environment asymmetry of the quantum bits), so that the practical value of the scheme disclosed by the invention is further fully described.

The present disclosure is described in further detail below with reference to specific examples; specifically, the disclosed scheme provides a simulation method of a quantum chip layout, for example, for a quantum chip layout containing a coupler architecture, the disclosed scheme utilizes simulation data to determine whether coupling Guan Duandian exists in the coupler architecture in the quantum chip layout, so as to judge the design rationality of the quantum chip layout containing the coupler architecture; further, after design rationality verification is performed, the scheme of the present disclosure may further perform data post-processing, so as to quickly obtain an equivalent coupling strength between two qubits in the coupler architecture of the uncoupled Guan Duandian (may also be referred to as a coupling open point).

Taking a quantum chip layout of a superconducting quantum chip as an example, and elaborating the scheme from three aspects, specifically, a first part, introducing theoretical knowledge of the quantum chip layout of the superconducting quantum chip, and defining the problem to be solved by the scheme of the disclosure; a second section illustrating core steps for implementing the disclosed schemes; and the third part, application demonstration, applies the scheme and the existing scheme (such as an equivalent circuit modeling method) to the quantum chip layout containing the coupler architecture so as to verify the validity and universality of the scheme.

First part, problem characterization and theoretical knowledge

The superconducting quantum chip is a physical carrier for realizing quantum computation, and in order to realize accurate control of quantum information, the quantum chip layout of the superconducting quantum chip needs to be effectively designed. For example, the mainstream design architecture of the superconducting quantum chip is a coupler architecture, i.e. a structure of a Qubit (Q) -coupler (C) -Qubit (Q) (which may be abbreviated as Q-C-Q); in the structure of Q-C-Q, the coupler is used for coupling two adjacent qubits, and at the moment, the equivalent coupling strength between the two coupled qubits can be adjusted by adjusting the actual frequency of the coupler so as to realize the turn-off or turn-on of the coupling of the two qubits. Therefore, verification of the validity of the coupler architecture is essential after the quantum chip layout design is completed.

Note that the point at which the coupling between two qubits is turned off may be referred to as coupling Guan Duandian; and the open point of coupling between two qubits may be referred to as a coupling open point; it is understood that other points than the coupling off point are both on states, and that other points than the coupling off point may be referred to as coupling on points.

In a specific example, the coupling off point may be represented by an actual frequency of the coupler, e.g., the coupling off point represents: the actual frequency of the coupler is a frequency at which the coupling of two qubits can be turned off (for example, the frequency may be referred to as a turn-off frequency).

Ideally, the two qubits in the coupler architecture are perfectly symmetrical and in resonance, i.e. the bare frequencies of the two qubits (the frequencies of the qubits without any coupling, which may be referred to as bare frequencies) are equal, in the absence of any coupling of the qubits. In practice, however, there is an equivalent coupling between the two qubits, which causes the actual frequencies (also called eigenfrequencies) of the two qubits to split and create a frequency difference. At this time, the relationship between the equivalent coupling strength g between two qubits and the frequency difference (may also be referred to as an intrinsic frequency difference) Δ is:

g=Δ/2 formula (1)

Therefore, the real frequency of the coupler can be continuously changed, the intrinsic frequency difference of the two quantum bits can be obtained through simulation, and then the target association relation between the intrinsic frequency difference and the frequency of the coupler can be obtained; further, if a minimum point appears in the target association relationship, for example, a zero point appears (at the zero point, the equivalent coupling strength between two qubits is approximately 0), or the equivalent coupling strength between two qubits at the minimum point is smaller than the strength threshold, it indicates that the coupler architecture has coupling Guan Duandian, and the minimum point is the coupling off point.

In an actual quantum chip layout, even if the configurations of two quantum bits in a coupler architecture are consistent, different electromagnetic environments are generated due to different surrounding layouts of the quantum bits in the coupler architecture, so that the two quantum bits are in a non-resonance state (namely, the bare frequency difference of the two quantum bits is not 0), and at this time, the equivalent coupling strength of the two quantum bits cannot be obtained directly through a resonance sweep method, so that the effectiveness of the coupler architecture cannot be verified. For this reason, the present disclosure proposes a modified formula of equivalent coupling strength in the case where there is a bare frequency difference of the qubits (i.e., the bare frequency difference is not zero):

here g _eff Representing the equivalent coupling strength between two qubits;representing the difference of the intrinsic frequencies of the two qubits, i.e.>ω ₁ Represents the eigenfrequency, ω, of the first of the two qubits (e.g., denoted Q1) ₂ Represents the eigenfrequency of the second of the two qubits (e.g., denoted as Q2), where ω is if there is an equivalent coupling between the two qubits ₁ And omega ₂ Can be obtained directly through simulation. Delta ₀ Representing the bare frequency difference of two qubits, i.e. delta ₀ ＝|ω ₀₁ -ω ₀₂ |，ω ₀₁ Represents the bare frequency, ω, of the first qubit Q1 ₀₂ Representing the bare frequency of the second qubit Q2.

Further, the following formula can be obtained:

from the equation (3), the equivalent coupling strength g _eff When the actual frequency of the coupler changes, the frequency differenceAn inflection point, which is a minimum point, occurs.

It is noted that in one example, at this minimum point, the equivalent coupling strength g between two qubits _eff Can be approximately 0, at which time the intrinsic frequency of the two qubits differsApproximately equal to the bare frequency difference delta ₀ I.e.)>Therefore, by judging the intrinsic frequency difference +.>Whether the curve (corresponding to the target association relation) changing along with the actual frequency of the coupler has an inflection point or not is verified, whether the coupler architecture can realize the closing and opening of the equivalent coupling between the quantum bits or not is further verified, and the design effectiveness of the quantum chip containing the coupler architecture is further verified.

It should be noted that, in the coupler architecture, the coupling strength between the qubits is typically around 5-20MHz, and the bare frequency difference between the two qubits may be on the order of tens to hundreds of megahertz. In addition, considering the simulation error of simulating the quantum chip layout, under the condition of a certain bare frequency difference, the inflection point in the target association relation (such as a curve) between the intrinsic frequency difference of the two quantum bits and the actual frequency of the coupler is generally submerged in the bare frequency difference and the simulation error, so that the problem is avoided.

In addition, it should be noted that, the scheme disclosed in the present disclosure is applicable to a coupler architecture with symmetric qubits (such as symmetric electromagnetic environments of the qubits), and also applicable to a coupler architecture with asymmetric qubits (such as asymmetric electromagnetic environments of the qubits), so that the present disclosure has strong practicability and application value.

The second part, the specific steps of the scheme of the invention:

specifically, as shown in fig. 5, the specific steps include:

step S501: and inputting the quantum chip layout.

For example, a quantum chip layout of a superconducting quantum chip to be simulated is input, and the quantum chip layout of the superconducting quantum chip comprises the coupler architecture. The coupler architecture comprises at least: two qubits and a coupler, e.g., a first qubit Q1-coupler C-a second qubit Q2.

Step S502: the equivalent inductance of the coupler in the coupler architecture is adjusted to decouple the coupler from each qubit, e.g., decouple the coupler from the first qubit Q1 and decouple the coupler from the second qubit Q2.

It should be noted that, the purpose of adjusting the actual frequency of the coupler can be achieved by adjusting the equivalent inductance of the coupler, so as to achieve that the coupler is in a decoupling state with each qubit; for example, the equivalent inductance of the coupler is adjusted to be less than a preset inductance value (e.g., to be less than 0.5 nH) so that the actual frequency of the coupler reaches a larger value (corresponding to the target frequency described above), and at this time, the coupler and each qubit are in a decoupled state, so that the first qubit Q1 and the second qubit Q2 are in an approximately direct coupling state.

Step S503: the current equivalent inductance of each qubit in the coupler architecture is determined, for example, the current equivalent inductance of the first qubit Q1 is determined, and the current equivalent inductance of the second qubit Q2 is determined.

Step S504: and judging whether the two qubits in the coupler architecture are in a target resonance state or not. For example, it is determined whether or not the first qubit Q1 and the second qubit Q2 are in the target resonance state.

For example, under the condition that each quantum bit is in the current equivalent inductance, simulating the quantum chip layout, and obtaining the intrinsic frequency of each quantum bit, thereby obtaining the intrinsic frequency difference; at this time, it can be determined whether the difference between the intrinsic frequencies is smaller than a preset threshold (for example, smaller than 10 MHz) in the case where each qubit is at the current equivalent inductance; if yes, determining that the two quantum bits are in a target resonance state, and entering step S506; otherwise, it is determined that the two qubits are not in the target resonance state, and the process proceeds to step S505 to readjust the equivalent inductance of the qubits, so as to readjust whether the two qubits are in the target resonance state.

Step S505: the equivalent inductance of at least one of the two qubits is adjusted, e.g., the equivalent inductance of the first qubit Q1 is adjusted, and/or the equivalent inductance of the second qubit Q2 in the coupler architecture is adjusted. And returns to step S503 after the adjustment is completed.

It will be appreciated that in the case of decoupling the coupler from the first qubit Q1 and decoupling the coupler from the second qubit Q2, i.e. approximately directly coupling the two qubits, adjusting the equivalent inductance of the qubit may specifically comprise: the equivalent inductances of the two qubits are adjusted simultaneously; alternatively, the equivalent inductance of one of the two qubits is adjusted, e.g., the equivalent inductance of the first qubit Q1 is adjusted, and the equivalent inductance of the second qubit Q2 is not adjusted. In this way, the first qubit Q1 and the second qubit Q2 are brought into the target resonance state.

Further, in a specific example, the equivalent inductance of a qubit may be adjusted around the parameter design value of a given qubit, thus facilitating rapid bringing of two qubits into a target resonance state.

Step S506: under the condition that the two qubits are in a target resonance state, a target association relation between the intrinsic frequency difference and the actual frequency of the coupler is obtained, for example, a curve between the intrinsic frequency difference and the actual frequency of the coupler is obtained.

Specifically, when the first qubit Q1 is in a first target inductance and the second qubit Q2 is in a second target inductance, that is, the two qubits are in a target resonance state, the equivalent inductances of the couplers are adjusted in a preset adjustment interval, and the intrinsic frequency differences of different couplers under different equivalent inductances are obtained through simulation, so that a change curve of the intrinsic frequency differences and the equivalent inductances of the couplers, that is, a target sweep frequency curve is obtained.

It will be appreciated that in this example, multiple adjustments are required to the equivalent inductance of the coupler, i.e. the equivalent inductance of the coupler is swept. Further, under the condition that the equivalent inductance of the coupler is determined, the eigenfrequency of each quantum bit is simulated, and a frequency difference is obtained; after the equivalent inductance of the coupler is adjusted, the eigenfrequency of each quantum bit can be simulated to obtain a frequency difference; further, after adjusting the equivalent inductance of the coupler once, the eigenfrequency of each quantum bit can be simulated again to obtain a corresponding frequency difference; and then after multiple times of adjustment, multiple frequency differences can be obtained; thus, the frequency sweep of the coupler is completed.

Step S507: it is determined whether or not there is a target point (i.e., the inflection point described above) in the target association. If yes, go to step S508; otherwise, step S509 is performed.

Step S508: and obtaining a first simulation result, wherein the first simulation result characterizes that the coupler architecture meets the preset architecture requirement.

At this time, the target point is the coupling off point of the two qubits in the coupler architecture.

Step S509: and obtaining a second simulation result, wherein the second simulation result characterizes that the coupler architecture does not meet the preset architecture requirement. That is, the coupling off points of the two qubits in the coupler architecture are represented to be not present, and at this time, the coupler architecture is indicated to not meet the preset architecture requirement.

It should be noted that, under the condition that the coupler architecture meets the preset architecture requirement, the target association relationship can be used to quickly obtain the target equivalent coupling strength between two qubits at any non-target point, for example, the intrinsic frequency difference at the target point is used as delta in the above formula (2) ₀ As well asAnd obtaining the intrinsic frequency difference at any non-target point (i.e. the coupling opening point) based on the target association relationship, and taking the intrinsic frequency difference as delta in the formula (2), so that the target equivalent coupling strength between two quantum bits at any non-target point can be obtained rapidly by using the formula (2).

Third part, application display

In order to verify the effect of the scheme of the present disclosure, the scheme of the present disclosure is applied to an actual superconducting quantum chip containing a coupler architecture, and meanwhile, an equivalent circuit method commonly used in the industry is compared with the scheme of the present disclosure, so that the validity and universality of the scheme of the present disclosure are verified.

The quantum chip layout of the superconducting quantum chip with the coupler architecture to be verified is shown in fig. 6 (a), and the quantum chip layout comprises three quantum bits, namely a quantum bit Q1, a quantum bit Q2 and a quantum bit Q3, wherein each quantum bit corresponds to one reading cavity, and comprises two couplers, namely a coupler C12 (used for coupling the quantum bit Q1 and the quantum bit Q2) and a coupler C23 (used for coupling the quantum bit Q2 and the quantum bit Q3). In this example, the Q2-C23-Q3 structure is taken as the test unit of the target coupler architecture, at this time, the difference between the surrounding layouts of the qubit Q2 and the qubit Q3 can be obviously seen, at this time, a large bare frequency difference is necessarily present between the qubit Q2 and the qubit Q3, so that the frequency sweep of the coupler needs to be performed after the adjustment to the near-resonance state.

Here, sapphire is used as a substrate in this example, and the relative dielectric constant is 10; the overall size of the substrate is similar to that of actual micro-nano processing, and the length, width and height are respectively taken as follows: 10000um×10000um×400um.

In this example, following strictly the procedure described above, first, the equivalent inductance of coupler C23 is adjusted to 0.5nH so that qubit Q2 forms an approximately direct coupling with qubit Q3; continuously adjusting equivalent inductances of the quantum bit Q2 and the quantum bit Q3, wherein the equivalent inductances are 8.1nH and 8.03nH respectively, and simulating to obtain an intrinsic frequency difference of the quantum bit Q2 and the quantum bit Q3 of 9.9MHz, so as to meet the requirement of a target resonance state; further, the actual frequency of the coupler C23 is adjusted by adjusting the equivalent inductance of the coupler C23, and the difference between the intrinsic frequencies of the qubit Q2 and the qubit Q3 is obtained by simulation, resulting in a curve as shown in fig. 6 (b).

As can be seen from FIG. 6 (b) above, at the actual frequency of coupler C23 of about 15GHz, a distinct inflection point appears, thus being the coupling Guan Duandian of qubit Q2 and qubit Q3, and at the same time, a delta is obtained ₀ =2.5 MHz. Further, coupler C23 is at 10GHz, then there is At this time, the equivalent coupling strength of the qubit Q2 and the qubit Q3 at 10GHz can be obtained according to the above formula (2), and is about 7.4MHz.

In order to further verify the correctness of the scheme, the simulation modeling analysis is carried out on the Q2-C23-Q3 structure by adopting the existing equivalent circuit modeling method, the obtained result is shown in the following figure 6 (C), 6 (C shows the variation characteristic of the equivalent coupling strength between the quantum bit Q2 and the quantum bit Q3 along with the actual frequency of the coupler, it is worth noting that the sign of the equivalent coupling strength obtained by the equivalent circuit modeling method is divided (only the absolute value has physical significance in practice), and the process that the equivalent coupling strength crosses zero point from positive to negative is observed in the figure 6 (C), so that the coupler structure has coupling Guan Duandian (namely, the point with zero equivalent coupling strength), but because of the roughness of the equivalent circuit modeling, the position of a specific coupling relation breakpoint is not identical with the position of the coupling relation breakpoint predicted by the scheme of the present disclosure, but the trend of the integral variation of the equivalent coupling strength is consistent, which is enough to prove the correctness and the effectiveness of the scheme of the present disclosure.

In summary, the scheme of the present disclosure has the following advantages:

first, practicality: the method is suitable for an asymmetric coupler architecture in an actual complex quantum chip layout, and the rationality and effectiveness of the coupler structure design can be determined.

Second, accuracy: the determination mode of the equivalent coupling strength of two quantum bits at any coupling opening point under the condition of bare frequency difference is provided.

Third, robustness: according to the scheme, only the intrinsic frequency difference of two quantum bits is needed to be simulated, the dependence on simulation precision is small, and the robustness is high.

The scheme of the disclosure also provides a simulation device of the quantum chip layout, as shown in fig. 7, comprising:

the first processing unit 701 is configured to determine a target association relationship corresponding to a target coupler architecture in the quantum chip layout, where the target coupler architecture includes at least two quantum bits and a coupler; wherein the coupler is used for coupling the two qubits; the target association relation characterizes the association relation between the intrinsic frequency difference between two quantum bits and the actual frequency of the coupler; and

the second processing unit 702 is configured to obtain a first simulation result when the target point exists in the target association relationship, where the first simulation result characterizes that the target coupler architecture meets a preset architecture requirement; and the equivalent coupling strength between the two quantum bits at the target point meets the coupling requirement.

In a specific example of the present disclosure, the second processing unit 702 is further configured to

And under the condition that the target point does not exist in the target association relationship, obtaining a second simulation result, wherein the second simulation result characterizes that the target coupler architecture does not meet the preset architecture requirement.

In a specific example of the solution of the present disclosure, the second processing unit 702 is further configured to:

acquiring a target bare frequency difference of the two quantum bits under the condition that the target point exists in the target association relation;

based on the target association relationship, obtaining an intrinsic frequency difference at a first point; the first point is any point except the target point in the target association relation;

and obtaining the target equivalent coupling strength between the two quantum bits at the first point based on the target bare frequency difference of the two quantum bits and the intrinsic frequency difference at the first point.

In a specific example of the solution of the present disclosure, the second processing unit 702 is specifically configured to:

under the condition that a target point exists in the target association relationship, acquiring an intrinsic frequency difference at the target point based on the target association relationship;

And obtaining the target bare frequency difference of the two quantum bits based on the intrinsic frequency difference at the target point.

In a specific example of the solution of the present disclosure, the first processing unit 701 is specifically configured to:

and under the condition that the two quantum bits are in a target resonance state, determining a target association relation corresponding to a target coupler architecture in the quantum chip layout.

In a specific example of the solution of the present disclosure, the first processing unit 701 is further configured to:

determining a target equivalent inductance of the coupler that enables the coupler to be in a decoupled state from a first qubit and enables the coupler to be in a decoupled state from a second qubit;

wherein the coupler is at the target equivalent inductance, and the actual frequency of the coupler is the target frequency.

under the condition that the first qubit is positioned in the first target inductance and the second qubit is positioned in the second target inductance, performing the following simulation steps for a plurality of times to obtain the intrinsic frequency difference of the two qubits when the coupler is positioned at different actual frequencies; wherein the actual frequencies of the couplers in the different simulation steps are different;

the current simulation steps comprise:

after the intrinsic frequency difference of the two quantum bits, which is the current actual frequency of the coupler, is obtained, the actual frequency of the coupler is adjusted within a preset frequency range;

In a specific example of the solution of the present disclosure, the quantum chip layout is a quantum chip layout of a superconducting quantum chip.

Descriptions of specific functions and examples of each unit of the apparatus in the embodiments of the present disclosure may refer to related descriptions of corresponding steps in the foregoing method embodiments, which are not repeated herein.

The present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the above method of applying a quantum computing device.

The present disclosure also provides a computer program product comprising a computer program which, when executed by a processor, implements the method described above as applied to a classical computing device;

alternatively, the computer program when executed by at least one quantum processing unit implements the method as described for application to a quantum computing device.

The present disclosure also provides a quantum computing device comprising:

at least one quantum processing unit;

the instructions are executed by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method applied to the quantum computing device.

It will be appreciated that the quantum processing units (quantum processing unit, QPU), also referred to as quantum processors or quantum chips, used in the description of the present disclosure may relate to physical chips comprising a plurality of quantum bits interconnected in a particular manner.

Moreover, it is to be understood that the qubits described in the present disclosure may refer to the basic information units of a quantum computing device. Qubits are contained in QPUs and the concept of classical digital bits is generalized.

In the technical scheme of the disclosure, the acquisition, storage, application and the like of the related user personal information all conform to the regulations of related laws and regulations, and the public sequence is not violated.

According to embodiments of the present disclosure, the present disclosure also provides a computing device, a readable storage medium, and a computer program product.

FIG. 8 illustrates a schematic block diagram of an example computing device 800 that may be used to implement embodiments of the present disclosure. Computing devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Computing devices may also represent various forms of mobile apparatuses, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing apparatuses. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 8, the apparatus 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the simulation method of a quantum chip layout. For example, in some embodiments, the simulation method of the quantum chip layout may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 800 via ROM 802 and/or communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the above-described simulation method of a quantum chip layout may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the simulation method of the quantum chip layout in any other suitable way (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions, improvements, etc. that are within the principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A simulation method of a quantum chip layout comprises the following steps:

2. The method of claim 1, further comprising:

3. The method of claim 1 or 2, further comprising:

4. The method of claim 3, wherein the obtaining the target bare frequency difference of the two qubits if there is a target point in the target association comprises:

5. The method according to any one of claims 1-4, wherein determining a target association relationship corresponding to a target coupler architecture in a quantum chip layout includes:

6. The method of claim 5, further comprising:

under the condition that the two quantum bits are in a target resonance state, determining a target association relationship corresponding to a target coupler architecture in the quantum chip layout comprises the following steps:

7. The method of claim 6, wherein the determining a first target inductance and a second target inductance capable of placing the two qubits in the target resonance state comprises:

8. The method of claim 7, wherein the determining a target frequency of the coupler that enables the coupler to be in a decoupled state from the first qubit and the coupler to be in a decoupled state from the second qubit comprises:

9. The method according to any one of claims 6-8, wherein determining, in a case where the first qubit is at the first target inductance and the second qubit is at the second target inductance, a target association relationship corresponding to a target coupler architecture in the quantum chip layout includes:

the current simulation steps comprise:

10. The method of claim 9, wherein after deriving the difference in the intrinsic frequencies of the two qubits for which the coupler is at the current actual frequency, the method further comprises:

adjusting the actual frequency of the coupler within a preset frequency range;

11. The method of any of claims 1-10, wherein the quantum chip layout is a quantum chip layout of a superconducting quantum chip.

12. A quantum chip layout simulation apparatus, comprising:

13. The apparatus of claim 12, wherein the second processing unit is further configured to

14. The apparatus of claim 12 or 13, wherein the second processing unit is further configured to:

15. The apparatus of claim 14, wherein the second processing unit is specifically configured to:

16. The apparatus according to any of claims 12-15, wherein the first processing unit is specifically configured to:

17. The apparatus of claim 16, wherein the first processing unit is further configured to:

18. The apparatus of claim 17, wherein the first processing unit is specifically configured to:

19. The apparatus of claim 18, wherein the first processing unit is specifically configured to:

20. The apparatus according to any one of claims 17-19, wherein the first processing unit is specifically configured to:

the current simulation steps comprise:

21. The apparatus of claim 20, wherein the first processing unit is further configured to:

22. The apparatus of any of claims 12-21, wherein the quantum chip layout is a quantum chip layout of a superconducting quantum chip.

23. A computing device, comprising:

at least one quantum processing unit QPU;

The instructions being executable by the at least one QPU to enable the at least one QPU to perform the method of any one of claims 1 to 11;

alternatively, it includes:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-11.

24. A non-transitory computer-readable storage medium storing computer instructions which, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method of any one of claims 1-11;

alternatively, the computer instructions are for causing the computer to perform the method according to any one of claims 1-11.

25. A computer program product comprising a computer program which, when executed by at least one quantum processing unit, implements the method according to any of claims 1-11;

or the computer program, when executed by a processor, implements the method according to any of claims 1-11.