CN116743684A - PCIe switch with multiple non-transparent bridge ports and communication method thereof - Google Patents
PCIe switch with multiple non-transparent bridge ports and communication method thereof Download PDFInfo
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- CN116743684A CN116743684A CN202310708807.XA CN202310708807A CN116743684A CN 116743684 A CN116743684 A CN 116743684A CN 202310708807 A CN202310708807 A CN 202310708807A CN 116743684 A CN116743684 A CN 116743684A
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- 238000000034 method Methods 0.000 title claims description 20
- 238000012544 monitoring process Methods 0.000 claims abstract description 22
- 238000012545 processing Methods 0.000 claims description 10
- 238000013507 mapping Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/555—Error detection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/111—Switch interfaces, e.g. port details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/24—Interrupt
- G06F2213/2424—Interrupt packet, e.g. event
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- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
Abstract
The application discloses a PCIe switch with a plurality of non-transparent bridge ports, which comprises the non-transparent bridge ports and a main control module, wherein the non-transparent bridge ports are used for analyzing PCIe data packets, and interrupt states are set according to feedback of the main control module, the main control module is in communication connection with the non-transparent bridge ports, and comprises doorbell registers and/or temporary storage registers of the non-transparent bridge ports, which are used for monitoring the resource occupation states of the non-transparent bridge ports, so that the problem of conflict caused by that a plurality of root complexes access the same root complex resource at the same time is effectively avoided.
Description
Technical Field
The application relates to the technical field of computer communication, in particular to a PCIe switch with a plurality of non-transparent bridge ports and a communication method thereof.
Background
Peripheral component interconnect express (Peripheral Component Interconnect Express, abbreviated as "PCIe") is a local bus technology and interface standard. PCIe devices use a separate address space, i.e., the address space of the PCIe bus, also known as the PCIe bus domain. Three types of devices are specified in the PCIe protocol, including Root Complex ("RC"), switch, and end point ("EP"). The PCIe switch can extend PCIe interfaces and interconnect different devices with PCIe interfaces to exchange and process information. The inside of a PCIe switch contains multiple PCI-PCI bridges, which are commonly referred to as transparent bridges. Devices suspended from a transparent bridge all belong to the same PCIe bus domain, and since only one RC is specified in the tree topology of the same PCIe bus domain in the PCIe protocol, other ports in the one PCIe bus domain except for the RC are typically connected to the EP.
Based on no participation of RC, the EP in the same PCIe bus domain can adopt peer-to-peer (P2P) transmission for data transmission. While two RCs need to be connected through a PCIe Non-transparent bridge (Non-Transparent Bridging, simply "NTB"). The NTB may isolate address spaces of different PCIe bus domains to connect different RCs, where the NTB acts as a PCIe device for both PCIe bus domains connected thereto. The NTB enabled port typically includes resources such as a doorbell register (doorbell registers) for sending interrupt messages between RCs and a scratch pad register (scratch pad registers) for providing command words for exchanging small amounts of information.
PCIe switches having multiple NTB ports may connect multiple RCs that exchange information by accessing each other's doorbell registers and scratch registers. However, in a PCIe switch with multiple NTB ports, once multiple RCs access the resources of the same RC and perform a write operation, multiple write requests accessed simultaneously may overwrite each other to lose information or cause subsequent information processing errors.
Disclosure of Invention
In view of some or all of the problems in the prior art, a first aspect of the present application provides a PCIe switch having a plurality of non-transparent bridge ports, comprising:
the non-transparent bridge port is used for connecting RC and analyzing PCIe data packets so as to acquire address information carried in the data packets and setting an interrupt state according to feedback of the main control module; and
the main control module comprises a doorbell register and/or a temporary storage register of the non-transparent bridge port, and is in communication connection with the non-transparent bridge port, and is used for monitoring the resource occupation state of the non-transparent bridge port, in particular a root complex connected with the non-transparent bridge port.
Further, the non-transparent bridge port comprises a packet monitoring module, and the packet monitoring module is used for analyzing and acquiring address information carried in the PCIe data packet.
Further, the packet monitoring module includes addresses mapped by resources of other non-transparent bridge ports, wherein the resources include doorbell registers and/or temporary registers.
Further, the non-transparent bridge port comprises an interrupt handling module for setting an interrupt state according to feedback of the main control module.
A second aspect of the present application provides a communication method of a PCIe switch as described above, each root complex connected to the PCIe switch being accessible to each other, wherein the root complex connected to the PCIe switch may exchange information by performing a write operation to a doorbell register or a scratch register corresponding to another root complex connected to the PCIe switch, the write operation comprising the steps of:
the root complex sends a memory write packet, generates a write request through a non-transparent bridge port and sends the write request to the main control module; and
the main control module inquires the resource occupation condition corresponding to the target root complex according to the target address in the write request:
if the resources corresponding to the target root complex are occupied, the main control module sends an error state to the non-transparent bridge port, and writing operation is not performed; and
and if the resources corresponding to the target root complex are not occupied, writing the data in the write request into the resources corresponding to the target root complex.
Further, the write operation further includes the steps of:
upon receipt of the error condition, the non-transparent bridge port sets an interrupt condition and composes an interrupt message packet, such as a message signaled interrupt (Message Signaled Interrupt, MSI) or MSI-X, etc., to the root complex.
Further, the write operation further includes the steps of:
after receiving the interrupt message packet, the root complex sends a memory write packet to clear the interrupt flag, and waits for a specified duration before resending the memory write packet to generate a write request.
Further, the generating of the write request includes:
after receiving the memory write packet, the non-transparent bridge port analyzes a target address in the memory write packet, and sends a write request to the main control module according to the target address.
Further, the non-transparent bridge port parses the memory write packet through a packet monitoring module.
Further, the target address includes a mapping address of the resource corresponding to the target root complex at the current non-transparent bridge port.
Further, the non-transparent bridge port sets an interrupt state through an interrupt processing module and forms an interrupt message packet.
The application provides a PCIe switch with a plurality of non-transparent bridge ports and a communication method thereof, wherein a packet monitoring module is arranged at each non-transparent bridge port to analyze PCIe data packets, and then an interrupt processing module is arranged at each non-transparent bridge port, so that an interrupt state can be set when target resources are occupied, and an interrupt message packet such as MSI or MSI-X is formed to inform RC. Wherein whether the target resource is occupied is monitored by the main control module. The method and the device can effectively reduce the query packet sent for querying the state by automatically judging and feeding back the state of the target resource through hardware, simplify the flow of a software layer and improve the efficiency and the speed.
Drawings
To further clarify the above and other advantages and features of embodiments of the present application, a more particular description of embodiments of the application will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the application and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 illustrates a schematic diagram of a PCIe switch having a plurality of non-transparent bridge ports in accordance with one embodiment of the application; and
FIG. 2 illustrates a flow diagram of a write operation between root complexes of a PCIe switch having multiple non-transparent bridge ports in accordance with one embodiment of the application.
Detailed Description
In the following description, the present application is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the application. Similarly, for purposes of explanation, specific numbers and configurations are set forth in order to provide a thorough understanding of embodiments of the present application. However, the application is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiments of the present application describe the steps of the method in a specific order, however, this is merely for the purpose of illustrating the specific embodiments, and not for limiting the order of the steps. In contrast, in different embodiments of the present application, the sequence of each step may be adjusted according to the adjustment of the actual requirement.
In the present application, the modules according to the present application may be implemented using software, hardware, firmware, or a combination thereof. When implemented in software, the functions of the modules may be performed by a computer program flow, e.g., the modules may be implemented by code segments (e.g., code segments in a language such as C, C ++) stored in a storage device (e.g., hard disk, memory, etc.), which when executed by a processor, perform the corresponding functions of the modules. When a module is implemented in hardware, the functionality of the module may be implemented by providing corresponding hardware structures, such as by hardware programming of a programmable device, e.g., a Field Programmable Gate Array (FPGA), or by designing an Application Specific Integrated Circuit (ASIC) comprising a plurality of transistors, resistors, and capacitors, etc. When implemented in firmware, the functions of the module may be written in program code form in a read-only memory of the device, such as EPROM or EEPROM, and the corresponding functions of the module may be implemented when the program code is executed by a processor.
In order to solve the conflict problem existing when a plurality of Root Complexes (RC) access the resources of the same RC in a PCIe switch with a plurality of Non-transparent bridge (Non-Transparent Bridging, NTB) ports, the application provides a PCIe switch with a plurality of Non-transparent bridge ports and a communication method thereof. The PCIe switch is connected to a plurality of RCs through a plurality of NTB ports, where the address of each NTB port, for example, a doorbell register or a scratch register, is mapped into the address space (bar space) of the other NTB port. Meanwhile, a packet monitoring module is arranged on each NTB port to monitor a memory read packet (memory read packet) or a memory write packet (memory write packet) of the PCIe standard, and analyze the address in the memory read packet or the memory write packet to judge whether the address falls into the address space of the resources of other NTB ports. When the address in the memory read packet or the memory write packet is monitored to be in the range of a certain NTB port address space, the packet monitoring module sends a corresponding read-write request to the main control module and waits for a status mark. In addition, in order to simplify the flow of the software layer and improve the efficiency and the speed, the application mainly judges and feeds back the state automatically through hardware, specifically, an interrupt processing module is firstly arranged on each NTB port, and when the interrupt processing module receives the error state returned by the main control module, the interrupt processing module can set the interrupt state and inform the corresponding root complex. The main control module comprises doorbell registers or temporary storage registers of all ports, processes read-write requests of all NTB ports, monitors conflict generated by the read-write requests, and feeds back the state of each read-write request.
The embodiments of the present application will be further described with reference to the accompanying drawings.
FIG. 1 illustrates a schematic diagram of a PCIe switch having multiple non-transparent bridge ports in accordance with one embodiment of the application. As shown in fig. 1, a PCIe switch having a plurality of non-transparent bridge ports includes a main control module 101 and N non-transparent bridge ports 121 to 12N. As shown, the main control module 101 is communicatively coupled to the non-transparent bridge ports 121 through 12N. Wherein N is a natural number greater than 1.
The non-transparent bridge ports 121 through 12N are used to isolate address spaces of different PCIe bus domains to connect different RCs 001 through 00N. In the embodiment of the present application, the non-transparent bridge ports 121 to 12N can parse the PCIe standard data packet sent by the RC 001 to 00N to obtain the address information carried therein, and in addition, the non-transparent bridge ports 121 to 12N may set corresponding states and form an interrupt message packet, for example, a message packet such as a message signal interrupt (Message Signaled Interrupt, MSI) or MSI-X, and notify the root complex. As described above, in one embodiment of the present application, the Bar space of each NTB port includes mapping addresses of all other NTB port resources, so that the mapping addresses can determine the final sending destination of the PCIe standard packet according to the address information obtained by parsing. The PCIe standard data packet comprises a memory read packet (memory read packet) and a memory write packet (memory write packet).
In one embodiment of the present application, the monitoring and parsing of the PCIe standard data packet by the NTB ports are implemented by a packet monitoring module, as shown in fig. 1211 to 12N1, where each NTB port includes a packet monitoring module. And the packet monitoring module is provided with packet monitoring logic for analyzing and acquiring address information carried in the PCIe data packet. In one embodiment of the present application, the packet monitoring module may further extract data in the PCIe packet, and may further send the extracted data to the host control module together when sending the write request. In one embodiment of the application, the packet monitoring logic is implemented entirely at the hardware level. It should be understood that in other embodiments of the application, the packet monitoring module may also employ software, firmware, or a combination of hardware to achieve this functionality.
In one embodiment of the present application, the interrupt message packet is formed by interrupt processing modules, as shown in fig. 1212 to 12N2, each NTB port includes an interrupt processing module, and the interrupt processing module sets an interrupt state after receiving the error state returned by the main control module 101, and forms an interrupt message packet to be returned to the RC to report the write error state. In one embodiment of the application, the interrupt handling module is implemented entirely at the hardware level. It should be understood that in other embodiments of the application, the packet monitoring module may also employ software, firmware, or a combination of hardware to achieve this functionality.
The master control module 101 includes the resources of the NTB ports, that is, doorbell registers and/or temporary registers of each NTB port, and may monitor the resource occupation condition of the NTB ports, especially the RC connected to the NTB ports, so as to avoid the conflict problem that multiple RCs access the same resource.
The doorbell register and the temporary storage register which correspond to each other can be accessed to exchange information among the RCs connected with the PCIe switch. In general, access conflicts are easily caused when multiple RCs access resources corresponding to the same RC and perform write operations. Based on this, FIG. 2 illustrates a flow diagram of a write operation between root complexes of a PCIe switch having multiple non-transparent bridge ports according to one embodiment of the application. As shown in fig. 2, the write operation includes:
first, in step 201, a write request is generated. When the RC needs to access another RC and perform writing operation, a memory writing packet is firstly sent to an NTB port, and a writing request is generated through the NTB port and sent to a main control module. In one embodiment of the present application, after the NTB port receives a memory write packet, the packet monitoring module analyzes a target address in the memory write packet, and sends a write request to the host control module according to the target address. In one embodiment of the present application, the target address refers to a mapped address of a resource corresponding to the target RC at the current NTB port. In one embodiment of the present application, the packet monitoring module may further extract data in the PCIe packet, and may further send the extracted data to the main control module together when sending the write request;
next, at step 202, the resource occupancy is queried. After receiving a write request, the main control module determines a target RC according to a target address in the write request, acquires a resource occupation condition corresponding to the target RC, returns an error state if the resource corresponding to the target RC is occupied, indicates that writing fails, enters step 231, interrupts operation, and can perform data writing in step 204 if the resource corresponding to the target RC is unoccupied;
in step 231, the operation is interrupted. After the NTB port receives the error state returned by the main control module, setting an interrupt state, forming an interrupt message packet, returning the message packet such as message signal interrupt (Message Signaled Interrupt, MSI) or MSI-X to the RC, and reporting the writing error state; in one embodiment of the present application, the NTB port sets an interrupt status through an interrupt processing module, and forms an interrupt message packet;
next, at step 232, the interrupt clears. After receiving the interrupt message packet, the RC sends a memory write packet to clear the interrupt flag, waits for a specified duration, and then resends the interrupt packet back to step 201, and sends the memory write packet to generate a write request. In addition, if the RC has sent the memory write packet and has not received the interrupt message packet, it proves that the resource corresponding to the target RC is idle, so that the RC can continue to send a new memory write packet and continue to send new data to the target RC; and
in step 204, data is written. And when the resources corresponding to the target RC are idle, the main control module writes the data in the write request into the resources corresponding to the target RC, so that the write operation is completed. In addition, in order to better ensure the communication security, avoid that the RC regards the states such as dead halt, message receiving failure and the like as successful writing, in one embodiment of the application, an MSI or MSI-X message packet is sent to inform the RC after the data writing is successful.
And writing according to the steps until all data are sent, finishing information interaction among RCs, wherein in the process, the state of the target resource is mainly judged and fed back automatically through hardware, and compared with a mode of sending a query packet, the method has higher efficiency.
In addition, in practical applications, a situation that a plurality of RCs send write requests simultaneously may also occur, so as to solve this problem, in one embodiment of the present application, when the master control module receives a plurality of write requests simultaneously, it will process the grant rights sent by the NTB port with the highest priority according to the preset priority. In one embodiment of the present application, the preset priority refers to ordering from big to small according to ports. In yet another embodiment of the present application, the preset priority refers to ordering from small to large ports. In still another embodiment of the present application, the preset priority may be customized by the user according to the actual requirement.
While various embodiments of the present application have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the application. Thus, the breadth and scope of the present application as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A PCIe switch having a plurality of non-transparent bridge ports, comprising:
the non-transparent bridge port is configured to be connected with RC, analyze PCIe data packets and set an interrupt state according to feedback of the main control module; and
and the main control module comprises a doorbell register and/or a temporary storage register of the non-transparent bridge port, and is in communication connection with the non-transparent bridge port, and is configured to monitor the resource occupation state of the non-transparent bridge port.
2. The PCIe switch of claim 1 wherein the non-transparent bridge port comprises a packet monitoring module configured to parse and obtain address information in the PCIe data packet.
3. The PCIe switch as defined in claim 1 wherein the address space of the non-transparent bridge port comprises addresses of resource mappings of other non-transparent bridge ports, wherein the resources comprise doorbell registers and/or scratch registers.
4. The PCIe switch as defined in claim 1 wherein the non-transparent bridge port comprises an interrupt handling module configured to set an interrupt state according to feedback from the master control module.
5. The communication method of a PCIe switch according to any one of claims 1 to 4, wherein a root complex connected to the PCIe switch exchanges information by writing operation to a resource corresponding to another root complex connected to the PCIe switch, wherein the writing operation includes the steps of:
the root complex sends a memory write packet, generates a write request through a non-transparent bridge port and sends the write request to the main control module; and
the main control module inquires the resource occupation condition corresponding to the target root complex according to the target address in the write request:
if the resources corresponding to the target root complex are occupied, the main control module sends an error state to the non-transparent bridge port, and writing operation is not performed; and
and if the resources corresponding to the target root complex are not occupied, writing the data in the write request into the resources corresponding to the target root complex.
6. The communication method as claimed in claim 5, further comprising the step of:
and after the non-transparent bridge port receives the error state, setting an interrupt state, and forming an interrupt message packet and sending the interrupt message packet to the root complex.
7. The communication method as claimed in claim 6, further comprising the step of:
after receiving the interrupt message packet, the root complex sends a memory write packet to clear the interrupt flag, and waits for a specified duration before resending the memory write packet to regenerate the write request.
8. The communication method of claim 5, wherein the non-transparent bridge port parses the memory write packet through a packet monitoring module, wherein the memory write packet is a PCIe standard data packet.
9. The communication method of claim 8, wherein the target address comprises a mapped address of a resource corresponding to the target root complex at a current non-transparent bridge port.
10. The communication method of claim 6, wherein the non-transparent bridge port sets an interrupt state through an interrupt processing module and composes an interrupt message packet.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310708807.XA CN116743684A (en) | 2023-06-14 | 2023-06-14 | PCIe switch with multiple non-transparent bridge ports and communication method thereof |
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| CN202310708807.XA CN116743684A (en) | 2023-06-14 | 2023-06-14 | PCIe switch with multiple non-transparent bridge ports and communication method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743240A (en) * | 2024-02-19 | 2024-03-22 | 井芯微电子技术(天津)有限公司 | PCIe bridge device with transparent and non-transparent modes |
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- 2023-06-14 CN CN202310708807.XA patent/CN116743684A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743240A (en) * | 2024-02-19 | 2024-03-22 | 井芯微电子技术(天津)有限公司 | PCIe bridge device with transparent and non-transparent modes |
| CN117743240B (en) * | 2024-02-19 | 2024-04-19 | 井芯微电子技术(天津)有限公司 | PCIe bridge device with transparent and non-transparent modes |
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