CN116743119A - Method and circuit for adjusting top unevenness of radio frequency pulse signal - Google Patents
Method and circuit for adjusting top unevenness of radio frequency pulse signal Download PDFInfo
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- CN116743119A CN116743119A CN202310039915.2A CN202310039915A CN116743119A CN 116743119 A CN116743119 A CN 116743119A CN 202310039915 A CN202310039915 A CN 202310039915A CN 116743119 A CN116743119 A CN 116743119A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention relates to the technical field of signal processing, in particular to a method and a circuit for adjusting the top unevenness of a radio frequency pulse signal, wherein the circuit comprises the following components: the amplifier group is used for receiving the input radio frequency pulse signal and carrying out first-stage amplification on the radio frequency pulse signal to obtain an amplified signal; the radio frequency detector is connected with the amplifier group through a directional coupler and is used for outputting pulse envelope voltage of an amplified signal; the FPGA logic unit is used for outputting an adjustable voltage based on the unevenness of the front end part and the rear end part of the pulse envelope voltage; the analog switch is used for switching the fixed voltage and the adjustable voltage based on an external receiving and transmitting control signal so as to output a power supply voltage; under the action of the amplified power supply voltage, the radio frequency pulse signal is amplified by the amplifier group to obtain an output signal with a flat pulse top, and then the pulse top of the pulse signal is adjusted by adjusting the adjustable voltage, so that the pulse top is flatter, and the quality of the output radio frequency pulse signal is improved.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a method and a circuit for adjusting the top unevenness of a radio frequency pulse signal.
Background
The degree of difference of the output signal size at different time in the radio frequency pulse signal is meant, the degree of difference of the output signal size at different time in the radio frequency pulse signal is especially obvious, the radio frequency pulse signal is more apparent on a high-power amplifier, the front side of the radio frequency pulse signal is high, the back side of the radio frequency pulse signal is low, the quality of a received signal of a receiver is influenced by the fact that the degree of difference of the top of the radio frequency pulse signal is not even, and the problem that the received pulse signal cannot be completely demodulated can occur in the receiver when the degree of difference of the top of the radio frequency pulse signal is too large during long-distance communication.
In the prior art, an energy storage capacitor is adopted, the problem of output power reduction caused by voltage reduction at two ends of the capacitor when the pulse work is carried out due to insufficient energy storage capacitor is avoided, in addition, the potential difference generated at two ends of a power line in the moment of high current of pulse work is reduced by shortening the wiring length of the power line as much as possible, the two modes also reduce the pulse irregularity at the top of a radio frequency pulse signal when the low pulse work is carried out only through the early-stage optimal design, the energy storage capacitor cannot be infinitely increased according to the space requirement, the power wiring needs a certain length from the power end to the power end, and the top irregularity of the high-power radio frequency pulse signal is still obvious after the processing of the power wiring by the existing means, so that the processing effect is poor.
How to improve the processing effect of the top unevenness of the radio frequency pulse signal is a technical problem to be solved at present.
Disclosure of Invention
The present invention has been made in view of the above-mentioned problems, and has as its object to provide a method and a circuit for adjusting the top unevenness of a radio frequency pulse signal which overcome or at least partially solve the above-mentioned problems.
In a first aspect, the present invention provides a radio frequency pulse signal top unevenness adjustment circuit, comprising:
the amplifier group is used for receiving an input radio frequency pulse signal, and carrying out first-stage amplification on the radio frequency pulse signal to obtain an amplified signal, wherein the amplified signal has unevenness at the top of the radio frequency pulse signal;
the radio frequency detector is connected with the amplifier group through a directional coupler and is used for outputting pulse envelope voltage of the amplified signal;
an FPGA logic unit for outputting an adjustable voltage based on the unevenness of the front end portion and the rear end portion of the pulse envelope voltage;
the analog switch is used for switching the fixed voltage and the adjustable voltage based on an external receiving and transmitting control signal so as to output a power supply voltage;
the operational amplifier is used for amplifying the power supply voltage and providing the amplified power supply voltage for the amplifier group;
under the action of the amplified power supply voltage, the radio frequency pulse signal is amplified by the amplifier group to obtain an output signal with a flat pulse top.
Further, the amplifier group includes: a first stage amplifier and a second stage amplifier, the second stage amplifier comprising one or more amplifiers.
Further, between the radio frequency detector and the FPGA logic unit, the method further includes:
and the ADC sampling chip is used for converting the analog signal of the pulse envelope voltage into a digital signal.
Further, between the FPGA logic unit and the analog switch, further comprising:
and the DAC output module is used for converting the digital signal of the adjustable voltage into an analog signal.
Further, the FPGA logic unit is configured to:
controlling the adjustable voltage to increase when the difference between the front end part and the rear end part of the pulse envelope voltage is larger than a first threshold value;
when the difference value between the front end part and the rear end part of the pulse envelope voltage is smaller than a second threshold value, controlling the adjustable voltage to be reduced, wherein the absolute value of the first threshold value is equal to that of the second threshold value;
when the difference between the front end part and the rear end part of the pulse envelope voltage is greater than or equal to the second threshold value and less than or equal to the first threshold value, the adjustable voltage is not required to be adjusted.
Further, the first threshold and the second threshold are determined based on when the radio frequency pulse signal top irregularity meets a preset value.
Further, the analog switch comprises a first input end, a second input end, a receiving and transmitting control signal input end and a public output end;
the first input end inputs fixed voltage, and the second input end inputs adjustable voltage;
when the receiving and transmitting control signal input end receives the receiving signal, switching to a fixed voltage to enable the power supply voltage output by the public output end to be the fixed voltage;
and when the receiving and transmitting control signal input end receives the signal, switching to the adjustable voltage to enable the power supply voltage output by the common output end to be the adjustable voltage.
In a second aspect, the present invention further provides a method for adjusting top unevenness of a radio frequency pulse signal, which is applied to any one of the radio frequency pulse signal top unevenness adjusting circuits in the first aspect, and includes:
acquiring a radio frequency pulse signal to be adjusted;
amplifying the radio frequency pulse signal to obtain an amplified signal;
performing detection processing on the amplified signal to obtain a pulse envelope voltage of the amplified signal;
generating an adjustable voltage based on the irregularities of the front end portion and the back end portion of the pulse envelope voltage;
based on an external receiving and transmitting control signal, switching the fixed voltage and the adjustable voltage to output a power supply voltage;
under the action of the power supply voltage, an output signal with a flat pulse top is obtained.
Further, after outputting the power supply voltage based on the adjustable voltage, it further includes:
under the action of the power supply voltage, judging whether the top of the radio frequency pulse signal of the output signal is flat or not;
if not, the adjustable voltage is adjusted.
One or more technical solutions in the embodiments of the present invention at least have the following technical effects or advantages:
the invention provides a radio frequency pulse signal top unevenness adjusting circuit, which comprises: the amplifier group is used for receiving an input radio frequency pulse signal, and carrying out first-stage amplification on the radio frequency pulse signal to obtain an amplified signal, wherein the amplified signal has unevenness at the top of the radio frequency pulse signal; the radio frequency detector is connected with the amplifier group through a directional coupler and is used for outputting pulse envelope voltage of the amplifier; the FPGA logic unit is used for outputting an adjustable voltage based on the unevenness of the front end part and the rear end part of the pulse envelope voltage; the analog switch is used for switching the fixed voltage and the adjustable voltage based on an external receiving and transmitting control signal so as to output a power supply voltage; the operational amplifier is used for amplifying the power supply voltage and providing the amplified power supply voltage for the amplifier group; under the action of the amplified power supply voltage, the radio frequency pulse signal is amplified by the amplifier group to obtain an output signal with a flat pulse top, and then the pulse top of the pulse signal is adjusted by adjusting the adjustable voltage, so that the pulse top is flatter, and the quality of the output radio frequency pulse signal is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also throughout the drawings, like reference numerals are used to designate like parts. In the drawings:
FIG. 1 is a schematic diagram showing a structure of a circuit for adjusting the top unevenness of a RF pulse signal according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a radio frequency detector according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a pulse envelope voltage detected by a radio frequency detector in an embodiment of the invention;
fig. 4 shows a schematic circuit structure of an ADC sampling chip according to an embodiment of the invention;
FIG. 5 shows a schematic diagram of processing logic of an FPGA logic unit in an embodiment of the invention;
FIG. 6 shows a schematic diagram of a connection circuit of an analog switch and an operational amplifier in an embodiment of the invention;
FIG. 7 is a schematic diagram showing the variation of the power supply voltage output by the analog switch with the transmit-receive control signal according to the embodiment of the present invention;
FIG. 8 shows a schematic diagram of a front end portion of a pulse envelope voltage in an embodiment of the invention;
FIG. 9 shows a schematic diagram of the back end portion of a pulse envelope voltage in an embodiment of the invention;
FIG. 10 is a schematic diagram of a pulse signal after passing through a first stage amplifier in an embodiment of the present invention;
FIG. 11 is a schematic diagram of a final adjusted pulse signal in an embodiment of the present invention;
fig. 12 is a schematic flowchart showing a step flow of a method for adjusting top unevenness of a radio frequency pulse signal according to an embodiment of the invention.
Description of the embodiments
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Examples
The embodiment of the invention provides a radio frequency pulse signal top unevenness adjusting circuit, which comprises:
the amplifier group 101 is configured to receive an input radio frequency pulse signal, and perform first-stage amplification on the radio frequency pulse signal to obtain an amplified signal, where the amplified signal has pulse top unevenness;
the radio frequency detector 102 is connected with the amplifier group through a directional coupler and is used for outputting pulse envelope voltage of an amplified signal;
an FPGA logic unit 103 for outputting an adjustable voltage based on the unevenness of the front-end portion and the rear-end portion of the pulse envelope voltage;
an analog switch 104 for switching the fixed voltage and the adjustable voltage based on an external transceiving control signal to output a supply voltage;
an operational amplifier 105 for amplifying the power supply voltage and supplying the amplified power supply voltage to the amplifier group;
under the action of the amplified power supply voltage, the radio frequency pulse signal is amplified by the amplifier group to obtain an output signal with a flat pulse top.
Wherein the amplifier group 101 includes: a first stage amplifier 1011 and a second stage amplifier 1012, the second stage amplifier 1012 comprising one or more amplifiers, where the second stage amplifier 1012 is a plurality of amplifiers, the plurality of amplifiers are connected in series.
The amplifier group 101 is used to amplify the rf pulse signal, and a multistage amplifier is used because the amplification factor of the one-stage amplifier is insufficient.
The radio frequency detector 102 is connected to the amplifier group 101 through a directional coupler, and the coupled signal is input to the radio frequency detector 102, so that the radio frequency detector 102 detects the signal to obtain the pulse envelope voltage of the amplified signal.
As shown in fig. 2, the circuit structure of the radio frequency detector 102 is shown, and the input end of the radio frequency detector 102 is provided with a pi-type resistance attenuator, wherein the pi-type resistance attenuator comprises R15, R13 and R16. The specific amount of attenuation is determined by the magnitude of the amplified signal and the power of the maximum allowable input signal to the radio frequency detector 102.
The coupling degree of the directional coupler is 40dB, the coupling power is 14dBm when the output power is 54dBm, and the ADL5903 of the radio frequency detector 102 using the ideno semiconductor allows the maximum input power to be 10dBm. In the invention, an 8dB pi-shaped attenuator is adopted, wherein R15 is 120Ω, R13 is 51Ω, and R16 is 120Ω. To ensure that the power of the coupling signal of the directional coupler into the radio frequency detector 102 at nominal output does not exceed 10dBm. The radio frequency detector 102 detects the pulse envelope voltage of the amplified signal. As shown in fig. 3, a schematic diagram of the voltage of the envelope of the pulse detected by the radio frequency detector 102 is shown.
In the circuit for adjusting the unevenness of the top of the rf pulse signal, an ADC sampling chip 106 is further disposed between the rf detector 102 and the FPGA logic unit 103, and is configured to convert an analog signal of the pulse envelope voltage into a digital signal.
As shown in fig. 4, the circuit structure of the ADC sampling chip 106 is shown, the ADC sampling chip 106 is a 12-bit four-way high-speed sampler, the sampling rate reaches 4M/s, the signal can be sampled every 250ns, the ADC sampling chip 106 can sample the pulse envelope voltage, and the reflected power and the operating current can be detected in other ways, wherein the relationship between the AD value collected by the ADC sampling chip 106 and the actual voltage is as follows:
V÷Vref×4096=AD
where V is the actual voltage, vref is 2.5V of the internal reference voltage of the ADC sampling chip 106, and thus 1mV corresponds to 1.64 AD values, and then the output voltage of the rf detector 102 with 0.1dB power fluctuation is 3.77mV, and correspondingly, in order to adjust the pulse unevenness, the AD value fluctuation of the front end portion and the back end portion of the pulse envelope voltage needs to be controlled within ±6.
Where the power fluctuation of the radio frequency detector 102 is 0.1dB, the corresponding voltage fluctuation is determined based on the slope 37.7 of the pulse envelope voltage as shown in fig. 3, i.e., the output voltage varies by 37.7mV when the power increases by 1dB, then the voltage fluctuation is 3.77mV when the pulse top irregularity of the pulse envelope voltage is within 0.1dB.
The ADC sampling chip 106 transmits the collected pulse envelope voltage to the FPGA logic unit 103, and the FPGA logic unit 103 is specifically configured to:
when the difference value between the front end part and the rear end part of the pulse envelope voltage is larger than a first threshold value, controlling the adjustable voltage to increase; thereby outputting an increased adjustable voltage.
When the difference between the front end portion and the rear end portion of the pulse envelope voltage is smaller than the second threshold value, the adjustable voltage is controlled to decrease, thereby outputting a decreased adjustable voltage. The absolute value of the first threshold is equal to the absolute value of the second threshold.
When the difference between the front end portion and the rear end portion of the pulse envelope voltage is greater than or equal to the second threshold value and less than or equal to the first threshold value, the adjustable voltage is not required to be adjusted.
Wherein the first and second thresholds are determined based on when the pulse top irregularity meets a preset value. According to the above description, the preset value is 0.1dB, and the first threshold is 6 AD values, and the second threshold is-6 AD values.
As shown in fig. 5, after the digital signal of the pulse envelope voltage obtained by sampling the ADC sampling chip 106 in S501, S502 is executed, the FPGA logic unit 103 processes the digital signal of the pulse envelope voltage, specifically, S503, it is determined whether the difference of the front end portion minus the rear end portion of the pulse envelope voltage is greater than 6 AD values, if yes, S504 is executed, the output adjustable voltage is increased, and then sampling is continued through the AD sampling chip 106; if not, executing S605, judging whether the difference value of the front end part minus the rear end part of the pulse envelope voltage is smaller than-6 AD values, if so, executing S506, reducing the output adjustable voltage, and then continuing to sample through the AD sampling chip 106; if the difference of the front end part minus the back end part of the pulse envelope voltage is greater than or equal to-6 AD values and less than or equal to 6 AD values, S507 is executed to directly output the adjustable voltage without adjustment.
For the data collected by the ADC sampling chip 106, the rising edge of the collected rf pulse signal is avoided being used for calculation, and the data in 5us before the external transceiving control signal becomes low level is also avoided being used for calculation, for the data in 5us after the external transceiving control signal becomes high level.
The first 10 data after the data discarded by the first 5us are subjected to average processing to obtain a front end part of the pulse envelope voltage, and the first 10 data after the data discarded by the second 5us are subjected to average processing to obtain a rear end part of the pulse envelope voltage.
The step of adjusting the adjustable voltage is 30mv, and after each time of adjusting the adjustable voltage, the ADC sampling is continued until the difference between the front end part and the rear end part of the collected pulse envelope voltage is greater than or equal to a second threshold (-6 AD values) and less than or equal to a first threshold (6 AD values). At this point, the pulse top irregularity indicating the pulse envelope voltage reaches the requirement of 0.1dB fluctuation. The adjustable voltage output by the FPGA logic 103 is balanced.
Also included between FPGA logic unit 103 and analog switch 104 is: the DAC output module 107 is configured to convert the digital signal of the adjustable voltage into an analog signal.
When the adjustable voltage output by the FPGA logic unit 103 reaches equilibrium, the output voltage of the DAC output module 107 is 2.33V.
Next, the voltage output from the DAC output module 107 is input to an analog switch 104, and the analog switch 104 is used for switching between a fixed voltage and an adjustable voltage based on an external transmit-receive control signal to output a supply voltage, and then the supply voltage is input to an operational amplifier 105, and the operational amplifier 105 amplifies the supply voltage and supplies the amplified supply voltage to the amplifier group 101.
The analog switch 104 includes a first input terminal, a second input terminal, a transmit-receive control signal input terminal, and a common output terminal; the first input end inputs fixed voltage, the second input end inputs adjustable voltage, and when the receiving and transmitting control signal input end receives the receiving signal, the first input end is switched to the fixed voltage, so that the power supply voltage output by the public output end is the fixed voltage; when the receiving and transmitting control signal input end receives the signal, the voltage is switched to the adjustable voltage, so that the power supply voltage output by the common output end is the adjustable voltage.
The connection circuit between the analog switch 104 and the operational amplifier 105 is shown in fig. 6. Wherein U1 is an analog switch 104, which can switch two different voltages. Pin7 of the analog switch 104 obtains a fixed voltage 1.744V by voltage division, and since the FPGA logic unit 103 controls the DAC output module 107 to also output a voltage of 1.744V to pin2 of the analog switch 104. When pin6 of the analog switch 104 switches the transmission/reception control signal, the voltage input by pin7 and pin2 of the analog switch 104 is 1.744V, and therefore the voltage output by the common output terminal pin1 of the analog switch 104 is 1.744V.
The voltage of 1.744V output by the output terminal pin1 of the analog switch 104 is twice as high-speed operational amplification by the operational amplifier 105 (U2) and then output to the amplifier group 101 through pin6 of U2 for power supply, wherein the amplification factor of the operational amplifier 105 is obtained from the values of R4 and R5. The specific input-output voltage relationship is:
Vout=（R4+R5）/R5*Vin
the change of the power supply voltage outputted from the analog switch 104 according to the transmission/reception control signal is shown in fig. 7.
The pulse top irregularities acquired before no adjustment of the adjustable voltage are shown in fig. 8 and 9, where the front end part of the pulse envelope voltage is shown in fig. 8 and the back end part of the pulse envelope voltage is shown in fig. 9.
By converting the formulas dBw =10 log (P/1W) and 10log1 w=10 log1000 mw=30 dBm, the highest pulse power is 54.45dBm converted to 278.6W and the lowest pulse power is 53.95dBm converted to 248.3W.
（278.6W-248.3W）/248.3W*100%=12.2%
This resulted in a pulse top irregularity of up to 12.2% before no adjustment was made to the pulse top irregularity. And after the pulse top irregularity was adjusted, the pulse top irregularity reached 0.1dB.
Finally, under the action of the power supply voltage amplified by the operational amplifier 105, the radio frequency pulse signal is amplified by the amplifier group 101 to obtain an output signal with a flat pulse top.
The power supply voltage output by the analog switch 104 is amplified by one time by the operational amplifier 105 and then supplied to the first-stage amplifier of the amplifier group 101, and the output power of the first-stage amplifier is only 14dBm, so that the second-stage amplifier is required to output rated power for amplification. The pulse signal after passing through the first stage amplifier is shown in fig. 10. The final adjusted pulse signal is shown in fig. 11.
One or more technical solutions in the embodiments of the present invention at least have the following technical effects or advantages:
the invention provides a radio frequency pulse signal top unevenness adjusting circuit, which comprises: the amplifier group is used for receiving an input radio frequency pulse signal, and carrying out first-stage amplification on the radio frequency pulse signal to obtain an amplified signal, wherein the amplified signal has pulse top unevenness; the radio frequency detector is connected with the amplifier group through a directional coupler and is used for outputting pulse envelope voltage of the amplifier; the FPGA logic unit is used for outputting an adjustable voltage based on the unevenness of the front end part and the rear end part of the pulse envelope voltage; the analog switch is used for switching the fixed voltage and the adjustable voltage based on an external receiving and transmitting control signal so as to output a power supply voltage; the operational amplifier is used for amplifying the power supply voltage and providing the amplified power supply voltage for the amplifier group; under the action of the amplified power supply voltage, the radio frequency pulse signal is amplified by the amplifier group to obtain an output signal with a flat pulse top, and then the pulse top of the radio frequency pulse signal is adjusted by adjusting the adjustable voltage, so that the pulse top is flatter, and the quality of the output radio frequency pulse signal is improved.
Examples
Based on the same inventive concept, the embodiment of the present invention further provides a method for adjusting the top unevenness of a radio frequency pulse signal, which is applied to the circuit for adjusting the top unevenness of a radio frequency pulse signal according to any one of the first embodiment, as shown in fig. 12, and includes:
s1201, acquiring a radio frequency pulse signal to be adjusted;
s1202, amplifying the radio frequency pulse signal to obtain an amplified signal;
s1203, performing detection processing on the amplified signal to obtain a pulse envelope voltage of the amplified signal;
s1204 generating an adjustable voltage based on the unevenness of the front end portion and the back end portion of the pulse envelope voltage;
s1205, switching the fixed voltage and the adjustable voltage based on an external receiving and transmitting control signal so as to output a power supply voltage;
s1206, under the action of the power supply voltage, obtaining an output signal with a flat pulse top.
In an alternative embodiment, after S1205, the method further includes: under the action of the power supply voltage, judging whether the pulse top of the output signal is flat, and if not, continuously adjusting the adjustable voltage.
And finally obtaining the output signal with flat pulse top by continuously adjusting the adjustable voltage.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. A radio frequency pulse signal top irregularity adjustment circuit, comprising:
the amplifier group is used for receiving an input radio frequency pulse signal, and carrying out first-stage amplification on the radio frequency pulse signal to obtain an amplified signal, wherein the amplified signal has pulse top unevenness;
the radio frequency detector is connected with the amplifier group through a directional coupler and is used for outputting pulse envelope voltage of the amplified signal;
an FPGA logic unit for outputting an adjustable voltage based on the unevenness of the front end portion and the rear end portion of the pulse envelope voltage;
the analog switch is used for switching the fixed voltage and the adjustable voltage based on an external receiving and transmitting control signal so as to output a power supply voltage;
the operational amplifier is used for amplifying the power supply voltage and providing the amplified power supply voltage for the amplifier group;
under the action of the amplified power supply voltage, the radio frequency pulse signal is amplified by the amplifier group to obtain an output signal with a flat pulse top.
2. The rf pulse signal top unevenness adjustment circuit of claim 1, wherein the amplifier bank comprises: a first stage amplifier and a second stage amplifier, the second stage amplifier comprising one or more amplifiers.
3. The radio frequency pulse signal top unevenness adjustment circuit of claim 1, further comprising, between the radio frequency detector and the FPGA logic unit:
and the ADC sampling chip is used for converting the analog signal of the pulse envelope voltage into a digital signal.
4. The radio frequency pulse signal top unevenness adjustment circuit of claim 1, further comprising, between the FPGA logic unit and the analog switch:
and the DAC output module is used for converting the digital signal of the adjustable voltage into an analog signal.
5. The rf pulse signal top unevenness adjustment circuit of claim 1, wherein the FPGA logic unit is configured to:
controlling the adjustable voltage to increase when the difference between the front end part and the rear end part of the pulse envelope voltage is larger than a first threshold value;
when the difference value between the front end part and the rear end part of the pulse envelope voltage is smaller than a second threshold value, controlling the adjustable voltage to be reduced, wherein the absolute value of the first threshold value is equal to that of the second threshold value;
when the difference between the front end part and the rear end part of the pulse envelope voltage is greater than or equal to the second threshold value and less than or equal to the first threshold value, the adjustable voltage is not required to be adjusted.
6. The rf pulse signal top irregularity adjustment circuit of claim 5, wherein the first threshold and the second threshold are determined based on when the rf pulse signal top irregularity meets a preset value.
7. The rf pulse signal top unevenness adjustment circuit of claim 1, wherein the analog switch comprises a first input, a second input, a transmit-receive control signal input, and a common output;
the first input end inputs fixed voltage, and the second input end inputs adjustable voltage;
when the receiving and transmitting control signal input end receives the receiving signal, switching to a fixed voltage to enable the power supply voltage output by the public output end to be the fixed voltage;
and when the receiving and transmitting control signal input end receives the signal, switching to the adjustable voltage to enable the power supply voltage output by the common output end to be the adjustable voltage.
8. The method for adjusting the top unevenness of the radio frequency pulse signal is applied to the circuit for adjusting the top unevenness of the radio frequency pulse signal according to any one of claims 1 to 7, and is characterized by comprising the following steps:
acquiring a radio frequency pulse signal to be adjusted;
amplifying the radio frequency pulse signal to obtain an amplified signal;
performing detection processing on the amplified signal to obtain a pulse envelope voltage of the amplified signal;
generating an adjustable voltage based on the irregularities of the front end portion and the back end portion of the pulse envelope voltage;
based on an external receiving and transmitting control signal, switching the fixed voltage and the adjustable voltage to output a power supply voltage;
under the action of the power supply voltage, an output signal with a flat pulse top is obtained.
9. The method of claim 8, further comprising, after outputting a supply voltage based on the adjustable voltage:
under the action of the power supply voltage, judging whether the top of the radio frequency pulse signal of the output signal is flat or not;
if not, the adjustable voltage is adjusted.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310039915.2A CN116743119A (en) | 2023-01-12 | 2023-01-12 | Method and circuit for adjusting top unevenness of radio frequency pulse signal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310039915.2A CN116743119A (en) | 2023-01-12 | 2023-01-12 | Method and circuit for adjusting top unevenness of radio frequency pulse signal |
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| CN116743119A true CN116743119A (en) | 2023-09-12 |
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| CN202310039915.2A Pending CN116743119A (en) | 2023-01-12 | 2023-01-12 | Method and circuit for adjusting top unevenness of radio frequency pulse signal |
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| CN (1) | CN116743119A (en) |
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2023
- 2023-01-12 CN CN202310039915.2A patent/CN116743119A/en active Pending
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