CN116741802A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

Info

Publication number
CN116741802A
CN116741802A CN202310542611.8A CN202310542611A CN116741802A CN 116741802 A CN116741802 A CN 116741802A CN 202310542611 A CN202310542611 A CN 202310542611A CN 116741802 A CN116741802 A CN 116741802A
Authority
CN
China
Prior art keywords
source
layer
drain
insulating layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310542611.8A
Other languages
Chinese (zh)
Inventor
陈定业
李威养
林家彬
王志庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/864,104 external-priority patent/US20230378300A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116741802A publication Critical patent/CN116741802A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

In a method of manufacturing a semiconductor device, a fin structure is formed in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate, source/drain regions of the fin structure are etched to form source/drain spacers, an end portion of the first semiconductor layer in the source/drain spacers is laterally etched, a first insulating layer is formed on sidewalls of the source/drain spacers, the first insulating layer is partially etched to form a first bottom spacer at a bottom of the source/drain spacers, a second insulating layer is formed on sidewalls of the source/drain spacers, the second insulating layer is partially etched to form an inner spacer on an end face of the first semiconductor layer, and the second insulating layer remains as a second bottom spacer at a bottom of the source/drain spacers, and a source/drain epitaxial layer is formed in the source/drain spacers. The embodiment of the invention also provides a semiconductor device.

Description

Method for manufacturing semiconductor device and semiconductor device
Technical Field
Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor device.
Background
As the semiconductor industry moves toward nanotechnology process nodes for higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate Field Effect Transistors (FETs), including fin FETs (finfets) that use fin structures as channel regions and full-gate-all-around (GAA) FETs that use multiple nanoplatelets or nanowires as channel regions.
Disclosure of Invention
Some embodiments of the present invention provide a method of manufacturing a semiconductor device, the method comprising: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate; forming a sacrificial gate structure over the fin structure; etching source/drain regions of the fin structure not covered by the sacrificial gate structure, thereby forming source/drain spacers; laterally etching an end portion of the first semiconductor layer in the source/drain interval; forming a first insulating layer on sidewalls of the source/drain spacers; partially etching the first insulating layer, thereby forming a first bottom spacer at the bottom of the source/drain spacer; forming a second insulating layer on sidewalls of the source/drain spacers; partially etching the second insulating layer to form an internal spacer on an end face of the first semiconductor layer, and leaving a portion of the second insulating layer at a bottom of the source/drain spacer as a second bottom spacer; and forming a source/drain epitaxial layer in the source/drain spacers.
Further embodiments of the present invention provide a method of manufacturing a semiconductor device, the method comprising: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate; forming a sacrificial gate structure over the fin structure; etching source/drain regions of the fin structure disposed between the sacrificial gate structures to form source/drain spacers; laterally etching an end portion of the first semiconductor layer in the source/drain interval; forming a first insulating layer on sidewalls of the source/drain spacers; partially etching the first insulating layer to form a first internal spacer on an end face of the first semiconductor layer, and leaving a portion of the first insulating layer at a bottom of the source/drain spacer as a first bottom spacer; forming a second insulating layer on sidewalls of the source/drain spacers; partially etching the second insulating layer to form second inner spacers on the first inner spacers, respectively, and leaving portions of the second insulating layer at bottoms of the source/drain spacers as second bottom spacers; and forming a source/drain epitaxial layer in the source/drain spacers.
Still further embodiments of the present invention provide a semiconductor device including: a semiconductor fin or line disposed over and vertically disposed over a bottom fin structure disposed over a substrate; a gate structure disposed over the semiconductor wafer or line; a source/drain epitaxial layer disposed over the semiconductor die or line on opposite sides of the gate structure; and a first bottom spacer and a second bottom spacer disposed between the bottom fin structure and the source/drain epitaxial layer, wherein the second bottom spacer is disposed between the first bottom spacer and the source/drain epitaxial layer, and the second bottom spacer is made of a different insulating material than the first bottom spacer.
Drawings
The invention is best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 illustrates one of the stages of a sequential fabrication process of a semiconductor GAA FET device in accordance with an embodiment of the invention.
Fig. 2 illustrates one of the stages of a sequential fabrication process of a semiconductor GAA FET device in accordance with an embodiment of the invention.
Fig. 3A and 3B illustrate one of the stages of a sequential fabrication process of a semiconductor GAA FET device in accordance with an embodiment of the invention.
Fig. 4A, 4B and 4C illustrate one of the stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 5A, 5B and 5C illustrate one of the stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 6A, 6B and 6C illustrate one of the stages of a sequential fabrication process of a semiconductor GAA FET device in accordance with an embodiment of the invention.
Fig. 7A, 7B and 7C illustrate one of the stages of a sequential fabrication process of a semiconductor GAA FET device in accordance with an embodiment of the invention.
Fig. 8A, 8B and 8C illustrate one of the stages of a sequential fabrication process of a semiconductor GAA FET device in accordance with an embodiment of the invention.
Fig. 9A, 9B, and 9C illustrate one of the stages of a sequential fabrication process of a semiconductor GAA FET device in accordance with an embodiment of the invention.
Fig. 10A, 10B and 10C illustrate one of the stages of the sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 11A, 11B and 11C illustrate one of the stages of the sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 12A, 12B, 13, 14, 15A and 15B illustrate views of various stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 16A and 16B illustrate views of various stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 17A and 17B illustrate views of various stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 18A and 18B illustrate views of various stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 19A and 19B illustrate views of various stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 20A and 20B illustrate views of various stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Fig. 21A, 21B, 21C, 21D, and 21E illustrate views of various stages of a sequential fabrication process of a semiconductor GAA FET device according to an embodiment of the invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, of the different components used to implement the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired properties of the device. Further, in the following description, forming the first member over or on the second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also include an embodiment in which additional members interposed between the first member and the second member may be formed so that the first member and the second member may not be in direct contact. The various components may be arbitrarily drawn for simplicity and clarity.
Further, spatially relative terms such as "under …," "under …," "lower," "over …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, the term "made of" may mean "comprising" or "consisting of. In the present invention, unless otherwise indicated, the phrase "one of A, B and C" refers to "A, B and/or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and not to one element from a, one element from B, and one element from C. In the present invention, a source and a drain are used interchangeably, and the source and the drain may be referred to as a source/drain. The source/drain regions may be referred to as sources or drains, individually or collectively depending on the context.
Suppressing the leakage current (off-current) of semiconductor FET devices is one of the key issues of advanced semiconductor devices. In the present invention, a semiconductor device including a GAA FET with advanced isolation structures under source/drain epitaxial layers and a method of fabricating the same are described.
Fig. 1-15B illustrate various stages of a sequential fabrication operation of a semiconductor FET device. It will be appreciated that for additional embodiments of the method, additional operations may be provided before, during, and after the process shown in fig. 1-15B, and that some of the operations described below may be replaced or eliminated. The order of operations/processes may be interchanged.
As shown in fig. 1, the first semiconductor layers 20 and the second semiconductor layers 25 are alternately formed over the substrate 10. In some embodiments, the substrate 10 includes a single crystalline semiconductor layer on at least a surface portion thereof. The substrate 10 may comprise single crystal semiconductor materials such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP. In certain embodiments, the substrate 10 is made of crystalline Si.
The substrate 10 may include one or more buffer layers (not shown) in its surface area. The buffer layer may function to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material such as, but not limited to Si, ge, geSn, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, gaN, gaP and InP. In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layer may be increased from 30 atomic% germanium for the bottom-most buffer layer to 70 atomic% germanium for the top-most buffer layer.
The first semiconductor layer 20 and the second semiconductor layer 25 are made of materials having different lattice constants, and may include one or more layers of Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb or InP.
In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are made of Si, si compound, siGe, ge, or Ge compound. In some embodiments, the first semiconductor layer 20 is Si 1-x Ge x Wherein x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the second semiconductor layer 25 is Si or Si 1-y Ge y Wherein y is less than x and equal to or less than about 0.2. In this disclosure, "M" compound "or" M-based compound "means that the host of the compound is M.
In other embodiments, the second semiconductor layer 25 is Si 1-x Ge x Wherein x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the first semiconductor layer 20 is Si or Si 1-y Ge y Wherein y is less than x and equal to or less than about 0.2.
A first semiconductor layer 20 and a second semiconductor layer 25 are epitaxially formed over the substrate 10. The thickness of the first semiconductor layer 20 may be equal to or greater than the thickness of the second semiconductor layer 25, and in some embodiments, the thickness of the first semiconductor layer 20 is in the range of about 5nm to about 60nm, and in other embodiments, the thickness of the first semiconductor layer 20 is in the range of about 10nm to about 30 nm. In some embodiments, the thickness of the second semiconductor layer 25 is in the range of about 5nm to about 60nm, and in other embodiments, the thickness of the second semiconductor layer 25 is in the range of about 10nm to about 30 nm. The thickness of the first semiconductor layer 20 may be the same as or different from the thickness of the second semiconductor layer 25. Although four first semiconductor layers 20 and four second semiconductor layers 25 are shown in fig. 1, the number is not limited to four, and may be 1, 2, 3, or 4 or more, and less than 20. In some embodiments, the number of first semiconductor layers 20 is one more than the number of second semiconductor layers 25 (i.e., the top layer is the first semiconductor layer 20).
After forming the stacked semiconductor layers, fin structures 29 are formed using one or more photolithography and etching operations, as shown in fig. 2. The fin structure may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithographic processes including a double patterning process or a multiple patterning process. Typically, double patterning or multiple patterning processes combine lithography and self-aligned processes, allowing creation of patterns with, for example, smaller pitches than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fin structure.
As shown in fig. 2, fin structures 29 extend in the X-direction and are arranged in the Y-direction. The number of fin structures is not limited to two as shown in fig. 2, and may be as few as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of fin structure 29 to improve pattern fidelity in patterning operations. As shown in fig. 2, the fin structure 29 has an upper portion composed of stacked first and second semiconductor layers 20, 25 located above the base portion 11 of the fin structure 29 (bottom fin structure).
In some embodiments, the width of the upper portion of fin structure 29 along the Y-direction is in the range of about 8nm to about 100nm, and in other embodiments, in the range of about 15nm to about 30 nm.
After forming fin structure 29, a layer of insulating material comprising one or more layers of insulating material is formed over the substrate such that the fin structure is fully embedded in the insulating layer. The insulating material for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), siOCN, siCN, fluorine doped silicate glass (FSG), or a low-k dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma Enhanced CVD (PECVD), or flowable CVD. An annealing operation may be performed after the insulating layer is formed. Then, a planarization operation (e.g., a Chemical Mechanical Polishing (CMP) method and/or an etch-back method) is performed so that the upper surface of the uppermost second semiconductor layer 25 is exposed from the insulating material layer. In some embodiments, one or more fin liner layers are formed over the fin structure prior to forming the insulating material layer. In some embodiments, the fin liner layer includes a first fin liner layer formed over the substrate 10 and the sidewalls of the base portion 11 of the fin structure 29 and a second fin liner layer formed on the first fin liner layer. The fin liner layer is made of silicon nitride or a silicon nitride-based material (e.g., siON, siCN, or SiOCN). The fin liner layer may be deposited by one or more processes, such as Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD), although any acceptable process may be utilized.
Then, as shown in fig. 2, the insulating material layer is recessed to form the isolation insulating layer 15, thereby exposing an upper portion of the fin structure 29. By this operation, the fin structures 29 are separated from each other by the isolation insulating layer 15, also referred to as Shallow Trench Isolation (STI) of the isolation insulating layer 15. The isolation insulating layer 15 may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectrics (e.g., carbon doped oxides), very low-k dielectrics (e.g., porous carbon doped silicon dioxide), polymers (e.g., polyimide), combinations of these, and the like. In some embodiments, the isolation insulating layer 15 is formed by a process such as CVD, flowable CVD (FCVD), or spin-on-glass process, however any acceptable process may be utilized.
In some embodiments, isolation insulating layer 15 is recessed until an upper portion of fin structure 29 located above base portion 11 is exposed. In other embodiments, an upper portion of fin structure 29 is not exposed. The first semiconductor layer 20 is a sacrificial layer which is then partially removed, and the second semiconductor layer 25 is then formed as a semiconductor line which is a channel region of the GAA FET. In other embodiments, the second semiconductor layer 25 is a sacrificial layer that is then partially removed, and the first semiconductor layer 20 is then formed as a semiconductor line that is a channel region.
After forming the isolation insulating layer 15, a sacrificial (dummy) gate structure 40 is formed, as shown in fig. 3A and 3B. Fig. 3A and 3B illustrate the structure after forming a sacrificial gate structure 40 over exposed fin structure 29. A sacrificial gate structure 40 is formed over a portion of the fin structure that will become the channel region. The sacrificial gate structure 40 defines the channel region (channel length) of the GAAFET. The sacrificial gate structure 40 includes a sacrificial gate dielectric layer 41 and a sacrificial gate electrode layer 42. Sacrificial gate dielectric layer 41 comprises one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 41 is in the range of about 1nm to about 5 nm.
Sacrificial gate structure 40 is formed by first blanket depositing a sacrificial gate dielectric layer 41 over the fin structure. A sacrificial gate electrode layer 42 is then blanket deposited over the sacrificial gate dielectric layer and over the fin structure such that the fin structure is fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer comprises silicon, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD, or other suitable process, including LPCVD and PECVD. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. The mask layer includes a pad silicon nitride layer 43 and a silicon oxide mask layer 44.
Next, a patterning operation is performed, and the mask layer and the sacrificial gate electrode layer are patterned into a sacrificial gate structure 40, as shown in fig. 3A and 3B. The sacrificial gate structure includes a sacrificial gate dielectric layer 41, a sacrificial gate electrode layer 42 (e.g., polysilicon), a pad silicon nitride layer 43, and a silicon oxide mask layer 44. By patterning the sacrificial gate structure, the stacked layers of the first and second semiconductor layers 20 and 25 are partially exposed on opposite sides of the sacrificial gate structure, thereby defining source/drain regions, as shown in fig. 3A. In fig. 3A and 3B, one sacrificial gate structure is formed over two fin structures, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X-direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.
Further, a first capping layer 45 for the gate sidewall spacers is formed over the sacrificial gate structure 40, as shown in fig. 3A and 3B. The capping layer 45 is conformally deposited such that it has a substantially equal thickness on the vertical surfaces (e.g., sidewalls), horizontal surfaces, and top of the sacrificial gate structure, respectively. In some embodiments, the first cover layer 45 includes a first layer 45A and a second layer 45B formed over the first layer 45A and made of a different material than the first layer 45A. In some embodiments, each of the first layer and the second layer has a thickness in a range of about 2nm to about 20 nm. In some embodiments, second layer 45B is thinner than first layer 45A. The first and second layers comprise one or more of silicon oxide, silicon nitride, siON, siCN, siOC, siOCN, or any other suitable dielectric material. The capping layer 45 (sidewall spacer) may be formed by ALD or CVD or any other suitable method.
In fig. 4A to 4C to 10A to 10C, "a" illustrates a perspective view, "B" illustrates a cross-sectional view along the Y direction, and "C" illustrates a cross-sectional view along the X direction between two sacrificial gate structures.
After the first cover layer 45 is formed, fig. 4A to 4C show structures corresponding to fig. 3A and 3B. The first capping layer 45 is then anisotropically etched to remove the horizontal portions of the first capping layer 45 disposed on top of the source/drain regions and the sacrificial gate structure while leaving the first capping layer 45 on the sides of the sacrificial gate structure 40 and the fin structure 29 as sidewall spacers 45.
Then, as shown in fig. 5A to 5C, the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25 is etched down at the source/drain region (e.g., between two sacrificial gate structures) by using one or more photolithography and etching operations, thereby forming recessed source/drain spacers 21. In some embodiments, the substrate 10 (or the base portion 11 of the fin structure) is also partially etched. In some embodiments, the n-type FET and the p-type FET are fabricated separately, and in this case, the regions for one type of FET are processed while the regions for the other type of FET are covered by a protective layer (e.g., a silicon nitride layer). In some embodiments, as shown in fig. 5A-5C, recessed space 21 has a U-shape. In other embodiments, recessed space 21 has a V-shape showing the (111) facets of the silicon crystal. In other embodiments, the recessed space 21 has an inverted trapezoidal shape or a rectangular shape.
In some embodiments, the recessed source/drain spacers 21 are formed by a dry etching process, which may be anisotropic. Including BF can be used 2 、Cl 2 、CH 3 F、CH 4 、HBr、O 2 A process gas mixture of Ar or other etchant gases to perform an anisotropic etching process. The plasma is a remote plasma generated in a separate plasma generation chamber connected to the process chamber. The process gas may be activated into the plasma by any suitable method of generating a plasma, such as a Transformer Coupled Plasma (TCP) system, an Inductively Coupled Plasma (ICP) system, and magnetically enhanced reactive ion technology. The process gas used in the plasma etching process includes an etchant gas, such as H 2 Ar, other gases or combinations of gases. In some embodiments, a plasma etching process using hydrogen (H) radicals is used, such as N 2 Carrier gas of Ar, he or Xe. By combining H 2 The gas flows into the plasma generation chamber and ignites the plasma within the plasma generation chamber to form H radicals. In some embodiments, an additional gas, such as Ar, may be ignited into a plasma within the plasma generation chamber. The H radicals can selectively etch the (100) plane lying either above the (111) plane or above the (110) plane. In some cases, the etch rate of the (100) plane may be about three times the etch rate of the (111) plane. Due to this selectivity, in the etching process During the process, etching by H radicals may tend to slow down or stop along the (111) plane or the (110) plane of silicon.
In some embodiments, the isolation insulating layer 15 is also recessed, as shown in fig. 5A and 5B. In some embodiments, the amount of recess is in the range of about 5nm to about 40nm, depending on design and/or process requirements. In some embodiments, the bottom of the source/drain spacers 21 is located below the uppermost surface of the isolation insulating layer 15.
In some embodiments, sidewall spacers 45 (which may be referred to as fin spacers) formed on the sides of the source/drain regions of the fin structure are also recessed (etched) during the recess etch of the source/drain regions. In some embodiments, the top surface of the recessed fin spacer is substantially flush with or above the bottom surface of the bottommost first semiconductor layer of the first semiconductor layer 20 and below the top surface of the bottommost second semiconductor layer of the second semiconductor layer 25. In some embodiments, a difference in height between a top surface of the recessed fin spacer 45 and a bottom surface of the bottommost first semiconductor layer of the first semiconductor layer 20 is less than about 10nm.
Further, as shown in fig. 6A to 6C, the first semiconductor layer 20 is etched laterally in the X direction within the source/drain spacers 21, thereby forming cavities, recesses or lateral grooves 22. When the first semiconductor layer 20 is SiGe and the second semiconductor layer 25 is Si, a wet etchant (e.g., without limitation, H 2 O 2 、CH 3 Mixed solution of COOH and HF) to selectively etch the first semiconductor layer 20, then through H 2 And (3) cleaning. In some embodiments, the etching by the mixed solution and the cleaning by the water are repeated 10 to 20 times. In some embodiments, the etching time of the mixed solution is in the range of about 1 minute to about 2 minutes. In some embodiments, the mixed solution is used at a temperature in the range of about 60 ℃ to about 90 ℃. In some embodiments, other etchants are used.
In some embodiments, the lateral recess of the first semiconductor layer 20 is in the range of about 4nm to about 9 nm. In some embodiments, the end portions of the second semiconductor layer 25 are also slightly etched by an amount of about 5nm or less. During the lateral etching of the first semiconductor layer 20, the isolation insulating layer 15 is also slightly recessed or etched. In some embodiments, the recess of the isolation insulating layer 15 is less than about 3nm. In some embodiments, the portion of isolation insulating layer 15 that is vertically below fin spacers 45 is also partially recessed. In some embodiments, the portion of the isolation insulating layer 15 formed on the sidewalls of the bottom fin structure 11 is narrower than the fin spacers 45.
Next, as shown in fig. 7A to 7C, the first insulating layer 30 is conformally formed in the source/drain interval 21. The first insulating layer 30 is formed on the etched lateral end portions (e.g., cavities) of the first semiconductor layer 20 and on the end faces of the second semiconductor layer 25 in the source/drain spacers 21, and over the sacrificial gate structure 40. The first insulating layer 30 comprises one of silicon nitride and silicon oxide, siON, siOC, siCN and SiOCN, or any other suitable dielectric material. The first insulating layer 30 is made of a material different from that of the sidewall spacer 45 (first cover layer). In certain embodiments, the first insulating layer 30 is made of SiOCN. In some embodiments, the first insulating layer 30 includes SiOCN formed by a topography selective process. In some embodiments, the material formed by the topography selective method has a harder bottom portion and a softer sidewall portion, thereby making removal of the sidewall portion easier than the bottom portion. In some embodiments, the first insulating layer 30 is formed by performing a process at a plasma power (e.g., input RF power) of about 20W to about 100W and a pressure of about 10 torr to about 20 torr. The plasma power for forming the sidewall portion is smaller than that for forming the bottom portion of the first insulating layer 30. In some embodiments, the high power produces a harder material, while the low power produces a softer or porous material. In some embodiments, one or more conditions (e.g., plasma power) are changed (e.g., from high power to low power) during the film deposition process. In some embodiments, a first insulating layer is deposited under high power conditions to form a portion on the bottom of the source/drain spacer, and then changed to low power conditions to form a portion on the source/drain Portions on the inter-pole spacing sidewalls. In some embodiments, the first insulating layer 30 is made of SiO x C y N z Is made up by using 0.1-0.4 of x, 0.05-0.1 of y and 0.2-0.5 of z.
In some embodiments, the first insulating layer 30 has a thickness in the range of about 1.0nm to about 10.0 nm. In other embodiments, the first insulating layer 30 has a thickness in the range of about 2.0nm to about 6.0 nm. When the thickness is too large, the remaining spacing of the source/drain spacing is too small, which may affect the formation of the source/drain epitaxial layer. When the thickness is too small, a substantial filling effect by the insulating layer at the bottom of the source/drain interval may not be obtained.
By conformally forming the first insulating layer 30, the cavity of the first semiconductor layer 20 in the source/drain spacers 21 is completely filled with the first insulating layer 30. As shown, the bottom of the source/drain spacers 21 and the walls surrounding the source/drain spacers 21 are covered by a first insulating layer 30.
Next, as shown in fig. 8A to 8C, portions of the first insulating layer 30 are removed by one or more etching operations to expose the sides of the first and second semiconductor layers and leave the bottom 30B of the first insulating layer. In some embodiments, a wet etch using dilute HF (hydrofluoric acid) is used to partially remove the first insulating layer 30. In some embodiments, the HF etch is performed at: HF: H 2 O=1:100 for about 5 seconds to about 20 seconds. Since the first insulating layer 30 is formed by a topography selective method, softer portions formed on the sidewalls of the source/drain spacers 21 are etched more than harder portions formed at the bottom of the source/drain spacers 21. In some embodiments, the remaining bottom portion 30B has a thickness in the range of about 2nm to about 5 nm. When the thickness is too thin, it may be easily damaged by process variations, and when the thickness is too large, it may affect the formation of the source/drain epitaxial layer. In some embodiments, the first insulating layer 30 formed on the fin spacers and the isolation insulating layer is also partially removed by an amount of about 1-2 nm. The remaining portion of the first insulating layer 30 over the fin spacers is used as a protective layer for the fin structure.
Next, as shown in fig. 9A to 9C, the second insulating layer 32 is conformally formed in the source/drain interval 21. A second insulating layer 32 is formed on the exposed lateral ends of the first semiconductor layer 20 and on the exposed end surfaces of the second semiconductor layer 25 in the source/drain spacers 21 and over the sacrificial gate structure 40.
The second insulating layer 32 is made of the same material as the first insulating layer 30 or a different material and includes one of silicon nitride and silicon oxide, siON, siOC, siCN and SiOCN or any other suitable dielectric material. In certain embodiments, silicon nitride is used. In some embodiments, the second insulating layer 32 is made of a different material than the sidewall spacers 45.
In some embodiments, the second insulating layer 32 has a thickness in the range of about 2.0nm to about 15.0 nm. In other embodiments, the second insulating layer 32 has a thickness in the range of about 5.0nm to about 10.0 nm.
Further, as shown in fig. 10A to 10C, isotropic etching and/or anisotropic etching is performed to remove a portion of the second insulating layer 32, thereby forming the internal spacers 35 on the end surfaces of the first semiconductor layer 20. In some embodiments, the second insulating layer 32 formed over the sacrificial gate structure 40 is completely removed. In some embodiments, portions of the second insulating layer 32 remain as bottom spacers 35B, as shown in fig. 10A-10C. The bottom spacer 35B suppresses junction leakage.
In some embodiments, the etching operation for the second insulating layer is a plasma etch performed at a bias power in the range of about 100W to about 300W. The power is changed during the etching so that the power for etching the bottom portion is lower than the power for etching the sidewall portion. Since the bottom spacer 35B is formed at the bottom of the source/drain interval, the difference in height between the bottommost first semiconductor layer of the first semiconductor layer 20 and the bottom of the source/drain interval is reduced. Thus, after forming the inner spacers 35, continuous bottom spacers 35B are formed between adjacent gate structures.
In some embodiments, as shown in fig. 10C, the bottom spacer 35B completely covers the end face of the bottommost first semiconductor layer of the first semiconductor layer 20 and continuously covers the remaining bottom portion 30B of the first insulating layer.
After forming the internal spacers 35, one or more source/drain epitaxial layers are formed in the source/drain spacers 21, as shown in fig. 11A to 11C. In some embodiments, the source/drain epitaxial layer 50 includes a first epitaxial layer 52 formed on an end face of the second semiconductor layer 25, a second epitaxial layer 54 formed on the first epitaxial layer 52 and over the inner spacers 35, and a third epitaxial layer 56 formed on the second epitaxial layer 54, thereby completely filling the source/drain spacers.
In some embodiments, for n-type GAAFET, the first epitaxial layer 52 is one or more of SiAs, siCA, or SiPAs, and the second and third epitaxial layers are one or more of SiP, siCP, or SiC. In some embodiments, for p-type GAAFET, the first epitaxial layer 52 is one or more of sibs or sigesbs, and the second and third epitaxial layers are one or more of SiGe or SiGeSn, which may contain B.
In some embodiments, the thickness (lateral thickness) of the first epitaxial layer 52 on the end of the second semiconductor layer 25 is in the range from about 2nm to about 4nm, and the doping amount of the first epitaxial layer 52 is smaller than the doping amounts of the second epitaxial layer and the third epitaxial layer. In some embodiments, the thickness (lateral thickness) of the second epitaxial layer 54 is in the range of about 2nm to about 4nm, and the doping amount of the second epitaxial layer 54 is less than the doping amount of the third epitaxial layer. In some embodiments, the thickness of the third epitaxial layer 56 is in the range of about 7nm to about 30 nm.
Fig. 12A to 15B show various stages after formation of the structure (formation of the epitaxial layer 50) corresponding to fig. 11A to 11C. In fig. 12A to 15B, the epitaxial layer 50 is shown as one layer. Although fig. 1 to 3B and 12A to 15B illustrate four second semiconductor layers and first semiconductor layers, and fig. 4A to 11C illustrate three second semiconductor layers and first semiconductor layers, the structure and manufacturing operation thereof are substantially the same.
After forming the source/drain epitaxial layer 50, an interlayer dielectric (ILD) layer 70 is formed over the source/drain epitaxial layer 50, the sacrificial gate structure 40, and the sidewall spacers 45. Materials for ILD layer 70 include compounds comprising Si, O, C, and/or H, such as silicon oxide, siCOH, and SiOC. An organic material, such as a polymer, may be used for ILD layer 70. In some embodiments, etch stop layer 68 is formed prior to formation of ILD layer 70. In some embodiments, etch stop layer 68 comprises silicon nitride or SiON. After formation of ILD layer 70, one or more planarization operations, such as CMP, are performed, leaving a top portion of sacrificial gate electrode layer 42 exposed, as shown in fig. 12A.
In some embodiments, as shown in fig. 12B, portions of ILD layer 70 and etch stop layer 68 penetrate into recesses formed in isolation insulating layer 15. In some embodiments, the first insulating layer 30 remaining in the recess is disposed between the ILD layer 70 (and/or the etch stop layer 68) and the isolation insulating layer 15.
Then, the sacrificial gate electrode layer 42 and the sacrificial gate dielectric layer 41 are removed. ILD layer 70 protects source/drain epitaxial layer 50 during removal of sacrificial gate structure 40. Plasma dry and/or wet etching may be used to remove the sacrificial gate structure 40. When the sacrificial gate electrode layer 42 is polysilicon and the ILD layer 70 is silicon oxide, a wet etchant (e.g., TMAH solution) may be used to selectively remove the sacrificial gate electrode layer 42. Thereafter, a plasma dry etch and/or a wet etch is used to remove the sacrificial gate dielectric layer 41.
After the sacrificial gate structure is removed, the first semiconductor layer 20 is removed, thereby forming a line or a sheet (channel region) of the second semiconductor layer 25, as shown in fig. 13. The first semiconductor layer 20 may be removed/etched using an etchant that may selectively etch the first semiconductor layer 20 with respect to the second semiconductor layer 25 and with respect to the inner spacer 35 (as an etch stop).
Further, as shown in fig. 14, a metal gate structure including a gate dielectric layer 82 and a gate electrode layer 84 is formed to surround each semiconductor die or line 25.
In some embodiments, gate dielectric layer 82 comprises a high-k dielectric layer, such as hafnium oxide. In some embodiments, gate electrode layer 84 includes one or more work function adjustment layers. The work function adjusting layer is made of a conductive material such as a single layer of TiN, taN, taAlC, tiC, taC, co, al, tiAl, hfTi, tiSi, taSi, tiAlC or a plurality of layers of two or more of these materials. For n-channel FETs, one or more of TaN, taAlC, tiN, tiC, co, tiAl, hfTi, tiSi and TaSi are used as work function tuning layers, and for p-channel FETs, one or more of TiAlC, al, tiAl, taN, taAlC, tiN, tiC and Co are used as work function tuning layers. The work function adjusting layer may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable process. Further, for an n-channel FET and a p-channel FET, which may use different metal layers, work function adjustment layers may be formed separately. In some embodiments, a bulk gate electrode layer comprising W, co, ni, mo or other suitable material is formed over the work function adjusting material layer.
After forming the metal gate structure, ILD layer 70 is patterned and conductive contact layer 72 is formed over epitaxial layer 50, and conductive contact plug 75 is formed on conductive contact layer 72, as shown in fig. 15A and 15B. In some embodiments, the conductive contact layer 72 includes one or more of Co, ni, W, ti, ta, cu, al, their silicides, tiN, and TaN. The conductive contact plug 75 includes one or more layers of Co, ni, W, ti, ta, cu, al, tiN and TaN.
Although fig. 12A to 15B show four channel regions 25, the number of channel regions 25 is not limited to four, and may be one, two, three, or more, and may be as many as 10 or 15. By adjusting the number of semiconductor lines or slices, the drive current of the GAAFET device can be adjusted.
Fig. 16A and 16B illustrate views of various stages of a sequential fabrication process of a semiconductor GAAFET device according to an embodiment of the invention. The same or similar materials, configurations, dimensions and/or processes as those of the foregoing embodiments described with reference to the foregoing embodiments may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
In the etching operation as explained with reference to fig. 8A to 8C, as shown in fig. 16A, a portion 30S of the first insulating layer remains on the end portion of the first semiconductor layer 20, and an internal spacer 35 is formed over the remaining first insulating layer 30S, as shown in fig. 16B. In some embodiments, the thickness (lateral direction) of the remaining first insulating layer 30S is in a range from about 0.1nm to about 3 nm. In some embodiments, the dielectric constant of the remaining insulating layer 30S is smaller than that of the internal spacers 35, and thus parasitic capacitance can be reduced by using a two-layer structure.
Fig. 17A and 17B through 20A and 20B illustrate views of various stages of a sequential fabrication process of a semiconductor GAAFET device according to an embodiment of the present invention. The same or similar materials, configurations, dimensions and/or processes as those of the foregoing embodiments described with reference to the foregoing embodiments may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
In some embodiments, the bottom portion 30B of the first insulating layer has an upwardly convex curved upper surface, as shown in fig. 17A and 17B. In some embodiments, the top of the bottom portion 30B of the first insulating layer is lower than the bottom surface of the bottommost first semiconductor layer of the first semiconductor layer 20. In some embodiments, after forming the inner spacer 35 and the bottom spacer 35B, the bottom spacer 35B is discontinuous and a portion of the upper surface of the bottom portion 30B of the first insulating layer is exposed, as shown in fig. 17B.
In some embodiments, the bottom portion 30B of the first insulating layer has a curved upper surface that protrudes upward, and the top of the bottom portion 30B of the first insulating layer is equal to or higher than the bottom surface of the bottommost first semiconductor layer of the first semiconductor layer 20, as shown in fig. 18A and 18B. In some embodiments, after forming the inner spacer 35 and the bottom spacer 35B, the bottom spacer 35B is discontinuous and a portion of the upper surface of the bottom portion 30B of the first insulating layer is exposed, as shown in fig. 18B.
In some embodiments, the bottom portion 30B of the first insulating layer has a planar surface, as shown in fig. 19A and 19B. In some embodiments, the top of the bottom portion 30B of the first insulating layer is lower than the bottom surface of the bottommost first semiconductor layer of the first semiconductor layer 20. In some embodiments, after forming the inner spacer 35 and the bottom spacer 35B, the bottom spacer 35B is discontinuous and a portion of the upper surface of the bottom portion 30B of the first insulating layer is exposed, as shown in fig. 19B.
In some embodiments, the bottom portion 30B of the first insulating layer has a flat surface, and the top of the bottom portion 30B of the first insulating layer is equal to or higher than the bottom surface of the bottommost first semiconductor layer of the first semiconductor layer 20, as shown in fig. 20A and 20B. In some embodiments, after forming the inner spacer 35 and the bottom spacer 35B, the bottom spacer 35B is discontinuous and a portion of the upper surface of the bottom portion 30B of the first insulating layer is exposed, as shown in fig. 20B.
In other embodiments, the bottom spacer 35B is continuous, and in the structures shown in fig. 17B, 18B, 19B, and 20B, no portion of the upper surface of the bottom portion 30B of the first insulating layer is exposed.
Fig. 21A to 21E are views showing various stages of a sequential fabrication process of a semiconductor GAAFET device according to an embodiment of the present invention. The same or similar materials, configurations, dimensions and/or processes as those of the foregoing embodiments described with reference to the foregoing embodiments may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
In some embodiments, an air gap or void 49 is formed at the bottom of the source/drain epitaxial layer 50, which may also suppress off-current of the GAA FET, as shown in fig. 21A and 21C. In some embodiments, when the structure of fig. 17A-20B is employed, the air gap passes through the bottom spacer 35B, as shown in fig. 21D.
In some embodiments, the upper surface of the third epitaxial layer 56 has an upwardly convex curved upper surface, as shown in fig. 21B and 21C. In some embodiments, when the structure of fig. 17A-20B is employed, portions of epitaxial layer 50 penetrate bottom spacers 35B and separate bottom spacers 35B, as shown in fig. 21E.
In the foregoing embodiment, two layers of the bottom spacer are formed at the bottom of the source/drain epitaxial layer, which can suppress junction leakage current and/or off-current.
It will be understood that not all advantages need be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.
According to some embodiments of the present invention, in a method of manufacturing a semiconductor device, a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate, a sacrificial gate structure is formed over the fin structure, source/drain regions of the fin structure not covered by the sacrificial gate structure are etched to form source/drain spacers, ends of the first semiconductor layer are laterally etched in the source/drain spacers, a first insulating layer is formed on sidewalls of the source/drain spacers, the first insulating layer is partially etched to form a first bottom spacer at a bottom of the source/drain spacers, a second insulating layer is formed on sidewalls of the source/drain spacers, the second insulating layer is partially etched to form an inner spacer on an end face of the first semiconductor layer, and a portion of the second insulating layer remains at a bottom of the source/drain spacers as a second bottom spacer, and a source/drain epitaxial layer is formed in the source/drain spacers. In one or more of the foregoing or following embodiments, the second bottom spacer at least partially covers the first bottom spacer. In one or more of the foregoing or following embodiments, the second bottom spacer completely covers the first bottom spacer. In one or more of the foregoing or following embodiments, an air gap is formed between the source/drain epitaxial layer and the second bottom spacer. In one or more of the foregoing or following embodiments, one of the inner spacers formed on the end face of the bottommost first semiconductor layer of the first semiconductor layer and the second bottom spacer are continuous. In one or more of the foregoing or following embodiments, the first insulating layer has a lower dielectric constant than the second insulating layer. In one or more of the foregoing or following embodiments, the first insulating layer includes SiOCN. In one or more of the foregoing or following embodiments, the first insulating layer is made of SiO x C y N z Is made up by using 0.1-0.4 of x, 0.05-0.1 of y and 0.2-0.5 of z. In one or more of the foregoing or following embodiments, the first insulationThe layer includes a first portion and a second portion, the second portion having a higher etch resistance relative to a dilute HF solution.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate, a sacrificial gate structure is formed over the fin structure, source/drain regions of the fin structure disposed between the sacrificial gate structures are etched to form source/drain spacers, ends of the first semiconductor layer are laterally etched in the source/drain spacers, a first insulating layer is formed on sidewalls of the source/drain spacers, the first insulating layer is partially etched to form a first internal spacer on an end face of the first semiconductor layer, and a portion of the first insulating layer is left as a first bottom spacer at a bottom of the source/drain spacers, a second insulating layer is formed on sidewalls of the source/drain spacers, the second insulating layer is partially etched to form second internal spacers on the first internal spacers, respectively, and a portion of the second insulating layer is left as a second bottom spacer at a bottom of the source/drain spacers, and a source/drain layer is formed in the source/drain spacers. In one or more of the foregoing or following embodiments, the first insulating layer is partially etched using a wet etching operation. In one or more of the foregoing or following embodiments, the first insulating layer is formed by a plasma deposition method with varying power during deposition. In one or more of the foregoing or following embodiments, the power is in the range of 20W to 100W. In one or more of the foregoing or following embodiments, the second bottom spacer partially covers the first bottom spacer. In one or more of the foregoing or following embodiments, the source/drain epitaxial layer contacts the first bottom spacer. In one or more of the foregoing or following embodiments, an air gap is formed between the source/drain epitaxial layer and the first bottom spacer and the second bottom spacer.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate is formed. An upper portion of the fin structure protrudes from the isolation insulating layer. Forming a sacrificial gate structure over the fin structure, etching source/drain regions of the fin structure not covered by the sacrificial gate structure, thereby forming source/drain spacers, laterally etching ends of the first semiconductor layer in the source/drain spacers, forming a first insulating layer on sidewalls of the source/drain spacers, partially etching the first insulating layer, thereby forming a first bottom spacer at a bottom of the source/drain spacers, forming a second insulating layer on sidewalls of the source/drain spacers, partially etching the second insulating layer, thereby forming an inner spacer, and leaving portions of the second insulating layer at the bottom of the source/drain spacers as second bottom spacers, forming a source/drain epitaxial layer in the source/drain spacers, and forming an interlayer dielectric (ILD) layer over the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, during etching of the source/drain regions, portions of the isolation insulating layer are etched to form recesses. In one or more of the foregoing or following embodiments, a first insulating layer is formed on an inner sidewall of the groove, a portion of the first insulating layer remaining after the first insulating layer is partially etched. In one or more of the foregoing or following embodiments, an ILD layer is formed over the first insulating layer remaining in the recess.
According to another aspect of an embodiment of the present invention, there is disclosed a semiconductor device including: a semiconductor fin or line disposed over and vertically disposed over a bottom fin structure disposed over a substrate; a gate structure disposed over the semiconductor wafer or line; a source/drain epitaxial layer disposed over the semiconductor die or line on opposite sides of the gate structure; and a first bottom spacer and a second bottom spacer disposed between the bottom fin structure and the source/drain epitaxial layer, wherein the second bottom spacer is disposed between the first bottom spacer and the source/drain epitaxial layer, and the second bottom spacer is made of a different insulating material than the first bottom spacer. In some embodiments, the semiconductor device further comprises: an internal spacer is disposed between the gate structure and the source/drain epitaxial layer, the internal spacer being made of the same material as the second bottom spacer. In some embodiments, the second bottom spacer and the bottommost inner spacer of the inner spacers are continuous. In some embodiments, the semiconductor device further comprises: an air gap is disposed under the source/drain epitaxial layer.
According to another aspect of the invention, a semiconductor device includes a semiconductor fin or line disposed over and vertically disposed over a bottom fin structure disposed over a substrate, a gate structure, a source/drain epitaxial layer, and first and second bottom spacers disposed between the bottom fin structure and the source/drain epitaxial layer. The second bottom spacer is disposed between the first bottom spacer and the source/drain epitaxial layer, and the second bottom spacer is made of a different insulating material than the first bottom spacer. In one or more of the foregoing or following embodiments, the semiconductor device further includes an internal spacer disposed between the gate structure and the source/drain epitaxial layer. The inner spacer is made of the same material as the second bottom spacer. In one or more of the foregoing or following embodiments, the second bottom spacer and the bottommost inner spacer of the inner spacers are continuous. In one or more of the foregoing or following embodiments, the semiconductor device further includes an air gap disposed under the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, the first bottom spacer comprises SiOCN. In one or more of the foregoing or following embodiments, the first bottom spacer is made of SiO x C y N z Is made up by using 0.1-0.4 of x, 0.05-0.1 of y and 0.2-0.5 of z. In one or more of the foregoing or following embodiments, the second bottom spacer comprises silicon nitride. In one or more of the foregoing or following embodiments, a top of the first bottom spacer is located below a top of the bottom fin structure. In one or more of the foregoing or following embodiments, a top portion of the first bottom spacer is located above a top portion of the bottom fin structure.
According to another aspect of the present invention, a semiconductor device includes: a first group of semiconductor wafers or wires arrangedA second set of semiconductor dice or lines disposed over the bottom fin structure, the bottom fin structure disposed over the substrate, a first gate structure disposed over the first set of semiconductor dice or lines, a second gate structure disposed over the second set of semiconductor dice or lines, a source/drain epitaxial layer disposed between the first set of semiconductor dice or lines and the second set of semiconductor dice or lines, a first internal spacer disposed between the first gate structure and the source/drain epitaxial layer, a second internal spacer disposed between the second gate structure and the source/drain epitaxial layer, and a first bottom spacer and a second bottom spacer disposed between the bottom fin structure and the source/drain epitaxial layer. The second bottom spacer is disposed between the first bottom spacer and the source/drain epitaxial layer, and the second bottom spacer is made of a different insulating material than the first bottom spacer, and the first bottom-most inner spacer of the first inner spacer, the second bottom spacer, and the second bottom-most spacer of the second inner spacer are continuous. In one or more of the foregoing or following embodiments, the semiconductor device further includes an air gap disposed under the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, the first bottom spacer comprises SiOCN. In one or more of the foregoing or following embodiments, the first bottom spacer is made of SiO x C y N z Is made up by using 0.1-0.4 of x, 0.05-0.1 of y and 0.2-0.5 of z. In one or more of the foregoing or following embodiments, the second bottom spacer comprises silicon nitride. In one or more of the foregoing or following embodiments, a top of the first bottom spacer is located below a top of the bottom fin structure. In one or more of the foregoing or following embodiments, a top portion of the first bottom spacer is located above a top portion of the bottom fin structure.
According to another aspect of the present disclosure, a semiconductor device includes: a first set of semiconductor fins or lines disposed over and vertically disposed over the bottom fin structure, the bottom fin structure disposed over the substrate, a second set of semiconductor fins or lines disposed over and vertically disposed over the bottom fin structure, an isolation insulating layer disposed over the substrate, a first gate structure disposed over the first set of semiconductor fins or lines, a second gate structure disposed over the second set of semiconductor fins or lines, a source/drain epitaxial layer disposed between the first set of semiconductor fins or lines and the second set of semiconductor fins or lines, a first internal spacer disposed between the first gate structure and the source/drain epitaxial layer, a second internal spacer disposed between the second gate structure and the source/drain epitaxial layer, a first bottom spacer and a second bottom spacer disposed between the bottom structure and the source/drain epitaxial layer, and an interlayer dielectric (ILD) layer. The second bottom spacer is disposed between the first bottom spacer and the source/drain epitaxial layer, and the second bottom spacer is made of an insulating material different from the first bottom spacer, the isolation insulating layer includes a recess portion, and an insulating layer made of the same material as the first bottom spacer is disposed between the isolation insulating layer and the ILD layer in the recess portion. In one or more of the foregoing or following embodiments, the bottommost first inner spacer of the first inner spacer is spaced apart from the bottommost second inner spacer of the second inner spacer. In one or more of the foregoing or following embodiments, a bottommost one of the first internal spacers and a bottommost one of the second internal spacers are separated by a source/drain epitaxial layer. In one or more of the foregoing or following embodiments, a bottommost one of the first inner spacers and a bottommost one of the second inner spacers are separated by an air gap.
The foregoing outlines features of a drop-on embodiment so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples presented herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate;
forming a sacrificial gate structure over the fin structure;
etching source/drain regions of the fin structure not covered by the sacrificial gate structure, thereby forming source/drain spacers;
laterally etching an end portion of the first semiconductor layer in the source/drain interval;
forming a first insulating layer on sidewalls of the source/drain spacers;
Partially etching the first insulating layer, thereby forming a first bottom spacer at a bottom of the source/drain spacer;
forming a second insulating layer on the sidewalls of the source/drain spacers;
partially etching the second insulating layer to form an internal spacer on an end face of the first semiconductor layer, and leaving a portion of the second insulating layer at the bottom of the source/drain spacer as a second bottom spacer; and
a source/drain epitaxial layer is formed in the source/drain spacers.
2. The method of claim 1, wherein the second bottom spacer at least partially covers the first bottom spacer.
3. The method of claim 1, wherein the second bottom spacer completely covers the first bottom spacer.
4. The method of claim 1, wherein an air gap is formed between the source/drain epitaxial layer and the second bottom spacer.
5. The method of claim 1, wherein one of the internal spacers formed on the end face of the bottommost first semiconductor layer of the first semiconductor layer is continuous with the second bottom spacer.
6. The method of claim 1, wherein the first insulating layer has a lower dielectric constant than the second insulating layer.
7. The method of claim 1, wherein the first insulating layer comprises SiOCN.
8. The method of claim 7, wherein the first insulating layer is formed of SiO x C y N z Is prepared, wherein x is more than or equal to 0.1 and less than or equal to 0.4, y is more than or equal to 0.05 and less than or equal to 0.1, and z is more than or equal to 0.2 and less than or equal to 0.5.
9. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked over a substrate;
forming a sacrificial gate structure over the fin structure;
etching source/drain regions of the fin structure disposed between the sacrificial gate structures to form source/drain spacers;
laterally etching an end portion of the first semiconductor layer in the source/drain interval;
forming a first insulating layer on sidewalls of the source/drain spacers;
partially etching the first insulating layer to form a first internal spacer on an end face of the first semiconductor layer, and leaving a portion of the first insulating layer at a bottom of the source/drain spacer as a first bottom spacer;
Forming a second insulating layer on the sidewalls of the source/drain spacers;
partially etching the second insulating layer to form second inner spacers on the first inner spacers, respectively, and leaving portions of the second insulating layer at the bottoms of the source/drain spacers as second bottom spacers; and
a source/drain epitaxial layer is formed in the source/drain spacers.
10. A semiconductor device, comprising:
a semiconductor fin or line disposed over and vertically arranged over a bottom fin structure disposed over a substrate;
a gate structure disposed over the semiconductor die or line;
a source/drain epitaxial layer disposed over the semiconductor die or line on opposite sides of the gate structure; and
a first bottom spacer and a second bottom spacer disposed between the bottom fin structure and the source/drain epitaxial layer,
wherein the second bottom spacer is disposed between the first bottom spacer and the source/drain epitaxial layer, and the second bottom spacer is made of a different insulating material than the first bottom spacer.
CN202310542611.8A 2022-05-17 2023-05-15 Method for manufacturing semiconductor device and semiconductor device Pending CN116741802A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/342,795 2022-05-17
US17/864,104 2022-07-13
US17/864,104 US20230378300A1 (en) 2022-05-17 2022-07-13 Methods of manufacturing semiconductor devices and semiconductor devices

Publications (1)

Publication Number Publication Date
CN116741802A true CN116741802A (en) 2023-09-12

Family

ID=87914190

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310542611.8A Pending CN116741802A (en) 2022-05-17 2023-05-15 Method for manufacturing semiconductor device and semiconductor device

Country Status (1)

Country Link
CN (1) CN116741802A (en)

Similar Documents

Publication Publication Date Title
CN110416081B (en) Selective recessing of source/drain regions of NFET/PFET
US11791421B2 (en) Nanosheet field-effect transistor device and method of forming
KR102558315B1 (en) Ferroelectric random access memory devices and methods
TW202141803A (en) Semiconductor device and method for fabricating the same
CN113690141B (en) Method for manufacturing semiconductor device and semiconductor device
US20230317820A1 (en) Semiconductor device with gate dielectric formed using selective deposition
US11393898B2 (en) Method of manufacturing a semiconductor device and a semiconductor device
CN110970505A (en) Semiconductor device and method for manufacturing the same
CN113539964A (en) Method for manufacturing semiconductor device
US11532502B2 (en) Reducing parasitic capacitance in field-effect transistors
TW202240900A (en) Semiconductor device and method of forming the same
CN113130394A (en) Semiconductor device and method for manufacturing the same
US20230378300A1 (en) Methods of manufacturing semiconductor devices and semiconductor devices
CN220510031U (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
TWI844226B (en) Semiconductor device and method of manufacturing the same
CN116741802A (en) Method for manufacturing semiconductor device and semiconductor device
CN220121843U (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
US20230395693A1 (en) Semiconductor device and manufacturing method thereof
US20230027567A1 (en) Method of manufacturing a semiconductor device and a semiconductor device
US20240113199A1 (en) Semiconductor device and manufacturing method thereof
US20230317830A1 (en) Methods of manufacturing a semiconductor device with local isolation and a semiconductor device with local isolation
US20230378269A1 (en) Semiconductor device structure and methods of forming the same
US20230317791A1 (en) Semiconductor device and manufacturing method thereof
TW202139291A (en) Semiconductor structure and method of forming the same
TW202141640A (en) Semiconductor devices and methods for forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination