CN116741758A

CN116741758A - Integrated circuit package and method of forming the same

Info

Publication number: CN116741758A
Application number: CN202310543194.9A
Authority: CN
Inventors: 谢秉颖; 王卜; 郑礼辉; 施应庆; 陈宏宇
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-17
Filing date: 2023-05-15
Publication date: 2023-09-12

Abstract

One embodiment is an integrated circuit package comprising a package assembly including an integrated circuit die and a conductive connector connected to the integrated circuit die, the conductive connector disposed at a first side of the package assembly. The integrated circuit package also includes a metal layer on a second side of the package assembly, the second side being opposite the first side. The integrated circuit package also includes a thermal interface material on the metal layer. The integrated circuit package also includes a cover over the thermal interface material. The integrated circuit package also includes a retaining structure on a sidewall of the package stack and on a sidewall of the thermal interface material. The integrated circuit package also includes a package substrate connected to the conductive connector, the cover being adhered to the package substrate. Embodiments of the application also disclose methods of forming integrated circuit packages.

Description

Integrated circuit package and method of forming the same

Technical Field

Embodiments of the application relate to integrated circuit packages and methods of forming the same.

Background

The semiconductor industry has experienced a rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). The increase in integration density is due, in large part, to the iterative reduction in minimum feature size, allowing more components to be integrated into a given area. With the growing demand for small electronic devices, there is a need for smaller, more innovative semiconductor chip packaging techniques.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided an integrated circuit package including: a package assembly including an integrated circuit die and a conductive connector connected to the integrated circuit die, the conductive connector disposed at a first side of the package assembly; a metal layer on a second side of the package assembly, the second side being opposite the first side; a thermal interface material located on the metal layer; a cover positioned over the thermal interface material; a retaining structure on the package assembly and the sidewalls of the thermal interface material; and a package substrate connected to the conductive connector, the cap being adhered to the package substrate.

According to another aspect of an embodiment of the present application, there is provided a method of forming an integrated circuit package, comprising: packaging the integrated circuit die in a packaging region of the wafer; depositing a backside metal layer on a backside of the integrated circuit die; dividing the packaging region and the wafer to form a packaging assembly; after dividing the package region, connecting the package assembly to the package substrate; placing a thermal interface material on the backside metal layer; a thermal interface material distribution holding structure adjacent to the package assembly; attaching a cover to the package substrate, the cover coupled to the thermal interface material; and performing a bonding process to bond the thermal interface material to the backside metal layer and the cap, the bonding process being performed at a temperature above a melting point of the thermal interface material.

According to yet another aspect of an embodiment of the present application, there is provided a method of forming an integrated circuit package, comprising: bonding a plurality of integrated circuit dies to a wafer in a package region of the wafer; encapsulating the plurality of integrated circuit die with a molding compound; forming a backside metal layer on a backside of the molding compound and the plurality of integrated circuit die; dividing the packaging region and the wafer to form a packaging assembly; bonding the package assembly to a package substrate; depositing a first flux on a backside of the integrated circuit die of the bonded package assembly; attaching a thermal interface material to the first flux, the thermal interface material comprising indium; forming a retaining structure adjacent the package assembly and the thermal interface material; and attaching the cover to the package substrate, the thermal interface material and the retaining structure being coupled to the cover.

Drawings

The various aspects of the application are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of an integrated circuit die.

Fig. 2-14 are views of intermediate stages in the manufacture of an integrated circuit package according to some embodiments.

Fig. 15 is a cross-sectional view of an integrated circuit package according to some embodiments.

Fig. 16-19 are views of intermediate stages in the manufacture of an integrated circuit package according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

According to various embodiments, an integrated circuit package is formed by packaging integrated circuit die in a wafer. The wafer is singulated to form intermediate package assemblies. The intermediate package assembly is then attached to a package substrate to form an integrated circuit package. In some embodiments, the heat spreading structure is attached to the intermediate package assembly after the intermediate package assembly is attached to the package substrate, and the heat spreading structure may comprise indium. A retaining structure (e.g., retaining wall) may be formed on the package substrate proximate the intermediate package assembly and the heat dissipating structure. A lid (lid) may then be attached over the intermediate package assembly and the retaining structure, followed by a thermal clamping and/or reflow process to attach the lid and/or the heat dissipating structure. By having a retaining structure, any subsequent bleeding or reflow of the metal (e.g., indium) of the heat dissipating structure is inhibited during thermal clamping, reflow, or normal operation of the package. The suppression includes preventing metal overflow from shorting the package assembly and preventing void formation in the heat dissipating structure, thereby improving package reliability and performance.

Fig. 1 is a cross-sectional view of an integrated circuit die 50. The integrated circuit die 50 will be packaged in a subsequent process to form an integrated circuit package. Each integrated circuit die 50 may be a logic device (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a microcontroller, etc.), a memory device (e.g., a Dynamic Random Access Memory (DRAM) chip, a Static Random Access Memory (SRAM) chip, etc.), a power management device (e.g., a Power Management Integrated Circuit (PMIC) chip), a Radio Frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a Digital Signal Processing (DSP) chip), a front-end device (e.g., an analog front-end (AFE) chip), etc., or a combination thereof (e.g., a system on chip (SoC) chip). The integrated circuit die 50 may be formed in a wafer, which may include different chip regions that individually form the plurality of integrated circuit die 50 in subsequent steps. Integrated circuit die 50 includes a semiconductor substrate 52, interconnect structures 54, die connectors 56, and dielectric layers 58.

The semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may comprise other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium phosphide; or a combination thereof. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. The semiconductor substrate 52 has an active surface (e.g., an upward facing surface) and an inactive surface (e.g., a downward facing surface). The devices are located on the active surface of semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be devoid of devices.

An interconnect structure 54 is located over the active surface of semiconductor substrate 52 for electrically connecting the devices of semiconductor substrate 52 to form an integrated circuit. Interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. Acceptable dielectric materials for the dielectric layer include: oxides such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; a similar material; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. Other dielectric materials, such as polymers, such as Polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB) based polymers, and the like, may also be used. The metallization layers may include conductive vias and/or conductive lines for interconnecting devices of the semiconductor substrate 52. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. Interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

Die connectors 56 are located on the front side 50F of the integrated circuit die 50. The die connector 56 may be a conductive post, pad, or the like that is connected to the outside. The die connectors 56 are located in and/or on the interconnect structure 54. For example, die connectors 56 may be part of an upper metallization layer of interconnect structure 54. The die connectors 56 may be formed of metal, such as copper, aluminum, etc., and may be formed by plating, etc.

Optionally, solder regions (not separately shown) may be provided on the die connectors 56 during formation of the integrated circuit die 50. The solder regions may be used to perform Chip Probe (CP) tests on the integrated circuit die 50. For example, the solder regions may be solder balls, solder bumps, or the like for attaching the chip probes to the die connectors 56. Chip probing tests may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a Known Good Die (KGD). Thus, only the KGD integrated circuit die 50 is packaged through subsequent processing, and chips that do not pass the chip probe test are not packaged. After testing, the solder regions may be removed in a subsequent process step.

Dielectric layer 58 is located at front side 50F of integrated circuit die 50. Dielectric layer 58 is located in and/or on interconnect structure 54. For example, dielectric layer 58/may be an upper dielectric layer of interconnect structure 54. Dielectric layer 58 laterally encapsulates die connector 56. Dielectric layer 58 may be an oxide, nitride, carbide, polymer, or the like, or a combination thereof. Dielectric layer 58 may be formed, for example, by spin coating, lamination, chemical Vapor Deposition (CVD), and the like. Initially, dielectric layer 58 may bury die connectors 56 such that the top surface of dielectric layer 58 is higher than the top surface of die connectors 56. During formation of integrated circuit die 50, die connectors 56 are exposed by dielectric layer 58. Exposing the die connectors 56 may remove any solder regions that may exist on the die connectors 56. A removal process may be applied to each layer to remove excess material on the die connectors 56. The removal process may be a planarization process such as Chemical Mechanical Polishing (CMP), etch back, combinations thereof, and the like. After the planarization process, the top surface of die connector 56 and the top surface of dielectric layer 58 are substantially coplanar (within process variations) so that they are flush with one another. The die connectors 56 and dielectric layer 58 are exposed at the front side 50F of the integrated circuit die 50.

In some embodiments, integrated circuit die 50 is a stacked device that includes a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a hybrid memory cube (HMC, hybrid memory cub) device, a high bandwidth memory (HBM, high bandwidth memory) device, or the like. In these embodiments, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by Through Substrate Vias (TSVs), such as through silicon vias. Each of the semiconductor substrates 52 may (or may not) have a separate interconnect structure 54.

Fig. 2-14 are views of intermediate stages in the manufacture of an integrated circuit package 200 according to some embodiments. FIGS. 2-13 illustrate the formation of a package assembly 210 including an interposer (such as for a chip-on-substrate wafer)chip-on-wafer-on-substrate) device 200). The package assembly 210 may be a chip-on-wafer (CoW) package assembly.

The integrated circuit package 200 will be formed by initially packaging the integrated circuit die 50 to form a package assembly 210 in the wafer 100 (see fig. 13). One package region 100A of the wafer 100 is shown, with the integrated circuit die 50 packaged to form a package assembly 210 in each package region 100A in the wafer 100A. It should be appreciated that any number of package regions may be processed simultaneously to form any number of package assemblies. The package region 100A of the wafer 100 is to be divided into package assemblies 210. The package assembly 210 is attached to a package substrate 220 (see fig. 8 or 16). The heat spreader structure 212/214/230/232/234/236 will then be formed over the package assembly 210 and the package substrate 220 to complete the formation of the integrated circuit package 200 (see, e.g., fig. 13, 15, or 18).

In fig. 2, a wafer 110 is obtained or formed. Wafer 110 includes devices located in package region 100A, and package region 100A is to be singulated for inclusion in package assembly 210 in subsequent processing. The devices in wafer 110 may be intermediaries, integrated circuit dies, etc. In some embodiments, the interposer 102 is formed in the wafer 110, the interposer 102 including a substrate 112, an interconnect structure 114, and conductive vias 120.

The substrate 112 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layer semiconductor substrate, or the like. The substrate 112 may include: semiconductor materials such as silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphate, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. Substrate 112 may be doped or undoped. In embodiments where an interposer is formed in wafer 110, the active devices are not typically included in substrate 112, although the interposer may include passive devices formed in and/or on the front surface (e.g., the surface facing upward in fig. 2) of substrate 112. In embodiments where integrated circuit devices are formed in wafer 110, active devices such as transistors, capacitors, resistors, diodes, etc. may be formed in and/or on the front surface of substrate 112.

Interconnect structure 114 is located over the front surface of substrate 112 and is used to electrically connect devices (if any) of substrate 112. The interconnect structure 114s may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. Acceptable dielectric materials for the dielectric layer include: oxides such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; a similar material; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. Other dielectric materials, such as polymers, such as Polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB) based polymers, and the like, may also be used. The metallization layer may include conductive vias and/or conductive lines to interconnect any devices together and/or to external devices. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. Interconnect structure 114 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

In some embodiments, die connectors 116 and dielectric layer 118 are located at the front side of wafer 110. In particular, wafer 110 may include die connectors 116 and dielectric layers 118 similar to integrated circuit die 50 described with respect to fig. 1. For example, die connectors 116 and dielectric layer 118 may be part of an upper metallization layer of interconnect structure 114.

Conductive vias 120 extend into the interconnect structure 114 and/or the substrate 112. Conductive via 120 is electrically connected to the metallization layer of interconnect structure 144. Conductive vias 120 are sometimes also referred to as Through Substrate Vias (TSVs). As an example of forming the conductive via 120, a recess may be formed in the interconnect structure 114 and/or the substrate 112 by, for example, etching, milling, laser techniques, combinations thereof, and/or the like. A thin dielectric material may be formed in the recess, for example, by using an oxidation technique. A thin barrier layer may be conformally deposited in the opening, for example, by CVD, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, nitride, carbide, combinations thereof, and the like. A conductive material may be deposited over the barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and/or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and/or the like. Excess conductive material and barrier layer are removed from the surface of interconnect structure 114 or substrate 112, for example, by CMP. The barrier layer and the remaining portion of the conductive material form a conductive via 120.

In fig. 3, an integrated circuit die 50 (e.g., a first integrated circuit die 50A and a plurality of second integrated circuit dies 50B) is attached to a wafer 110. In the illustrated embodiment, the plurality of integrated circuit dies 50 are positioned adjacent to one another, including a first integrated circuit die 50A and a second integrated circuit die 50B, with the first integrated circuit die 50A being located between the second integrated circuit die 50B. In some embodiments, the first integrated circuit die 50A is a logic device, such as a CPU, GPU, etc., and the second integrated circuit die 50B is a memory device, such as a DRAM chip, HMC module, HBM module, etc. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are the same type of device (e.g., soC).

In the illustrated embodiment, the integrated circuit die 50 is attached to the wafer 110 by solder joints, such as with conductive connectors 132. Integrated circuit die 50 may be placed on interconnect structure 114 using, for example, a pick and place tool. The conductive connector 132 may be formed of a reflowable conductive material (e.g., solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof). In some embodiments, the conductive connector 132 is formed by initially forming a solder layer by methods such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is structurally formed, reflow soldering may be performed to shape the conductive connector 132 into a desired bump shape. Attaching the integrated circuit die 50 to the wafer 110 may include placing the integrated circuit die 50 on the wafer 110 and reflowing the conductive connectors 132. Conductive connectors 132 form joints between corresponding die connectors 116 of wafer 110 and die connectors 56 in integrated circuit die 50, thereby electrically connecting interposer 102 to integrated circuit die 50.

The underfill 134 may be formed around the conductive connectors 132 or between the wafer 110 and the integrated circuit die 50. The underfill 134 may reduce stress and protect the joint due to reflow of the conductive connector 132. The underfill 134 may be formed of an underfill material such as a molding compound, epoxy, or the like. The underfill 134 may be formed by a capillary flow process after the integrated circuit die 50 is attached to the wafer 110, or may be formed by a suitable deposition method before the integrated chip die 50 is attached to the wafer 110. The underfill 134 may be applied in liquid or semi-liquid form and then cured.

In other embodiments (not separately shown), the integrated circuit die 50 is attached to the wafer 110 by direct bonding. For example, metal-to-metal and dielectric-to-dielectric bonding, fusion bonding, dielectric bonding, metal bonding, and the like may be used to directly bond the corresponding dielectric layers 58, 118 and/or die connectors 56, 116 of the integrated circuit die 50 and wafer 110 without the use of adhesives or solders. When direct bonding is used, the underfill 134 may be omitted. Furthermore, hybrid bonding techniques may be used, for example, some integrated circuit dies 50 may be attached to wafer 110 by solder joints, while other integrated circuit dies 50 may be attached to wafer 110 by direct bonding.

In fig. 4, an encapsulant 136 is formed over and around the integrated circuit die 50. After formation, an encapsulant 136 encapsulates the integrated circuit die 50, and the underfill 134 (if present) or conductive connectors 132. The encapsulant 136 may be a molding compound, epoxy, or similar material. The encapsulant 136 may be applied by compression molding, transfer molding, or the like, and the encapsulant 136 is formed over the wafer 110 such that the integrated circuit die 50 is buried or covered. The sealant 136 may be applied in liquid or semi-liquid form and subsequently cured. Encapsulant 136 may be thinned to expose integrated circuit die 50. The thinning process may be an abrasive process, chemical Mechanical Polishing (CMP), etch back, combinations thereof, and the like. After the thinning process, the top surface of the integrated circuit die 50 and the top surface of the encapsulant 136 are coplanar (within process variations) such that they are flush with each other. Thinning is performed until a desired amount of integrated circuit die 50 and/or encapsulant 136 is removed.

In fig. 5, substrate 112 is thinned to expose conductive vias 120. The exposure of the conductive via 120 may be accomplished by a thinning process, such as a grinding process, chemical Mechanical Polishing (CMP), etching back, combinations thereof, and the like. In some embodiments (not separately shown), the thinning process for exposing the conductive vias 120 includes CMP, and the conductive vias 120 protrude at the backside of the wafer 110 due to sagging that occurs during the CMP process. In these embodiments, an insulating layer (not separately shown) surrounding the protruding portion of the conductive via 120 may be selectively formed on the back surface of the substrate 112. The insulating layer may be formed of a silicon-containing insulator such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition method such as spin coating, CVD, plasma Enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), or the like. After thinning the substrate 112, the exposed surfaces of the conductive vias 120 and the insulating layer (if present) or substrate 112 are coplanar (within process variations) such that they are flush with each other and exposed at the backside of the wafer 110.

In fig. 6, UBM 146 is formed on the exposed surfaces of conductive via 120 and substrate 112. As an example of forming UBM 146 in the present embodiment, a seed layer (not separately shown) is formed on the exposed surfaces of conductive via 120 and substrate 112. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using PVD, for example. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed through a spin coating process or the like, and the photoresist may be exposed to light to be patterned. The pattern of the photoresist corresponds to UBM 146. Openings are patterned through the photoresist to expose the seed layer. A conductive material is then formed in the opening of the photoresist and over the exposed portion of the seed layer. The conductive material may be formed by a plating or the like process such as electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. Then, the photoresist and portions of the seed layer where the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process. The remaining portion of the seed layer and the conductive material form UBM 146.

Further, a conductive connector 148 is formed on UBM 146. The conductive connectors 148 may be Ball Grid Array (BGA) connectors, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel palladium immersion gold (ENEPIG) techniques, or the like. The conductive connector 148 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 148 is formed by initially forming a solder layer by evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 148 includes a metal pillar (e.g., copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and may be formed by a plating process.

In fig. 7, a backside metal 212 is formed along the backside surface of the package assembly 210. The backside metal 212 is formed from one or more layers. The backside metal 212 may include multiple layers, each having different compositions and functions, such as adhesion layers, diffusion barrier layers, and oxidation resistance layers. In some embodiments, at least one of the layers is formed of a material having a high thermal conductivity. One or more layers of the backside metal 212 may be formed of a metal or metal nitride, such as aluminum, titanium nitride, nickel vanadium, silver, gold, copper, etc., which may be conformally formed by a PVD process such as sputtering or evaporation, a plating process such as electroless plating or electroplating, a printing process such as inkjet printing, etc. The backside metal 212 will then be singulated such that each package assembly 210 includes portions of the backside metal 212.

Although the backside metal 212 is shown as being formed after the conductive connector 148, in some embodiments the backside metal 212 may be formed before the conductive connector 148.

Further, the dicing process is performed by cutting along the scribe line region (e.g., around the package region 100A). The singulation process may include sawing, cutting, and the like. For example, the singulation process may include sawing the encapsulant 136, the interconnect structure 114, and the substrate 112. The singulation process separates the package regions 100A from adjacent package regions. Thereby creating singulated package assemblies 210 from package area 100A. The singulation process forms the interposer 102 from separate portions of the wafer 110. As a result of the singulation process, the outer sidewalls of the interposer 102, the backside metal 212, and the encapsulant 136 are laterally co-planar (within process variations).

Fig. 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14 illustrate various additional steps in manufacturing an embodiment package. The package assembly 210 including the heat dissipation structure will be attached to a package substrate 220 (see fig. 13) to complete the formation of the integrated circuit package 200. A single package assembly 210, a single package substrate 220, and a single integrated circuit package 200 are shown. It should be appreciated that multiple package assemblies may be processed simultaneously to form multiple integrated circuit packages 200.

In fig. 8, package assembly 210 is attached to package substrate 220 using conductive connectors 148. The package substrate 220 includes a substrate core 222, and the substrate core 222 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Further, the substrate core 222 may be an SOI substrate. Typically, the SOI substrate comprises a layer formed of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In another embodiment, the substrate core 222 is an insulating core, such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR 4. Alternatives to the core material include Bismaleimide Triazine (BT) resin, or other Printed Circuit Board (PCB) materials or films. The substrate core 222 may use a laminate film, such as a flavourant laminate film (ABF) or other laminate film.

The substrate core 222 may include active devices and passive devices (not separately shown). Transistors, capacitors, resistors, combinations thereof, and the like may be used to generate the structural and functional requirements of the system design. The devices may be formed using any suitable method.

The substrate core 222 may also include a metallization layer and a via, and a bond pad 224 over the metallization layer and the via. Metallization layers may be formed on the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layer may be composed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers and may be formed by any suitable process (e.g., deposition, damascene, etc.). In some embodiments, substrate core 222 is substantially free of active devices and passive devices.

The conductive connector 148 is reflowed to attach the UBM 146 to the bond pad 224. The conductive connectors 148 connect the package assembly 210 (including the interconnect structure 114) to a package substrate 220 (including the metallization layer of the substrate core 222). Thus, the package substrate 220 is electrically connected to the integrated circuit die 50. In some embodiments, passive devices (e.g., surface Mounted Devices (SMDs), not separately shown) may be connected to package assembly 210 (e.g., to UBM 146) prior to mounting on package substrate 220. In these embodiments, the passive devices may be bonded to the same surface of the package assembly 210 as the conductive connectors 148. In some embodiments, passive devices 226 (e.g., SMDs) may be attached to the package substrate 220, such as to the bond pads 224.

In some embodiments, an underfill 228 is formed between the package assembly 210 and the package substrate 220 that surrounds the conductive connectors 148. The underfill 288 may be formed by a capillary flow process after the package assembly 210 is attached, or may be formed by any suitable deposition method prior to the package assembly 210 is attached. The underfill 228 may be a continuous material that extends from the package substrate 220 to the substrate 112.

Although not shown, the package substrate 220 may have conductive connectors formed on bonding pads on a side of the package assembly 210 opposite the package substrate 220 (bottom side in fig. 8).

In fig. 9A and 9B, the backside metal 212 is coated with a flux 214. In some embodiments, the flux 214 is a clean-free flux. Flux 214 may be sprayed onto the backside metal 212. As shown in the plan view of fig. 9B, the flux 214 substantially covers the backside metal 212 (within process variations). In another embodiment, the flux 214 does not substantially cover the backside metal 212.

In fig. 10, a Thermal Interface Material (TIM) 232 is placed on the package assembly 210 using a pick and place tool. For some embodiments, TIM232 is formed on a separate structure (e.g., wafer or carrier) and then placed on package assembly 210. TIM232 comprises indium, silver, tin, or the like, or alloys thereof. Thickness T of TIM232 ₁ In the range of 10 μm to 1000 μm, such as 100 μm. For some embodiments, TIM232 is thicker than backside metal 212. For some embodiments, TIM232 has the same width as package assembly 210. For some embodiments, TIM232 may have the same area (in plan view) as package assembly 210. In other embodiments. The widths and areas of TIM232 and package assembly 210 may be different (see, e.g., fig. 15).

For fig. 11, TIM232 is coated with a flux 234. In some embodiments, the flux 344 is a clean-free flux. The flux 234 may be sprayed onto the TIM 232. Similar to the solder flux 214, the solder flux 234 substantially covers the TIM232 (within process variations). For another embodiment, the solder flux 234 does not substantially cover the TIM 232.

In fig. 12A and 12B, an adhesive 216 and a retaining structure 218 are formed on a package substrate 220. The adhesive 216 is used to subsequently adhere the cover 230 (see fig. 13) to the package substrate 220. Retaining structure 218 is used to retain any subsequent bleed or reflow of TIM232 to prevent TIM232 from reaching, for example, passive device 226, etc. The adhesive 216 may be a Thermal Interface Material (TIM), die Attach Film (DAF), or the like, and may be dispensed on a package substrate. For example, the adhesive 216 may be a gel containing a polymeric material and a filler. The polymeric material of the gel may be PI, PBO, epoxy-based polymer, silicon-based polymer, acrylic-based polymer, or the like, or a combination thereof. The filler of the gel may include aluminum, copper, tin, boron nitride, and the like, or combinations thereof.

In some embodiments, the retaining structure 218 may be formed simultaneously with the adhesive 216 and of the same material as the adhesive 216. In some embodiments, the retaining structure 218 may be formed from a material other than the adhesive 216. The retaining structure 218 may be dispensed on the package substrate 220, the underfill 228, and/or the package assembly 210. For some embodiments, retaining structures 218 are formed on sidewalls of package assembly 210 and on sidewalls and top surfaces of TIM 232. In some embodiments, the retaining structure is spaced apart from the package assembly 210 (see, e.g., fig. 16-19). The retaining structure 228 may be formed on the underfill 228. In some embodiments, the retaining structure 218 completely covers the underfill 228 outside of the package assembly 210, while in other embodiments, the retaining structure 218 only partially covers the underfill 228.

In some embodiments, retaining structure 218 is formed to have a top surface that is higher than the top surface of TIM232, while in other embodiments, the top surface of retaining structure 218 is lower than the top surface of TIM 232. As shown in fig. 12B, the retaining structure 218 may surround the package assembly 210, and the adhesive 216 may be formed along an edge of the package substrate 220.

Although retaining structure 218 is shown with flat and parallel sidewalls, the present invention is not limited to the shape of retaining structure 218 as shown. For example, the retaining structure 288 may have curved, bent, angled, and/or non-parallel sidewalls.

In fig. 13, a cover 230 with an optional backside metal 236 is attached to TIM 232 and package substrate 220. The cover 230 may be a thermally conductive cover, a heat sink, or the like. In the illustrated embodiment, the cover 230 is a thermally conductive cover that is also attached to the package substrate 220. The bottom of the thermally conductive cover has a recess so that the thermally conductive cover may cover the package assembly 210 and the TIM 232. In some embodiments where the cover 230 is a thermally conductive cover, the thermally conductive cover may also cover the passive devices 226. As shown in fig. 13, the retaining structure 218 may physically contact the cover 230. Retaining structure 218 will prevent subsequent bleeding of the material of TIM 232 onto package substrate 220 and/or passive device 226.

The cover 230 may be formed of a material having high thermal conductivity, such as metal, e.g., copper, nickel, indium, steel, iron, etc. In some embodiments, the cover 230 is composed of copper, nickel, and indium. The cover 230 protects the package assembly 210 and forms a thermally conductive path to conduct heat from various components of the package assembly 210 (e.g., the integrated circuit die 50). The cover 230 is thermally coupled to a backside surface of the package assembly 210, such as the backside surface of the backside metal 212, by a TIM 232 and an optional backside metal 236. The back side metal 236 may be similar to the back side metal 212 described above and will not be repeated here. The backside metal 236 may be formed on the flux 234 or the cover 230 prior to attaching the cover 230.

For some embodiments, lid 230 is attached and TIM 232 is bonded in a multi-step process. After a multi-step process, TIM 232 may have a thickness T less than after placement on package assembly 210 ₁ Thickness T of (2) ₂ . In a first process step, lid 230 is attached to TIM 232 and package substrate 220 by a thermal clamping process. In some embodiments, the thermal clamping process involves heating the structure while applying force to the cover 230 and/or the package substrate 220. In the thermal clamping process, the heating temperature is below the melting temperature of the metal of TIM 232. For example, if TIM 232 is made of indium having a melting temperature of 156.6C, the heating temperature of the thermal clamping process will remain below 156.6C.

In a second process step, TIM 232 is bonded or connected to backside metal 212/236 and lid 230. The second process step involves heating the structure to a temperature above the melting temperature of the metal of TIM 232. For example, if TIM 232 is made of indium with a melting temperature of 156.6C, the heating temperature of the thermal clamping process will reach over 156.6C. In some embodiments, the second process step also involves a thermal clamping process, including heating the structure while applying force to the cover 230 and/or the package substrate 220. For some embodiments, all steps of the multi-step process of attaching cover 230 and connecting TIM 232 are performed in the same process chamber without damaging the environment of the chamber.

By having retaining structure 218, any subsequent bleeding or reflow of the metal (e.g., indium) of TIM 232 during thermal clamping, reflow, or normal operation of the package is thus inhibited. This inhibition may prevent metal overflow from shorting the package assembly and void formation in TIM 232, thereby improving package reliability and performance.

Other components and processes may also be included. For example, test structures may be included for use in performing verification tests on a helper 3D package or 3DIC device. The test structures may, for example, include test pads formed in the redistribution layer or on the substrate to enable testing of the 3D package or 3DIC, use of probes and/or probe cards, and the like. The intermediate structure and the final structure may be subjected to a verification test. Furthermore, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good die to improve yield and reduce cost.

Fig. 14 shows an optional step of clip curing the package 200. In some embodiments, the clamp cure process may replace the second step of the multi-step process described above in fig. 13. As shown in fig. 14, the package 200 is placed in a jig 250, and heat may be applied to the package 200. For some embodiments, the pinch-cure process involves heating the structure to a temperature above the melting temperature of the metal of TIM 232. For example, if TIM 232 is made of indium with a melting temperature of 156.6C, the heating temperature of the thermal clamping process will be higher than 156.6C. In some embodiments, this second process step also involves a thermal clamping process, including heating the structure while applying force to the cover 230 and/or the package substrate 220.

Fig. 15 illustrates a cross-sectional view of an integrated circuit package 200 according to other embodiments. This embodiment is similar to the embodiment described in fig. 1-14, except that the TIM 232 is smaller in width than the package assembly 210 and the retaining structure 218 extends above the encapsulant 136 and the top surface of the backside metal 212. Width W of TIM 232, for some embodiments ₂ May be smaller than the width W of the package assembly 210 ₁ 。

Fig. 16-19 are views of intermediate stages in the manufacture of an integrated circuit package 200 according to other embodiments. This embodiment is similar to the embodiment described in fig. 1-14, except that the retaining structure 218 does not contact the package assembly 210, but is spaced apart from the package assembly 210. After attaching the cover 230, the space between the retaining structure 218 and the package assembly 210 may form a void. The void may accommodate the reflowed metal of TIM 232.

The process points in fig. 16 are similar to those in fig. 11, and a description of the implementation of this process stage will not be repeated here.

In fig. 17A and 17B, the retaining structure 218 and the adhesive 216 are formed on a package substrate 220. The materials and processes of the retaining structure 218 and the adhesive 216 may be similar to those described above in fig. 12A and 12B.

In this embodiment, the retaining structure 218 is spaced apart from the package assembly 210. Although retaining structure 218 is shown as having a top surface that is higher than the top surface of TIM 232, in other embodiments, the top surface of retaining structure 228 may be lower than the top surface of TIM 232. Similar to the description of fig. 12B, in fig. 17B, the retaining structure 218 may surround the package assembly 210, and the adhesive 216 may be formed along an edge of the package substrate 220.

In fig. 18, a cover 230 with an optional backside metal 236 is attached to the TIM 232 and the package substrate 220. The retaining structure 218 forms a void 238 between the package assembly 210 and the retaining structure 218. As shown in fig. 18, the retaining structure 218 may be in physical contact with the cover 230 such that the cover 230 forms a surface of the void 238. After melting of the metal of TIM 232, voids 238 formed by retaining structure 218 will accommodate the material of TIM 232 (see, e.g., fig. 19).

In fig. 19, the structure of fig. 18 undergoes the multi-step attachment and bonding process described above in fig. 13, resulting in overflow 232' of TIM 232 onto the sides of package assembly 210 and underfill 228, as well as onto package substrate 220. Although FIG. 19 illustrates overflow 232' substantially filling void 238, in some embodiments void 238 is only partially filled.

By having void 238 formed by retaining structure 218, the metal (e.g., indium) that accommodates TIM 232 bleeds or reflows during thermal clamping, reflow, or any subsequent operation of the package. This accommodation prevents metal from spilling out to short the package assembly and prevents void formation in TIM 232, thereby improving package reliability and performance.

Embodiments may take advantage of this. In some embodiments, the heat spreading structure is attached to the package assembly after the package assembly is attached to the package substrate. A retaining structure (e.g., a retaining wall) may be formed on the package substrate proximate the package assembly and the heat dissipating structure. The cover may then be attached to the heat dissipating structure and the retaining structure, and then subjected to a thermal clamping and/or reflow process to attach the cover and/or the heat dissipating structure. By having the retaining structure, any subsequent bleeding or reflow of the metal (e.g., indium) of the heat dissipating structure during thermal clamping, reflow, or normal operation of the package is inhibited. This suppression can prevent metal from overflowing to short the package assembly and prevent void formation in the heat dissipation structure, thereby improving the reliability and performance of the package.

In one embodiment, an integrated circuit package includes a package assembly including an integrated circuit die and a conductive connector connected to the integrated circuit die, the conductive connector disposed at a first side of the package assembly. The device also includes a metal layer on a second side of the package assembly, the second side being opposite the first side. The device also includes a thermal interface material on the metal layer. The device also includes a cover over the thermal interface material. The device also includes a retaining structure on the package assembly and the sidewall of the thermal interface material. The device further includes a package substrate connected to the conductive connector, the cover being adhered to the package substrate.

Implementations may include one or more of the following features. The retaining structure extends above the top surface of the package assembly. The thermal interface material is made of indium. The retaining structure is in physical contact with the closure. The thermal interface material is thicker than the backside metal layer. The device further includes an underfill between the package substrate and the package assembly, the retention structure being in physical contact with the underfill. The package is a chip-on-wafer package. The retaining structure includes a polymeric material and a filler material. The device further includes an adhesive adhering the cover to the package substrate, the adhesive and the retaining structure having the same material composition.

In one embodiment, a method of forming an integrated circuit package includes packaging an integrated circuit die in a packaging region of a wafer. The method further includes depositing a backside metal layer on the backside of the integrated circuit die. The method further includes dividing the package region from the wafer to form a package assembly. The method further includes connecting the package assembly to the package substrate after the dividing the package regions. The method further includes placing a thermal interface material on the backside metal layer. The method further includes dispensing a retention structure adjacent the package assembly and the thermal interface material. The method also includes attaching a cover to the package substrate, the cover coupled to the thermal interface material. The method further includes performing a bonding process to bond the thermal interface material to the backside metal layer and the lid, the bonding process being performed at a temperature above a melting point of the thermal interface material.

Implementations may include one or more of the following features. The retaining structure is in physical contact with the package assembly. The retaining structure is spaced apart from the package assembly. After the bonding process is performed, an overflow portion of the thermal interface material extends over the sidewalls of the package assembly. An underfill is formed between the package substrate and the package assembly wherein an overflow portion of the thermal interface material extends over the sidewalls of the underfill after the bonding process is performed. The retaining structure is in physical contact with the closure. The method further includes dispensing an adhesive layer on the top surface of the package substrate after placing the thermal interface material on the backside metal layer and before attaching the lid to the package substrate, the adhesive layer adhering the lid to the package substrate. The adhesive layer and the retaining structure have the same material composition.

In one embodiment, a method of forming an integrated circuit package includes bonding a plurality of integrated circuit dies to a wafer in a package region of the wafer. The method also includes encapsulating the plurality of integrated circuit dies with a molding compound. The method also includes forming a backside metal layer on the backside of the molding compound and the plurality of integrated circuit dies. The method further includes dividing the package region from the wafer to form a package assembly. The method further includes bonding the package assembly to a package substrate. The method further includes depositing a first flux on a backside of the integrated circuit die of the bonded package assembly. The method also includes attaching a thermal interface material to the first flux, the thermal interface material including indium. The method further includes forming a retaining structure adjacent the package assembly and the thermal interface material. The method further includes attaching a cover to the package substrate, the thermal interface material and the retaining structure being coupled to the cover.

Implementations may include one or more of the following features. The method further includes performing a bonding process to bond the thermal interface material to the backside metal layer and the lid, the bonding process being performed at a temperature above a melting point of the thermal interface material, wherein after the bonding process is performed, an overflow portion of the thermal interface material extends over the sidewalls of the package assembly. The retaining structure is in physical contact with the package assembly.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit package, comprising:

a package assembly including an integrated circuit die and a conductive connector connected to the integrated circuit die, the conductive connector disposed at a first side of the package assembly;

A metal layer on a second side of the package assembly, the second side being opposite the first side;

a thermal interface material on the metal layer;

a cover positioned over the thermal interface material;

a retaining structure located on a sidewall of the package group and the thermal interface material; and

a package substrate connected to the conductive connector, the cover being adhered to the package substrate.

2. The integrated circuit package of claim 1, wherein the retaining structure extends above a top surface of the package assembly.

3. The integrated circuit package of claim 1, wherein the thermal interface material is made of indium.

4. The integrated circuit package of claim 1, wherein the retaining structure is in physical contact with the cover.

5. The integrated circuit package of claim 1, wherein the thermal interface material is thicker than the metal layer.

6. The integrated circuit package of claim 1, further comprising:

an underfill between the package substrate and the package assembly, the retention structure in physical contact with the underfill.

7. The integrated circuit package of claim 1, wherein the package is a chip-on-wafer package.

8. The integrated circuit package of claim 1, wherein the retention structure comprises a polymeric material and a filler material.

9. A method of forming an integrated circuit package, comprising:

packaging the integrated circuit die in a packaging region of the wafer;

depositing a backside metal layer on a backside of the integrated circuit die;

dividing the packaging region and the wafer to form a packaging assembly;

after the encapsulation areas are separated, connecting the encapsulation assembly to an encapsulation substrate;

placing a thermal interface material on the backside metal layer;

a thermal interface material dispensing retaining structure adjacent to the package assembly and the thermal interface material;

attaching a cover to the package substrate, the cover coupled to the thermal interface material; and

a bonding process is performed to bond the thermal interface material to the backside metal layer and the cover, the bonding process being performed at a temperature above a melting point of the thermal interface material.

10. A method of forming an integrated circuit package, comprising:

bonding a plurality of integrated circuit dies to a wafer in a package region of the wafer;

encapsulating the plurality of integrated circuit dies with a molding compound;

Forming a backside metal layer on a backside of the molding compound and the plurality of integrated circuit dies;

dividing the packaging region and the wafer to form a packaging assembly;

bonding the package assembly to a package substrate;

depositing a first flux on a backside of the integrated circuit die of the bonded package assembly;

attaching a thermal interface material to the first flux, the thermal interface material comprising indium;

forming a retaining structure adjacent to the package assembly and the thermal interface material; and

a cover is attached to the package substrate, the thermal interface material and the retaining structure being coupled to the cover.