CN116741217A

CN116741217A - Magnetic random access memory cell, read-write method and memory

Info

Publication number: CN116741217A
Application number: CN202310817783.1A
Authority: CN
Inventors: 王朝; 王昭昊; 刘旭; 赵巍胜
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2023-07-05
Filing date: 2023-07-05
Publication date: 2023-09-12

Abstract

The invention provides a magnetic random access memory unit, which comprises a first memory, a second memory, a first switching element and a second switching element; wherein the first memory includes a first spin-orbit torque layer and a first magnetic tunnel junction disposed on the first spin-orbit torque layer; the second memory comprises a second spin-orbit torque layer and a second magnetic tunnel junction arranged on the second spin-orbit torque layer, wherein a first input end of the first spin-orbit torque layer is connected with a first signal line through the first switching element, a first output end of the first spin-orbit torque layer is connected with a second input end of the second spin-orbit torque layer through the second switching element, and a second output end of the second spin-orbit torque layer is connected with a second signal line; the invention can solve the problems of complex process and poor data reading and writing performance of the existing magnetic random memory unit for multi-bit data storage.

Description

Magnetic random access memory cell, read-write method and memory

Technical Field

The present invention relates to the field of semiconductor devices, and in particular, to a magnetic random access memory, a read-write method, and a memory.

Background

With the continuous shrinking of semiconductor process dimensions, moore's law slows down, and the increase in leakage current and interconnect delay become bottlenecks in conventional CMOS memories. The magnetic random access memory (Magnetic Random Access Memory, MRAM) has the advantages of unlimited erasing times, non-volatility, high reading and writing speed, irradiation resistance and the like, is hopeful to become a general memory, and is an ideal device for constructing the next generation of nonvolatile main memory and cache. Magnetic tunnel junctions (Magnetic Tunnel Junction, MTJs) are the basic memory cells of magnetic random access memories. Spin-Transfer Torque magnetic random access memory (STT-MRAM) has the defects of long incubation time, read-write interference and the like, and further development of the Spin-Transfer Torque magnetic random access memory is limited. Spin-Orbit Torque magnetic random access memory (SOT-MRAM) is widely paid attention to in industry and academia due to the advantages of high writing speed, separation of read and write paths, low power consumption and the like.

To increase the storage density, writing of various data is currently typically achieved with multiple MTJ-Level cells (MLCs), which requires careful adjustment of the characteristics of each MTJ to achieve different threshold switching currents and resistance states with sufficient margin. A typical MLC is achieved by connecting MTJs in two planes in series, the MTJs having different areas, where the fabrication process typically involves multiple etching steps, the process is complex, and one-step writing of data is difficult to achieve.

Disclosure of Invention

The invention aims to provide a magnetic random access memory unit, which solves the problems of complex process and poor data reading and writing performance of the existing magnetic random access memory unit for multi-bit data storage. Another object of the present invention is to provide a data writing method. It is still another object of the present invention to provide a data reading method. It is a further object of the present invention to provide a magnetic random access memory.

In order to achieve the above object, one aspect of the present invention discloses a magnetic random access memory unit, which includes a first memory, a second memory, a first switching element, and a second switching element;

wherein the first memory includes a first spin-orbit torque layer and a first magnetic tunnel junction disposed on the first spin-orbit torque layer; the second memory includes a second spin-orbit torque layer, a second magnetic tunnel junction disposed on the second spin-orbit torque layer, the first magnetic tunnel junction and the second magnetic tunnel junction being electrically connected;

the first spin-orbit torque layer comprises a first input end and a first output end for transmitting spin-orbit torque current, and the second spin-orbit torque layer comprises a second input end and a second output end for transmitting spin-orbit torque current;

The first input end of the first spin orbit moment layer is connected with a first signal line through the first switching element, the first output end of the first spin orbit moment layer is connected with the second input end of the second spin orbit moment layer through the second switching element, and the second output end of the second spin orbit moment layer is connected with a second signal line;

the critical switching currents of the first magnetic tunnel junction and the second magnetic tunnel junction are different, the first switching element and the second switching element are turned on when data is written, and the first switching element is turned on and the second switching element is turned off when data is read.

Preferably, the first magnetic tunnel junction comprises a first fixed layer, a first barrier layer and a first free layer which are sequentially arranged from top to bottom;

the second magnetic tunnel junction comprises a second fixed layer, a second barrier layer and a second free layer which are sequentially arranged from top to bottom;

the first free layer of the first magnetic tunnel junction is fixed with the first spin-orbit torque layer, and the second free layer of the second magnetic tunnel junction is fixed with the second spin-orbit torque layer.

Preferably, the critical switching currents of the first free layer and the second free layer of the first magnetic tunnel junction and the second magnetic tunnel junction are different.

Preferably, the cross-sectional area of the first spin-orbit torque layer of the first magnetic tunnel junction is greater than the cross-sectional area of the second spin-orbit torque layer of the second magnetic tunnel junction; and/or the number of the groups of groups,

the free layer of the first magnetic tunnel junction has an area greater than an area of the free layer of the second magnetic tunnel junction.

Preferably, the first barrier layer and the second barrier layer of the first magnetic tunnel junction and the second magnetic tunnel junction are different in area.

Preferably, the first fixed layer of the first magnetic tunnel junction and the second fixed layer of the second magnetic tunnel junction are electrically connected.

Preferably, a first electrode fixedly connected with the first fixed layer is arranged at the top of the first magnetic tunnel junction, and a second electrode fixedly connected with the second fixed layer is arranged at the top of the second magnetic tunnel junction;

the first electrode of the first magnetic tunnel junction is electrically connected with the second electrode of the second magnetic tunnel junction.

Preferably, the first switching element includes a first transistor;

the control end of the first transistor is connected with a first control line for inputting a first control signal, the first end of the first transistor is connected with a first signal line for inputting a first write signal, and the second end of the first transistor is connected with a first input end of the first spin orbit moment layer.

Preferably, the second switching element includes a second transistor;

the control end of the second transistor is connected with a second control line for inputting a second control signal, the first end of the second transistor is connected with the first output end of the first spin orbit moment layer, and the second end of the second transistor is connected with the first input end of the second spin orbit moment layer.

Preferably, a first input end of the first spin orbit torque layer is provided with a first input electrode, and a first output end of the first spin orbit torque layer is provided with a first output electrode;

the second end of the first transistor is electrically connected with the first input electrode.

Preferably, a second input end of the second spin orbit torque layer is provided with a second input electrode, and a second output end of the second spin orbit torque layer is provided with a second output electrode connected with a second signal line for inputting a second write signal;

the first end of the second transistor is electrically connected with the first output electrode, and the second end of the second transistor is electrically connected with the second input electrode.

Preferably, the circuit further comprises a data writing module, wherein the data writing module is used for determining at least one signal to be written according to data to be written, the signal to be written is a first writing signal input by a first signal line or a second writing signal input by a second signal line, determining the current magnitude of the signal to be written according to critical flip currents of the first magnetic tunnel junction and the second magnetic tunnel junction, controlling the first switching element and the second switching element to be conducted, and inputting the at least one signal to be written.

Preferably, the data writing module is specifically configured to determine, through the reading module, a series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction, determine, according to the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction, whether resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction need to be changed, and if so, form a corresponding signal to be written.

Preferably, the reading module is used for controlling the first switching element to be turned on and controlling the second switching element to be turned off; and inputting a read voltage, determining the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction according to the change of the read voltage, and determining the data stored in the first memory and the second memory according to the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction.

The invention also discloses a data writing method of the magnetic random access memory unit, which comprises the following steps:

determining at least one signal to be written according to data to be written, wherein the signal to be written is a first writing signal input by a first signal line or a second writing signal input by a second signal line;

determining the current magnitude of the signal to be written according to the critical flip currents of the first magnetic tunnel junction and the second magnetic tunnel junction;

And controlling the first switching element and the second switching element to be conducted, and inputting the at least one signal to be written.

Preferably, the determining at least one signal to be written according to the data to be written specifically includes:

determining, by a read module, a series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction;

and determining whether the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction need to be changed according to the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction, and if so, forming corresponding signals to be written.

The invention also discloses a data reading method of the magnetic random access memory unit, which comprises the following steps:

controlling the first switching element to be conducted and controlling the second switching element to be disconnected;

and inputting a read voltage, determining the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction according to the change of the read voltage, and determining the data stored in the first memory and the second memory according to the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction.

The invention also discloses a magnetic random access memory which comprises a plurality of magnetic random access memory units which are arranged in an array manner.

The first spin orbit moment layer of the first memory of the magnetic random access memory unit is connected with a first signal line through a first switch element, the first spin orbit moment layer is connected with the second spin orbit moment layer of the second memory through a second switch element, and the second spin orbit moment layer is further connected with a second signal line. And the first magnetic tunnel junction is electrically connected with the second magnetic tunnel junction. The critical flip currents of the first magnetic tunnel junction and the second magnetic tunnel junction are different, so that when data is written, the first switching element and the second switching element are conducted, and the first magnetic tunnel junction and the second magnetic tunnel junction are enabled to present four different resistor combinations by controlling the magnitude and the direction of the current input into the first spin-orbit moment layer and the second spin-orbit moment layer, so that 2-bit data storage is realized. When data is read, the first switching element is turned on, the second switching element is turned off, and the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series to read the data.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art magnetic random access memory cell;

FIG. 2 is a schematic diagram of another prior art magnetic random access memory cell;

FIG. 3 is a schematic diagram of yet another prior art magnetic random access memory cell;

FIG. 4 is a schematic diagram of a magnetic random access memory cell of the present invention;

FIG. 5 is a schematic diagram of the magnetic random access memory cell data writing of the present invention;

FIG. 6 is a schematic diagram of a magnetic random access memory cell according to the present invention;

FIG. 7 is a schematic diagram of a magnetic random access memory of the present invention;

fig. 8 shows a schematic structural diagram of the computer device of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In one or more embodiments of the invention, the MRAM (Magnetic Random Access Memory ) is a Non-Volatile (Non-Volatile) magnetic random access memory. MRAM has high-speed read-write capability of Static Random Access Memory (SRAM) and high integration of Dynamic Random Access Memory (DRAM), and can be basically rewritten indefinitely.

In one or more embodiments of the invention, an MTJ (Magnetic Tunnel Junction, magnetic tunnel junction device) is a magnetic memory device capable of storing 1 bit (bit) of data, the data value depending on its magnetic moment direction.

In one or more embodiments of the present invention, STT (Spin-Transfer Torque) is a technique that can cause the magnetic moment of a magnetic tunnel junction device to flip.

In one or more embodiments of the present invention, SOT (Spin-Orbit Torque) refers to a technique in which a heavy metal layer is provided under a magnetic tunnel junction, and a current flows through the heavy metal layer to cause the magnetic moment of the magnetic tunnel junction to be inverted.

In one or more embodiments of the invention, the SOT-MTJ uses the SOT principle to flip the MTJ magnetic moment, and the SOT-MTJ uses a heavy metal layer as the spin-orbit torque layer, which constitutes the SOT-MTJ with a magnetic tunnel junction thereon.

In one or more embodiments of the present invention, bit-Cell is the memory Cell, the smallest unit of stored data, and in MRAM, a Bit-Cell is typically composed of one or several MOS transistors and one or several MTJs.

In one or more embodiments of the present invention, MLC (Multi-Level Cell) refers to a technology of storing Multi-Bit (Bit) data in one Bit-Cell, thereby increasing storage density.

In the prior art, as shown in fig. 1, in order to realize multi-bit data storage, a magnetic random access memory is provided with three magnetic tunnel junctions MTJ6, MTJ7 and MTJ8 longitudinally overlapped, and a reading electrode 21 is disposed on top of MTJ 8. The bottom layer is a spin coupling layer 24 provided with an SOT current input electrode 22 and an SOT current output electrode 23.MTJ6, MTJ7, and MTJ8 comprise a fixed layer 12, barrier layer 13, and free layer 14, respectively. In this structure, SOT current and STT current are required to act together to achieve writing of multiple resistance states. The critical switching current of the magnetic tunnel junction is different due to the different dimensions. Such as MTJ6, may have a strong STT write, or may be implemented by SOT current plus STT. While MTJ7 and MTJ8 magnetic tunnel junctions are primarily data written by STT current. However, the magnetic random access memory adopts STT writing, the writing speed is low, and simultaneously, three magnetic tunnel junctions are longitudinally overlapped, and multiple times of etching are needed in manufacturing, so that the forming process is complex and the cost is high.

FIG. 2 shows another tandem MLC (S-MLC) Bit-Cell structure, where the memory Cell is a STT-MTJ (MTJ 1) regrown on an SOT-MTJ (MTJ 2). When writing MTJ1, WLa is off and WLb is on; when writing MTJ2, WLa is turned on and WLb is turned off; WLa is closed and WLb is open during read operation, SL and BL are read-write current input lines. STT-MTJs are used in S-MLCs, and the slower flip speed of STT-MTJs reduces the write speed of the circuit. In addition, the STT-MTJ write current Iwrite is large, reducing the reliability of the MTJ. In addition, the film layers are too many, multiple times of etching are needed in manufacturing, and the process is complex.

FIG. 3 shows a parallel MLC (P-MLC) Bit-Cell structure with memory cells formed by two SOT magnetic tunnel junctions MTJ1 and MTJ2 in parallel, and with two SOTs having different critical switching currents. During writing operation, the WLb switching element is closed, the WLa switching element is opened, two MTJs are turned to the same state (the desired state of the magnetic tunnel junction which is not easy to turn over) by using a large current, and then the MTJ1 which is easy to turn over is turned to the desired state by using a small current; during read operation, WLa is closed, WLb is open, SL and BL are read-write current input lines. The P-MLC uses a parallel structure, which can greatly reduce the read margin. For example, MTJ2 is low resistance 10kΩ, high resistance 30kΩ, MTJ1 is low resistance 20kΩ, high resistance 60kΩ, four resistances in parallel are 6.7kΩ, 8.6kΩ, 12kΩ, and 20kΩ, respectively, and four resistances in series are 30kΩ, 50kΩ, 70kΩ, and 90kΩ, respectively, and it is apparent that the series resistance margin is larger, and thus the reliability is higher, the reading speed is faster, any of the existing structures cannot simultaneously utilize the advantages of pure SOT writing and multiple magnetic tunnel junction series reading, for example, fig. 2 cannot be realized with pure SOT writing, and fig. 3 cannot utilize magnetic tunnel junction series reading, and writing needs to be structurally improved, but the direct combination of the schemes in the two prior arts of fig. 2 and 3 cannot achieve the effects of both advantages.

In this embodiment, the switching element being turned on indicates that the switching element is turned on, and the path in which the switching element is turned on may be opened, and the switching element being turned off indicates that the switching element is turned off, and the path in which the switching element is turned off may be opened. The electrical connection in the embodiment may be implemented by a direct contact manner or may be implemented by a non-direct contact manner, which is not limited in the present application.

In the existing SOT-MLC scheme, the STT+SOT type writing speed is low, but the reading speed and reliability are high, and the SOT parallel scheme is high in writing speed and low in reading speed and reliability, so that a more perfect solution is needed.

Based on the problems of the prior art, according to one aspect of the present application, as shown in fig. 4, the present embodiment discloses a magnetic random access memory cell. The magnetic random access memory unit includes a first memory, a second memory, a first switching element N0, and a second switching element N1.

Wherein the first memory includes a first spin-orbit torque layer 300 and a first magnetic tunnel junction MTJ0 disposed on the first spin-orbit torque layer 300; the second memory includes a second spin-orbit torque layer 400 and a second magnetic tunnel junction MTJ1 disposed on the second spin-orbit torque layer 400, the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 being electrically connected.

The first spin-orbit torque layer 300 includes a first input terminal and a first output terminal for transmitting spin-orbit torque current, and the second spin-orbit torque layer 400 includes a second input terminal and a second output terminal for transmitting spin-orbit torque current.

The first input terminal of the first spin-orbit torque layer 300 is connected to the first signal line BL through the first switching element N0, the first output terminal of the first spin-orbit torque layer 300 is connected to the second input terminal of the second spin-orbit torque layer 400 through the second switching element N1, and the second output terminal of the second spin-orbit torque layer 400 is connected to the second signal line SL.

The critical switching currents of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are different, the first switching element N0 and the second switching element N1 are turned on when data is written, the first switching element N0 is turned on when data is read, and the second switching element N1 is turned off.

The first spin-orbit torque layer 300 of the first memory of the magnetic random access memory unit of the present invention is connected to the first signal line BL through the first switching element N0, the first spin-orbit torque layer 300 is connected to the second spin-orbit torque layer 400 of the second memory through the second switching element N1, and the second spin-orbit torque layer 400 is further connected to the second signal line SL. And, the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are electrically connected. The critical switching currents of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are different, so that when data is written, the first switching element N0 and the second switching element N1 are turned on, and the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 exhibit four different resistance combinations by controlling the magnitudes and directions of currents input to the first spin-orbit torque layer 300 and the second spin-orbit torque layer 400, thereby realizing 2bit data storage, as shown in fig. 5. As shown in fig. 6, when data is read, the first switching element N0 is turned on, the second switching element N1 is turned off, the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are connected in series to read data, and the magnetic random access memory unit of the present invention writes data by inputting the SOT write current Iwrite, and reads data by determining the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction, only two switching elements are needed, and the forming process of the first memory and the second memory is simple, thereby reducing the cost of the magnetic random access memory and improving the read-write performance of the magnetic random access memory.

In a preferred embodiment, the first magnetic tunnel junction MTJ0 includes a first fixed layer 110, a first barrier layer 120, and a first free layer 130, which are sequentially disposed from top to bottom, respectively. The second magnetic tunnel junction MTJ1 includes a second fixed layer 210, a second barrier layer 220, and a second free layer 230 sequentially disposed from top to bottom; the first free layer 130 of the first magnetic tunnel junction MTJ0 is fixed with the first spin-orbit torque layer 300 and the second free layer 230 of the second magnetic tunnel junction MTJ1 is fixed with the second spin-orbit torque layer 400.

Specifically, the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are SOT-MTJs, respectively, which can store one bit of data. The films of the free layer, the fixed layer, the barrier layer and the like corresponding to the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are the same layer in the forming film stacking process, the materials and the thicknesses of the films of the layers are the same, and two SOT magnetic tunnel junctions with different sizes are formed through one etching process, so that the forming process of the magnetic random access memory unit is simpler and the cost is lower.

The resistance of the magnetic tunnel junction depends on the magnetization directions of the pinned and free layers, which are determined by the magnetic moment direction. The magnetic tunnel junction is in a low resistance state (low resistance state) when the magnetic moment directions of the fixed layer and the free layer are the same, and is in a high resistance state (high resistance state) when the magnetic moment directions of the fixed layer and the free layer are opposite. The high resistance state and the low resistance state of the magnetic tunnel junction may be respectively associated with different data in advance, for example, the high resistance state corresponds to data "1" and the low resistance state corresponds to data "0", and then a current or a voltage is input to the magnetic tunnel junction through the reading circuit, and it may be determined whether the resistance state of the magnetic tunnel junction is the resistance state of the high resistance state or the low resistance state according to a change of the current or the voltage, and it may be determined whether the data stored in the magnetic tunnel junction is "1" or "0" according to the resistance state of the magnetic tunnel junction. The high resistance state and the low resistance state are determined as common technical means in the art, and a person skilled in the art can determine the resistance value ranges of the high resistance state and the low resistance state of the magnetic tunnel junction according to common general knowledge, which is not described herein.

In a preferred embodiment, at least one of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 may further include an auxiliary layer disposed on the pinned layer, which may be used to stabilize a magnetic moment direction of the pinned layer, improving reliability of the magnetic random access memory cell.

Preferably, the spin-orbit torque layer is rectangular, so that the top surface area of the spin-orbit torque layer is larger than the area occupied by the magnetic tunnel junction arranged on the spin-orbit torque layer, and the outer edge of the magnetic tunnel junction is positioned on the inner side of the outer edge of the spin-orbit torque layer. The spin-orbit moment layer is preferably a heavy metal strip film or an antiferromagnetic strip film.

In a preferred embodiment, the critical switching currents of the first free layer 130 and the second free layer 230 of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are different.

It will be appreciated that the critical switching currents of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are different, even though the critical switching currents at which the magnetic moments of the free layers of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are deterministic to switch are different. For example, assuming that when the forward SOT current input to the first spin-orbit torque layer 300 is greater than the critical flip current of the free layer of the first magnetic tunnel junction MTJ0, the final magnetic moment direction of the first magnetic tunnel junction MTJ0 is parallel to the magnetic moment direction of the fixed layer of the first magnetic tunnel junction MTJ0, then when the negative SOT current input to the first spin-orbit torque layer 300 is greater than the critical flip current of the free layer of the first magnetic tunnel junction MTJ0, the final magnetic moment direction of the first magnetic tunnel junction MTJ0 is antiparallel to the magnetic moment direction of the fixed layer of the first magnetic tunnel junction MTJ 0. When the magnetic moment directions of the fixed layer and the free layer of the first magnetic tunnel junction MTJ0 are parallel, the resistance state of the first magnetic tunnel junction MTJ0 is a low resistance state. Conversely, when the magnetic moment directions of the fixed layer and the free layer of the first magnetic tunnel junction MTJ0 are antiparallel, the resistance state of the first magnetic tunnel junction MTJ0 is a high resistance state. Thus, the first magnetic tunnel junction MTJ0 can be made to assume two different resistance states by controlling the direction and magnitude of the SOT current. Similarly, the second magnetic tunnel junction MTJ1 can be made to assume two different resistance states by controlling the direction and magnitude of the SOT current. In the invention, the critical inversion currents of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are different, so that the directions and the magnitudes of the SOT currents input into the first spin-orbit torque layer 300 and the second spin-orbit torque layer 400 can be controlled, and four different resistance state combinations of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are realized.

Specifically, assume that the critical switching current IC0 of the first free layer 130 of the first magnetic tunnel junction MTJ0 is greater than the critical switching current IC1 of the second free layer 230 of the second magnetic tunnel junction MTJ 1. At the time of data writing, the first switching element N0 and the second switching element N1 are turned on, and a forward SOT current is input from the first signal line BL to the first spin-orbit torque layer 300, the second spin-orbit torque layer 400, and the second signal line SL such that the SOT current is greater than the critical switching current IC0 of the first free layer 130, and the first free layer 130 and the first fixed layer 110 of the first magnetic tunnel junction MTJ0 are switched to a parallel state (or antiparallel state). Similarly, a current from BL to SL through the second spin-orbit torque layer 400 exceeding IC1 causes the second magnetic tunnel junction MTJ1 to flip to the parallel (or antiparallel) state; the current from SL to BL through the first spin-orbit torque layer 300 exceeding IC0 causes the first magnetic tunnel junction MTJ0 to flip to an anti-parallel state (or parallel state); the current from SL to BL through the second spin-orbit torque layer 400 exceeding IC1 causes the second magnetic tunnel junction MTJ1 to flip to an anti-parallel state (or parallel state). The resistance states of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 obtained under the four current input conditions and the 2bit data obtained by corresponding storage are shown in table 1.

TABLE 1

MTJ0 magnetization state	MTJ1 magnetization state	Stored 2bit data [ MTJ0:MTJ1]
			Parallel to each other	Parallel to each other	11
Antiparallel arrangement	Parallel to each other	01
			Parallel to each other	Antiparallel arrangement	10
Antiparallel arrangement	Antiparallel arrangement	00

The first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are electrically connected, i.e., the first pinned layer 110 of the first magnetic tunnel junction MTJ0 is electrically connected with the second pinned layer 210 of the second magnetic tunnel junction MTJ 1. Specifically, a first electrode 140 fixedly connected to the first fixed layer 110 is disposed on the top of the first magnetic tunnel junction MTJ0, a second electrode 240 fixedly connected to the second fixed layer 210 is disposed on the top of the second magnetic tunnel junction MTJ1, and the first electrode 140 of the first magnetic tunnel junction MTJ0 is electrically connected to the second electrode 240 of the second magnetic tunnel junction MTJ 1. A first electrode 140 may be disposed on the first fixed layer 110 of the first magnetic tunnel junction MTJ0, a second electrode 240 may be disposed on the second fixed layer 210 of the second magnetic tunnel junction MTJ1, and the first electrode 140 may be electrically connected to the second electrode 240 to electrically connect the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ 1. In the data writing process, the SOT current mainly passes through the two switching elements and the two spin-orbit torque layers of the first spin-orbit torque layer 300 and the second spin-orbit torque layer 400, the shunt current (Ishunt) of a small amount of SOT current passes through the magnetic tunnel junction, the resistance of the magnetic tunnel junction is more than 20 times of the resistance of the spin-coupling layer and the on-resistance of the transistor, and the influence of Ishunt on the writing operation is negligible.

When reading data, the first switching element N0 is turned on, the second switching element N1 is turned off, and the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are connected in series in a loop from the first signal line BL to the second signal line SL due to the electrical connection of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ 1. Because the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 have different high and low resistance states and different resistance values of different resistance states when storing four types of 2bit data, four different resistance values can be obtained after the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are connected in series, and the numerical value of the 2bit data stored in the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 can be determined by reading the resistance values of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 after the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are connected in series.

In an alternative embodiment, the cross-sectional area of the first spin-orbit torque layer 300 of the first magnetic tunnel junction MTJ0 is greater than the cross-sectional area of the second spin-orbit torque layer 400 of the second magnetic tunnel junction MTJ 1.

Specifically, the width W0 of the first spin-orbit torque layer 300 of the first magnetic tunnel junction MTJ0 is greater than the width of the second spin-orbit torque layer 400 of the second magnetic tunnel junction MTJ1, so the area of the first section 330 of the first spin-orbit torque layer 300 is greater than the second section 430 of the first spin-orbit torque layer 300, which results in a smaller current density for the first section 330 than for the second section 430 when the same current flows through the first section 330 and the second section 430. The critical switching current of the first free layer 130 needs to be greater than the critical switching current of the second free layer 230 when the volume of the first free layer 130 of the first magnetic tunnel junction MTJ0 is the same as the volume of the second free layer 230 of the second magnetic tunnel junction MTJ 1. Wherein, when the film thicknesses and characteristics of the first free layer 130 and the second free layer 230 are the same, the area size of the first free layer 130 and the second free layer 230 is proportional to the volume size. Of course, the critical switching currents of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 may be determined through experiments, and the areas of the first free layer 130 and the second free layer 230 may be set to be different, so that the magnitude relation of the critical switching currents of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 may be ensured. In a preferred embodiment, the free layer of the first magnetic tunnel junction MTJ0 has an area greater than the free layer of the second magnetic tunnel junction MTJ 1.

In particular, when the film thicknesses and characteristics of the first and second free layers 130 and 230 are the same, the area sizes of the first and second free layers 130 and 230 are proportional to the volume sizes. Then the critical switching current of the first magnetic tunnel junction MTJ0 is greater than the second magnetic tunnel junction MTJ1 by setting the first free layer 130 area of the first magnetic tunnel junction MTJ0 to be greater than the second free layer 230 area of the second magnetic tunnel junction MTJ1.

In a preferred embodiment, the resistances of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are different. Thus, the low and high resistance states of the first and second magnetic tunnel junctions MTJ0 and MTJ1 may be connected in series to obtain four different series resistances.

In a preferred embodiment, the first barrier layer 120 and the second barrier layer 220 of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 have different areas, so that the resistances of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 can be different. For example, in the present embodiment, the thicknesses and characteristics of the film layers of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are the same, so that the area of the first barrier layer 120 of the first magnetic tunnel junction MTJ0 is larger than the area of the second barrier layer 220 of the second magnetic tunnel junction MTJ1, and the resistance of the second magnetic tunnel junction MTJ1 is larger than the resistance of the first magnetic tunnel junction MTJ 0.

In a preferred embodiment, the cross-sectional area of the first spin-orbit torque layer 300 of the first magnetic tunnel junction MTJ0 is greater than the cross-sectional area of the second spin-orbit torque layer 400 of the second magnetic tunnel junction MTJ1, and the area of the free layer of the first magnetic tunnel junction MTJ0 is greater than the area of the free layer of the second magnetic tunnel junction MTJ 1.

It is understood that the cross-sectional area of the first spin-orbit torque layer 300 is greater than the cross-sectional area of the second spin-orbit torque layer 400, and the current density of the first cross-section 330 is less than the second cross-section 430. Meanwhile, the area of the free layer of the first magnetic tunnel junction MTJ0 is larger than that of the free layer of the second magnetic tunnel junction MTJ1, so that the critical inversion current of the first magnetic tunnel junction MTJ0 is further ensured to be larger than that of the second magnetic tunnel junction MTJ 1.

It should be noted that, the positions of the first memory and the second memory may be interchanged, and the deterministic writing of 2bit data may also be implemented by controlling the magnitude and direction of the SOT current and defining the relationship between the resistance states of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 and the stored data, which may be set by those skilled in the art according to the actual situation and will not be described herein.

In a preferred embodiment, the first switching element N0 includes a first transistor. The control terminal of the first transistor is connected to a first control line WL inputting a first control signal, the first terminal is connected to a first signal line BL inputting a first write signal, and the second terminal is connected to a first input terminal of the first spin-orbit torque layer 300.

Wherein the control terminal of the first transistor is turned on in response to the first control signal of the first control line WL, and the first terminal transmits the SOT current inputted by the first write signal transmitted by the first signal line BL to the first spin-orbit torque layer 300 through the second terminal.

In a preferred embodiment, the second switching element N1 includes a second transistor. The control terminal of the second transistor is connected to a second control line WWL to which a second control signal is input, the first terminal is connected to the first output terminal of the first spin-orbit torque layer 300, and the second terminal is connected to the first input terminal of the second spin-orbit torque layer 400.

Wherein the control terminal of the second transistor is turned on or off in response to a second control signal of the second control line WWL, and when turned on, the first terminal thereof may transmit the SOT current of the first spin-orbit torque layer 300 to the second spin-orbit torque layer 400 through the second terminal. When disconnected, the loop in which the first spin-orbit torque layer 300 is connected in series with the second spin-orbit torque layer 400 is disconnected.

For example, as shown in fig. 5, taking the first transistor and the second transistor as NMOS as an example, when writing data, the first transistor is turned on in response to a high level by writing a first control signal of a high level (denoted as 1) to a control terminal of the first transistor by WL. The second transistor is turned on in response to the high level by writing a second control signal of the high level (denoted 1) to the control terminal of the second transistor via WWL.

When reading data, the first transistor is turned on in response to a high level by writing a first control signal of the high level (denoted as 1) to a control terminal of the first transistor by WL. The second control signal of low level (denoted as 0) is written to the control terminal of the second transistor by WWL, and the second transistor is not turned on when the low level acts, and maintains an off state.

In the preferred embodiment, the first switching element N0 is a first transistor, and in other embodiments, the first switching element N0 may be another control device, so long as the function of the first switching element N0 is achieved, and the present invention is not limited thereto. Similarly, in the preferred embodiment, the second switching element N1 is a second transistor, and in other embodiments, the second switching element N1 may be another control device, so long as the function of the second switching element N1 is achieved, which is not limited by the present invention. In this embodiment, the first transistor and the second transistor may be NMOS or PMOS, which is not limited in this invention. The control terminals of the first transistor and the second transistor are gates, the first terminal can be a source electrode or a drain electrode, and the second terminal can be a drain electrode or a source electrode.

In a preferred embodiment, a first input terminal of the first spin-orbit torque layer 300 is provided with a first input electrode 310, and a first output terminal of the first spin-orbit torque layer 300 is provided with a first output electrode 320; the second end of the first transistor is electrically connected to the first input electrode 310.

In a preferred embodiment, a second input terminal of the second spin-orbit torque layer 400 is provided with a second input electrode 410, and a second output terminal of the second spin-orbit torque layer 400 is provided with a second output electrode 420; the first end of the second transistor is electrically connected to the first output electrode 320, and the second end of the second transistor is electrically connected to the second input electrode 410.

It is understood that electrodes are provided in the current input/output directions of the first spin-orbit torque layer 300 and the second spin-orbit torque layer 400, respectively, and can be electrically connected to external signal lines and the first switching element N0 and the second switching element N1 to form a closed loop, thereby realizing data writing by writing the SOT write current Iwrite.

In a preferred embodiment, as shown in fig. 5, the magnetic random access memory cell further includes a data writing module. The data writing module is used for determining at least one signal to be written according to data to be written, wherein the signal to be written is a first writing signal or a second writing signal, and the current of the signal to be written is determined according to critical flip currents of the first magnetic tunnel junction (MTJ 0) and the second magnetic tunnel junction (MTJ 1); writing a first control signal into the control end of the first switching element N0 to enable the first switching element N0 to be conducted, writing a second control signal into the control end of the second switching element N1 to enable the second switching element N1 to be conducted, and inputting the at least one signal to be written.

In a preferred embodiment, the magnetic random access memory cell further comprises a read module. The reading module is configured to write a first control signal to a control terminal of the first switching element N0 to turn on the first switching element N0, and write a second control signal to a control terminal of the second switching element N1 to turn off the second switching element N1; and a read voltage is input through the first signal line BL and the second signal line SL, the resistance states of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are determined according to the change of the read voltage, namely, the read current Iread in a loop, and the data stored in the first memory and the second memory are determined according to the series resistances of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ 1.

In a preferred embodiment, as shown in fig. 6, when determining at least one signal to be written according to data to be written, the data writing module may determine, by the reading module, a series resistance of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1, and determine, according to resistance states of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1, whether the resistance states of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 need to be changed, if so, form the corresponding signal to be written.

It should be noted that, the data writing module and the reading module may be implemented by circuit structures, the specific circuit structures are designed as conventional technical means in the art, and those skilled in the art may implement the functions of the writing module and the reading module by adopting different circuit structures according to actual needs, which is not described herein again.

Preferably, the material of the electrode in this embodiment may be any one of tantalum Ta, aluminum Al, gold Au, or copper Cu.

Preferably, the materials of the free layer and the fixed layer may be ferromagnetic metals, and the material of the barrier layer may be an oxide. The magnetic tunnel junction has perpendicular magnetic anisotropy, which means that the magnetization directions of the free layer and the fixed layer forming the magnetic tunnel junction are in the perpendicular direction. The ferromagnetic metal can be a mixed metal material formed by at least one of cobalt iron CoFe, cobalt iron boron CoFeB or nickel iron NiFe, and the proportion of the mixed metal materials can be the same or different. The oxide can be magnesium oxide MgO or aluminum oxide Al ₂ O ₃ One of the oxides, for generating a tunneling magnetoresistance effect. In practical applications, ferromagnetic metals and oxides may be used as well, and the invention is not limited in this regard.

The free layer of the magnetic tunnel junction is contacted and fixed with the spin-orbit moment layer, each layer of the magnetic tunnel junction and the spin-orbit moment layer can be plated on the substrate in sequence from bottom to top by the traditional methods of ion beam epitaxy, atomic layer deposition or magnetron sputtering, and the like, and then two or more magnetic tunnel junctions can be prepared and formed by the traditional nanometer device processing technologies of photoetching, etching, and the like.

In a preferred embodiment, the spin-orbit torque layer is a spin-orbit torque layer composed of a heavy metal film, an antiferromagnetic film, or other material. The heavy metal film or the antiferromagnetic film can be made rectangular, and the top surface area of the heavy metal film or the antiferromagnetic film is preferably larger than the bottom surface area of the outline formed by the magnetic tunnel junction, and the bottom surface shape of the magnetic tunnel junction is completely embedded in the top surface shape of the heavy metal film or the antiferromagnetic film. Preferably, the spin-orbit torque layer may be made of one of platinum Pt, tantalum Ta, tungsten W, and the like. In practical applications, the spin-orbit torque layer may be formed from other possible materials, which are not limited in this regard.

In this embodiment, the first magnetic tunnel junction MTJ0 and/or the second magnetic tunnel junction MTJ1 includes a fixed layer on top, a free layer in contact with the spin-orbit torque layer, and a barrier layer provided between the fixed layer and the free layer, and the magnetic tunnel junction has a three-layer structure including only one free layer. In other embodiments, the free layer may be provided in multiple, i.e., more than two, free layers. The magnetic tunnel junction comprises a top fixed layer, a plurality of free layers, and barrier layers between every two adjacent layers, the bottommost free layer being disposed in contact with the spin-orbit torque layer. For example, in one specific example, when a two-layer free layer is included, a magnetic memory cell structure may include a spin-orbit torque layer, a second free layer, a barrier layer, a first free layer, a barrier layer, and a fixed layer disposed sequentially on the spin-orbit torque layer.

The invention is further illustrated by the following specific example. Assuming that a current through the SOT spin-orbit-torque layer from the first signal line BL to the second signal line SL will cause the magnetic tunnel junction magnetization to flip to a parallel state, a current through the SOT spin-orbit-torque layer from SL to BL will cause the magnetic tunnel junction magnetization to flip to an anti-parallel state. The magnitude of the current IHigh is defined to satisfy IHigh > IC0 > IC1, and the magnitude of the current ILow is defined to satisfy IC0 > ILow > IC1.

Regardless of the original data in the first memory and the second memory, the general steps of writing four data to the two MTJs are:

step0: WL and WWL are both high, and N0 and N1 are on.

Step1: the direction of the applied current is selected according to the desired state of MTJ0, the magnitude of the current is IHigh, so that the magnetization directions of MTJ0 and MTJ1 are both written to the desired state of MTJ0, if MTJ1 is the same as the target state of MTJ0, the write operation ends, and if the target states of MTJ0 and MTJ1 are different, step2 is entered.

Step2: a current ILow in the opposite direction to Step1 is applied, the magnitude of the current ILow, so that the magnetization direction of MTJ1 is written to the desired state of MTJ1, and the write operation ends.

The specific writing operation is as follows:

if the written data is 00:

Step1 is a current applied in the direction from SL to BL, and has a magnitude IHigh, and data 00 is written, and the write operation ends.

If the written data is 01:

step1 is a current applied in the direction from SL to BL, with a magnitude of IHigh, data 00 is written, and the write operation continues.

Step2 is a current applied in the direction from BL to SL, with the amplitude ILow, data 01 is written, and the write operation ends.

If the written data is 11:

step1 is a current applied in the direction from BL to SL, and has a magnitude IHigh, and data 11 is written, and the write operation ends.

If the written data is 10:

step1 is the application of current in the BL to SL direction, with a magnitude IHigh, data 11 is written, and the write operation continues.

Step2 is a current applied in the direction from SL to BL, the amplitude ILow, the data 10 is written, and the write operation ends.

Considering the original data in the memory cell, the general steps of writing four data to two MTJs are:

step3: WL high turns on N0 and WWL low turns off N1.

Step4: determining the resistance values of a first magnetic tunnel junction (MTJ 0) and a second magnetic tunnel junction (MTJ 1) in a memory, and ending the writing operation if the data to be written is the same as the original data; if the data to be written is different from the original data, step5 is entered.

Step5: WL and WWL are both high level, N0 and N1 are opened, and the data to be written and the original data are determined to be written. For example, if the original data is 00 and the data to be written is 01, only a current in the BL to SL direction needs to be applied, the amplitude is ILow, the data 01 is written, and the writing operation ends.

The read settings and operations are as follows:

assume that the high and low resistance values of MTJ0 and MTJ1 are shown in table 2.

TABLE 2

The resistances of the heavy metal layer (spin-orbit torque layer) and the resistances of the switching elements were ignored, and the series resistances of the four states of the two memories were shown in table 3 from high to low, respectively.

TABLE 3 Table 3

Data	00	10	01	11
					Resistor (N k omega)	(k+1)×(1+TMR)	k+1+k×TMR	k+1+TMR	k+1

The median set reference resistance can be taken between two adjacent resistance values as shown in table 4.

TABLE 4 Table 4

	Reference resistance 0	Reference resistor 1	Reference resistor 2
				Resistor (N k omega)	k+1+(k+0.5)×TMR	(k+1)×(1+0.5×TMR)	k+1+0.5×TMR

The steps of reading are as follows:

step6: WL high turns on N0 and WWL low turns off N1.

Step7: comparing the serial resistances of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 obtained by reading with a reference resistance 1, and if the serial resistance is large, the MTJ1 is in a high-resistance antiparallel state, and the data is X0, namely 00 or 10; if the series resistance is small, MTJ1 is in a low resistance parallel state and the data is X1, i.e., 01 or 11.

Step8: if the data is X0, comparing the series resistance with the reference resistance 0, and if the series resistance is large, the MTJ0 is in a high resistance antiparallel state, and the data is 00; if the series resistance is small, MTJ0 is in the low resistance parallel state and the data is 10. If the data is X1, comparing the series resistance with a reference resistance 2, and if the series resistance is large, the MTJ0 is in a high resistance antiparallel state, and the data is 01; if the series resistance is small, MTJ0 is in the low resistance parallel state and the data is 11.

The advantages of the magnetic random access memory cell of the present invention over the prior art are shown in table 5.

TABLE 5

	STT series SOT	SOT parallel SOT	The invention is that
				Write performance	STT weak X	SOT strong-	SOT strong-
Read performance	Series strong-	Parallel weak x	Series strong-
				Process for producing a solid-state image sensor	Complex x	Simple-	Simple-

In conclusion, SOT writing is adopted in the writing, so that the speed is high, and the power consumption is low; the serial mode is adopted in reading, so that the resistance difference of different states is larger, 4 data states are easy to distinguish, the reading speed is high, the reliability is high, and the scheme only needs two MOS tubes, so that the area is saved; the manufacturing process is consistent with standard SOT-MRAM without introducing a new film.

Based on the same principle, the embodiment also discloses a data writing method of the magnetic random access memory unit. The method comprises the following steps:

s100: at least one signal to be written is determined according to the data to be written, wherein the signal to be written is a first writing signal input by the first signal line BL or a second writing signal input by the second signal line SL.

S200: the current magnitude of the signal to be written is determined according to the critical switching currents of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ 1.

S300: the first switching element N0 and the second switching element N1 are controlled to be conducted, and the at least one signal to be written is input.

In a preferred embodiment, the determining at least one signal to be written according to the data to be written specifically includes:

determining, by a read module, a series resistance of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ 1;

and determining whether the resistance states of the first magnetic tunnel junction (MTJ 0) and the second magnetic tunnel junction (MTJ 1) need to be changed according to the series resistance of the first magnetic tunnel junction (MTJ 0) and the second magnetic tunnel junction (MTJ 1), and if so, forming corresponding signals to be written.

Since the principle of solving the problem by the method is similar to that of the magnetic random access memory unit, the implementation of the method can be referred to the implementation of the magnetic random access memory unit, and the description is omitted herein.

Based on the same principle, the embodiment also discloses a data reading method of the magnetic random access memory unit. The method comprises the following steps:

s400: controlling the first switching element N0 to be conducted and controlling the second switching element N1 to be disconnected;

s500: and inputting a read voltage, determining the series resistance of the first magnetic tunnel junction (MTJ 0) and the second magnetic tunnel junction (MTJ 1) according to the change of the read voltage, and determining the data stored by the first memory and the second memory according to the series resistance of the first magnetic tunnel junction (MTJ 0) and the second magnetic tunnel junction (MTJ 1).

Based on the same principle, the embodiment also discloses a magnetic random access memory, which comprises a plurality of magnetic random access memory units arranged in an array manner.

In one specific example, as shown in fig. 7, the mram is composed of the mram cells of the present embodiment of the 2X4 array. Wherein each memory cell of the array comprises an MTJ ₀ And an MTJ ₁ And two switching elements, BL ₀ 、BL ₁ 、BL ₂ And BL ₃ Respectively are the first signal lines WL ₀ And WL (WL) ₁ Respectively a first control line, WWL ₀ And WWL ₁ Respectively second control lines SL ₀ 、SL ₁ 、SL ₂ And SL (SL) ₃ And the second signal lines respectively.

Magnetic random access memory, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technique. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of applications for magnetic random access memory include, but are not limited to, random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium which can be used to store information which can be accessed by a computing device.

Since the principle of the memory for solving the problem is similar to that of the above magnetic random access memory unit, the implementation of the memory can be referred to the implementation of the magnetic random access memory unit, and the description thereof is omitted herein.

Based on the same principle, the embodiment also discloses a computer device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor.

The processor and/or the memory may comprise a magnetic random access memory unit as described in this embodiment.

The magnetic random access memory unit described in the above embodiment may be provided in a product device having a certain function. A typical implementation device is a computer device, which may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

In a typical example the computer device comprises in particular a memory, a processor and a computer program stored on the memory and executable on the processor, said processor and/or said memory comprising a magnetic random access memory unit as described in the present embodiment.

Reference is now made to FIG. 8, which illustrates a schematic diagram of a computer device suitable for use in implementing embodiments of the present application.

As shown in fig. 8, the computer device includes a Central Processing Unit (CPU) 601, which can perform various appropriate works and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. In the RAM603, various programs and data required for system operation are also stored. The CPU601, ROM602, and RAM603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, mouse, etc.; an output portion 607 including a Cathode Ray Tube (CRT), a liquid crystal feedback device (LCD), and the like, and a speaker, and the like; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The drive 610 is also connected to the I/O interface 605 as needed. Removable media 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on drive 610 as needed, so that a computer program read therefrom is mounted as needed as storage section 608.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims

1. A magnetic random access memory cell, comprising a first memory, a second memory, a first switching element and a second switching element;

2. The magnetic random access memory cell of claim 1 wherein the first magnetic tunnel junction comprises a first fixed layer, a first barrier layer, and a first free layer, respectively, disposed sequentially from top to bottom;

3. The magnetic random access memory cell of claim 2 wherein the critical switching currents of the first free layer and the second free layer of the first magnetic tunnel junction and the second magnetic tunnel junction are different.

4. The magnetic random access memory cell of claim 3 wherein a cross-sectional area of a first spin-orbit torque layer of the first magnetic tunnel junction is greater than a cross-sectional area of a second spin-orbit torque layer of the second magnetic tunnel junction; and/or the number of the groups of groups,

5. The magnetic random access memory cell of claim 2 wherein the first barrier layer and the second barrier layer of the first magnetic tunnel junction and the second magnetic tunnel junction are different in area.

6. The magnetic random access memory cell of claim 2 wherein the first pinned layer of the first magnetic tunnel junction and the second pinned layer of the second magnetic tunnel junction are electrically connected.

7. The magnetic random access memory cell of claim 3 wherein a first electrode is provided on top of the first magnetic tunnel junction and fixedly connected to the first fixed layer, and a second electrode is provided on top of the second magnetic tunnel junction and fixedly connected to the second fixed layer;

8. The magnetic random access memory cell of claim 1 wherein the first switching element comprises a first transistor;

9. The magnetic random access memory cell of claim 8 wherein the second switching element comprises a second transistor;

10. The magnetic random access memory cell of claim 8, wherein a first input terminal of the first spin-orbit torque layer is provided with a first input electrode and a first output terminal of the first spin-orbit torque layer is provided with a first output electrode;

11. The magnetic random access memory cell according to claim 10, wherein a second input terminal of the second spin-orbit torque layer is provided with a second input electrode, and a second output terminal of the second spin-orbit torque layer is provided with a second output electrode connected to a second signal line to which a second write signal is input;

12. The mram cell of claim 1, further comprising a data writing module configured to determine at least one signal to be written according to data to be written, where the signal to be written is a first write signal input to a first signal line or a second write signal input to a second signal line, determine current magnitudes of the signal to be written according to critical flip currents of the first magnetic tunnel junction and the second magnetic tunnel junction, control the first switching element and the second switching element to be turned on, and input the at least one signal to be written.

13. The mram cell of claim 12, wherein the data writing module is specifically configured to determine, by the reading module, a series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction, and determine, according to the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction, whether a resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction needs to be changed, and if so, form a corresponding signal to be written.

14. The mram cell of claim 1, wherein the read module is configured to control the first switching element to be on and the second switching element to be off; and inputting a read voltage, determining the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction according to the change of the read voltage, and determining the data stored in the first memory and the second memory according to the series resistance of the first magnetic tunnel junction and the second magnetic tunnel junction.

15. A method of writing data to a magnetic random access memory cell according to any of claims 1 to 14, comprising:

16. The method of claim 15, wherein determining at least one signal to be written based on the data to be written comprises:

17. A method of reading data from a mram cell as claimed in any one of claims 1 to 14, comprising:

18. A magnetic random access memory comprising a plurality of magnetic random access memory cells according to any one of claims 1 to 14 arranged in an array.