CN116738920A

CN116738920A - Chip 3D design method and system of three-dimensional geometric kernel

Info

Publication number: CN116738920A
Application number: CN202311008069.4A
Authority: CN
Inventors: 王嘉诚; 张少仲
Original assignee: Zhongcheng Hualong Computer Technology Co Ltd
Current assignee: Zhongcheng Hualong Computer Technology Co Ltd
Priority date: 2023-08-11
Filing date: 2023-08-11
Publication date: 2023-09-12
Anticipated expiration: 2043-08-11
Also published as: CN116738920B

Abstract

The invention discloses a chip 3D design method and system of a three-dimensional geometric kernel, belonging to the technical field of integrated circuits, wherein the method comprises the following steps: constructing a three-dimensional geometric kernel, and generating a chip preliminary three-dimensional geometric model by utilizing a first generation contrast network GAN; optimizing parameters of the preliminary three-dimensional geometric model based on multi-physical field coupling analysis by using a second generation countermeasure network GAN, wherein the second GAN is a local optimization process; setting a judgment condition for local optimization, and entering a space visualization judgment state after triggering the judgment condition; a designer adjusts device parameters in a space visualization scene, and after adjustment is completed, an iteration flow direction is selected; and performing iterative optimization on the chip three-dimensional geometric model for a plurality of times to obtain a final chip three-dimensional geometric model, and exporting the final chip 3D design into a universal CAD format. The intelligent technology-based chip 3D design method can comprehensively improve design efficiency and optimize performance.

Description

Chip 3D design method and system of three-dimensional geometric kernel

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a chip 3D design method and system of a three-dimensional geometric kernel.

Background

With the continued development of integrated circuit technology, chip designs have become increasingly complex. Conventional two-dimensional chip design methods have failed to meet the ever-increasing performance requirements and stringent size and power consumption constraints. Therefore, three-dimensional chip design has received a great deal of attention as a new design method. However, there are still some problems in the existing three-dimensional chip design technology.

Existing chip design methods are usually based on manual design or aided design tools, and require a designer to have a lot of experience and expertise in the design process. This design approach relies heavily on the personal abilities and experience accumulation of the designer, resulting in long time consuming and inefficient design processes. The designer needs to invest a lot of time and effort to become familiar with complex design rules, to master the adjustment of various dimensions, shapes, positions, etc., and to understand the interactions of various physical fields. During this process, the designer may need to try and adjust repeatedly and be prone to human error, which may lead to unstable design quality and even affect subsequent production and testing links.

In addition, because the existing design method is difficult to realize comprehensive optimization of design parameters, designers often need to adjust and optimize the parameters one by one. This certainly consumes a lot of time and effort, and in practice it is difficult for the designer to guarantee that the optimum combination of design parameters is found in a limited time. This may lead to design results that do not meet the desired performance objectives, thereby reducing product competitiveness.

Meanwhile, with the development of integrated circuit technology and the change of market demands, the complexity of chip design is increasing. In this case, the conventional method based on the manual design or the aided design tool faces greater challenges, and designers need to continuously learn and adapt to new design rules and techniques, further increasing the difficulty and burden of the design process.

Furthermore, the existing chip design method generally lacks visual space visualization function, so that a designer cannot intuitively perceive the influence of adjustment on the whole design when adjusting parameters such as the size, shape, position and the like of a device. This can lead to tedious, inefficient iterative processes for the design, and difficulty in achieving the desired optimization.

Meanwhile, considering the specialty and accuracy of high-level designers can help to optimize the performance and effect of chip design, therefore, a chip 3D design method combining intelligent and specialty two-aspect three-dimensional geometric kernels is needed, which can effectively solve the problems in the prior art, improve the design efficiency and the overall performance, fully exert the specialty advantages of the designers and reduce human errors in the design process.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a chip 3D design method of a three-dimensional geometric kernel, which comprises the following steps:

constructing a three-dimensional geometric kernel for representing a three-dimensional geometric model of the chip;

generating a chip preliminary three-dimensional geometric model by utilizing a first generation contrast network GAN;

optimizing parameters of the preliminary three-dimensional geometric model based on multi-physical field coupling analysis by using a second generation countermeasure network GAN, wherein the chip 3D design of the second generation countermeasure network GAN is optimized into a local optimization process according to the result of the multi-physical field coupling analysis;

setting a judgment condition in each local optimization process, and entering a space visualization judgment state after triggering the judgment condition;

the designer adjusts the size, shape and position parameters of the device in a space visualization scene;

after the designer finishes adjustment, selecting an iterative flow direction;

performing multiple iterative optimization on the chip three-dimensional geometric model, optimizing the chip three-dimensional geometric model according to the result of the multi-physical field coupling analysis through the second generation countermeasure network GAN in each iteration, performing parameter adjustment through spatial visualization when triggering a judgment condition, and determining an iterative flow direction;

And after multiple iterative optimization, obtaining a final chip three-dimensional geometric model, and exporting the final chip 3D design into a universal CAD format.

The multi-physical field coupling analysis comprises coupling analysis based on multiple physical fields between interest points, wherein the interest points are a signal source and a signal destination of a path to be optimized.

Extracting performance indexes from the result of the multi-physical field coupling analysis, wherein the performance indexes comprise electromagnetic interference (EMI) level, thermal resistance and signal integrity;

feeding the extracted performance index back to the customized loss function of the second GAN;

the generator and arbiter of the second GAN will be locally optimized based on the results of the multiple physical field coupling analysis.

The second generation countermeasure network GAN is a framework using a multi-task learning MTL, and 3D design of a learning chip is optimized to be locally optimized and performance indexes of the learning chip are predicted;

the second GAN generator comprises two sub-networks, wherein the first sub-network is used for optimizing the 3D design of the chip to be locally optimized, and the second sub-network is used for predicting the electromagnetic interference EMI level, thermal resistance and signal integrity performance of the generated design;

the second sub-network receives the generated output of the second sub-network as input, outputs corresponding performance prediction, and feeds back the performance prediction to the first sub-network.

The constructing a three-dimensional geometric kernel for representing a three-dimensional geometric model of a chip comprises:

the chip 3D design data is expressed as a voxel grid, namely, a three-dimensional space is divided into cube units with equal size, and each cube unit represents a voxel;

each voxel is represented by a binary value, 1 representing that there is material in the location, 0 representing a blank;

each chip 3D design is represented as a three-dimensional 0-1 tensor.

Extracting a local chip 3D design between two interest points from a chip 3D design generated by a first GAN, and representing the local chip 3D design as a smaller three-dimensional geometric kernel data structure;

constructing a second GAN model, which comprises a generator G2 and a discriminator D2;

generator G2 receives as input a random noise vector and outputs a three-dimensional tensor of the same size as the extracted local chip 3D design, representing the generated local chip 3D design.

Generating a local 3D design by using a trained generator G2, and replacing the local 3D design to a corresponding part in the whole chip 3D design before the local optimization;

and re-inputting the whole chip design after the local optimization into the multi-physical field coupling analysis software.

Calculating a connection weight for each device according to the connection relation between the devices, wherein the connection weight represents the association degree of paths between the devices and a plurality of pairs of interest points;

during the training of the second GAN, calculating an adjustment amplitude for each device, including a parameter difference amplitude for the device between the local design generated by the comparison generator G2 and the non-local optimization;

and setting a threshold value for the connection weight and the adjustment amplitude respectively, and triggering a judgment condition when the connection weight of a certain device exceeds the threshold value and the adjustment amplitude also exceeds the threshold value.

Wherein the iterative flow direction comprises:

selecting to re-perform local optimization on the points of interest subjected to the local optimization again;

the optimization iteration is selected to continue.

The invention also discloses a chip 3D design system of the three-dimensional geometric kernel, which is used for realizing the method, and comprises the following steps:

the three-dimensional space identification module is used for constructing a three-dimensional geometric model of the three-dimensional geometric kernel representation chip;

the first GAN module is used for generating a chip preliminary three-dimensional geometric model by utilizing the first generation reactance network GAN;

the multi-physical field coupling analysis is used for carrying out multi-physical field coupling analysis;

The second GAN module is used for optimizing parameters of the preliminary three-dimensional geometric model according to the result of the multi-physical field coupling analysis based on the multi-physical field coupling analysis by using a second generation countermeasure network GAN, and the 3D design of the chip of the second generation countermeasure network GAN is optimized into a local optimization process;

the space visual judgment module is used for enabling the system to enter a space visual judgment state after triggering the judgment condition according to the set judgment condition in each local optimization process;

the virtual reality technology module is used for enabling a designer to adjust the size, shape and position parameters of the device in a space visualization scene;

and enabling the designer to select an iterative flow direction after adjustment is completed;

and the deriving module is used for deriving the chip 3D design of the final chip three-dimensional geometric model into a universal CAD format after multiple iterative optimization.

The method of the invention utilizes GAN and multi-physical field coupling analysis to realize the parameter driving design of the three-dimensional geometric model of the chip, and improves the automation degree and the optimizing effect of the design process. By generating the application of the countermeasure network (GAN), the invention can automatically generate the three-dimensional geometric model of the chip, and improves the design efficiency through multiple iterative optimization. The method of the invention is based on the coupling analysis of multiple physical fields such as electric field, magnetic field, temperature field and the like between interest points, and realizes the comprehensive performance consideration of chip design. The invention allows the designer to directly adjust the parameters such as the size, the shape, the position and the like of the device in a space visualization scene, thereby improving the flexibility and the accuracy of the design.

Therefore, the chip 3D design method based on the three-dimensional geometric kernel combines the generation of the countermeasure network (GAN) and the multi-physical field coupling analysis to realize parameter driving design, improves the design efficiency and the performance, and simultaneously provides a more visual and easy-to-operate design environment for designers.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

fig. 1 is a flowchart illustrating a chip 3D design method of a three-dimensional geometric core according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two.

It should be understood that although the terms first, second, third, etc. may be used to describe … … in embodiments of the present invention, these … … should not be limited to these terms. These terms are only used to distinguish … …. For example, the first … … may also be referred to as the second … …, and similarly the second … … may also be referred to as the first … …, without departing from the scope of embodiments of the present invention.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a commodity or device comprising such element.

As shown in fig. 1, the invention discloses a chip 3D design method of a three-dimensional geometric kernel, which combines generation of an countermeasure network GAN and multi-physical field coupling analysis to perform parameter driven design, and comprises the following steps:

And constructing a three-dimensional geometric kernel for representing the three-dimensional geometric model of the chip.

And utilizing the first generation reactance network GAN to control and generate a chip preliminary three-dimensional geometric model.

The method comprises the steps of optimizing and adjusting parameters of a preliminary three-dimensional geometric model according to the result of multi-physical field coupling analysis by using a second generation countermeasure network GAN based on multi-physical field coupling analysis, specifically comprising the step of optimizing a 3D design of the chip of the second generation countermeasure network GAN as a local optimization process, wherein the parameters of the preliminary three-dimensional geometric model are optimized and adjusted according to the result of the multi-physical field coupling analysis, and the electromagnetic, thermal and signal integrity performance of the chip is improved.

Setting a judgment condition in each local optimization process, and entering a space visualization judgment state after triggering the judgment condition. Under the space visualization scene, the designer can directly adjust parameters such as the size, the shape, the position and the like of the device in space in an interactive mode. And selecting an iterative flow direction after the adjustment is completed.

And performing iterative optimization on the chip three-dimensional geometric model for multiple times, optimizing and adjusting parameters according to the result of the multi-physical field coupling analysis by the second generation countermeasure network GAN in each iteration, and performing parameter adjustment and determining the iterative flow direction through spatial visualization when a judgment condition is triggered.

After multiple iterative optimizations, a final chip three-dimensional geometric model is obtained, and the final design is exported into a universal CAD format, such as STEP, IGES, etc., for further manufacturing and testing.

The chip 3D design method based on the three-dimensional geometric kernel can realize a flexible, efficient and innovative chip design flow.

In a certain embodiment, when the chip design is performed by using the generation countermeasure network GAN, the design quality can be improved by combining the multi-physical field coupling analysis software to perform the coupling analysis of the electric field, the magnetic field, the temperature field and other multi-physical fields, and in order to integrate the result of the multi-physical field coupling analysis into the GAN, the performance index calculated by the multi-physical field coupling analysis software is introduced into the loss function, so that the GAN generator can consider the influence of the multi-physical field when generating the chip model. The method specifically comprises the following steps:

step k1, designing a general loss function for the generator and the arbiter when training to generate the first countermeasure network GAN.

And step k2, when the first GAN generator generates a new chip three-dimensional geometric model, the new chip three-dimensional geometric model is imported into multi-physical field coupling analysis software, and the multi-physical field coupling analysis software performs multi-physical field coupling analysis on the chip model.

Step k3, before the multi-physical field coupling analysis is performed, relevant analysis parameters such as working frequency, temperature range, electromagnetic boundary conditions and the like need to be set.

And step k4, after the analysis parameters are set, coupling analysis is carried out on the chip model by using multi-physical field coupling analysis software, wherein the step comprises the step of analyzing the comprehensive influence of the multi-physical field on the chip performance.

And step k5, extracting performance indexes from the result of the multi-physical field coupling analysis, wherein the performance indexes comprise electromagnetic interference (EMI) level, thermal resistance and signal integrity.

And step k6, feeding the extracted performance index back to the customized loss function of the second GAN. The generator and arbiter at the second GAN will be locally optimized based on the results of the multiple physical field coupling analysis.

In one embodiment, for the generator (G) and the arbiter (D), the first GAN of the invention uses a loss function form that is binary cross-entropy loss (binarycross-entopylos) expressed as follows:

L1_{D}=-mathbb{E}{x_text{2D}simP_text{data}}[logD(x_text{3D})]-mathbb{E}{x_text{2D}simP_text{data}}[log(1-D(G(x_text{2D})))],

wherein,,

l1_ { D }: is the loss function of the arbiter D. The discriminators are trained by optimizing this loss function so that they can more accurately distinguish between true three-dimensional chip design samples and counterfeit samples generated by the generator.

x_text {2D }: is a two-dimensional chip design vector extracted from the real data distribution P_text { data }. It represents a sample point in the two-dimensional chip design space.

P_text { data }: is the true data distribution, representing the probability distribution of the two-dimensional chip design vector in the training data set. x_text {2D } is sampled from this distribution.

x_text {3D }: is a true three-dimensional chip design sample corresponding to the two-dimensional chip design vector x_text {2D }.

G: is a generator, which is a neural network model responsible for mapping the input two-dimensional chip design vector x_text {2D } to the three-dimensional chip design space. The goal of the generator is to learn to generate three-dimensional chip design samples that resemble the true data distribution.

G (x_text {2D }): is a three-dimensional chip design sample generated by generator G. The generator converts the input two-dimensional chip design vector x_text {2D } into three-dimensional chip design samples which are similar to the real data distribution.

D: the system is a discriminator, which is a neural network model and is responsible for classifying input three-dimensional chip design samples and judging whether the three-dimensional chip design samples are real samples or fake samples generated by a generator. The goal of the arbiter is to maximize the classification accuracy for the true samples and the generated samples.

D (x_text {3D }): this is the prediction of the input sample x_text {3D } (true three-dimensional chip design) by the arbiter D. The value of D (x_text {3D }) is between [0,1], the closer the value is to 1, indicating that the more the arbiter considers the sample to be a true sample.

D (G (x_text { 2D)): this is a prediction of the input samples G (x_text {2D }) (the generated three-dimensional chip design) by the arbiter D. The value of D (G (x_text {2D })) is between [0,1], the closer the value is to 1, indicating that the more the arbiter considers the sample to be a true sample.

mathbb { E } is the expected symbol, representing the average of all possible values in the corresponding distribution. The average of the loss values corresponding to the two-dimensional chip design vector x_text {2D } extracted from the true data distribution p_text { data } is calculated in this loss function.

The loss function l1_ { D } contains two parts, the first part calculates the loss of the arbiter on the real sample and the second part calculates the loss of the arbiter on the fake sample generated by the generator. It is desirable to minimize this loss function so that the arbiter can better distinguish between true three-dimensional chip design samples and counterfeit samples generated by the generator.

For mathbb { E } { x_text {2D } simP_text { data } [ log D (x_text {3D }) ], this measure the ability of the arbiter D to identify a real three-dimensional chip design sample, and the arbiter can determine the real three-dimensional chip design sample as a real sample.

For mathbb { E } { x_text {2D } simP_text { data } [ log (1-D (G (x_text { 2D))) ] is a term used to measure the ability of the arbiter D to recognize the three-dimensional chip design sample generated by the generator G, it is desirable that the arbiter be able to determine the generated three-dimensional chip design sample as a counterfeit sample.

The true data distribution p_text { data } refers to a probability distribution followed by actual data. In machine learning and statistical modeling, it is assumed that the training dataset is sampled from an independent co-distribution (i.i.d) of some unknown true probability distribution. This true data distribution may reflect the inherent structure and pattern of the data. P_text { data } is the probability distribution of the true two-dimensional chip design vector. P_text { data } describes the probabilistic nature of the two-dimensional chip design vector observed in the training dataset. By sampling the two-dimensional chip design vector x_text {2D } from p_text { data }, a true sample with similar structure and features can be obtained. In training the generator and the arbiter, the expected generator learns to generate samples similar to the true data distribution p_text { data }. The samples generated by the generator thus have characteristics similar to those of real data, making it difficult for the arbiter to distinguish between the generated samples and the real samples.

L1_{G}=-mathbb{E}{x_text{2D}simP_text{data}}[logD(G(x_text{2D}))],

L1_ { G } is the loss function of the generator. This loss function measures the ability of the generator G to generate samples that are similar to the actual three-dimensional chip design samples, and it is desirable to minimize this loss function so that the generator can generate samples that more closely approximate the actual data distribution.

For mathbb { E } { x_text {2D } simP_text { data } [ log D (G (x_text { 2D)) ], this measures the probability that the three-dimensional chip design sample generated by generator G is misjudged by arbiter D as a true sample, it is desirable to have a generator built so that the sample generated by it can spoof the arbiter to some extent, wherein:

l1_ { G }: is the loss function of the generator G, which is trained by optimizing this loss function so that it can generate three-dimensional chip design samples that more closely approximate the true data distribution.

G: this is a generator, which is a neural network model responsible for mapping the input two-dimensional chip design vector x_text {2D } to the three-dimensional chip design space. The goal of the generator is to learn to generate three-dimensional chip design samples that resemble the true data distribution.

G (x_text {2D }): this is a three-dimensional chip design sample generated by generator G. The generator converts the input two-dimensional chip design vector x_text {2D } into three-dimensional chip design samples which are similar to the real data distribution.

D: the discriminator is a neural network model and is responsible for classifying input three-dimensional chip design samples and judging whether the three-dimensional chip design samples are real samples or fake samples generated by a generator. The goal of the arbiter is to maximize the classification accuracy for the true samples and the generated samples.

D (G (x_text { 2D)): this is a prediction of the input samples G (x_text {2D }) (the generated three-dimensional chip design) by the arbiter D. The value of D (G (x_text {2D })) is between [0,1], the closer the value is to 1, indicating that the more the arbiter considers the sample to be a true sample. log is a log sign and may be a base 10 log.

mathbb { E }: this is the expected sign, representing the average of all possible values in the corresponding distribution. In this penalty function, we calculate the average of the penalty values corresponding to the two-dimensional chip design vector x_text {2D } extracted from the true data distribution p_text { data }.

The above is a defined form of binary cross entropy loss of the first GAN, which is used to control the generation of the preliminary three-dimensional geometric model as there are no results of the multiple physical field coupling analysis at this time.

In one embodiment, for the second GAN, three performance indicators, electromagnetic interference (EMI) level, thermal resistance (Rth), and Signal Integrity (SI), are considered, and samples generated by the generator are required to meet the requirements of the three performance indicators, and penalty terms related to the performance of the three indicators are added to the loss functions of the generator and the arbiter, respectively. In order to apply the chip 3D design of the three-dimensional geometric kernel to be optimized according to the present invention, it is necessary to customize the penalty functions of the generator (G) and the arbiter (D), the definition of the custom penalty functions is as follows:

L2_{D}=-mathbb{E}{x_G2_text{3D}simP_text{data}}[logD_2(x_G2_text{3D})]-mathbb{E}{x_G2_text{3D}simP_text{data}}[log(1-D_2(G_2(x_G2_text{3D})))]+P_{EMI}(x_G2_text{3D})+P_{Rth}(x_G2_text{3D})+P_{SI}(x_G2_text{3D})，

wherein,,

l2_ { D }: representing the arbiter loss function of the second GAN.

mathbb { E }: an operator is expected to calculate the average.

x_g2_text {3D }: representing a locally optimized 3D generation of the second GAN.

P_text { data }: representing the probability distribution of the real data.

D_2: the second GAN's arbiter is responsible for distinguishing the real local design from the local design generated by the generator.

x_g2_text {3d } simp_text { data }: represents 3D generation sampled from the true data probability distribution p_text { data }.

log d_2 (x_g2_text {3D }): representing the logarithmic probability when the arbiter d_2 processes the true local design x_g2_text {3D }.

G_2: the generator of the second GAN is responsible for generating samples that look like a real local design.

D2 (g_2 (x_g2_text { 3D)): representing an evaluation of the local design generated by the generator g_2 by the arbiter d_2.

log (1-d_2 (g_2 (x_g2_text {3D }))): representing the logarithmic probability when the arbiter d_2 processes the local design x_g2_text {3D } generated by the generator g_2.

P_ { EMI } (x_g2_text {3D }): representing penalty terms associated with electromagnetic interference. This term measures the electromagnetic interference of the local design generated by generator g_2.

P_ { Rth } (x_g2_text {3D }): representing a penalty term associated with thermal resistance. This term measures the thermal resistance of the local design generated by generator g_2.

P_ { SI } (x_g2_text {3D }): representing penalty terms related to signal integrity. This term measures the signal integrity of the local design generated by generator g_2.

L2_{G}=-mathbb{E}{x_G2_text{3D}simP_text{data}}[logD_2(G_2(x_G2_text{3D}))]+P_{EMI}(x_G2_text{3D})+P_{Rth}(x_G2_text{3D})+P_{SI}(x_G2_text{3D})，

Wherein,,

l2_ { G }: representing the generator penalty function of the second GAN.

mathbb { E }: an operator is expected to calculate the average.

P_text { data }: representing the probability distribution of the real data.

log d_2 (g_2 (x_g2_text {3D })): representing the logarithmic probability when the arbiter d_2 processes the local design x_g2_text {3D } generated by the generator g_2.

For x_g2_text {3D } simp_text { data }, it means that one 3D generated sample is sampled from the real data probability distribution p_text { data } and assigned to x_g2_text {3D }, one 3D generated sample is sampled from the real data distribution p_text { data } when the generator loss l2_g } is calculated, and then input into the generator g_2. This is done in order to train the generator g_2 so that the samples it generates are closer to the true data distribution p_text { data }.

The real data refers to locally optimized 3D designs known to have good performance characteristics (such as low electromagnetic interference, low thermal resistance, and high signal integrity), which are typically from actual engineering design cases or data optimized by a professional engineer. These data are collected from actual application scenarios, real world observations or experiences. These data are used as benchmarks for GAN training, with the goal of enabling the generator to learn how to generate a local design with similar performance characteristics.

During the training process, the data generated by the generator is referred to as "generated data" or "spurious data" which attempt to simulate the distribution of real data. Through the countermeasure process between the training generator and the arbiter, the generator gradually learns to generate samples that are closer to the real data.

To calculate p_ { EMI } (x_g2_text {3D }), p_ { Rth } (x_g2_text {3D }) and p_ { SI } (x_g2_text {3D }) one generated 3D design, i.e., g_2 (x_g2_text {3D }), needs to be derived from the second generator G2. Here x_g2_text {3D } is the 3D tensor of the local area to be optimized that is input to G2.

EMI (g_2 (x_g2_text {3D })) is the electromagnetic interference performance of the generated 3D design.

Rth (g_2 (x_g2_text { 3D)): is the thermal resistance performance of the generated 3D design.

SI (g_2 (x_g2_text { 3D)): is the signal integrity performance of the generated 3D design.

Electromagnetic interference penalty function p_ { EMI }:

，

this formulation shows that if the EMI performance of the generated 3D design exceeds the target threshold t_ { EMI }, a penalty is incurred. The square term in the penalty function subjects the worse performing design to a greater penalty. alpha_ { EMI } is a positive number weight coefficient used to adjust the weight of the EMI penalty function.

Thermal resistance penalty function p_ { Rth }:

，

This formulation yields a penalty if the Rth performance of the generated 3D design exceeds the target threshold t_ { Rth }. The square term in the penalty function subjects the worse performing design to a greater penalty. alpha_ { Rth } is a positive number weight coefficient used to adjust the weight of the Rth penalty function.

Signal integrity penalty function p_ { SI }:

，

this formulation yields a penalty if the SI performance of the generated 3D design exceeds the target threshold T_ { SI }. The square term in the penalty function subjects the worse performing design to a greater penalty. alpha_ { SI } is a positive number weight coefficient used to adjust the weight of the SI penalty function.

In one embodiment, the second GAN may learn the results of simulation generation through training of real data and predict corresponding electromagnetic interference (EMI), thermal resistance (Rth), and Signal Integrity (SI) performance during generation. An architecture for multitasking MTL is used, where a second GAN learns to generate a 3D design and predict its performance metrics at the same time.

In this architecture, the second GAN generator will comprise two parts: one sub-network is used to generate a 3D design, i.e., g2 (x_g2_text {3D }); the other sub-network is used for predicting the EMI, rth and SI performances of the generated design, and the sub-network can receive the generated 3D design as input, output corresponding performance predictions, and feed the performance predictions back to the first sub-network for updating the loss function by the first sub-network.

To train this multitasking GAN architecture, a training dataset with EMI, rth and SI tags needs to be prepared. During training, it is desirable to minimize the difference between the performance metrics predicted by the generator and the performance metrics of the real data in order for the generator to learn to predict these performance values.

The penalty function includes both generating and predicting the penalty of the task to guide the generator in the training process to learn to generate 3D designs with good performance metrics and predict those performance metrics at the same time. Thus, during the generation process, the second GAN can generate both 3D designs and predict the EMI, rth, and SI performance of the designs. And after the two layers of sub-networks of the second GAN are circularly iterated for a plurality of times, obtaining a local optimization result of the second GAN.

In one embodiment, multi-physics field coupling analysis software is generally used to simulate physical processes in complex systems, and the following description is provided of how the multi-physics field coupling analysis software may be used to obtain electromagnetic interference (EMI) levels, thermal resistance (Rth), and Signal Integrity (SI) performance metrics.

The 3D design of the chip is created or imported in multi-physics field coupling analysis software, including chip geometry, material properties, boundary conditions, and other parameters related to electromagnetic, thermal, and signal transmission. And setting a corresponding analysis type for each performance index. For EMI analysis, electromagnetic analysis tools such as finite element method FEM methods are used to simulate the propagation and interference of electromagnetic fields. For thermal resistance analysis, thermal analysis, including steady state or transient thermal conduction analysis, is required to calculate temperature distribution and thermal resistance. For signal integrity analysis, transmission line theory, circuit models, or electromagnetic simulations are used to model the propagation characteristics of signals in interconnect lines.

After the simulation parameters are set, multi-physical field coupling analysis software is run to calculate the required performance index. The software will solve the corresponding physical equations, including maxwell's equations, heat conduction equations, kirchhoff's law, etc., to provide detailed results for each performance index.

And extracting performance indexes such as an EMI level, thermal resistance, signal integrity and the like according to the simulation result. From the electromagnetic analysis results, electromagnetic interference intensities such as conducted interference and radiated interference can be obtained for evaluating the EMI level. From the thermal analysis results, thermal resistance is calculated from the thermal resistance path from the power device to the heat sink or environment. From the signal integrity analysis results, signal integrity may be assessed based on the signal delay parameter.

In one embodiment, the simulated EMI analysis, thermal resistance analysis, and signal integrity analysis can be implemented by industry specific software and a variety of tool libraries, any collection capable of performing the simulated EMI analysis, thermal resistance analysis, and signal integrity analysis can be implemented as multi-physical field coupling analysis software.

ANSYSHFSS is a high-frequency structure simulator based on finite element method FEM, which is widely applied to electromagnetic compatibility EMC and electromagnetic interference EMI analysis, and can simulate a complex 3D geometric structure and analyze the propagation and interference effects of electromagnetic waves in the structure.

ANSYSIcepak for thermal management simulation supports importing 3D geometry, importing geometric models from CAD software, such as STEP, IGES, or Parasolid formats, for thermal analysis, the imported 3D models may include chip, electronic components, and system-level structures. Flotherm is a piece of software used for thermal analysis of electronic devices, and calculates thermal resistance, temperature distribution and heat dissipation performance through finite element method FEM and computational fluid dynamics CFD simulation.

KeysightAdvancedDesignSystem (ADS) is a software widely used in microwave and radio frequency circuit design. Momentum and FEM solvers in ADS can process the imported 3D geometry data for electromagnetic field and signal integrity analysis. The system comprises a transmission line theory, a circuit model and an electromagnetic simulation tool, and can be used for evaluating parameters such as signal integrity, distortion, delay and the like.

Cadence is a software for signal integrity and power integrity (analysis cadence is primarily used for signal integrity and power integrity analysis that supports importing 3D geometry, importing 3D geometry models of circuit boards or packages from CAD software, and evaluating the propagation characteristics of signals in interconnect lines using the simulation and analysis tools of the signal nature.

Wherein obtaining performance metrics from the results of the software operation including electromagnetic interference (EMI) levels, thermal resistance, signal integrity, includes:

after electromagnetic simulation is completed in ANSYSHFSS, data such as field distribution, S-parameters, transmission loss, etc. are checked. To obtain EMI levels requires calculation of field strength or power density, which can be done by post-processing tools to evaluate field strength at a specified receiver location or area, the area between points of interest, which are signal input points and signal output points (signal source and signal destination) for the path to be optimized, can be selected in the present invention.

After thermal analysis by ANSYSIcepak or FloTHERM, temperature profiles, heat flows and other thermal performance metrics can be obtained. Two temperature points of interest (typically a signal input point and a signal output point for the path to be optimized) are determined to calculate the thermal resistance. The thermal resistance can be calculated by the following formula: thermal resistance= (junction temperature-ambient temperature)/power consumption. In the post-processing stage, these temperature values and power consumption are extracted from the software, and then the thermal resistance is calculated.

For signal integrity analysis, time domain waveforms are extracted from KeyichtADS and cadence. Simulations in ADS or signature can generate time domain waveforms to evaluate signal integrity parameters, such as signal delay. To determine the time domain waveform input to output, two nodes are selected, such as a signal source (input) and a signal destination (output), and the waveform is further analyzed after simulation using built-in waveform analysis tools to calculate signal delays.

In one embodiment, to generate a three-dimensional geometric model of a chip using a first generation-opposing network GAN, the representation of the 3D chip design data is first determined, and then a first GAN model is constructed and trained.

The 3D design data is represented as a voxel grid, i.e. the three-dimensional space is divided into equally sized cube units, each representing a voxel. Each voxel is represented by a binary value, e.g. 1 for the position with material and 0 for the blank. Thus each 3D design may be represented as a three-dimensional 0-1 tensor.

Similarly, the chip 2D designs are also divided into grid cells in a two-dimensional space, each grid cell representing a voxel, each voxel being represented by a binary value, e.g. 1 for the material in the location and 0 for the blank, so that each 2D design can be represented as a two-dimensional 0-1 tensor.

A first generation resist network GAN model is constructed, comprising a generator (G) and a discriminator (D), the loss function of the first GAN is binary cross entropy loss (binarycross-entopylos). Wherein the generator receives as input a 2D mesh vector of a two-dimensional chip design and outputs a 3D tensor of the same size as the training data representing the generated chip design. The arbiter receives a 3D tensor as input (real chip design or generator generated design) and outputs a scalar representing the probability that the input design is a real design.

In the training data preparation stage, a large amount of chip 2D to chip 3D design data is collected and converted into the form of voxel grids, and the data are arranged into a training data set for training GAN.

GAN is trained using binary cross entropy loss as a loss function. The generator G receives as input a 2D mesh vector of one-to-one two-dimensional chip design. The generator will transform the input vector into a 3D tensor of the same size as the training data, through a series of convolution layers and activation functions, representing the generated chip design.

The arbiter D receives as input a 3D tensor. This 3D tensor may be a real chip design or a design generated by the generator. The actual chip design is from the training dataset and the design generated by the generator is the 3D tensor output by the generator. The task of the arbiter is to distinguish whether the input 3D tensor is a real design or a generated design. To accomplish this task, the arbiter typically contains a series of convolution layers, activation functions, and full connection layers, ultimately outputting a scalar representing the probability that the input design is a true design. During the training process, the generator attempts to generate a chip design that can spoof the discriminant, while the discriminant attempts to more accurately distinguish between the actual design and the generated design. After training is completed, the generator will learn to generate a chip design similar to the training data. A random 3D chip design is generated using the trained generator.

In one embodiment, an antagonism network (GAN) is created using existing deep learning libraries and toolboxes such as TensorFlow or pyrerch. TensorFlow is an open source deep learning framework developed by Google, and PyTorch is an open source deep learning framework developed by Facebook.

In one embodiment, a preliminary 3D chip design is generated via a first GAN, and after performance data between points of interest is obtained by multi-physical field coupling analysis software, a second GAN is used to optimize the 3D design between two points of interest based on the performance data between the points of interest. The interest points refer to a pair of signal input points and signal output points determined in the analysis process of the multi-physical field coupling analysis software. The local optimization between the interest points comprises the following processes:

from the entire 3D chip design generated by the first GAN, a local 3D design between two points of interest is extracted, which is represented as a smaller three-dimensional geometry kernel data structure.

A second Generation Antagonism Network (GAN) model is constructed, comprising a generator (G2) and a discriminator (D2). Generator G2 receives as input the spatial structure tensor vector of the part of the chip 3D design and outputs a 3D tensor of the same size as the extracted part 3D design, representing the generated modified part design. The arbiter D2 receives as input a 3D tensor (real partial design or generator generated design) and outputs a scalar representing the probability that the input design is a real design.

A number of local spatial structure tensors of the chip 3D design are collected to local 3D improved design data, including multi-physical field coupling analysis results of electric field, magnetic field, temperature field, signal delay between points of interest. From these data, a training data set is created for training the second GAN.

According to the custom loss function definition, penalty terms P_ { EMI } (x), P_ { Rth } (x), and P_ { SI } (x) related to electromagnetic interference (EMI) level, thermal resistance (Rth), and Signal Integrity (SI) are calculated and added to the original loss functions L1_ { D } and L1_ { G } to obtain the custom loss function.

The second GAN is trained to minimize the custom loss function. During the training process, the generator G2 attempts to generate a local design that can fool the discriminant D2, and the discriminant D2 attempts to more accurately distinguish between the actual design and the generated design. After training is completed, generator G2 will learn to generate a local design similar to the training data.

An optimized local 3D design is generated by using the trained generator G2 and is replaced to the corresponding part in the original chip design (the whole chip 3D design before the local optimization). In this case, it is desirable that the whole chip, particularly the portion between the points of interest, has better performance.

And inputting the whole chip design after the local optimization into multi-physical field coupling analysis software to verify whether the performance indexes among the interest points are improved. And when the performance indexes among the interest points are qualified, carrying out local optimization on the next pair of interest points.

In this step, the second GAN performs iterative optimization by calculating a penalty term of the customized loss function according to the estimated multi-physical field coupling analysis result, but the second GAN performs training learning only to optimize the local design between the points of interest, so that on one hand, the multi-physical field coupling analysis result obtained through training prediction has an error with the precision of the simulation software, and on the other hand, the second GAN performs training and improvement on the local part and the simulation result of the simulation software on the whole chip has a difference. Therefore, it is also necessary to input the entire chip design into the multi-physical field coupling analysis software to verify whether the performance index between the points of interest is improved.

Wherein, like the generator of the first GAN, the generator G2 of the second GAN receives as input a vector. This vector will be converted by generator G2 into a tensor representing the local 3D design. The inputs to the arbiter D2 of the second GAN comprise the actual local 3D design data and the local design data generated by the generator G2. Unlike the arbiter input of the first GAN which focuses mainly on the whole chip design, the input of the arbiter D2 of the second GAN focuses more on the local design. In defining the custom penalty function for the second GAN, it is necessary to combine the results of multiple physical field coupling analyses of electric field, magnetic field, temperature field, etc. with the training dataset, take these performance indicators EMI, rth, SI as additional penalty terms p_ { EMI } (x), p_ { Rth } (x), and p_ { SI } (x), and add them to the original penalty functions l1_ { D } and l1_ { G }. The second GAN is caused to focus on performance metrics between points of interest during training.

In one embodiment, a connection weight is calculated for each device based on the connection relationship between the devices, the connection weight representing the degree of association of the device with the paths between the pairs of points of interest.

After the second GAN generates the local optimization results, the adjustment amplitude of each device is calculated, including the parameter difference amplitude of the device between the local design generated by the comparison generator G2 and the non-local optimization.

And setting a threshold value for the connection weight and the adjustment amplitude respectively, and triggering a judgment condition when the connection weight of a certain device exceeds the threshold value and the adjustment amplitude also exceeds the threshold value. The threshold value can be adjusted according to actual requirements and optimization targets. The connection weight and the adjustment amplitude of the device are compared with corresponding thresholds. The decision condition is triggered only if both the connection weight and the adjustment amplitude exceed the threshold.

In one embodiment, to determine the connection weights, all paths associated with each device are first identified, which refer to signal transmission lines connecting points of interest (signal input points or output points). Devices are associated with paths, including devices located on these paths or in communication with other devices on the paths.

Determining path weights includes assigning weights based on the importance of the paths throughout the circuit.

Path weights are determined based on the importance of the path in the overall circuit.

And determining the connection weight of the devices according to the path weight of each device related path. The specific calculation method may be to add all path weights related to the device, where in determining the connection weights of the trigger decision conditions, the path currently performing local 3D optimization needs to be excluded, and when the connection weights of the computing device and all paths other than the current path exceed a set threshold, the trigger decision conditions will be triggered when the adjustment amplitude exceeds the threshold.

In one embodiment, if the designer believes that the current adjustment may affect the optimization between other points of interest associated with the device, it may be selected to re-optimize locally again between points of interest that have been locally optimized, which will trigger the second GAN to re-optimize locally again between points of interest that have been locally optimized.

If the designer believes that the current adjustment does not affect the optimization between other points of interest associated with the device, it may choose to continue to optimize between the next points of interest. In this case, the entire optimization process will continue.

In one embodiment, a designer may utilize virtual reality VR techniques to directly adjust parameters such as size, shape, position, etc. of the device in a space visualization scene. The designer wears VR helmet and tracking glove, gets into virtual reality environment. A three-dimensional model of the circuit design is presented in a virtual environment, including various devices, connection lines, and points of interest. The designer uses a gesture or VR controller to select the device that needs to be adjusted. After selection, a series of control points may appear around the device to adjust the size, shape and position of the device. By grasping and dragging the control points, the designer can directly adjust the size and shape of the selected device. The control points are dragged outward to increase the size of the device or the control points are dragged inward to decrease the size of the device. The designer may grab the selected device and drag in space to adjust the position of the device in the virtual environment. Real-time auxiliary lines and marks are used for indicating the relative position relationship between the device and other elements in the adjustment process so as to facilitate accurate adjustment. After the adjustment is completed, the designer may choose the iteration direction through the VR interface, for example, may choose "continue optimization", or choose "re-optimize the optimized set of points of interest".

Through using VR technique, designer can adjust each element of circuit design in visual scene in space directly perceivedly, improves design efficiency and accuracy. Meanwhile, the VR environment provides an immersive experience for designers, and is helpful for better understanding the spatial relationship and functional characteristics of circuit designs.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

The foregoing description of the preferred embodiments of the present invention has been presented for purposes of clarity and understanding, and is not intended to limit the invention to the particular embodiments disclosed, but is intended to cover all modifications, alternatives, and improvements within the spirit and scope of the invention as outlined by the appended claims.

Claims

1. A chip 3D design method of a three-dimensional geometric kernel, the method comprising:

after the designer finishes adjustment, selecting an iterative flow direction;

2. The method for 3D design of a chip of a three-dimensional geometrical kernel of claim 1, wherein,

the multiple physical field coupling analysis includes coupling analysis based on multiple physical fields between points of interest, which are signal sources and signal destinations of a path to be optimized.

3. The method for 3D design of a chip of a three-dimensional geometrical kernel of claim 1, wherein,

extracting performance indexes from the results of the multi-physical field coupling analysis, wherein the performance indexes comprise electromagnetic interference (EMI) level, thermal resistance and signal integrity;

4. The method for chip 3D design of three-dimensional geometric kernel as defined in claim 3,

the second generation countermeasure network GAN is a framework using a multi-task learning MTL and simultaneously learns that the 3D design of the chip is optimized to be locally optimized and predicts the performance index thereof;

5. The method for 3D design of a chip of a three-dimensional geometrical kernel according to claim 1, wherein the constructing the three-dimensional geometrical kernel for representing the three-dimensional geometrical model of the chip comprises:

Each chip 3D design is represented as a three-dimensional 0-1 tensor.

6. The method for 3D designing a chip of a three-dimensional geometric core according to claim 5,

7. The method for 3D design of a chip of a three-dimensional geometrical kernel of claim 6, wherein,

8. The method for 3D design of a chip of a three-dimensional geometrical kernel of claim 1, wherein,

9. The chip 3D design method of a three-dimensional geometric kernel as defined in claim 1, wherein the iterative flow direction comprises:

the optimization iteration is selected to continue.

10. A chip 3D design system of a three-dimensional geometric kernel for implementing the method of one of claims 1-9, the system comprising: