CN116737497A

CN116737497A - Data acquisition method and device, electronic equipment and storage medium

Info

Publication number: CN116737497A
Application number: CN202310706240.2A
Authority: CN
Inventors: 郭伯亚
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-06-14
Filing date: 2023-06-14
Publication date: 2023-09-12

Abstract

The embodiment of the invention provides a data acquisition method, a data acquisition device, electronic equipment and a storage medium, wherein the first power supply protection chip is controlled to supply power to a first protocol conversion chip; the first target data of the first key chip is obtained through the first protocol conversion chip, so that the problem of obtaining the fault data of the key chip under the condition of no shutdown or disassembly is solved, the debugging and analysis efficiency is improved, and the operation and maintenance cost is reduced.

Description

Data acquisition method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of data acquisition technology, and in particular, to a data acquisition method, a data acquisition device, a server, an electronic device, and a computer readable storage medium.

Background

In order to improve the computation density and the storage density of the server and increase the access speed, chips such as PCIe Switch, PCIe re-timer, RAID and SAS expander are often used in the design of the server, and play a key role in the operation process of the server, so that once the chips fail, the performance and the data of the server can be greatly negatively influenced, and when the key chips fail in the operation process of the server, under the condition of remaining the failure, the limitation of a chassis and a board card structure generally causes that the debug interface debug of the chips cannot be directly connected, and if the server is stopped or the board card is detached to be connected with the debug interface debug, the failure can not be guaranteed to be reproduced again, and effective failure data information cannot be collected to analyze the problem.

Disclosure of Invention

The embodiment of the invention provides a data acquisition method, a data acquisition device, electronic equipment and a computer readable storage medium, so as to solve the problem of acquiring critical chip fault data without stopping or dismantling a machine.

The embodiment of the invention discloses a data acquisition method which is applied to a server, wherein the server comprises a first key chip, the first key chip is configured with a corresponding first protocol conversion chip and a first power protection chip, and the method comprises the following steps:

controlling the first power supply protection chip to supply power to the first protocol conversion chip;

and acquiring first target data of the first key chip through the first protocol conversion chip.

Optionally, the server may include a second key chip, where the first key chip has a corresponding first serial port type, the second key chip has a corresponding second serial port type, and the first serial port type is different from the second serial port type, and the second key chip is configured with a corresponding second protocol conversion chip and a second power protection chip, and may further include:

controlling the second power supply protection chip to supply power to the second protocol conversion chip;

And acquiring second target data of the second key chip through the second protocol conversion chip.

Optionally, the server may include a baseboard management controller, and the step of controlling the first power protection chip to supply power to the first protocol conversion chip may include:

sending a first power supply instruction to the baseboard management controller;

and the baseboard management controller responds to the first power supply instruction and adjusts an enabling signal of the first power supply protection chip so as to control the first power supply protection chip to supply power to the first protocol conversion chip.

Optionally, the server may include a baseboard management controller, and the step of controlling the second power protection chip to supply power to the second protocol conversion chip may include:

sending a second power supply instruction to the baseboard management controller;

and the baseboard management controller responds to the second power supply instruction and adjusts an enabling signal of the second power supply protection chip so as to control the second power supply protection chip to supply power to the second protocol conversion chip.

Optionally, the plurality of first critical chips may be configured with corresponding first multiplexer chips for electrically connecting the plurality of first critical chips and the first protocol conversion chip; the plurality of second critical chips are configured with corresponding second multiplexer chips for electrically connecting the plurality of second critical chips and the second protocol conversion chip.

Alternatively, the baseboard management controller may be configured with corresponding universal input output extension chips for electrically connecting with the first power supply protection chip and the second power supply protection chip, respectively.

Optionally, the server may include a south bridge chip, where the south bridge chip is electrically connected to the first protocol conversion chip and the second protocol conversion chip, and the south bridge chip is configured to obtain the first target data and/or the second target data.

The embodiment of the invention also discloses a data acquisition device which is applied to a server, wherein the server comprises a first key chip, and the first key chip is configured with a corresponding first protocol conversion chip and a first power protection chip, and can comprise:

the first power supply control module is used for controlling the first power supply protection chip to supply power to the first protocol conversion chip;

the first data acquisition module is used for acquiring first target data of the first key chip through the first protocol conversion chip.

The second power supply control module is used for controlling the second power supply protection chip to supply power to the second protocol conversion chip;

and the second data acquisition module is used for acquiring second target data of the second key chip through the second protocol conversion chip.

Optionally, the server may include a baseboard management controller, and the first power supply control module may include:

the first instruction sending submodule is used for sending a first power supply instruction to the baseboard management controller;

the first power supply control module invokes a sub-module, configured to adjust an enable signal of the first power supply protection chip in response to the first power supply instruction by the baseboard management controller, so as to invoke the first power supply control module.

Optionally, the server may include a baseboard management controller, and the second power supply control module may include:

the second instruction sending submodule is used for sending a second power supply instruction to the baseboard management controller;

the second power supply control module invokes a sub-module, configured to adjust an enable signal of the second power supply protection chip by using the baseboard management controller in response to the second power supply instruction, so as to invoke the second power supply control module.

The embodiment of the invention also discloses a server, which can comprise a first key chip, wherein the first key chip is provided with a corresponding first protocol conversion chip and a first power supply protection chip, and the server is used for controlling the first power supply protection chip to supply power to the first protocol conversion chip; and acquiring first target data of the first key chip through the first protocol conversion chip.

The embodiment of the invention also discloses electronic equipment, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;

the memory is used for storing a computer program;

the processor is configured to implement the method according to the embodiment of the present invention when executing the program stored in the memory.

Embodiments of the present invention also disclose a computer-readable storage medium having instructions stored thereon, which when executed by one or more processors, cause the processors to perform the method according to the embodiments of the present invention.

The embodiment of the invention has the following advantages:

according to the embodiment of the invention, the first power supply protection chip is controlled to supply power to the first protocol conversion chip; the first target data of the first key chip is obtained through the first protocol conversion chip, so that the problem of obtaining the fault data of the key chip under the condition of no shutdown or disassembly is solved, the debugging and analysis efficiency is improved, and the operation and maintenance cost is reduced.

Drawings

FIG. 1 is a flow chart of steps of a method for data acquisition provided in an embodiment of the present invention;

FIG. 2 is a schematic diagram of a circuit design provided in an embodiment of the present invention;

FIG. 3 is a block diagram of a data acquisition device provided in an embodiment of the present invention;

FIG. 4 is a block diagram of the hardware architecture of an electronic device provided in various embodiments of the invention;

fig. 5 is a schematic diagram of a computer readable medium provided in an embodiment of the invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

In order to enable those skilled in the art to better understand the embodiments of the present invention, the following description is given of technical terms related to the embodiments of the present invention.

PCIe: PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard that has many improvements over previous standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical size, better scaling of bus device performance, more detailed error detection and reporting mechanisms, and native hot plug functionality.

PCIe switch chip: refers to a chip that provides expansion or aggregation capability for PCIe and allows more devices to connect to one PCle port, which acts as a packet router, identifying which path a given packet needs to travel based on address or other routing information.

PCIe repeater chip: the Retimer chip is a mixed signal analog/digital chip, and its principle is to use an internal clock recovery circuit to retime an input signal to eliminate clock offset and jitter and correct phase and time offset of the signal, and it can prolong the transmission distance of an interface and improve signal quality.

RAID: redundant Arrays of Independent Disks, also called redundant array of independent disks, is a method of storing the same data in different places of multiple hard disks. By placing data on multiple hard disks, input and output operations can overlap in a balanced manner, improving performance, a type of multi-disk management technology that provides high performance storage with moderate cost and high data reliability to the host environment.

SCSI (small computer system interface): small Computer System Interface A small computer system interface is an independent processor standard for the interface between a computer and an intelligent device, such as a hard disk, a floppy drive, an optical drive, a printer, a scanner, etc., and a system level interface is an intelligent universal interface standard and is an interface standard between various computers and external devices.

SAS: serial Attached SCSI, also known as serial SCSI technology, is a disk connection technology.

SAS expander: a device that expands one SAS port into multiple SAS ports may be understood as a SAS switch.

UART: universal Asynchronous Receiver/Transmitter, also known as a universal asynchronous receiver Transmitter, is an asynchronous receiver Transmitter, which is part of the computer hardware and converts the data to be transmitted between serial and parallel communications, as a chip for converting parallel input signals into serial output signals, UART is typically integrated on the connection of other communication interfaces.

I2C: inter-Integrated Circuit, also known as an integrated circuit bus, is a two-wire serial communication bus for communication between devices, and is a simple, bi-directional two-wire synchronous serial bus that requires only two wires to transfer information between devices connected to the bus.

In the existing server board card design, because the UART/I2C interface of each chip is designed independently and is usually designed as a 1x3 interface, when the chip needs to be debugged, an external tool is needed to be connected to the interface, in order to prevent the interface from being mistakenly touched by a client in daily operation, and based on the angle of protecting the data security of the server, the debug interface of the chip is usually arranged beside the chip and the interfaces are not reserved at the front part and the rear part of the chassis, therefore, when the server breaks down or the chip debug interface needs to be operated, the server needs to be stopped or disassembled, so that the reproduction of the fault is difficult to ensure and valid fault data is lost.

Referring to fig. 1, a flowchart illustrating steps of a data acquisition method provided in an embodiment of the present invention may specifically include the following steps:

step 101, controlling the first power supply protection chip to supply power to the first protocol conversion chip;

step 102, obtaining first target data of the first key chip through the first protocol conversion chip.

In a specific implementation, the embodiment of the invention can be applied to a server, the server can comprise a first key chip, the first key chip can be configured with a corresponding first protocol conversion chip and a first power protection chip, the embodiment of the invention can control the first power protection chip to supply power to the first protocol conversion chip, first target data of the first key chip can be obtained through the first protocol conversion chip, the server can be a server comprising the first key chip, the first key chip can comprise a PCIe Switch, a PCIe counter, a RAID and an SAS expanser chip, the first protocol conversion chip can be electrically connected with the first key chip, the first power protection chip can be electrically connected with the first protocol conversion chip, the first power protection chip can be controlled to supply power to the first protocol conversion chip, then fault data of the first key chip Switch, the PCIe counter, the RAID and the SAS expanser chip can be obtained through the first protocol conversion chip, as first target data, an exemplary UART signal line of the first key conversion chip can be electrically connected with a UART signal line of the first key chip at a first interface, namely, the first key chip can be accessed to a key system at a high-speed, and the first power protection chip can be accessed by a high-level power protection system, and the first key system can be accessed by a high-speed key system.

Of course, the above examples are merely examples, and those skilled in the art may use other chips having a key role in the server as the first key chip, which is not limited to the embodiments of the present invention.

On the basis of the above embodiments, modified embodiments of the above embodiments are proposed, and it is to be noted here that only the differences from the above embodiments are described in the modified embodiments for the sake of brevity of description.

In an alternative embodiment of the present invention, further comprising:

In practical application, the serial port types can be divided into UART serial ports and I2C serial ports, and the specification attributes corresponding to the different serial port types are different, for example, the number of signal lines of the UART serial ports can be 3, the number of signal lines of the I2C serial ports is 2, the communication mode of the UART serial ports is full duplex communication, and the communication mode of the I2C serial ports is half duplex communication, and as the specification attributes corresponding to the different serial port types are different, the chips with the different serial port types need to be distinguished.

In a specific implementation, the server in the embodiment of the present invention may include a second key chip, where the first key chip may have a corresponding first serial port type, the second key chip may have a corresponding second serial port type, and the first serial port type and the second serial port type are different, and the second key chip may be further configured with a corresponding second protocol conversion chip and a second power protection chip, and exemplarily, the first key chip may be a chip having a corresponding first serial port type, for example, a key chip having a UART serial port, and the second key chip may be a chip having a corresponding second serial port type, for example, a key chip having an I2C serial port, where the UART serial port and the I2C serial port are different, and the second key chip may be further configured with a corresponding second protocol conversion chip and a second power protection chip, and may control the second power protection chip to supply power to the second protocol conversion chip; the second target data of the second key chip is obtained through a second protocol conversion chip, specifically, the second key chip can be a PCIe Switch, a PCIe retimer, a RAID and a SAS expander chip with an I2C serial port, the second protocol conversion chip can be electrically connected with the second key chip, the second power supply protection chip can be electrically connected with the second protocol conversion chip, the second power supply protection chip can be controlled to supply power to the second protocol conversion chip, and then fault data of the PCIe Switch, the PCIe retimer, the RAID and the SAS expander chip with the I2C serial port can be obtained through the second protocol conversion chip to serve as the second target data.

Of course, the foregoing is merely exemplary, and those skilled in the art may use other chips having a key role in the server as the second key chip, which is not limited to the embodiment of the present invention.

According to the embodiment of the invention, the second power supply protection chip is controlled to supply power to the second protocol conversion chip; and acquiring second target data of the second key chip through the second protocol conversion chip, so that the key chips with different serial port types are distinguished, the pertinence of acquiring fault data of the key chips is improved, and the efficiency of acquiring the target data is further improved.

In an alternative embodiment of the present invention, the server is configured with a baseboard management controller, and the step of controlling the first power protection chip to supply power to the first protocol conversion chip includes:

The baseboard management controller, also known as a baseboard management controller (baseboard management controller, BMC), is a specialized service processor that uses sensors to monitor the status of a computer, web server, or other hardware driven device and communicates with the system administrator via separate connection lines. BMCs are part of the intelligent platform control interface (IPMI, intelligent Platform Management Interface) and are typically contained within a motherboard or main circuit board of a device being monitored. The sensors of the BMC are used to measure internal physical variables such as: temperature, humidity, power supply voltage, fan speed, communication parameters, and Operating System (OS) functions. If any of these variables is outside the scope of the established limits, it will notify the administrator. The relevant technician can take the correct action with the remote control. The monitoring device may be power cycled or restarted when necessary. In this way, a single administrator can remotely control numerous servers and other devices simultaneously. This saves the overall cost of the network and ensures reliability.

In a specific implementation, the server in the embodiment of the present invention may include a baseboard management controller, where the baseboard management controller may send a first power supply instruction to the baseboard management controller, and the baseboard management controller may respond to the first power supply instruction, adjust an enable signal of the first power supply protection chip to control the first power supply protection chip to supply power to the first protocol conversion chip, and exemplarily, the first power supply protection chip may have a corresponding enable signal, where a default setting of the enable signal may be low, and may send the first power supply instruction to the baseboard management controller, where the first power supply instruction may be an ipmitool (Intelligent Platform Management Interface tool, also referred to as an intelligent platform management interface tool) instruction created by a user, and the baseboard management controller may respond to the first power supply instruction, pull up the enable signal of the first power supply protection chip to control the first power supply protection chip to supply power to the first protocol conversion chip, and the first protocol conversion chip may be electrically connected to the first key chip, and the first power supply protection chip may be electrically connected to the first protocol conversion chip, and may control the first power supply protection chip to the first key conversion chip, and then may obtain data through a SAS (SAS, and may obtain the first data through a first protocol conversion circuit, and may be a first data transmission line, and may obtain the first data through the first key conversion chip, and a first data transmission line may be a first data transmission, and a failure state may be a first data transmission state, and a second data transmission state may be a first data transmission state.

According to the embodiment of the invention, a first power supply instruction is sent to the baseboard management controller; the baseboard management controller responds to the first power supply instruction, adjusts the enabling signal of the first power supply protection chip to control the first power supply protection chip to supply power to the first protocol conversion chip, so that a user can remotely control a plurality of servers and equipment at the same time, operation and maintenance cost is saved, data safety is guaranteed, and efficiency of acquiring target data is improved.

In an alternative embodiment of the present invention, the step of controlling the second power protection chip to supply power to the second protocol conversion chip includes:

In a specific implementation, the server in the embodiment of the present invention may include a baseboard management controller, where the baseboard management controller may send a second power supply instruction to the baseboard management controller, and the baseboard management controller may respond to the second power supply instruction, adjust an enable signal of the second power supply protection chip to control the second power supply protection chip to supply power to the second protocol conversion chip, and exemplarily, the second power supply protection chip may have a corresponding enable signal, where a default setting of the enable signal may be low, and may send the second power supply instruction to the baseboard management controller, where the second power supply instruction may be an ipmitool (Intelligent Platform Management Interface tool, also referred to as an intelligent platform management interface tool) instruction created by a user, and the baseboard management controller may respond to the second power supply instruction, pull up the enable signal of the second power supply protection chip to control the second power supply protection chip to supply power to the second protocol conversion chip, and the second protocol conversion chip may be electrically connected with the second key chip, and the second power supply protection chip may be controlled to electrically connect with the second protocol conversion chip, and may then control the second power supply protection chip to the second protocol conversion chip to obtain data through a SAS (SAS) and may be a second key chip, and may obtain data string through a second interface, and may be a second data string, which may be a data string, and a data string may be obtained by a second key chip, and a second data string, or a second data string, and a second data string may be read by a second key interface, and a second key interface.

According to the embodiment of the invention, the second power supply instruction is sent to the baseboard management controller; the baseboard management controller responds to the second power supply instruction, adjusts the enabling signal of the second power supply protection chip to control the second power supply protection chip to supply power to the second protocol conversion chip, so that a user can remotely control a plurality of servers and equipment at the same time, operation and maintenance cost is saved, data safety is guaranteed, and efficiency of acquiring target data is improved.

In an alternative embodiment of the present invention, a plurality of the first critical chips are configured with corresponding first multiplexer chips for electrically connecting the plurality of first critical chips and the first protocol conversion chip; the plurality of second critical chips are configured with corresponding second multiplexer chips for electrically connecting the plurality of second critical chips and the second protocol conversion chip.

In practice, the multiplexer MUX is a device that receives a plurality of input signals and synthesizes a single output signal in a recoverable manner for each input signal. A multiplexer is an integrated system that typically contains a number of data inputs and has a single output.

In a specific implementation, a first key chip with the same first serial port type can be electrically connected together through a first multiplexer chip and a first protocol conversion chip, and a second key chip with the same second serial port type can be electrically connected together through a second multiplexer chip and a second protocol conversion chip, so that the circuit is simplified.

In the embodiment of the invention, the plurality of first key chips are configured with the corresponding first multiplexer chips, and the first multiplexer chips are used for electrically connecting the plurality of first key chips with the first protocol conversion chip; the plurality of second key chips are configured with corresponding second multiplexer chips, and the second multiplexer chips are used for electrically connecting the plurality of second key chips with the second protocol conversion chip, so that the acquisition of target data of the plurality of key chips is completed on the basis of avoiding occupying a large number of pins, the cost of the circuit layout and operation and maintenance process is reduced, and the data acquisition efficiency is improved.

In an alternative embodiment of the present invention, the baseboard management controller is configured with corresponding universal input output extension chips, and the universal input output extension chips are used for electrically connecting with the first power supply protection chip and the second power supply protection chip respectively.

In practical application, a plurality of power protection chips are directly connected with a baseboard management controller, so that a large number of interfaces are occupied, interface tension is caused, the baseboard management controller can also increase the workload of software designers because of a large number of interface programming, and a hardware design engineer can develop a plurality of modules because of different circuits of different projects, which can cause the rise of research and development cost and operation cost.

In a specific implementation, the baseboard management controller in the embodiment of the present invention may be configured with a corresponding General purpose input/output extension chip, where the General purpose input/output extension chip may be used to be electrically connected to the first power protection chip and the second power protection chip, respectively, and the General purpose input/output extension chip may be a GPIO extension chip, for example, GPIO (General-purpose input/output, also called General purpose input/output), and P0-P3 with a function similar to 8051, where PINs may be freely used by a user through program control, and PIN PINs may be used as General Purpose Input (GPI) or General Purpose Output (GPO) or General Purpose Input and Output (GPIO) according to practical considerations, for example, as clk generator, chip select, etc.

According to the embodiment of the invention, the baseboard management controller is configured with the corresponding general purpose input/output extension chip, the general purpose input/output extension chip is used for being respectively electrically connected with the first power supply protection chip and the second power supply protection chip, and the general purpose input/output extension chip is connected with the plurality of power supply protection chips, so that the target data of the key chip is obtained under the condition of reducing the GPIO interface occupying the BMC, the data obtaining efficiency is further improved, and the cost is reduced.

In an optional embodiment of the present invention, the server includes a south bridge chip, where the south bridge chip is electrically connected to the first protocol conversion chip and the second protocol conversion chip, and the south bridge chip is used to obtain the first target data and/or the second target data.

In practical applications, the south bridge chip may be PCH (Platform Controller Hub), where the south bridge chip is the most important component of the motherboard chipset except the north bridge chip. The layout is generally located on the main board far below the CPU slot and near the PCI slot, and the layout is in consideration of the fact that the I/O bus connected with the layout is more, the layout is more beneficial to wiring far from the processor, and the wiring principle of equal length of signal wires is easier to realize.

In a specific implementation, the server in the embodiment of the present invention may include a south bridge chip, where the south bridge chip may be electrically connected to the first protocol conversion chip and the second protocol conversion chip, and is used to obtain the first target data, and/or the second target data, and for example, the protocol conversion chip connected to the UART interface key chip and the protocol conversion chip connected to the I2C interface key chip may be electrically connected to the south bridge chip PCH, and specifically, a USB signal of the PCH may be connected to a USB interface of the protocol conversion chip, where USB (Universal Serial Bus, also referred to as a universal serial bus) is a technical specification of an input/output interface, and is widely applied to information communication products such as personal computers and mobile devices, and is extended to other related fields such as photographic equipment, digital televisions (set top boxes), game machines, and so on.

In addition, when the application platform is AMD, the USB signal may be provided directly by the CPU, since the AMD mobile platform is not equipped with a PCH.

According to the embodiment of the invention, the server comprises the south bridge chip, the south bridge chip is respectively and electrically connected with the first protocol conversion chip and the second protocol conversion chip, and the south bridge chip is used for acquiring the first target data and/or the second target data, so that the occupation of interfaces is reduced, the efficiency of acquiring the target data is improved, and the operation and maintenance cost is further reduced.

In order that those skilled in the art will better understand the embodiments of the present invention, a complete description of the embodiments of the present invention will be provided below.

In order to increase the computation density and storage density of the server and increase the IO access speed, chips such as PCIe switch, PCIe counter, RAID, SAS expander and the like are often used in the design of the server. PCIe Switch can extend more PCIe signals, enabling the server to install more PCIe devices, and improving IO speed. The PCIe re-timer chip provides more stable link quality for PCIe equipment, ensures data transmission stability and reduces fault rate. RAID and SAS expanders can provide more storage space and improve data storage security by using different redundancy algorithms. The four common chips as exemplified above play a key role in the operation of the server, and once the chip fails, the chip has a great negative effect on the performance and data of the server, and in the existing server board card design, the UART/I2C interface of each chip is designed separately, usually as a 1x3 header, and an external tool is connected to the header when a debug is needed. In order to prevent a client from touching a chip debug interface by mistake and based on the data security of a server, the debug header of the chip is usually deployed beside the chip, an interface is not reserved at the front and rear parts of a chassis, and if a key chip fails in the running process of the server, the chip debug interface cannot be directly connected under the condition of keeping a failure state due to the structural limitation of the chassis and a board card; if the server is stopped or the board card is disassembled to be connected with the debug interface, the failure is difficult to ensure to be repeated again, and effective data information cannot be collected to analyze the problem.

Referring to fig. 2, a schematic diagram of a circuit design provided in an embodiment of the present invention is shown;

the specific flow is as follows:

on the hardware line, the USB signal of PCH is connected to the USB interface of the protocol conversion chip, and the UART/I2C interface of the protocol conversion chip is connected to the key chip. Preferably, the key chips of a plurality of same serial signals can simplify circuit design and save cost through the MUX chip, the power supply protection chip provides a power supply protection function for the protocol conversion chip, the power supply protection chip enable signal (enable) is connected to the BMC, preferably, the BMC GPIO interface can be saved through the GPIO extension chip when a plurality of power supply protection chips are arranged in the design, it is noted that an AMD platform has no PCH, USB signals are directly provided by the CPU, PCH can be changed into the AMD CPU according to an actual platform in the scheme design, when the key chips need to be accessed through serial ports, the BMC enable power supply protection chip is enabled through an ipmitool instruction under an operating system, and then the key chips can be accessed through serial ports through serial port tools or other software under the operating system.

The design scheme of the circuit is described in detail below by way of example, two key chips, named U1 and U2, can be provided, serial port signals of the two key chips are UART and I2C respectively, and the two key chips are correspondingly formed by two protocol conversion chips (U3, U4) and two power protection chips (U5, U6):

The USB signals of the PCH are respectively connected to the protocol conversion chips U3 and U4;

the UART signal of the protocol conversion chip U3 is connected to the key chip U1; the I2C signal of the protocol conversion chip U4 is connected to the key chip U2;

the power protection chips U5 and U6 respectively provide power for the protocol conversion chips U3 and U4, enable signals of the power protection chips are connected to the BMC, and the enable signals are low by default;

when the key chip U1 is required to be accessed, firstly, an ipmitool instruction is used for pulling up an enabling signal of the power protection chip U5, and then, the U1 can be accessed by serial software Outband of an operating system; after the access is completed, the enable signal of U5 can be pulled down.

The problem that if a key chip fails in the operation process of the server in the above manner, under the condition of keeping a failure state, the chip debug interface cannot be directly connected due to the limitation of a chassis and a board card structure; if the server is stopped or the mounting and dismounting board card is disconnected with the debug interface, the fault can be repeatedly reproduced hardly, the problem that effective data information cannot be collected to analyze the problem is solved, the Outband access mode of the key chip is integrated into the design of the server, the serial port line is not required to be additionally connected, the key chip is accessed by using serial port software surrounding under the server operating system at any time, the circuit design is simple, the maturity is high, the manufacturing cost is low, the key chip is conveniently accessed by a developer at any time, the debugging work and the problem analysis work are convenient, the Outband circuit is controlled by the BMC, and a client does not normally feel and the access safety is improved.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.

Referring to fig. 3, a block diagram of a data acquisition device provided in an embodiment of the present invention is shown, which may specifically include the following modules:

a first power supply control module 301, configured to control the first power supply protection chip to supply power to the first protocol conversion chip;

the first data obtaining module 302 is configured to obtain, by using the first protocol conversion chip, first target data of the first key chip.

For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.

The embodiment of the invention also discloses a server, which comprises a first key chip, wherein the first key chip is provided with a corresponding first protocol conversion chip and a first power supply protection chip, and the server is used for controlling the first power supply protection chip to supply power to the first protocol conversion chip; and acquiring first target data of the first key chip through the first protocol conversion chip.

For the server embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and the relevant points are referred to in the description of the method embodiment.

In addition, the embodiment of the invention also provides electronic equipment, which comprises: the processor, the memory, the computer program stored in the memory and capable of running on the processor, the computer program realizes each process of the above data acquisition method embodiment when executed by the processor, and can achieve the same technical effect, and for avoiding repetition, the description is omitted here.

The embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, realizes the processes of the above-mentioned data acquisition method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here. Wherein the computer readable storage medium is selected from Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.

Fig. 4 is a schematic hardware structure of an electronic device implementing various embodiments of the present invention.

The electronic device 400 includes, but is not limited to: radio frequency unit 401, network module 402, audio output unit 403, input unit 404, sensor 405, display unit 406, user input unit 407, interface unit 408, memory 409, processor 410, and power source 411. Those skilled in the art will appreciate that the electronic device structure shown in fig. 4 is not limiting of the electronic device and that the electronic device may include more or fewer components than shown, or may combine certain components, or a different arrangement of components. In the embodiment of the invention, the electronic equipment comprises, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted terminal, a wearable device, a pedometer and the like.

It should be understood that, in the embodiment of the present invention, the radio frequency unit 401 may be used for receiving and transmitting signals during the process of receiving and transmitting information or communication, specifically, receiving downlink data from a base station and then processing the received downlink data by the processor 410; and, the uplink data is transmitted to the base station. Typically, the radio frequency unit 401 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 401 may also communicate with networks and other devices through a wireless communication system.

The electronic device provides wireless broadband internet access to the user through the network module 402, such as helping the user to send and receive e-mail, browse web pages, and access streaming media, etc.

The audio output unit 403 may convert audio data received by the radio frequency unit 401 or the network module 402 or stored in the memory 409 into an audio signal and output as sound. Also, the audio output unit 403 may also provide audio output (e.g., a call signal reception sound, a message reception sound, etc.) related to a specific function performed by the electronic device 400. The audio output unit 403 includes a speaker, a buzzer, a receiver, and the like.

The input unit 404 is used to receive an audio or video signal. The input unit 404 may include a graphics processor (Graphics Processing Unit, GPU) 4041 and a microphone 4042, the graphics processor 4041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 406. The image frames processed by the graphics processor 4041 may be stored in memory 409 (or other storage medium) or transmitted via the radio frequency unit 401 or the network module 402. The microphone 4042 may receive sound and may be capable of processing such sound into audio data. The processed audio data may be converted into a format output that can be transmitted to the mobile communication base station via the radio frequency unit 401 in the case of a telephone call mode.

The electronic device 400 also includes at least one sensor 405, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor that can adjust the brightness of the display panel 4061 according to the brightness of ambient light, and a proximity sensor that can turn off the display panel 4061 and/or the backlight when the electronic device 400 is moved to the ear. As one of the motion sensors, the accelerometer sensor can detect the acceleration in all directions (generally three axes), and can detect the gravity and direction when stationary, and can be used for recognizing the gesture of the electronic equipment (such as horizontal and vertical screen switching, related games, magnetometer gesture calibration), vibration recognition related functions (such as pedometer and knocking), and the like; the sensor 405 may further include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which are not described herein.

The display unit 406 is used to display information input by a user or information provided to the user. The display unit 406 may include a display panel 4061, and the display panel 4061 may be configured in the form of a liquid crystal display (Liquid Crystal Display, LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 407 may be used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the electronic device. Specifically, the user input unit 407 includes a touch panel 4071 and other input devices 4072. The touch panel 4071, also referred to as a touch screen, may collect touch operations thereon or thereabout by a user (e.g., operations of the user on the touch panel 4071 or thereabout using any suitable object or accessory such as a finger, stylus, etc.). The touch panel 4071 may include two parts, a touch detection device and a touch controller. The touch detection device detects the touch azimuth of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, and sends the touch point coordinates to the processor 410, and receives and executes commands sent from the processor 410. In addition, the touch panel 4071 may be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. The user input unit 407 may include other input devices 4072 in addition to the touch panel 4071. In particular, other input devices 4072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail herein.

Further, the touch panel 4071 may be overlaid on the display panel 4061, and when the touch panel 4071 detects a touch operation thereon or thereabout, the touch operation is transferred to the processor 410 to determine the type of touch event, and then the processor 410 provides a corresponding visual output on the display panel 4061 according to the type of touch event. Although in fig. 4, the touch panel 4071 and the display panel 4061 are two independent components for implementing the input and output functions of the electronic device, in some embodiments, the touch panel 4071 may be integrated with the display panel 4061 to implement the input and output functions of the electronic device, which is not limited herein.

The interface unit 408 is an interface to which an external device is connected to the electronic apparatus 400. For example, the external devices may include a wired or wireless headset port, an external power (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 408 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the electronic apparatus 400 or may be used to transmit data between the electronic apparatus 400 and an external device.

Memory 409 may be used to store software programs as well as various data. The memory 409 may mainly include a storage program area that may store an operating system, application programs required for at least one function (such as a sound playing function, an image playing function, etc.), and a storage data area; the storage data area may store data (such as audio data, phonebook, etc.) created according to the use of the handset, etc. In addition, memory 409 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.

The processor 410 is a control center of the electronic device, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and processes data by running or executing software programs and/or modules stored in the memory 409 and invoking data stored in the memory 409, thereby performing overall monitoring of the electronic device. Processor 410 may include one or more processing units; preferably, the processor 410 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 410.

The electronic device 400 may also include a power supply 411 (e.g., a battery) for powering the various components, and preferably the power supply 411 may be logically connected to the processor 410 via a power management system that performs functions such as managing charging, discharging, and power consumption.

In addition, the electronic device 400 includes some functional modules, which are not shown, and are not described herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.

In yet another embodiment provided by the present invention, as shown in fig. 5, there is further provided a computer readable storage medium 501 having instructions stored therein, which when run on a computer, cause the computer to perform the data acquisition method described in the above embodiment.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. The data acquisition method is characterized by being applied to a server, wherein the server comprises a first key chip, the first key chip is configured with a corresponding first protocol conversion chip and a first power protection chip, and the data acquisition method comprises the following steps:

2. The method of claim 1, wherein the server comprises a second critical chip, the first critical chip having a corresponding first serial port type, the second critical chip having a corresponding second serial port type, the first serial port type being different from the second serial port type, the second critical chip being configured with a corresponding second protocol conversion chip and a second power protection chip, further comprising:

3. The method of claim 2, wherein the server is configured with a baseboard management controller, and wherein the step of controlling the first power protection chip to supply power to the first protocol conversion chip comprises:

4. The method of claim 3, wherein the step of controlling the second power protection chip to supply power to the second protocol conversion chip comprises:

5. The method of claim 4, wherein a plurality of the first critical chips are configured with corresponding first multiplexer chips for electrically connecting the plurality of first critical chips and the first protocol conversion chip; the plurality of second critical chips are configured with corresponding second multiplexer chips for electrically connecting the plurality of second critical chips and the second protocol conversion chip.

6. The method of claim 4, wherein the baseboard management controller is configured with corresponding universal input output extension chips for electrically connecting with the first power protection chip and the second power protection chip, respectively.

7. The method of claim 4, wherein the server comprises a south bridge chip electrically connected to the first protocol conversion chip and the second protocol conversion chip, respectively, the south bridge chip being configured to obtain the first target data and/or the second target data.

8. The data acquisition device is characterized by being applied to a server, wherein the server comprises a first key chip, and the first key chip is configured with a corresponding first protocol conversion chip and a first power protection chip, and comprises:

9. The server is characterized by comprising a first key chip, wherein the first key chip is provided with a corresponding first protocol conversion chip and a first power supply protection chip, and the server is used for controlling the first power supply protection chip to supply power to the first protocol conversion chip; and acquiring first target data of the first key chip through the first protocol conversion chip.

10. An electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

the memory is used for storing a computer program;

the processor is configured to implement the method according to any one of claims 1-7 when executing a program stored on a memory.

11. A computer-readable storage medium having instructions stored thereon, which when executed by one or more processors, cause the processors to perform the method of any of claims 1-7.