CN116737358B - Memory refreshing method and electronic equipment - Google Patents
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Abstract
The application discloses a memory refreshing method and electronic equipment, relates to the field of computers, and is used for timely releasing memory resources. The memory refreshing method comprises the following steps: according to the behaviors of the application program of requesting to allocate memory resources and requesting to release the memory resources, determining a first threshold value of the memory resources occupied by the application program; if the size of the memory resources occupied by the application program is larger than a first threshold, triggering the application layer to send a refresh command to a time stamp manager in the user mode driving UMD, wherein the refresh command is used for indicating the time stamp manager to update the time stamp of the memory resources in the to-be-released state so as to release the memory resources in the to-be-released state.
Description
Technical Field
The present application relates to the field of computers, and in particular, to a memory refresh method and an electronic device.
Background
The application program, when rendering the graphics processing unit (graphics processing unit, GPU), continuously applies for new vertex buffer object (vertex buffer objects, VBO) memory resources or vertex array object (vertex array object, VAO) memory resources (collectively referred to herein as memory resources) and prepares to release old memory resources that are in a state to be released (PENDING FREE).
The application program needs to send a flush (flush) command to the kernel layer to trigger the kernel layer to release the memory resource in the to-be-released state. However, sometimes, when the application program performs GPU rendering once, the memory resource applied is too large, and a refresh command cannot be sent to the kernel layer to trigger the kernel layer to release the memory resource in a state to be released. So that the shortage of available memory causes the complete machine to be blocked, restarted or halted.
Disclosure of Invention
The embodiment of the application provides a memory refreshing method and electronic equipment, which are used for timely releasing memory resources.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:
In a first aspect, a memory refresh method is provided, including: according to the behaviors of the application program of requesting to allocate memory resources and requesting to release the memory resources, determining a first threshold value of the memory resources occupied by the application program; and if the size of the memory resources occupied by the application program is larger than the first threshold, triggering an application layer to send a refresh command to a time stamp manager in a User Mode Driver (UMD), wherein the refresh command is used for indicating the time stamp manager to update the time stamp of the memory resources in a to-be-released state so as to release the memory resources in the to-be-released state.
According to the memory refreshing method provided by the embodiment of the application, a first threshold value of memory resources occupied by an application program is determined according to the behaviors of the application program that memory resources are allocated and released; if the size of the memory resources occupied by the application program is larger than a first threshold, triggering the application layer to send a refresh command to a time stamp manager in the UMD, wherein the refresh command is used for indicating the time stamp manager to update the time stamp of the memory resources in a to-be-released state, and triggering a memory release flow based on a time stamp mechanism to release the memory resources in the to-be-released state. Thereby realizing timely release of memory resources.
In one possible implementation, determining the first threshold of memory resources occupied by the application program according to the actions of allocating memory resources and releasing memory resources requested by the application program includes: if the application program requests to release the memory resources within a preset time after the application program requests to allocate the memory resources, the first threshold value is determined to be larger than the maximum value of the memory resources occupied by the application program.
If an application program continuously requests allocation of memory resources and does not request release of memory resources within a preset time after the request of allocation of memory resources, the application program is an abnormal application, and eventually all available memory resources may be exhausted. If an application program can request to release memory resources within a preset time after each request to allocate memory resources, the application program is a normal application, and the memory resources occupied by the application program are limited and not all available memory resources are exhausted, so that it can be determined that the first threshold value of the memory resources occupied by the application program is greater than the maximum value of the memory resources occupied by the application program.
In one possible implementation, if the size of the memory resource occupied by the application program is greater than a first threshold, triggering the application layer to send a refresh command to a timestamp manager in the user mode driven UMD includes: if the size of the memory resources occupied by the application program is larger than the first threshold value and the available memory resources of the system are smaller than the second threshold value, triggering the application layer to send a refresh command to a timestamp manager in the user mode driven UMD.
When the available memory resources of the system are greater than or equal to the second threshold, it means that the available memory resources of the system still remain surplus, that is, although some application program continuously consumes the memory resources, the available memory resources of the system still remain surplus, so that the memory resources do not need to be immediately triggered and released, and the situation that the application program flash back occurs is avoided.
In one possible implementation, triggering the application layer to send a refresh command to a timestamp manager in the user mode driven UMD includes: the application layer is triggered to send a refresh command to the timestamp manager for a plurality of times, and the memory resource in the to-be-released state is empty.
Because the third party application program in the application layer sends the refresh command each time, the pipeline in the CPU triggers the release of the memory to be released once, therefore KGSL can trigger the third party application program in the application layer to send the refresh command to the timestamp manager continuously for a plurality of times until no memory resource is in the state to be released. Thereby avoiding repeated triggering and releasing of memory resources.
In one possible implementation, the size of the memory resource is indicated by the number of cache blocks of the memory resource.
The size of the memory resource may be indicated not only by a specific value (e.g., MB, GB) of the memory, but also by the number (e.g., M) of cache blocks occupied by the memory resource.
In one possible implementation, the memory resource refers to a vertex buffer object memory resource or a vertex array object memory resource.
It should be noted that the memory resource may also refer to other types of memory resources, and the present application is not limited thereto.
In a second aspect, there is provided an electronic device comprising a processor and a memory in which instructions are stored which, when executed by the processor, perform a method as described in the first aspect and any of its embodiments.
In a third aspect, there is provided a computer readable storage medium comprising instructions which, when run on an electronic device, cause the electronic device to perform the method of the first aspect and any implementation thereof.
In a fourth aspect, there is provided a computer program product comprising instructions which, when run on an electronic device as described above, cause the electronic device to perform the method of the first aspect and any of its embodiments.
In a fifth aspect, a chip system is provided, the chip system comprising a processor for supporting an electronic device to implement the functions referred to in the first aspect above. In one possible design, the device may further include interface circuitry that may be used to receive signals from other devices (e.g., memory) or to send signals to other devices (e.g., a communication interface). The system-on-chip may include a chip, and may also include other discrete devices.
The technical effects of the second to fifth aspects are referred to the technical effects of the first aspect and any of its embodiments and are not repeated here.
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Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
Fig. 2 is a schematic architecture diagram of software running on an electronic device according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an application layer, a driver layer, and a GPU according to an embodiment of the present application to release old memory resources;
FIG. 4 is a schematic diagram of an application layer, a driver layer, and a GPU according to an embodiment of the present application, in which the GPU cannot release old memory resources;
FIG. 5 is a flowchart of a memory refresh method according to an embodiment of the present application;
FIG. 6 is a schematic diagram of releasing memory resources by forced refresh according to an embodiment of the present application;
Fig. 7 is a schematic structural diagram of a chip system according to an embodiment of the present application.
Detailed Description
Some concepts to which the present application relates will be described first.
The terms "first," "second," and the like, in accordance with embodiments of the present application, are used solely for the purpose of distinguishing between similar features and not necessarily for the purpose of indicating a relative importance, number, sequence, or the like.
The terms "exemplary" or "such as" and the like, as used in relation to embodiments of the present application, are used to denote examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
The terms "coupled" and "connected" in accordance with embodiments of the application are to be construed broadly, and may refer, for example, to a physical direct connection, or to an indirect connection via electronic devices, such as, for example, electrical resistance, inductance, capacitance, or other electrical devices.
The embodiment of the application provides an electronic device, as shown in fig. 1, an electronic device 101 may be a device with a communication function, and the electronic device 101 may be mobile or fixed. The electronic device 101 may be deployed on land (e.g., indoor or outdoor, hand-held or vehicle-mounted, etc.), on water (e.g., ship, etc.), and in the air (e.g., aircraft, balloon, satellite, etc.). The electronic device 101 may be referred to as a User Equipment (UE), an access terminal, a terminal unit, a subscriber unit (subscriber unit), a terminal station, a Mobile Station (MS), a mobile station, a terminal agent, a terminal apparatus, or the like. For example, the electronic device may be a cell phone, tablet computer, notebook computer, etc. The embodiment of the application is not limited to the specific type, structure and the like of the electronic equipment. One possible configuration of the electronic device is described below.
Taking an electronic device as an example of a mobile phone, fig. 1 shows one possible structure of an electronic device 101. The electronic device 101 may include a processor 210, an external memory interface 220, an internal memory 221, a universal serial bus (universal serial bus, USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an ear-headphone interface 270D, a sensor module 280, keys 290, a motor 291, an indicator 292, a camera 293, a display 294, a subscriber identity module (subscriber identification module, SIM) card interface 295, and the like.
The sensor module 280 may include, among other things, a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.
It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device 101. In other embodiments of the application, the electronic device 101 may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
Processor 210 may include one or more processing units such as, for example: the processor 210 may be a field programmable gate array (field programmable GATE ARRAY, FPGA), an application-specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (central processing unit, CPU), an application processor (application processor, AP), a network processor (network processor, NP), a digital signal processor (DIGITAL SIGNAL processor, DSP), a micro control unit (micro controller unit, MCU), a programmable logic device (programmable logic device, PLD), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (IMAGE SIGNAL processor, ISP), a controller, a video codec, a baseband processor, a neural network processor (neural-network processing unit, NPU), or the like. Wherein the different processing units may be separate devices or may be integrated in one or more processors. For example, the processor 210 may be an application processor AP. Or the processor 210 may be integrated in a system on chip (SoC). Or the processor 210 may be integrated in an integrated circuit (INTEGRATED CIRCUIT, IC) chip. The processor 210 may include an Analog Front End (AFE) and a micro-controller unit (MCU) in an IC chip.
The controller may be a neural hub and a command center of the electronic device 101, among others. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.
A memory may also be provided in the processor 210 for storing instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. The memory may hold instructions or data that the processor 210 has just used or recycled. If the processor 210 needs to reuse the instruction or data, it may be called directly from the memory. Repeated accesses are avoided and the latency of the processor 210 is reduced, thereby improving the efficiency of the system.
In some embodiments, processor 210 may include one or more interfaces. The interfaces may include an integrated circuit (inter-INTEGRATED CIRCUIT, I2C) interface, an integrated circuit built-in audio (inter-INTEGRATED CIRCUIT SOUND, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a USB interface, among others.
It should be understood that the connection relationship between the modules illustrated in the embodiment of the present application is only illustrative, and does not limit the structure of the electronic device 101. In other embodiments of the present application, the electronic device 101 may also use different interfacing manners, or a combination of multiple interfacing manners, as in the above embodiments.
The power management module 240 is configured to receive a charging input from a charger. The charger may be a wireless charger (such as a wireless charging base of the electronic device 101 or other devices capable of wirelessly charging the electronic device 101), or may be a wired charger. For example, the power management module 240 may receive a charging input of a wired charger through the USB interface 230. The power management module 240 may receive wireless charging input through a wireless charging coil 242 of the electronic device.
The power management module 240 may also supply power to the electronic device while charging the battery 241. The power management module 240 receives input from the battery 241 to power the processor 210, the internal memory 221, the external memory interface 220, the display 294, the camera 293, the wireless communication module 260, and the like. The power management module 240 may also be configured to monitor parameters of the battery 241 such as battery capacity, battery cycle times, battery health (leakage, impedance), etc. In other embodiments, the power management module 240 may also be disposed in the processor 210.
The wireless communication function of the electronic device 101 may be implemented by the antenna 1, the antenna 2, the mobile communication module 250, the wireless communication module 260, a modem processor, a baseband processor, and the like.
The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 101 may be used to cover a single or multiple communication bands. Different antennas may also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.
The mobile communication module 250 may provide a solution for wireless communication including 2G/3G/4G/5G, etc. applied on the electronic device 101. The wireless communication module 260 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wi-Fi network, WIRELESS FIDELITY), bluetooth (BT), global navigation satellite system (global navigation SATELLITE SYSTEM, GNSS), frequency modulation (frequency modulation, FM), near Field Communication (NFC), infrared (IR), etc. applied on the electronic device 101. In some embodiments, antenna 1 and mobile communication module 250 of electronic device 101 are coupled, and antenna 2 and wireless communication module 260 are coupled, such that electronic device 101 may communicate with a network and other devices via wireless communication techniques.
The electronic device 101 implements display functions through a GPU, a display screen 294, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations for GPU rendering. Processor 210 may include one or more GPUs that execute program instructions to generate or change display information.
The display 294 is used to display images, videos, and the like. The display 294 includes a display panel. In some embodiments, the electronic device 101 may include 1 or N displays 294, N being a positive integer greater than 1.
The electronic device 101 may implement a photographing function through an ISP, a camera 293, a video codec, a GPU, a display screen 294, an application processor, and the like. The ISP is used to process the data fed back by the camera 293. In some embodiments, the ISP may be provided in the camera 293. The camera 293 is used to capture still images or video. In some embodiments, the electronic device 101 may include 1 or N cameras 293, N being a positive integer greater than 1. Exemplary cameras of embodiments of the present application include a wide angle camera and a main camera.
The external memory interface 220 may be used to connect external memory cards, such as Micro SanDisk (Micro SD) cards, to enable expansion of the memory capabilities of the electronic device 101. The external memory card communicates with the processor 210 through an external memory interface 220 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.
Internal memory 221 may be used to store computer executable program code that includes instructions. The processor 210 executes various functional applications of the electronic device 101 and data processing by executing instructions stored in the internal memory 221. In addition, the internal memory 221 may include a high-speed random access memory, and may further include a nonvolatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like.
The memory to which embodiments of the present application relate may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
The electronic device 101 may implement audio functionality through an audio module 270, speaker 270A, receiver 270B, microphone 270C, headphone interface 270D, application processor, and so forth. Such as music playing, recording, etc.
The audio module 270 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal. In some embodiments, the audio module 270 may be disposed in the processor 210, or some functional modules of the audio module 270 may be disposed in the processor 210. Speaker 270A, also referred to as a "horn," is used to convert audio electrical signals into sound signals. A receiver 270B, also referred to as a "earpiece", is used to convert the audio electrical signal into a sound signal. Microphone 270C, also referred to as a "microphone" or "microphone," is used to convert sound signals into electrical signals. The electronic device 101 may be provided with at least one microphone 270C. The earphone interface 270D is for connecting a wired earphone. Earphone interface 270D may be USB interface 230 or a 3.5mm open mobile terminal platform (open mobile terminal platform, OMTP) standard interface, american cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.
Keys 290 include a power on key, a volume key, etc. The keys 290 may be mechanical keys. Or may be a touch key. The electronic device 101 may receive key inputs, generating key signal inputs related to user settings and function controls of the electronic device 101. The motor 291 may generate a vibration alert. The motor 291 may be used for incoming call vibration alerting or for touch vibration feedback. The indicator 292 may be an indicator light, which may be used to indicate a state of charge, a change in power, or an indication message, missed call, notification, etc. The SIM card interface 295 is for interfacing with a SIM card. The SIM card may be inserted into the SIM card interface 295 or removed from the SIM card interface 295 to enable contact and separation from the electronic device 101. The electronic device 101 may support 1 or N SIM card interfaces, N being a positive integer greater than 1. The SIM card interface 295 may support a Nano SIN (Nano SIM) card, a micro SIM (Micro SIM) card, a SIM card, etc. In some embodiments, the electronic device 101 employs an embedded SIM (eSIM) card, which may be embedded in the electronic device 101 and not separable from the electronic device 101.
The processor 210 executes the memory refresh method provided by the embodiment of the present application by executing the programs and instructions stored in the internal memory 221. The programs run by the processor 210 may be based on an operating system, such as Android (Android)Apple (iOS)/>Windows (Windows) operating system, etc.
As shown in fig. 2, the program running on processor 210 is based onFor example, the programs run by the processor 210 are layered by function and may include an application layer, a framework layer, a native layer, a kernel layer, and a driver layer.
The application layer may include various applications that require GPU rendering.
The framework layer is used to provide application programming interfaces (application programming interface, APIs) and system resource services, such as GPU rendering APIs, to applications in the application layer.
The native layer may provide a static link library or a dynamic link library for API calls by the framework layer. For example, providing a static link library or a dynamic link library to a GPU rendering API in the framework layer.
The kernel layer includes an Operating System (OS) kernel. The operating system kernel is used for managing the processes, the memory, the driving program, the file system and the network system of the system.
The driving layer is used for driving hardware resources of the hardware layer. GPU driver may be included in the driver layer. The driving layer in the application comprises a User Mode Driver (UMD) and a kernel mode driver of the GPU. The UMD maintains a timestamp (TIME STAMP, TS) manager for maintaining timestamps for individual memory resources. The kernel mode driver includes, for example, a kernel graphics support layer (KERNEL GRAPHICS support layer, KGSL).
The process of the application layer, the driver layer and the GPU to release old VBO memory resources or VAO memory resources (simply referred to as memory resources) is shown in fig. 3, and includes:
S101, after the GPU rendering is completed, an application program in the application layer sends a refreshing command to UMD in the driving layer to indicate to release old memory resources.
And S102, after receiving the refresh command, the TS manager in the UMD sends a timestamp (such as TS 500) of the memory resource to be released to KGSL.
In S103, KGSL, a timestamp is marked for each memory resource, and when the timestamp issued by the UMD is the same as the timestamp of the KGSL for maintaining the memory resource, the timestamp (for example, TS 500) is sent to the GPU, and the pipeline of the GPU is triggered to start.
S104, the pipeline of the GPU switches the timestamp in the submitted state to the retirement (retired) state, switches the timestamp in the queuing (queued) state to the submitted state, and sets the timestamp issued by KGSL to the queuing (queued) state.
For example, the pipeline of the GPU switches timestamp TS300 in the committed (subtended) state to the retired (retired) state, switches timestamp TS400 in the queued (queued) state to the committed (subtended) state, and sets timestamp TS500 issued by KGSL to the queued (queued) state.
S105, the GPU instructs KGSL to release the memory resource corresponding to the timestamp (e.g. TS 300) in the retirement (retired) state.
S106, KGSL releases the memory resource corresponding to the timestamp (e.g., TS 300) in the retirement (retired) state.
If the memory resources applied by the application program during GPU rendering are too large, and new memory resources are continuously applied without sending a refresh command to UMD in the driving layer, the memory resource release process cannot be triggered, so that the memory resources in a state to be released are continuously accumulated, and the available memory is exhausted, so that the whole machine is blocked, restarted or halted. For example, as shown in fig. 4, the application cannot execute step S101 to send a refresh command to the UMD in the driver layer, so that the timestamp TS500 cannot be synchronized from the UMD to KGSL, the pipeline of the GPU will not update the timestamp, KGSL will not release the memory resource in the state to be released.
Therefore, in the memory refreshing method provided by the embodiment of the application, KGSL is used for triggering the application layer to send the refreshing command to the UMD by monitoring the size of memory resources occupied by each application program when the accumulation reaches the threshold value, so as to trigger the memory release flow based on the time stamp mechanism to release the memory resources in the state to be released.
As shown in fig. 5, the memory refresh method includes:
S201, determining a first threshold value of memory resources occupied by an application program according to the behaviors of the application program that memory resources are allocated and released.
As described above, in the embodiments of the present application, the memory resource may refer to VBO memory resource or VAO memory resource for GPU rendering. It should be noted that the memory resource may also refer to other types of memory resources, and the present application is not limited thereto.
The size of the memory resource may be indicated not only by a specific value (e.g., MB, GB) of the memory, but also by the number (e.g., M) of cache blocks occupied by the memory resource. The present application is described by taking specific values of memory as examples, but is not limited thereto.
Pile points can be added in the flow of requesting to allocate the memory resources and the flow of requesting to release the memory resources, and the behaviors of requesting to allocate the memory resources and requesting to release the memory resources of various application programs (such as chat programs, video programs and the like) can be obtained through big data statistics and the like. It should be noted that, the above request to release the memory resource refers to that the application program sends a refresh command to a timestamp manager in the UMD to trigger a memory release flow based on a timestamp mechanism. The refresh command is used to instruct the timestamp manager to update the timestamp of the memory resource in the to-be-released state to release the memory resource in the to-be-released state, and the description of steps S101-S105 is specifically referred to and will not be repeated herein.
For the memory release flow based on the timestamp mechanism, the application program requests to release the memory resource within a certain time after requesting to allocate the memory resource, so as to realize flexible allocation of the memory resource. If an application program continuously requests allocation of memory resources and does not request release of memory resources within a preset time after the request of allocation of memory resources, the application program is an abnormal application, and eventually all available memory resources may be exhausted. If an application program can request to release memory resources within a preset time after each request to allocate memory resources, the application program is a normal application, and the memory resources occupied by the application program are limited and not all available memory resources are exhausted, so that it can be determined that the first threshold value of the memory resources occupied by the application program is greater than the maximum value of the memory resources occupied by the application program.
That is, a corresponding first threshold value may be set for each application. Or for a plurality of application programs, a first threshold value of the unified application program occupying memory resources can be set for the plurality of application programs, namely the first threshold value is larger than the maximum value of the memory resources occupied by the plurality of application programs respectively. For example, if a certain chat program of the N application programs occupies the largest memory resource and has a size of 1G, the first threshold may be 1.5G.
S202, when the size of the memory resources occupied by the application program is larger than a first threshold, KGSL triggers a third party application program in the application layer to send a refresh command to a timestamp manager in the UMD.
For example, as shown in fig. 6, assuming that a certain chat program occupies a first threshold of 1.5G of memory resources, when the size of the memory resources occupied by the application program is greater than 1.5G, KGSL triggers the application program in the application layer to send a refresh command to the timestamp manager in the UMD to trigger a memory release procedure based on the timestamp mechanism, so that the foregoing steps S101-S105 can be continuously executed.
Further, if the size of the memory resources occupied by the application program is greater than a first threshold of the memory resources occupied by the application program and the available memory of the system is less than a second threshold, the application layer is triggered to send a refresh command to a timestamp manager in the user mode driven UMD. When the available memory resources of the system are greater than or equal to the second threshold, it means that the available memory resources of the system still remain surplus, that is, although some application program continuously consumes the memory resources, the available memory resources of the system still remain surplus, so that the memory resources do not need to be immediately triggered and released, and the situation that the application program flash back occurs is avoided.
In particular, since the third party application in the application layer sends the refresh command each time, the pipeline in the CPU triggers the release of the memory to be released once, so KGSL can trigger the third party application in the application layer to send the refresh command to the timestamp manager continuously for multiple times until there is no memory resource in the state to be released. Thereby avoiding repeated triggering and releasing of memory resources.
According to the memory refreshing method and the electronic device, a first threshold value of memory resources occupied by an application program is determined according to the behaviors of memory resources allocation and memory resources release requested by the application program; if the size of the memory resources occupied by the application program is larger than a first threshold, triggering the application layer to send a refresh command to a time stamp manager in the UMD, wherein the refresh command is used for indicating the time stamp manager to update the time stamp of the memory resources in a to-be-released state, and triggering a memory release flow based on a time stamp mechanism to release the memory resources in the to-be-released state. Thereby realizing timely release of memory resources.
As shown in fig. 7, the embodiment of the application further provides a chip system. The chip system 70 includes at least one processor 701 and at least one interface circuit 702. The at least one processor 701 and the at least one interface circuit 702 may be interconnected by wires. The processor 701 is configured to enable the electronic device to implement the steps in the above-described method embodiments, such as the method illustrated in fig. 5, and the at least one interface circuit 702 may be configured to receive signals from other devices (e.g., memory) or to transmit signals to other devices (e.g., a communication interface). The system-on-chip may include a chip, and may also include other discrete devices.
Embodiments of the present application also provide a computer-readable storage medium comprising instructions that, when executed on an electronic device as described above, cause the electronic device to perform the steps of the method embodiments described above, for example, performing the method shown in fig. 5.
Embodiments of the present application also provide a computer program product comprising instructions which, when run on an electronic device as described above, cause the electronic device to perform the steps of the method embodiments described above, for example to perform the method shown in fig. 5.
Technical effects concerning the chip system, the computer-readable storage medium, the computer program product refer to the technical effects of the previous method embodiments.
It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and module may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or components may be combined or integrated into another device, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physically separate, i.e., may be located in one device, or may be distributed over multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present application may be integrated in one device, or each module may exist alone physically, or two or more modules may be integrated in one device.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. A memory refresh method, comprising:
if the application program requests to release the memory resources within a preset time after the application program requests to allocate the memory resources, determining that the first threshold value is larger than the maximum value of the memory resources occupied by the application program; the request to release the memory resource means that the application program sends a refresh command to a time stamp manager in the user mode driving UMD so as to trigger a memory release flow based on a time stamp mechanism;
And if the size of the memory resources occupied by the application program is larger than the first threshold, triggering the application layer to send a refresh command to the timestamp manager, wherein the refresh command is used for indicating the timestamp manager to update the timestamp of the memory resources in the to-be-released state so as to release the memory resources in the to-be-released state.
2. The method of claim 1, wherein triggering the application layer to send a refresh command to a timestamp manager in the user mode driven UMD if the size of memory resources occupied by the application program is greater than the first threshold comprises:
And if the size of the memory resources occupied by the application program is larger than the first threshold value and the available memory resources of the system are smaller than the second threshold value, triggering the application layer to send a refresh command to a timestamp manager in the user mode driving UMD.
3. The method of claim 1 or 2, wherein the triggering the application layer to send a refresh command to a timestamp manager in the user mode driven UMD comprises:
and continuously triggering an application layer for multiple times to send the refresh command to the timestamp manager, wherein the memory resource in the to-be-released state is empty.
4. A method according to claim 1 or 2, characterized in that,
The size of the memory resource is indicated by the number of cache blocks of the memory resource.
5. A method according to claim 1 or 2, characterized in that,
The memory resource refers to a vertex buffer object memory resource or a vertex array object memory resource.
6. An electronic device comprising a processor and a memory, the memory storing instructions that, when executed by the processor, perform the method of any of claims 1-5.
7. A computer readable storage medium comprising instructions which, when executed on an electronic device, cause the electronic device to perform the method of any of claims 1-5.
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