CN116737086B - Read-write method of embedded nonvolatile memory - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000012937 correction Methods 0.000 claims abstract description 38
- 230000003139 buffering effect Effects 0.000 claims abstract description 5
- 238000003860 storage Methods 0.000 claims description 44
- 238000004891 communication Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 8
- 235000019580 granularity Nutrition 0.000 description 23
- 238000004590 computer program Methods 0.000 description 10
- 239000002245 particle Substances 0.000 description 9
- 238000012545 processing Methods 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 230000032683 aging Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000004422 calculation algorithm Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000013515 script Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a read-write method of an embedded nonvolatile memory, which comprises the following steps of S1: the processor receives the access instruction and puts the access instruction into an access instruction buffer queue; buffering and adjusting the sequence of the access instructions and sending the first access instruction; step S2: the read-write control module obtains the control mode of the access instruction; adjusting the control mode based on real-time access conditions to obtain a copy control mode; step 3, executing the access instruction in a control mode to obtain first data, and then executing the copy access instruction in a copy control mode to obtain second data; acquiring an access result of the access instruction based on the first data and the second data; the application is based on the existing nonvolatile memory structure, fully utilizes the embedded characteristic and the existing error correction technology, and enhances the reading reliability on the basis of not increasing or basically not increasing the cost of software and hardware by providing accurate redundancy.
Description
Technical Field
The application belongs to the technical field of memories, and particularly relates to a read-write method of an embedded nonvolatile memory.
Background
With the rapid development of the emerging information technology industries such as cloud computing, big data, internet of things, mobile internet and the like, the storage, transmission and processing of data are unprecedented both in speed and in scale. Statistically, the amount of information newly generated worldwide doubles every three years. How to safely and reliably persist such data is undoubtedly true. In general, user data are stored in a nonvolatile memory, and a conventional nonvolatile memory is a mechanical hard disk, and the hard disk has low production cost, large capacity and low stability and speed of reading and writing. With the continued development of information technology, a variety of storage technologies have emerged. The current advanced solid state disk is composed of flash memory particles, and has the advantages of shock resistance, falling resistance, high reading speed, low power consumption, low weight, low noise and the like, but has high production cost, small capacity and short service life. The solid state disk using the flash memory as a storage medium is one of the storage technologies, has low cost and is commonly used for large-scale data storage; the solid state disk of the flash memory is a basic storage unit; the voltage distribution state of the medium particles of the basic solid-state memory unit is wrong along with the increase of the using time length, on one hand, the programming interference among the medium particles in the programming process and the like can cause the voltage distribution of the medium to deviate along with the continuous increase of the erasing times of the medium particles, and the judgment error of reading the state of the medium particles can be greatly increased if the medium particles are read by using the reading voltage threshold under ideal conditions. On the other hand, as the placement time of the medium particles increases, electrons stored in the medium particles leak, which also causes the voltage distribution of the medium to shift, and similarly, the judgment error of reading the state of the medium particles increases greatly.
Furthermore, for various types of embedded nonvolatile memories, on one hand, with the continuous improvement and improvement of the integrated circuit technology of the memory chip, more and more components such as transistors distributed in unit area or volume, the gaps between circuits are smaller and smaller, and the integrated circuits face serious tests in the aspects of radiation resistance, electromagnetic interference resistance and the like. In order to save energy and reduce power consumption, a low-voltage or dynamic low-order voltage supply mode is often adopted in a memory chip circuit, and when the signal level is close to or lower than noise, the white noise and the thermal noise in the circuit can lead to the rapid performance degradation, and circuit faults frequently occur. On the other hand, because of the limitation of mathematical theory development, the error correction or correction technology is difficult to break through on algorithm to improve the execution speed of software and hardware; therefore, how to fully utilize the embedded characteristics and the existing correction technology based on the existing nonvolatile memory structure, and to enhance the reading reliability on the basis of not increasing or not substantially increasing the cost of software and hardware by providing accurate redundancy is a technical problem to be solved.
Disclosure of Invention
In order to solve the above-mentioned problems in the prior art, the present application provides a method for reading and writing an embedded nonvolatile memory, which includes:
step S1: the processor receives the access instruction and puts the access instruction into an access instruction buffer queue; buffering and adjusting the order of access instructions; the read-write control module is used for sending the first access instruction in the access instruction buffer queue to the memory;
the order of the access instructions is adjusted specifically as follows: determining an adjustment window, acquiring a control mode of a storage unit to which a data page to which an access instruction in the adjustment window belongs, reducing the distance between access instructions to specific storage units on the basis of guaranteeing the access timeliness of the access instructions, adjusting the access instructions to the specific storage units into the adjustment window or in front of the adjustment window, and adjusting the access instructions not to the specific storage units out of the adjustment window or in back of the adjustment window; wherein: the specific storage unit is a storage unit with the error occurrence frequency being greater than a preset frequency or the number of the error occurrence instructions in the latest M access instructions exceeding the upper limit value of the error instructions; m, the preset frequency and the upper limit value of the error instruction are preset values;
step S2: the read-write control module obtains the control mode of the access instruction; adjusting the control mode based on real-time access conditions to obtain a copy control mode; generating a copy of the access instruction to obtain a copy access instruction; the access positions of the access instruction and the copy access instruction are the same;
the control mode is adjusted based on the real-time access condition to obtain a copy control mode, which specifically comprises the following steps: adjusting parameter values in the control mode according to the parameter values in the real-time access conditions, so that the adjusted control mode is more suitable for a storage unit under the current access conditions under the condition that the access conditions are unchanged;
step S3, executing the access instruction in a control mode to obtain first data, and then executing the copy access instruction in a copy control mode to obtain second data; detecting whether the first data is in error or not, and accumulating a first error count if the first data is in error; detecting whether the second data is wrong, and if so, accumulating a second error count; acquiring an access result of the access instruction based on the first data and the second data;
the method comprises the steps that an access result of an access instruction is obtained based on first data and second data, specifically, a hardware error correction device or a software error correction device is adopted to correct the first data and/or the second data so as to obtain the access result of the access instruction;
step S4: determining a control mode of a storage unit corresponding to the data page based on the first error count and the second error count; the method comprises the following steps: calculating an addition value of the first error count and the second error count; when the sum is smaller than a preset count value, keeping the current control mode unchanged; otherwise, when the first error count is greater than or equal to the second error count, the current control mode is kept unchanged; when the first error count is smaller than the second error count, increasing the unit count value of the data unit by 1; the cell count value of the data cell counts only once for each data page; and further determining whether the ratio between the increased unit count value and the number of the data pages contained in the data unit exceeds a preset ratio, and if so, updating the control mode of the data page corresponding to the data unit.
Further, the order of adjusting the access instructions is started every a preset time length.
Further, when the execution unit of the processor is in an idle state, the sequence of the access instructions is started to be adjusted.
Further, the specific memory cell is one or more.
Further, the error count is used for accumulating the number of times that the data page has errors.
Further, the error count is used for accumulating bit error times.
Further, the preset ratio is 50%.
Further, the hardware error correction device is an ECC module.
An embedded nonvolatile memory read-write device comprises a memory and a read-write control module; the embedded nonvolatile memory read-write device is in communication connection with the processor through a memory access interface; and the read-write control module executes the read-write method of the embedded nonvolatile memory.
A chip comprising an embedded non-volatile memory read-write device and a processor; the embedded nonvolatile memory read-write device comprises a memory and a read-write control module; and the read-write control module executes the read-write method of the embedded nonvolatile memory.
The beneficial effects of the application include:
(1) The access order of the access instructions is adjusted according to the control mode level, the access instructions of the high-frequency and high-service-life storage unit area are delayed as much as possible, the continuous electromagnetic interference of the thermal storage unit is avoided, the access frequency and aging progress of the storage units in the memory are averaged on the basis of providing two-stage correction support, and the memory access efficiency and the service life are improved from a longer period;
(2) Setting a copy access instruction subjected to a refined adjustment control mode for a current access instruction through quantitative calculation, and greatly increasing the probability of a correct access result under the condition of not increasing control difficulty on the basis of meeting access time efficiency of the access instruction; forming a smooth transition of the control mode of the whole storage unit based on the copy control mode;
(3) Based on the characteristics of the embedded nonvolatile memory, the method of adjusting the sequence of the access instructions at the front end enables the rear end to introduce a software correction mode for auxiliary correction, greatly reduces the software correction cost of the access instructions, and reduces the rapid increase of parameters in a control mode by the software mode so as to avoid the increase of hardware cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and together with the description serve to explain the application, if necessary:
fig. 1 is a schematic diagram of a read-write method of an embedded nonvolatile memory provided by the application.
Detailed Description
The present application will now be described in detail with reference to the drawings and the specific embodiments thereof, wherein the exemplary embodiments and the description are for the purpose of illustrating the application only and are not to be construed as limiting the application. The application provides a read-write method of an embedded nonvolatile memory, which comprises the following steps:
step S1: the processor receives the access instruction and puts the access instruction into an access instruction buffer queue; buffering and adjusting the order of access instructions; the read-write control module is used for sending the first access instruction in the access instruction buffer queue to the memory;
preferably: starting the sequence of the access command to be adjusted every preset time length; for example: the preset time degree is equal to the waiting time limit length of the software error correction pool;
alternatively, the following is used: when an execution unit of the processor is in an idle state, starting to adjust the sequence of the access instructions;
the order of the access instructions is adjusted specifically as follows: determining an adjustment window, acquiring a control mode of a storage unit where a data page is located for an access instruction in the adjustment window, reducing the distance between the access instructions for a specific storage unit on the basis of ensuring the access timeliness of the access instructions, adjusting the access instruction for the specific storage unit into the adjustment window or in front of the adjustment window, and adjusting the access instruction not for the specific storage unit out of the adjustment window or in back of the adjustment window; wherein: the specific storage unit is a storage unit with the error occurrence frequency being greater than a preset frequency or the number of the error occurrence instructions in the latest M access instructions exceeding the upper limit value of the error instructions; m, the preset frequency and the upper limit value of the error instruction are preset values; by such adjustment, the software error correction pool is filled up in a concentrated way soon, so that the software error correction is started, and the time cost and the hardware cost of the software error correction are shared;
preferably: the specific memory unit is one or more;
alternatively, the adjusting the order of the access instructions specifically includes: determining an adjustment window, acquiring a control mode of a storage unit to which a data page corresponding to an access instruction in the adjustment window belongs, and adjusting the access instruction corresponding to a low-level control mode to be before the access instruction corresponding to a high-level control mode; wherein: presetting the level of a control mode;
the determining an adjustment window specifically includes: taking the average or minimum access instruction number corresponding to the access result which can be accommodated by the software error correction pool as the width of an adjustment window, and taking the instruction width started by the head of the buffer queue as the adjustment window;
preferably: presetting a control mode and the level of control parameters thereof; the set criterion is that the low-level control mode corresponds to a storage unit with lower ageing degree and/or access frequency, and the high-level control mode corresponds to a storage unit with higher ageing degree and/or access frequency; specific: the parameter value of the control parameter corresponding to the low-level control mode is smaller than the parameter value of the control parameter corresponding to the high-level control mode; when the first control parameter of the existing control mode A of the two control modes is smaller than the control mode B and the second control parameter of the control mode A is larger than the control mode B, considering that the level of the second control parameter is higher than the first control parameter, setting the control mode A as a high-level control mode and the control mode B as a low-level control mode; the level of the control parameter is related to the control difficulty, the control expense and the like; for example: setting the voltage as a first control parameter and the access time length as a second control parameter;
preferably: setting a first control parameter, a second control parameter and a third control parameter as voltage, a current threshold value and a time length; the corresponding levels are sequentially increased; obviously, the level can be set to be 2,3,4 and so on according to the number of the control parameters;
the order of the access instructions is adjusted, specifically comprising the following steps:
step S1_SA1, initializing and setting a processing pointer to point to an access instruction at the head of an access instruction buffer queue;
step S1_SA2, determining whether the level of the control mode corresponding to the current access instruction is lower than that of the control mode corresponding to the next access instruction adjacent to the current access instruction, if so, further determining whether the current access instruction reaches or is about to reach access timeliness, and if not, exchanging the positions of the current access instruction and the next access instruction;
step S1_SA3, moving the processing pointer backwards by one position;
step S1-SA 4, judging whether the length of the current processing pointer position from the head of the buffer queue is larger than or equal to the width of the adjustment window, if so, ending; otherwise, returning to the step S1_SA2;
the application adjusts the order of access instructions based on the control mode level, delays the access instructions of the high-frequency and long-life storage unit area as much as possible, avoids the continuous electromagnetic interference of the thermal storage unit, averages the access frequency and aging progress of the storage unit in the memory on the basis of providing two-stage correction support, and improves the memory access efficiency and the service life from a longer period;
step S2: the read-write control module obtains the control mode of the access instruction; adjusting the control mode based on real-time access conditions to obtain a copy control mode; generating a copy of the access instruction to obtain a copy access instruction; the access positions of the access instruction and the copy access instruction are the same; wherein: the access includes reading and writing; the access condition comprises one or a combination of access condition parameters such as memory temperature, memory use time, access times, memory service life, memory unit continuous access time, memory unit access frequency, local temperature, memory unit aging degree and the like; the control mode comprises one or a combination of control parameters such as voltage, threshold current and/or time length adopted in reading and writing;
the control mode of the read-write control module for obtaining the access instruction comprises the following specific steps: the read-write control module obtains an access position of an access instruction and maps the access position to a data page; acquiring a control mode corresponding to a storage unit to which the data page belongs; wherein: the memory comprises memory cells arranged in an array, and the memory cells comprise data pages;
the control mode is adjusted based on the real-time access condition to obtain a copy control mode, which specifically comprises the following steps: according to the parameter values in the access conditions, the parameter values in the control mode are adjusted, so that the adjusted control mode is more suitable for the storage unit under the current access conditions under the condition that the access conditions are unchanged, and the accuracy of access is improved;
according to the application, the copy access instruction in a refined adjustment control mode is set for the current access instruction through quantitative calculation, and the probability of a correct access result is greatly increased under the condition of not increasing the control difficulty on the basis of meeting the access time of the access instruction; forming a smooth transition of the control mode of the whole storage unit based on the copy control mode;
alternatively, the following is used: the method for adjusting the control mode based on the real-time access condition to obtain a copy control mode specifically comprises the following steps:
step s2_sa1: acquiring a first parameter part in the access condition parameters; obtaining a first adjusted granularity based on the first parameter portion; obtaining a second adjusted granularity based on the second parameter portion; wherein: the access condition parameters include a first parameter portion and a second parameter portion; the first parameter portion includes a parameter portion that increases over time; the second parameter portion is a parameter portion that may increase, decrease, or not change over time;
preferably: the first parameter part comprises one or a combination of memory use time, memory service life, access times and the like; the second parameter part comprises one or a combination of memory temperature and the change direction thereof, continuous access time length (times) and the change direction thereof, memory unit access frequency and the change direction thereof, local temperature and the change direction thereof and the like;
the first adjustment granularity is obtained based on the first parameter part, specifically: searching a first adjustment granularity comparison table to obtain a first adjustment granularity corresponding to the first parameter part;
preferably: a comparison table of the relation between the first parameter part and the first adjustment granularity is stored in advance; in the first adjustment granularity comparison table, parameter value ranges of different first parameter parts correspond to different first adjustment granularities; for example: the longer the memory use time length is, the shorter the service life is, and the more the access times are, the larger the corresponding first adjustment granularity is; it should be noted that the parameter value range correspondingly adjusts the granularity, rather than corresponding the granularity for each value; the relationship between the two cannot be expressed by continuous curves, but the fuzzy zones exist in different factors; so in step S3 a counting vote is required;
preferably: the first and second adjustment granularities are proportional values; for example: 1-5%;
the second adjustment granularity is obtained based on the second parameter part; the method comprises the following steps: searching a second adjustment granularity comparison table to obtain a second adjustment granularity corresponding to the second parameter part; the setting and using modes are the same as those of the first adjusting granularity comparison table;
alternatively, the following is used: calculating a second adjustment granularity corresponding to the second parameter portion by fitting a function f (p2+var_p2) -f (p 2) or (f (p2+var_p2) -f (p 2))/f (p 2); wherein: p2 is a second parameter part; var_p2 is a change value corresponding to the change direction; f () is a fitting function obtained by fitting based on the second parameter part and the corresponding optimal control parameter; it can be seen that this granularity of adjustment is in two directions, which can be positive or negative;
preferably: the optimal control parameter is the control parameter value when the memory access error rate is the lowest;
step s2_sa2: acquiring control parameters in a control mode; determining the number of control parameters to be adjusted and the adjustment value size based on the first adjustment granularity and the second adjustment granularity; so that the first adjustment granularityAnd/or a second adjustment of the granularity +.>The larger the number of control parameters to be adjusted is, the larger the number of control parameters to be adjusted is and/or the larger the adjustment value is;
preferably: determining the number of control parameters corresponding to the adjustment control mode CStr and an adjustment value thereof by adopting the following method; wherein:for controlling parameters->And->And->Other expressions and so forth;
respectively, the control parameter is increased or decreased by a unit value; />Indicating that the control parameter is increased by two unit values; for example: setting a unit value to be 1-5% of an original value; />Respectively representing the interval range within which the adjustment granularity falls; and->；
Preferably: the interval range is a preset value; the interval range can be set by average dividing the transformation range of the adjustment granularity;
step s3_sa3: updating the control mode based on the adjusted control parameters to obtain a copy control mode;
step 3, executing the access instruction in a control mode to obtain first data, and then executing the copy access instruction in a copy control mode to obtain second data; detecting whether the first data is in error or not, and accumulating a first error count if the first data is in error; detecting whether the second data is wrong, and if so, accumulating a second error count; acquiring an access result of the access instruction based on the first data and the second data;
preferably: the error count is used for accumulating the times of errors of the data page;
alternatively, the following is used: the error count is used for accumulating bit errors;
the access result of the access instruction is obtained based on the first data and the second data; the method comprises the following steps: the method comprises the steps that an access result of an access instruction is obtained based on first data and second data, specifically, a hardware error correction device or a software error correction device is adopted to correct the first data and/or the second data so as to obtain the access result of the access instruction;
more specifically, the method for acquiring the access result of the access instruction based on the first data and the second data includes the following steps:
step s3_sa1: if the first data or the second data are not in error, the first data or the second data which are not in error are used as an access result of the access instruction; if not, entering the next step;
step s3_sa2: if the second data and the second data are both in error, selecting the smaller one of the first error count and the second error count, and correcting the data error by adopting a hardware error correction device for the smaller one; if the error is uncorrectable, correcting data errors by adopting a hardware error correction device for more users; if the error is still uncorrectable, then entering the next step;
preferably: the hardware error correction device is an ECC module; when the ECC code is adopted to correct data, the number of data bits which can be corrected is related to the ECC correction intensity and the number of ECC bits, the more the data can be corrected, the more complex the algorithm adopted by the ECC module is, the more the number of ECC bits is, and the more the time and hardware cost are needed; therefore, in some cases, the separate buffer page setting ECC module is often not the best choice, and may obtain erroneous results with great hardware overhead wasted;
step s3_sa3: buffering the first data and the second data to a software error correction pool;
preferably: the software error correction pool is arranged in the read-write control module, and when the software error correction pool is full or the waiting time limit arrives, data in the software error correction pool are sent to the processor to perform software error correction;
alternatively, the following is used: the software error correction pool is arranged in the processor and can adopt a mode of centralized transmission or each transmission;
step s3_sa4: the processor adopts a software error correction device to correct the data in the software error correction pool; taking the correction result corresponding to the first data or the second data in the software error correction pool as an access result of the access instruction; of course, the software error correction pool contains a plurality of groups of first data and second data corresponding to a plurality of access instructions, the results of the data are obtained at the same time, and the software and hardware cost is shared;
preferably: the software error correction device is an LDPC decoding device;
preferably: the software error correction device comprises an LDPC hard decoding module and an LDPC soft decoding module;
based on the characteristics of the embedded nonvolatile memory, the application enables the rear end to introduce a software correction mode for auxiliary correction by adjusting the sequence of the access instructions at the front end, greatly reduces the software correction cost of the access instructions, reduces the rapid increase of parameters in a control mode by the software mode, thereby avoiding the increase of hardware cost, improving the access efficiency of the memory and prolonging the service life of the memory;
step S4: determining a control mode of a storage unit corresponding to the data page based on the first error count and the second error count; the method comprises the following steps: calculating an addition value of the first error count and the second error count; when the sum is smaller than a preset count value, keeping the current control mode unchanged; otherwise, when the first error count is greater than or equal to the second error count, the current control mode is kept unchanged; when the first error count is smaller than the second error count, increasing the unit count value of the data unit by 1; the cell count value of the data cell counts only once for each data page; further determining whether the ratio between the increased unit count value and the number of the data pages contained in the data unit exceeds a preset ratio, and if so, updating the control mode of the data page corresponding to the data unit;
preferably: the preset ratio is 50%;
the control mode of the data unit corresponding to the updated data page specifically comprises the following steps: the control mode of updating the data unit is a copy control mode;
alternatively, the following is used: the control mode of the data unit corresponding to the updated data page specifically comprises the following steps: when the control mode of the updated data unit is the latest N data page accesses, the copy control mode has the largest occurrence number;
alternatively, the following is used: the control mode of the data unit corresponding to the updated data page specifically comprises the following steps: the control mode of updating the data unit is to sequentially increase a control parameter in the control mode by a unit value when each updating time arrives; that is, only one control parameter is updated every time it is updated, and the next update updates another control parameter, and loops in turn;
based on the same inventive concept, the application also provides an embedded nonvolatile memory read-write device; the device comprises a memory and a read-write control module; the embedded nonvolatile memory read-write device is in communication connection with the processor through a memory access interface;
wherein: the memory is an embedded nonvolatile memory and comprises a plurality of memory units which are arranged in an array and used for storing data, wherein each memory unit comprises a plurality of data pages, and operations such as reading, writing, verifying, clearing and the like of the nonvolatile memory are performed by taking the data pages as units; the array structure is organized according to a row-column structure;
preferably: each column of memory cells is connected with the page through a bit line, and the grid electrode of each row of memory cells is connected with a word line decoder through a word line; the read-write control module controls the word line voltage generator and the data page; when the read operation is carried out, the control logic applies the read voltage to the selected word line through controlling the word line voltage generator, and after the read passing voltage is applied to the unselected word line, the control data page senses the data stored in the memory cells on the corresponding bit line according to different read operation methods, so that the data of the data page is read;
based on the same inventive concept, the application also provides a chip, which comprises the embedded nonvolatile memory read-write device and a processor; wherein: the processor is one or more;
the application is operational with numerous general purpose or special purpose computing system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
In the above embodiments, while the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory structures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed. The embodiments of the application are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
A computer program (also known as a program, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object or other unit suitable for use in a computing environment. The computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the application without departing from the spirit and scope of the application, which is intended to be covered by the claims.
Claims (10)
1. A method for reading from and writing to an embedded non-volatile memory, the method comprising:
step S1: the processor receives the access instruction and puts the access instruction into an access instruction buffer queue; buffering and adjusting the order of access instructions; the read-write control module is used for sending the first access instruction in the access instruction buffer queue to the memory;
the order of the access instructions is adjusted specifically as follows: determining an adjustment window, acquiring a control mode of a storage unit to which a data page to which an access instruction in the adjustment window belongs, reducing the distance between access instructions to specific storage units on the basis of guaranteeing the access timeliness of the access instructions, adjusting the access instructions to the specific storage units into the adjustment window or in front of the adjustment window, and adjusting the access instructions not to the specific storage units out of the adjustment window or in back of the adjustment window; wherein: the specific storage unit is a storage unit with the error occurrence frequency being greater than a preset frequency or the number of the error occurrence instructions in the latest M access instructions exceeding the upper limit value of the error instructions; m, the preset frequency and the upper limit value of the error instruction are preset values;
step S2: the read-write control module obtains the control mode of the access instruction; adjusting the control mode based on real-time access conditions to obtain a copy control mode; generating a copy of the access instruction to obtain a copy access instruction; the access positions of the access instruction and the copy access instruction are the same;
the control mode is adjusted based on the real-time access condition to obtain a copy control mode, which specifically comprises the following steps: adjusting parameter values in the control mode according to the parameter values in the real-time access conditions, so that the adjusted control mode is more suitable for a storage unit under the current access conditions under the condition that the access conditions are unchanged;
step S3, executing the access instruction in a control mode to obtain first data, and then executing the copy access instruction in a copy control mode to obtain second data; detecting whether the first data is in error or not, and accumulating a first error count if the first data is in error; detecting whether the second data is wrong, and if so, accumulating a second error count; acquiring an access result of the access instruction based on the first data and the second data;
the method comprises the steps that an access result of an access instruction is obtained based on first data and second data, specifically, a hardware error correction device or a software error correction device is adopted to correct the first data and/or the second data so as to obtain the access result of the access instruction;
step S4: determining a control mode of a storage unit corresponding to the data page based on the first error count and the second error count; the method comprises the following steps: calculating an addition value of the first error count and the second error count; when the sum is smaller than a preset count value, keeping the current control mode unchanged; otherwise, when the first error count is greater than or equal to the second error count, the current control mode is kept unchanged; when the first error count is smaller than the second error count, increasing the unit count value of the data unit by 1; the cell count value of the data cell counts only once for each data page; and further determining whether the ratio between the increased unit count value and the number of the data pages contained in the data unit exceeds a preset ratio, and if so, updating the control mode of the data page corresponding to the data unit.
2. The method of claim 1, wherein the order of access commands is initiated at predetermined intervals.
3. The method of claim 2, wherein the order of access instructions is initiated when an execution unit of the processor is in an idle state.
4. The method of claim 3, wherein the specific memory cells are one or more.
5. The method of claim 4, wherein the error count is used to accumulate the number of errors occurring in the data page.
6. The method of claim 4, wherein the error count is used to accumulate bit numbers.
7. The method of claim 4, wherein the predetermined ratio is 50%.
8. The method of claim 4, wherein the hardware error correction device is an ECC module.
9. An embedded nonvolatile memory read-write device is characterized by comprising a memory and a read-write control module; the embedded nonvolatile memory read-write device is in communication connection with the processor through a memory access interface; the read-write control module executes the read-write method of the embedded nonvolatile memory as claimed in claim 1.
10. A chip, characterized in that the chip comprises an embedded nonvolatile memory read-write device and a processor; the embedded nonvolatile memory read-write device comprises a memory and a read-write control module; the read-write control module executes the read-write method of the embedded nonvolatile memory as claimed in claim 1.
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