CN116724495A

CN116724495A - Receiver, electronic device and eye pattern detection method in receiver

Info

Publication number: CN116724495A
Application number: CN202180088004.8A
Authority: CN
Inventors: 王东; 赵兴; 宗洪强
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-01-30
Filing date: 2021-01-30
Publication date: 2023-09-08
Also published as: WO2022160309A1

Abstract

The application provides a receiver, electronic equipment and an eye pattern detection method in the receiver, relates to the technical field of electronics, and is used for solving the problem that burst error codes cannot be displayed in the prior art. The receiver includes two signal paths, a first signal path and a second signal path, respectively. The first signal path is a signal conversion path of normal service; the second signal path is an eye diagram detection path for drawing an eye diagram. In the receiver, the second signal path uses the clock signal recovered by the clock data recovery unit in the first signal path to perform phase shift, and the quality of the received signal can be intuitively reflected by collecting the digital signal sampled and output by the second signal path and drawing an eye diagram, and the parameters of the signal processing system are adjusted by processing the eye diagram to obtain the corresponding control signal, so that the error rate of the signal is reduced, and the reliability of the signal system is further improved.

Description

Receiver, electronic device and eye pattern detection method in receiver

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a receiver, an electronic device, and an eye pattern detection method in the receiver.

Background

In a high-speed serial digital signal system, noise such as intersymbol interference and crosstalk in a signal affects the bit error rate at the time of signal reception. In order to measure the performance of the digital signal system, the waveform of the received signal can be observed through an eye diagram to analyze the influence of noise such as inter-code crosstalk and the like on the performance of the signal system.

For the current receiver, some adopt the principle of probability to draw an eye pattern, the data which is not originally sampled is used, the statistical error exists, and the error code for burst cannot be displayed in the eye pattern; some use a single-channel analog-to-digital converter (ADC) architecture to draw an eye diagram, and when there is a frequency offset between a transmit digital-to-analog converter (tx_dac) and a receive analog-to-digital converter (rx_adc), the eye diagram cannot be drawn.

Disclosure of Invention

The application provides a receiver, electronic equipment and an eye pattern detection method in the receiver, which are used for solving the problems that burst error codes cannot be displayed and an eye pattern cannot be drawn in the prior art.

In a first aspect, the present application provides a receiver. The receiver includes a first signal path and a second signal path. The first signal path includes a first analog-to-digital converter and a first clock data recovery unit. The input end of the first clock data recovery unit is connected with the output end of the first analog-to-digital converter and is used for generating a first phase control word according to the digital signal output by the first analog-to-digital converter. The second signal path includes a second analog-to-digital converter, a second phase interpolator, and a second eye monitor. The input end of the second phase interpolator is connected with the output end of the first clock data recovery unit and is used for receiving the first phase control word and generating a second clock according to the first phase control word. The clock input end of the second analog-to-digital converter is connected with the output end of the second phase interpolator and is used for receiving a second clock and outputting a digital signal according to the second clock. The input end of the second eye monitor is connected with the output end of the second analog-to-digital converter, and is used for collecting the digital signals output by the second analog-to-digital converter according to the second clock samples and drawing an eye diagram according to the digital signals output by the second analog-to-digital converter.

Based on the receiver, the receiver comprises two signal paths, a first signal path and a second signal path, respectively. The first signal path is a signal conversion path of normal service; the second signal path is an eye diagram detection path for drawing an eye diagram. In the receiver, the second signal path uses the clock signal recovered by the clock data recovery unit in the first signal path to perform phase adjustment, the digital signal sampled and output by the second signal path is collected to draw an eye diagram, the quality of the received signal can be intuitively reflected, the corresponding control signal is obtained through processing the eye diagram, and the parameters of the signal processing system are regulated, so that the error rate of the signal is reduced, and the reliability of the signal system is further improved.

Optionally, the first signal path may further comprise a first phase interpolator. The input end of the first phase interpolator is connected with the output end of the first clock data recovery unit and is used for receiving the first phase control word and generating a first clock according to the first time Zhong Pianzhi signal and the first phase control word. The clock input end of the first analog-to-digital converter is connected with the output end of the first phase interpolator and is used for receiving the second clock and outputting a digital signal according to the first clock. Therefore, the first signal path for processing normal signal conversion service can adjust the sampling clock in the analog-to-digital converter in real time through the eye pattern state information fed back by the second signal path, thereby improving the performance and reliability of the receiver.

In a possible implementation, the second signal path may further comprise a second clock data recovery unit. The input end of the second clock data recovery unit is connected with the output end of the second analog-to-digital converter and is used for generating a second phase control word according to the digital signal output by the second analog-to-digital converter. The output end of the first clock data recovery unit and the output end of the second clock data recovery unit are connected with the input end of the second phase interpolator through the first selector. Therefore, when the second signal path is not used as an eye diagram detection path, signal conversion of normal service can be realized, and the flexibility of signal processing of the receiver is improved.

Optionally, the first signal path may further comprise a first eye diagram monitor. The output end of the first clock data recovery unit and the output end of the second clock data recovery unit are connected with the input end of the first phase interpolator through the second selector. The input end of the first eye diagram monitor is connected with the output end of the first analog-to-digital converter, and is used for collecting the digital signals output by the first analog-to-digital converter and drawing an eye diagram according to the digital signals output by the first analog-to-digital converter. Thus, the first signal path and the second signal path can be mutually an eye pattern detection path of the other path and are used for providing signal quality adjustment guidance for a normal service path, so that the quality of signal transmission is improved, and the performance and reliability of the receiver are improved.

Optionally, the first signal path may further comprise a first equalizer. The first equalizer is connected with the output end of the first analog-to-digital converter. The first eye diagram monitor is also connected with the output end of the first equalizer and is used for collecting the digital signals output by the first equalizer and drawing an eye diagram according to the digital signals output by the first equalizer. The eye patterns of the digital signals output before and after the first equalizer can be compared, and the signal regulation gain brought by the equalizer is judged, so that the equalization parameters of the equalizer in the signal conversion path of the normal service can be regulated according to the equalization parameters in the first equalizer.

Optionally, the second signal path may further comprise a second equalizer. The second equalizer is connected with the output end of the second analog-to-digital converter. The second eye monitor is also connected with the output end of the second equalizer and is used for collecting the digital signals output by the second equalizer and drawing an eye pattern according to the digital signals output by the second equalizer. The eye patterns of the digital signals output before and after the second equalizer can be compared, and the signal regulation gain brought by the equalizer is judged, so that the equalization parameters of the equalizer in the signal conversion path of the normal service can be regulated according to the equalization parameters in the second equalizer.

In a possible implementation, the second analog-to-digital converter may comprise at least one sub-analog-to-digital converter, the sub-analog-to-digital converter in the second analog-to-digital converter being identical to the sub-analog-to-digital converter in the first analog-to-digital converter. Therefore, normal signal conversion service is not affected during eye diagram detection.

In a second aspect, the present application provides an electronic device. The electronic device includes: a transceiver chip, and possibly a receiver as in any of the first aspects above. Wherein the receiver is disposed in the transceiver chip.

Optionally, the electronic device may further comprise a baseband processing chip coupled with the transceiver chip.

In a third aspect, the present application provides an eye pattern detection method in a receiver. The method is applied to any one of the possible receivers of the first aspect above. The method comprises the following steps: the first analog-to-digital converter and the second analog-to-digital converter receive the same analog signal. The second phase interpolator receives the first phase control word output by the first clock data recovery unit. The second phase interpolator generates a second clock based on the second clock bias signal and the first phase control word. The second clock bias signal is used for adjusting the sampling clock of the second analog-to-digital converter. The second analog-to-digital converter outputs a digital signal according to the second clock samples. The second eye monitor collects the digital signal output by the second analog-to-digital converter and draws the first eye according to the second time Zhong Pianzhi signal and the digital signal output by the second analog-to-digital converter.

Optionally, the second clock bias signal includes a plurality, and the value of the second clock bias signal may range from-0.5 unit interval UI to 0.5UI.

Alternatively, the step size of the second clock bias signal may be 0.01UI.

In a possible implementation manner, the method may further include: the first phase interpolator receives a first phase control word output by the first clock data recovery unit. The first phase interpolator generates a first clock from the first time Zhong Pianzhi signal and the first phase control word. The first analog-to-digital converter outputs a digital signal according to the first clock samples. Wherein the first timing Zhong Pianzhi signal is determined from a first eye diagram.

In a possible implementation manner, the second signal path may further include a second equalizer, where the second equalizer is connected to an output terminal of the second analog-to-digital converter; the second eye monitor is also connected to the output of the second equalizer. The method may further comprise: the second equalizer receives the digital signals output by the second analog-to-digital converter and generates a plurality of groups of equalized digital signals. The second eye monitor collects the equalized digital signal output from the second equalizer. The second eye monitor draws a second eye from the second clock bias signal and the equalized digital signal. The second eye monitor compares the first eye with the second eye.

It can be appreciated that any of the above-mentioned electronic devices and the eye pattern detection method in the receiver may be implemented by the corresponding receiver provided above, and therefore, the advantages achieved by the method can be referred to the advantages in the receiver provided in the first aspect and are not described herein.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

Fig. 4 is a schematic circuit diagram of a receiver according to an embodiment of the present application;

fig. 5 is a schematic diagram of a circuit structure of a receiver according to an embodiment of the present application;

fig. 6 is a schematic circuit diagram III of a receiver according to an embodiment of the present application;

fig. 7 is a schematic circuit diagram of a receiver according to an embodiment of the present application;

fig. 8 is a circuit receiving schematic diagram of a receiver according to an embodiment of the present application;

fig. 9 is a flowchart of an eye pattern detection method in a receiver according to an embodiment of the present application;

fig. 10 is a flowchart of drawing an eye diagram in a receiver according to an embodiment of the present application.

Wherein, 100-a first signal path; 200-a second signal path; 101-a first analog-to-digital converter; 102-a first clock data recovery unit; 103-a first phase interpolator; 104-a first equalizer; 105-a first eye diagram monitor; 106-a first control module; 107-a second selector; 108-a first adder; 201-a second analog-to-digital converter; 202-a second clock data recovery unit; 203-a second phase interpolator; 204-a second equalizer; 205-a second eye monitor; 206-a second control module; 207-a first selector; 208-a second adder.

Detailed Description

Technical terms related to the embodiments of the present application are described below.

(1) Eye pattern (eye diagram)

A digital communication symbol, which is displayed on an oscilloscope screen, is formed by a number of waveforms partially overlapping, shaped like an "eye" pattern. The large "eye" indicates that the signal quality of the system transmission is better; the small "eye" indicates that the noise such as inter-code interference in the system is large, resulting in poor signal quality.

(2) Eye diagram analysis method

In order to measure the performance of a digital signal transmission system, an oscilloscope is generally used to observe the waveform of a received signal to analyze the signal quality, and the influence of inter-symbol interference, photoelectricity and other noise on the system performance is particularly concerned, which is an eye diagram analysis method.

In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a-b, a-c, b-c or a-b-c, wherein a, b and c can be single or multiple. The character "/" generally indicates that the context-dependent object is an "or" relationship. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and the order of execution.

In the present application, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "coupled" may be a means of electrical connection for achieving signal transmission. "coupled" may be directly connected electrically, or indirectly connected electrically through an intermediary.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device may be a router or a switch. As shown in fig. 1, the electronic device includes at least one signal transmission channel and at least one signal reception channel therein.

For the signal transmission channel, the electric signal is sent to the optical emission sub-module (transmitter optical subassembly, TOSA) after passing through a digital-to-analog converter (digital to analog converter, DAC) in the optical module, and the TOSA converts the electric signal into an optical signal and then sends the optical signal through an optical fiber.

For the signal receiving channel, when receiving the optical signal sent by the optical fiber, the received optical signal is converted into an electrical signal by an optical receiving sub-module (receiver optical subassembly, ROSA), and the signal receiving processing is implemented by receiving the electrical signal by an analog-to-digital converter (analog to digital converter, ADC) in the optical module. The electronic device of fig. 1 can implement mutual conversion between optical signals and electrical signals, and can transmit and receive signals through optical fibers.

Fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device may be a terminal or a base station. As shown in fig. 2, the electronic device may include an application subsystem, a memory, a mass storage (baseband subsystem), a radio frequency integrated circuit (radio frequency intergreted circuit, RFIC), a radio frequency front end (radio frequency front end, RFFE) device, and an Antenna (ANT), which may be coupled via various interconnection buses or other electrical connections.

In fig. 2, ant_1 denotes a first antenna, ant_n denotes an nth antenna, and N is a positive integer greater than 1. Tx denotes a transmit path, rx denotes a receive path, and different numbers denote different paths. FBRx denotes a feedback reception path, PRx denotes a main reception path, and DRx denotes a diversity reception path. HB represents high frequency, LB represents low frequency, both refer to the relative high and low frequencies. BB represents the baseband. It should be understood that the labels and components in fig. 1 are for illustrative purposes only and as one possible implementation, embodiments of the present application include other implementations as well.

The application subsystem can be used as a main control system or a main computing system of the wireless communication device and is used for running a main operating system and application programs, managing software and hardware resources of the whole wireless communication device and providing a user operation interface for a user. The application subsystem may include one or more processing cores. In addition, driver software may be included in the application subsystem in relation to other subsystems (e.g., baseband subsystem). The baseband subsystem may also include one or more processing cores, as well as hardware accelerators (hardware accelerator, HACs), caches, and the like.

In fig. 2, RFFE devices, RFIC 1 (and optionally RFIC 2) may together comprise a radio frequency subsystem. The radio frequency subsystem may be further divided into a radio frequency receive path (RF receive path) and a radio frequency transmit path (RF transmit path). The rf receive path may receive rf signals via an antenna, process (e.g., amplify, filter, and downconvert) the rf signals to obtain baseband signals, and pass the baseband signals to a baseband subsystem. The rf transmit path may receive baseband signals from the baseband subsystem, rf process (e.g., up-convert, amplify, and filter) the baseband signals to obtain rf signals, and ultimately radiate the rf signals into space through the antenna. In particular, the radio frequency subsystem may include antenna switches, antenna tuners, low noise amplifiers (low noise amplifier, LNAs), power Amplifiers (PAs), mixers (mixers), local Oscillators (LOs), filters, etc., which may be integrated into one or more chips as desired. The antenna may also sometimes be considered part of the radio frequency subsystem.

The baseband subsystem may extract useful information or data bits from the baseband signal or convert the information or data bits to a baseband signal to be transmitted. The information or data bits may be data representing user data or control information such as voice, text, video, etc. For example, the baseband subsystem may implement signal processing operations such as modulation and demodulation, encoding and decoding, and the like. For different radio access technologies, e.g. 5G NR and 4G LTE, there is often not exactly the same baseband signal processing operation. Thus, to support the convergence of multiple mobile communication modes, the baseband subsystem may include multiple processing cores, or multiple HACs, simultaneously.

In addition, since the radio frequency signal is an analog signal, the signal processed by the baseband subsystem is mainly a digital signal, and an analog-to-digital conversion device is also required in the wireless communication device. The analog-to-digital conversion device includes an analog-to-digital converter (analog to digital converter, ADC) that converts the analog signal to a digital signal, and a digital-to-analog converter (digital to analog converter, DAC) that converts the digital signal to an analog signal.

It should be appreciated that in embodiments of the present application, a processing core may represent a processor, which may be a general-purpose processor or a processor designed for a particular application. For example, the processor may be a central processing unit (center processing unit, CPU) or a digital signal processor (digital signal processor, DSP). The processor may also be a microcontroller (micro control unit, MCU), a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processing, ISP), an audio signal processor (audio signal processor, ASP), and a specially designed processor for artificial intelligence (artificial intelligence, AI) applications. AI processors include, but are not limited to, neural network processors (neural network processing unit, NPU), tensor processors (tensor processing unit, TPU), and processors known as AI engines.

The hardware accelerator can be used for realizing some subfunctions with larger processing cost, such as assembly and analysis of data packets (data packets), encryption and decryption of the data packets, and the like. These sub-functions may also be implemented using a general purpose processor, but may be more appropriate using a hardware accelerator due to performance or cost considerations. Thus, the type and number of hardware accelerators may be specifically selected based on the requirements. In particular implementations, one or a combination of field programmable gate arrays (field programmable gate array, FPGA) and application specific integrated circuits (application specified intergated circuit, ASIC) may be used. Of course, one or more processing cores may also be used in a hardware accelerator.

The memory can be divided into volatile memory (NVM) and nonvolatile memory (non-NVM). Volatile memory refers to memory in which data stored internally is lost when power is turned off. Currently, volatile memory is mainly random access memory (random access memory, RAM), including Static RAM (SRAM) and Dynamic RAM (DRAM). The nonvolatile memory is a memory in which data stored therein is not lost even if power supply is interrupted. Common nonvolatile memories include Read Only Memory (ROM), optical disks, magnetic disks, and various memories based on flash memory (flash memory) technology, etc. Generally, the memory may be a volatile memory, and the mass storage may be a nonvolatile memory, such as a magnetic disk or a flash memory.

In the embodiment of the application, the baseband subsystem and the radio frequency subsystem form a communication subsystem together to provide a wireless communication function for wireless communication equipment. Typically, the baseband subsystem is responsible for managing the software and hardware resources of the communication subsystem and may configure the operating parameters of the radio frequency subsystem. One or more processing cores of the baseband subsystem may be integrated into one or more chips, which may be referred to as baseband processing chips or baseband chips. Similarly, an RFIC may be referred to as a radio frequency processing chip or a radio frequency chip. In addition, as technology evolves, the functional division of the radio frequency subsystem and the baseband subsystem in the communication subsystem may also be adjusted. For example, the functionality of a portion of the radio frequency subsystem is integrated into the baseband subsystem, or the functionality of a portion of the baseband subsystem is integrated into the radio frequency subsystem. In practical applications, wireless communication devices may employ a combination of different numbers and different types of processing cores based on the needs of the application scenario.

In an embodiment of the present application, the RF subsystem may include an independent antenna, an independent RF front end (RFFE) device, and an independent RF chip. Radio frequency chips are sometimes also referred to as receivers (receivers), transmitters (transmitters), transceivers (transceivers), or transceiver chips. The antenna, the radio frequency front end device and the radio frequency processing chip can all be manufactured and sold separately. Of course, the rf subsystem may also employ different devices or different integration schemes based on power consumption and performance requirements. For example, part of the devices belonging to the rf front-end are integrated in an rf chip, which may also be referred to as an rf antenna module or antenna module, and even both the antenna and the rf front-end devices are integrated in the rf chip.

In embodiments of the present application, the baseband subsystem may be implemented as a stand-alone chip, which may be referred to as a modem (modem) chip. The hardware components of the baseband subsystem may be manufactured and sold in units of modem chips. modem chips are sometimes also referred to as baseband chips or baseband processors. In addition, the baseband subsystem may be further integrated into a SoC chip, manufactured and sold in units of the SoC chip. The software components of the baseband subsystem may be built into the hardware components of the chip prior to shipment of the chip, may be imported from other nonvolatile memory into the hardware components of the chip after shipment of the chip, or may be downloaded and updated in an online manner via a network.

Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application. Fig. 3 shows some common devices for radio frequency signal processing in an electronic device, including a baseband signal processing chip and a radio frequency signal processing chip, which may also be referred to as a transceiver chip. It should be understood that, although only one rf receiving channel and one rf transmitting channel are shown in the rf signal processing chip in fig. 3, the wireless communication device in the embodiment of the present application is not limited thereto, and the wireless communication device may include one or more rf receiving channels and one or more rf transmitting channels.

For the radio frequency receiving channel, the radio frequency signal received from the antenna is sent to the radio frequency receiving channel through the selection of the antenna switch. Since the radio frequency signal received from the antenna is usually very weak, a low noise amplifier LNA is usually used for amplification. The amplified signal is processed by down conversion of a mixer, then is processed by a filter and an analog-to-digital converter ADC, and finally the baseband signal processing is completed. For the radio frequency transmission channel, the baseband signal may be converted into an analog signal by a digital-to-analog converter DAC, the analog signal is converted into a radio frequency signal by an up-conversion process of a mixer, the radio frequency signal is processed by a filter and a power amplifier PA, and finally, the radio frequency signal is radiated from a suitable antenna through the selection of an antenna switch.

In which the input signal and the local oscillator LO signal are mixed, up-conversion (corresponding to the radio frequency transmit channel) or down-conversion (corresponding to the radio frequency receive channel) operations may be implemented. The local oscillator LO is a common term in the radio frequency field, and is generally abbreviated as local oscillator. The local oscillator is sometimes referred to as a frequency synthesizer or synthesizer (frequency synthesizer), simply referred to as a frequency synthesizer. The main function of the local oscillator or the frequency synthesizer is to provide the required specific frequency for the radio frequency processing, such as the frequency point of the carrier wave. The higher frequencies may be implemented using a phase locked loop (phase locked loop, PLL) or delay locked loop (delay locked loop, DLL) or the like. The lower frequency can be realized by directly adopting a crystal oscillator or dividing the frequency of a high-frequency signal generated by devices such as a PLL.

In the embodiment of the present application, the signal receiving channel of the electronic device in fig. 1, the radio frequency subsystem of the electronic device in fig. 2, and the radio frequency signal processing chip of the electronic device in fig. 3 all need to use a receiver to implement conversion from an analog signal to a digital signal. At least one signal path is included in a receiver, which may include an analog-to-digital converter (analog to digital converter, ADC), a clock data recovery unit (clock data recovery, CDR), an Equalization (EQ) module, a forward error correction (forward error correction, FEC) module, and the like. The analog-to-digital converter ADC is used for converting the analog signal into a digital signal. The clock data recovery unit CDR is configured to detect a phase error of the digital signal output by the analog-to-digital conversion module, and perform filtering on the phase error to generate a phase control word (pi_code). The phase control word is the filtered phase error and is used for controlling the clock phase in the phase interpolators (phase interpolation, PI), and the multiphase clock generated by the phase interpolators PI is used for the analog-to-digital converter ADC to sample data to obtain a digital signal. The equalization EQ module is used for filtering an input signal and adjusting the quality of the signal. The forward error correction FEC module is used for carrying out coding processing according to a certain algorithm in advance before the signal is sent into a transmission channel, adding redundant codes with the characteristics of the signal, decoding the received signal according to a corresponding algorithm at a receiving end, thereby finding error codes generated in the signal transmission process, correcting the error codes and improving the reliability of signal transmission and conversion.

In order to judge the performance and reliability of the signal system, the waveform of the received signal can be observed through an eye diagram to analyze the influence of noise such as inter-code crosstalk on the performance of the signal system. Accordingly, embodiments of the present application provide a receiver having an eye pattern detection circuit built into the receiver.

The following is a description of a receiver provided by an embodiment of the present application.

Fig. 4 is a schematic circuit diagram of a receiver according to an embodiment of the present application. Referring to fig. 4, the receiver includes two signal paths, a first signal path 100 and a second signal path 200. Wherein, the first signal path 100 is a signal conversion path of normal service; the second signal path 200 is an eye diagram detection path for drawing an eye diagram. In the receiver, the second signal path 200 uses the clock signal recovered by the clock data recovery unit in the first signal path 100 to perform phase adjustment, and the quality of the received signal can be intuitively reflected by collecting the digital signal of the second signal path 200 and drawing an eye pattern, so that the reliability of a signal system is improved; in turn, the quality of the eye pattern drawn by the second signal path 200 is fed back to the first signal path 100, and is used as a basis for adjusting the clock bias signal and the equalization parameter in the first signal path, and a corresponding control signal is obtained through analysis and processing of the quality of the eye pattern and is used for adjusting the parameter of the signal processing system, so that the error rate of the transmission signal is reduced, and the performance and reliability of the receiver are improved.

Specifically, the first signal path 100 includes a first analog-to-digital converter 101 and a first clock data recovery unit 102. The input end of the first clock data recovery unit 102 is connected to the output end of the first analog-to-digital converter 101, and is used for performing clock recovery on the digital signal output by the first analog-to-digital converter 101, and generating a first phase control word. That is, the digital signal output from the first analog-to-digital converter 101 detects a phase error by the first clock data recovery unit 102, and generates the first phase control word after filtering the phase error. The first phase control word described above can be used to control the clock phases in the first signal path 100 and the second signal path 200 so that the clock signal used by the analog-to-digital converter in the second signal path 200 remains consistent with that in the first signal path 100.

The second signal path 200 includes a second analog-to-digital converter 201, a second phase interpolator 203, and a second eye monitor 205. The first analog-to-digital converter 101 and the second analog-to-digital converter 201 may receive the same analog signal; an input terminal of the second phase interpolator 203 is connected to an output terminal of the first clock data recovery unit 102, and is configured to receive the first phase control word and generate a second clock according to the second clock bias signal and the first phase control word. The clock input terminal of the second analog-to-digital converter 201 is connected to the output terminal of the second phase interpolator 203, and is configured to receive the second clock and sample and output a digital signal according to the second clock. The input end of the second eye monitor 205 is connected to the output end of the second analog-to-digital converter 201, and is used for collecting the digital signal sampled and output by the second analog-to-digital converter 201 according to the second clock, and drawing an eye diagram according to the digital signal.

The analog-to-digital converters, such as the first analog-to-digital converter 101 and the second analog-to-digital converter 201, may include a plurality of sub-analog-to-digital converters (e.g., sub-adc_1, … … sub-adc_n in fig. 4), and the plurality of sub-analog-to-digital converters are arranged in parallel, so that the frequency of each channel can be reduced by converting the high-frequency signal into a serial-to-parallel mode. For example, a 10G signal input is processed by 10 parallel sub-analog-to-digital converters, and each sub-analog-to-digital converter only needs to process 1G signal.

In addition, the analog-to-digital converter can also comprise a multiphase clock for receiving multiphase clock signals recovered by the phase interpolator so as to be sampled by a plurality of sub-analog-to-digital converters in the analog-to-digital converter and output digital signals. That is, the second analog-to-digital converter 201 performs phase adjustment using the clock recovered by the second phase interpolator 203, outputs a multi-phase clock, performs data sampling, and causes the second analog-to-digital converter 201 to output a digital signal.

A phase interpolator, such as the second phase interpolator 203, may include two input signals, a phase control word and a reference clock, respectively, and an output signal, a clock signal, which is derived from adjusting the reference clock based on the phase control word. The reference clock may be derived by a clock generator, such as a phase locked loop (phase locked loop, PLL) circuit.

The clock data recovery unit, such as the first clock data recovery unit 102, may include a feedforward equalizer (feedforward equalizer, FFE), a Phase Detector (PD), a Low Pass Filter (LPF), and/or an integrator (ACC). Wherein the feedforward equalizer is used for filtering the digital signal converted by the analog-to-digital converter, the phase detector is used for detecting clock phase errors of the digital signal, and the low-pass filter and/or the integrator is used for filtering the phase errors.

The clock data recovery unit in the embodiment of the present application may also include other functional devices, and the embodiment of the present application is not particularly limited.

It should be further noted that, the second clock bias signal may be configured by the second control module 206, where the second clock bias signal is used to change the value of the phase control word input to the second phase interpolator 203, that is, in the receiver shown in fig. 4, when the second phase interpolator 203 receives the first phase control word and the second clock bias signal, the second clock bias signal is superimposed on the first phase control word, so as to achieve the purpose of adjusting the clock phase, so as to sample signals at different clock positions, and an eye diagram is drawn by using the sampled data, so as to observe the quality of signal transmission.

The second clock bias signal typically ranges from at least one Unit Interval (UI), such as-0.5 UI to 0.5UI. In order to ensure the accuracy of the drawing of the sampled eye diagram, the adjustment step length of the second clock bias signal can be set to be 0.01UI or even smaller, and the embodiment of the application is not particularly limited.

The second control module 206 may pre-configure a range of the second clock bias signal, such as-0.5 UI to 0.5UI, and configure an adjustment step size of the second clock bias signal of 0.01UI, such as 0.01UI, when configuring the second clock bias signal. Each time the second eye monitor 205 collects a set of digital signals, the second control module 206 may be notified to change the value of the second clock bias signal once, e.g., from 0.1UI to 0.11UI. When the second clock bias signal has been converted by one unit interval UI, the second eye monitor may be notified to draw an eye pattern.

It should be appreciated that the second control module 206 may be disposed inside the second eye monitor 205, and as a control module inside the second eye monitor 205, the second control module 206 may also be disposed outside the second eye monitor, and the embodiment of the present application is not particularly limited.

The second clock bias signal may be superimposed on the first phase control word by using a second adder 208 as shown in fig. 4, where the adder may be disposed outside the second phase interpolator or may be disposed inside the second phase interpolator, and embodiments of the present application are not limited in particular.

Further, referring to fig. 4, the first signal path 100 further includes a first phase interpolator 103. The input terminal of the first phase interpolator 103 is connected to the output terminal of the first clock data recovery unit 102, and is configured to receive the first phase control word output by the first clock data recovery unit 102, and generate a first clock according to the first clock Zhong Pianzhi signal and the first phase control word. The clock input terminal of the first analog-to-digital converter 101 is connected to the output terminal of the first phase interpolator 103, and is configured to receive the first clock and output a digital signal according to the first clock.

Note that, similar to the second signal path 200, in the first signal path 100, when the first phase interpolator 103 generates the first clock, the first phase interpolator 103 may superimpose the first time Zhong Pianzhi signal on the first phase control word by the first adder 108 when the first phase interpolator 103 receives the first phase control word, so as to adjust the clock phase bias of the signal transition. Wherein the first clock bias signal may be based on an eye adjustment drawn by the second eye monitor 205 in the second signal path 200. Specifically, the eye diagram drawn by the second eye diagram monitor 205 may be sent to the upper eye diagram analysis software, where the upper eye diagram analysis software analyzes the state information of the eye diagram (such as the eye height, whether the eye is inclined, etc.), or the eye diagram analysis module of the second eye diagram monitor itself analyzes the state information of the eye diagram, and then the state information of the eye diagram obtained by analysis is fed back to the first control module 106 in the first signal path 100, where the value of the first clock bias signal is adjusted by the first control module 106. Thus, the first signal path 100 for processing the normal signal conversion service can adjust the clock in the first analog-to-digital converter 101 in real time so as to adjust the quality of the output digital signal, thereby improving the performance and reliability of the receiver.

The first control module 106 may be disposed inside the first clock data recovery unit 102 of the first signal path 100, or may be disposed outside the first clock data recovery unit 102, which is not particularly limited in the embodiment of the present application.

Fig. 5 shows a second circuit schematic diagram of the receiver according to the embodiment of the present application. Referring to fig. 5 in combination with fig. 3, the second signal path 200 may further include a second clock data recovery unit 202. An input terminal of the second clock data recovery unit 202 is connected to an output terminal of the second analog-to-digital converter 201, and is configured to generate a second phase control word according to the digital signal output by the second analog-to-digital converter 201. The output of the first clock data recovery unit 102 and the output of the second clock data recovery unit 202 are connected to the input of the second phase interpolator 203 via a first selector 207. Thus, when the second signal path 200 is not used as an eye diagram detection path, signal conversion of normal service can be realized, and thus flexibility of signal processing of the receiver is improved.

It should be understood that, in the second signal path 200, the structure of the second clock data recovery unit 202 may be identical to the structure of the first clock data recovery unit 102 in the first signal path 100, or may be other structures capable of implementing the corresponding function, and embodiments of the present application are not limited in particular.

In fig. 5, the input terminal of the second phase interpolator 203 may select to receive the first phase control word output by the output terminal of the first clock data recovery unit 102, or may select to receive the second phase control word output by the output terminal of the second clock data recovery unit 202. When the second signal path 200 is used as an eye diagram detection path, the input end of the second phase interpolator 203 receives the first phase control word output by the first clock data recovery unit 102, so that the second phase interpolator 203 in the second signal path 200 uses the clock signal recovered in the first signal path 100 to realize the detection and drawing of an eye diagram. When the second signal path 200 is used as a signal conversion path of normal service, the input end of the second phase interpolator 203 receives the second phase control word output by the second clock data recovery unit 202, so that the second phase interpolator 203 in the second signal path 200 uses the clock signal recovered by the second signal path 200 to realize signal conversion and processing of normal service. Thus, when the second channel path is not used as an eye pattern detection path, the signal conversion processing of the normal signal can be realized.

For example, as shown in fig. 5, the selection control terminal of the first selector 207 may be connected to the second control module 206, when the selection control signal of the first selector 207 is 1, the input terminal of the second phase interpolator 203 receives the first phase control word of the first clock data recovery unit 102, and after the first phase control word is overlapped with the second clock bias signal, and according to the reference clock, the second phase interpolator 203 outputs the second clock, continuously adjusts the value of the second clock bias signal, such as from-0.5 UI to 0.5UI, and under the condition of different second clock bias signals, collects the output of the second analog-digital converter 201, so that an eye diagram may be drawn, so as to observe the quality of signal processing.

When the selection control signal of the first selector 207 is 0, the input terminal of the second phase interpolator 203 receives the second phase control word of the second clock data recovery unit 202, and after the second phase control word is overlapped with the second clock bias signal, the second phase interpolator 203 outputs the second clock according to the reference clock, and at this time, the second analog-to-digital converter 201 performs normal signal conversion and processing. When normal signal conversion and processing is achieved, the second clock bias signal may adjust signal quality based on the detection of the eye pattern.

Fig. 6 shows a third circuit schematic diagram of the receiver according to the embodiment of the present application. Referring to fig. 6 in combination with fig. 5, the first signal path 100 may further include a first eye diagram monitor 105. The output of the first clock data recovery unit 102 and the output of the second clock data recovery unit 202 are connected to the input of the first phase interpolator 103 via a second selector 107. The input end of the first eye diagram monitor 105 is connected to the output end of the first analog-to-digital converter 101, and is used for collecting the digital signal output by the first analog-to-digital converter 101 and drawing an eye diagram according to the digital signal output by the first analog-to-digital converter 101.

It should be understood that the connection relationships of other circuit units in fig. 6 are identical to the connection relationships of circuits in fig. 5, and will not be described herein.

In fig. 6, the output terminal of the first clock data recovery unit 102 and the output terminal of the second clock data recovery unit 202 are connected to the input terminal of the second phase interpolator 203 through the first selector, and the output terminal of the first clock data recovery unit 102 and the output terminal of the second clock data recovery unit 202 are connected to the input terminal of the first phase interpolator 103 through the second selector 107. The connection relationship between the output end of the first clock data recovery unit 102, the output end of the second clock data recovery unit 202, the first selector 207, the second selector 107, the input end of the first phase interpolator 103, and the input end of the second phase interpolator 203 may be the connection manner shown in fig. 5, or may be another connection manner capable of implementing the functions shown in fig. 6, which is not limited in the embodiment of the present application.

As shown in fig. 6, when the input terminal of the first phase interpolator 103 and the input terminal of the second phase interpolator 203 are both selected to receive the output terminal data of the first clock data recovery unit 102, the first signal path 100 serves as a normal traffic path, the second signal path 200 serves as an eye pattern detection path, and the signal quality is observed.

When the input terminal of the first phase interpolator 103 and the input terminal of the second phase interpolator 203 are both selected to receive the output terminal data of the second clock data recovery unit 202, the first signal path 100 serves as an eye diagram detection path, observing the quality of the transition of the signal; the second signal path 200 acts as a normal traffic path.

In this way, the first signal path 100 and the second signal path 200 can be mutually used as an eye diagram detection path of another path, and are used for providing signal quality adjustment guidance for the signal conversion path of the normal service, so that the signal conversion path of the normal service generates corresponding control signals (such as clock bias signals and equalization parameters) and adjusts the output quality of the signals, thereby reducing the error rate of signal transmission and further improving the performance and reliability of the receiver.

Fig. 7 shows a schematic circuit diagram of a receiver according to an embodiment of the present application. In fig. 7, the second signal path 200 may be a signal conversion path of a sub-analog-to-digital converter added inside the first signal path 100. At least one sub-analog-to-digital converter may be included in the second signal path 200, wherein the sub-analog-to-digital converter in the second analog-to-digital converter 201 is identical to the sub-analog-to-digital converter in the first analog-to-digital converter 101.

In the above, it is mentioned that the first analog-to-digital converter 101 may include a plurality of sub-analog-to-digital converters, each of which processes a part of the signal, so that the conversion efficiency of the signal may be improved. In fig. 7, the second analog-to-digital converter 201 may be implemented with one of the sub-analog-to-digital converters (e.g., sub adc_n+1) in the first analog-to-digital converter 101, which uses the second clock generated by the second phase interpolator 203 to allow the second eye monitor to draw an eye with the sampled data, thereby observing the quality of the signal transmission and providing a reference basis for signal conditioning for signal conversion of normal traffic in the first signal path 100.

It should be appreciated that the second signal path 200 is disposed inside the chip of the first signal path 100, and the second signal path 200 is merely used as an eye pattern detection path of the first signal path 100, so that signal conversion of normal traffic is not affected during eye pattern detection.

It should be noted that the first equalizer 104 is further included in the first signal path 100 in fig. 4, 5, 6 and 7. Wherein the first equalizer 104 is connected to the output terminal of the first analog-to-digital converter 101, and realizes an equalized output when converting signals.

As shown in fig. 6, when the first signal path 100 is used as an eye diagram detection path, the first eye diagram monitor 105 is further connected to the output end of the first equalizer 104, and is configured to collect the digital signal output by the first equalizer 104, and according to the digital signal output by the first equalizer 104, determine the signal adjustment gain brought by the equalizer by comparing the eye diagrams of the digital signals output before and after the first equalizer 104, so as to adjust the equalization parameters of the equalizer in the signal conversion path of the normal service according to the equalization parameters in the first equalizer 104.

In addition, a second equalizer 204 is also included in the second signal path 200 in fig. 4, 5, 6 and 7. Wherein the second equalizer 204 is connected to the output terminal of the second analog-to-digital converter 201, and realizes an equalized output during the conversion of the signal. When the second signal path 200 is used as an eye diagram detection path, the second eye diagram monitor 205 is further connected to the output end of the second equalizer 204, and is configured to collect the digital signal output by the second equalizer 204, and according to the digital signal output by the second equalizer 204, determine the signal adjustment gain brought by the equalizer by comparing the eye diagrams of the digital signals output by the second equalizer 204 before and after, so as to adjust the equalization parameters of the equalizer in the signal conversion path of the normal service according to the equalization parameters in the second equalizer 204.

It should be appreciated that the above description only illustrates the role of the first equalizer 104 and the second equalizer 204 as equalizers in the eye-detection path, and that when the first equalizer 104 and the second equalizer 204 are used as equalizers in the signal conversion path of normal traffic, the first equalizer 104 and the second equalizer 204 can adjust their equalization parameters during signal conversion of normal traffic according to the eye-state in the eye-detection path.

Fig. 8 shows a schematic circuit diagram of a receiver according to an embodiment of the present application. Reference is made to fig. 8 when at least two signal paths for signal conversion of normal traffic are included in one receiver. In fig. 8, in each signal path for normal traffic, an eye pattern detection path is provided, and the structure of the eye pattern detection path can refer to the second signal path 200 in fig. 7, so that each signal path for normal traffic has a corresponding eye pattern detection path for adjusting signal quality, thereby improving performance and reliability of the receiver.

It should be understood that, in the receiver provided in the embodiment of the present application, the first signal path and the second signal path may be disposed inside the same chip, or may be disposed in two different chips, which is not particularly limited in the embodiment of the present application.

The circuit structure of the receiver according to the embodiment of the present application is described above with reference to fig. 4 to 8, and the eye pattern detection method in the receiver according to the embodiment of the present application is described below with reference to fig. 9.

Fig. 9 shows a flowchart of an eye pattern detection method in a receiver according to an embodiment of the present application. The method is applicable to any of the possible receivers of fig. 4-8. It should be appreciated that the method shown in fig. 9 is based on the scenario in which the first signal path 100 is the signal transition path of normal traffic and the second signal path 200 is the eye detection path.

Referring to fig. 9, the eye pattern detection method includes the following steps:

s901, the first analog-to-digital converter and the second analog-to-digital converter receive the same analog signal.

In the embodiment of the present application, in order to implement the drawing of the eye diagram and adjust the signal paths according to the situation of the eye diagram, the first signal path 100 and the second signal path 200 need to be based on the same sampling signal, so that the first analog-to-digital converter 101 and the second analog-to-digital converter 201 receive the same analog signal.

S902, the second phase interpolator receives the first phase control word output by the first clock data recovery unit.

In the receiver shown in fig. 4-8, the second phase interpolator 203 receives the first phase controller output by the first clock unit, and may enable the second signal path 200 as the eye pattern detection path to use the clock signal recovered by the clock data recovery unit in the first signal path 100, where the clock signal recovered by the clock data recovery unit is the first phase control word, so that the second signal path 200 performs phase shifting, and an eye pattern is drawn according to the digital signals output by different clock samples.

S903, the second phase interpolator generates a second clock based on the second clock bias signal and the first phase control word.

The second clock bias signals may be set to be plural, and the plural second clock bias signals are used to adjust the clocks of the second analog-to-digital converter 201. That is, a plurality of different clocks can be obtained by the plurality of second clock bias signals, and the plurality of sets of digital signals can be outputted according to the plurality of different clocks. The plurality of second clock bias signals may be within a unit interval, for example, take a value of between-0.5 UI and 0.5 UI. The second clock bias signal may be adjusted in steps of 0.01UI. That is, the next value of the second clock bias signal may be increased by 0.01UI based on the previous value of the second clock bias signal.

After the values in the range of-0.5 UI-0.5UI of the second clock bias signal are all completed, an eye diagram can be drawn according to the digital signals sampled and output by different clocks.

And S904, the second analog-to-digital converter samples and outputs a digital signal according to the second clock.

In step S903, a plurality of different clocks may be obtained by the plurality of second clock bias signals. A plurality of different clocks are respectively input into the second analog-to-digital converter 201, so that a plurality of groups of different digital signals can be obtained.

S905, the second eye monitor collects the digital signals output by the second analog-to-digital converter, and draws an eye pattern according to the second clock bias signal and the digital signals output by the second analog-to-digital converter.

It will be appreciated that each time a second clock bias signal is provided, the second phase interpolator 203 may derive a clock signal from which the second analog to digital converter 201 may sample and output a set of digital signals. After the second eye monitor 205 collects a plurality of different digital signals, an eye diagram may be drawn according to a correspondence relationship based on the plurality of clock bias signals and the plurality of different digital signals as the first eye diagram.

The first eye diagram may be drawn with the second clock bias signal as an abscissa and the digital signal derived from the second clock bias signal as an ordinate, for example.

In a possible implementation manner, the method may further include: the first phase interpolator 103 receives the first phase control word output by the first clock data recovery unit 102. The first phase interpolator 103 generates a first clock from the first time Zhong Pianzhi signal and the first phase control word. The first analog-to-digital converter 101 outputs a digital signal according to the first clock samples. Wherein the first timing Zhong Pianzhi signal is determined from a first eye diagram.

That is, after the first eye diagram is drawn through the second signal path 200, the related information of the first eye diagram may be fed back into the first signal path 100 so that the first signal path 100 adjusts the first timing Zhong Pianzhi signal and the equalization parameters, thereby improving the performance and reliability of the receiver.

More specifically, fig. 10 shows a flowchart for drawing an eye diagram in a receiver provided in an embodiment of the present application.

Referring to fig. 10, the method for drawing an eye pattern includes:

s1001, the equalization parameters in the first signal path and the first time Zhong Pianzhi signal are updated and fixed.

After updating the equalization parameters and the first clock bias signal in the first signal path, the equalization parameters and the first time Zhong Pianzhi signal of the first signal path are fixed when the clock recovery in the first signal path is stable so that the second signal path uses the first phase control word recovered by the first clock data recovery unit.

S1002, selecting and using a first phase control word output by a first clock data recovery unit in a first signal path;

s1003, superposing a second clock bias signal on the first phase control word.

For descriptions of the finger range of the second clock bias signal, reference may be made to the related descriptions in step S803, and the description thereof is omitted here.

S1004, the second eye monitor collects a group of digital signals;

s1005, it is determined whether the second clock bias signal covers one UI period.

If yes, go to step S1006; if not, step S1003 is performed.

S1006, drawing an eye pattern according to the acquired digital signals.

For how to draw the eye pattern, reference is made to the related description in step S1005, and the detailed description is omitted here.

S1007, judging whether the eye pattern is askew or not, and whether the sampling point is not in the center of the eye pattern or not.

If the eye pattern is skewed or the sampling point is not at the center of the eye pattern, step S1001 is performed.

In a possible implementation, the second signal path may further include a second equalizer 204, where the second equalizer 204 is connected to the output of the second analog-to-digital converter 201; the second eye monitor 205 is also connected to the output of the second equalizer 204. The method may further comprise: the second equalizer 204 receives the digital signals generated by the second analog-to-digital converter 201 and generates a plurality of sets of equalized digital signals. The second eye monitor 205 collects the equalized digital signal output from the second equalizer 204. The second eye monitor 205 draws an eye pattern from the second clock bias signal and the equalized digital signal as a second eye pattern. The second eye monitor 205 compares the first eye to the second eye.

Similarly, for the receiver shown in fig. 6, if the first signal path is used as an eye diagram detection path, the first eye diagram monitor may also collect multiple sets of equalized digital signals output by the first equalizer in the first signal path, so as to compare the eye diagrams before and after the first equalizer.

It should be appreciated that by comparing the first eye diagram and the second eye diagram, the difference of the signal quality of the digital signal converted by the analog-to-digital converter and the signal quality of the digital signal after being equalized or not can be known, so that the signal adjustment gain caused by the equalizer (such as the second equalizer 204) can be judged, and further the equalization parameters in the signal conversion path of the normal service can be adjusted according to the signal adjustment gain caused by the equalizer, so as to improve the signal quality and improve the performance and reliability of the receiver.

In the several embodiments provided in the present application, it should be understood that the disclosed circuits and methods may be implemented in other ways. For example, the above-described circuit embodiments are merely illustrative, e.g., the division of the described modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another device, or some features may be omitted, or not performed.

The units described as separate parts may or may not be physically separate, and the parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Finally, it should be noted that: the foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A receiver comprising a first signal path and a second signal path;

the first signal path comprises a first analog-to-digital converter and a first clock data recovery unit;

the input end of the first clock data recovery unit is connected with the output end of the first analog-to-digital converter and is used for generating a first phase control word according to the digital signal output by the first analog-to-digital converter;

The second signal path includes a second analog-to-digital converter, a second phase interpolator, and a second eye monitor;

the input end of the second phase interpolator is connected with the output end of the first clock data recovery unit and is used for receiving the first phase control word and generating a second clock according to the first phase control word;

the clock input end of the second analog-to-digital converter is connected with the output end of the second phase interpolator and is used for receiving a second clock and sampling and outputting a digital signal according to the second clock;

the input end of the second eye monitor is connected with the output end of the second analog-to-digital converter, and is used for collecting the digital signals sampled and output by the second analog-to-digital converter according to the second clock and drawing an eye diagram according to the digital signals output by the analog-to-digital converter.
The receiver of claim 1, wherein the first signal path further comprises a first phase interpolator;

the input end of the first phase interpolator is connected with the output end of the first clock data recovery unit and is used for receiving the first phase control word and generating a first clock according to a first time Zhong Pianzhi signal and the first phase control word;

The clock input end of the first analog-to-digital converter is connected with the output end of the first phase interpolator and is used for receiving a second clock and outputting a digital signal according to the first clock.
The receiver according to claim 1 or 2, wherein the second signal path further comprises a second clock data recovery unit;

the input end of the second clock data recovery unit is connected with the output end of the second analog-to-digital converter and is used for generating a second phase control word according to the digital signal output by the second analog-to-digital converter;

the output end of the first clock data recovery unit and the output end of the second clock data recovery unit are connected with the input end of the second phase interpolator through a first selector.
The receiver of claim 3, wherein the first signal path further comprises a first eye diagram monitor;

the output end of the first clock data recovery unit and the output end of the second clock data recovery unit are connected with the input end of the first phase interpolator through a second selector;

the input end of the first eye diagram monitor is connected with the output end of the first analog-to-digital converter, and is used for collecting the digital signals output by the first analog-to-digital converter and drawing an eye diagram according to the digital signals output by the first analog-to-digital converter.
The receiver of claim 4, wherein the first signal path further comprises a first equalizer coupled to an output of the first analog-to-digital converter;

the first eye diagram monitor is also connected with the output end of the first equalizer and is used for collecting the digital signals output by the first equalizer and drawing eye diagrams according to the digital signals output by the first equalizer.
The receiver of any of claims 1-5, wherein the second signal path further comprises a second equalizer coupled to an output of the second analog-to-digital converter;

the second eye monitor is further connected to the output end of the second equalizer, and is configured to collect the digital signal output by the second equalizer, and draw an eye pattern according to the digital signal output by the second equalizer.
The receiver according to claim 1 or 2, wherein the second analog-to-digital converter comprises at least one sub-analog-to-digital converter, the sub-analog-to-digital converter in the second analog-to-digital converter being identical to the sub-analog-to-digital converter in the first analog-to-digital converter.
An electronic device, comprising: a transceiver chip and a receiver as claimed in any one of claims 1 to 7; the receiver is disposed in the transceiver chip.
The electronic device of claim 8, further comprising a baseband processing chip coupled with the transceiver chip.
An eye pattern detection method in a receiver, applied to the receiver of any of claims 1 to 7, the method comprising:

the first analog-to-digital converter and the second analog-to-digital converter receive the same analog signal;

the second phase interpolator receives a first phase control word output by the first clock data recovery unit;

the second phase interpolator generates a second clock according to the second clock bias signal and the first phase control word; wherein the second clock bias signal is used to adjust the clock of the second analog-to-digital converter;

the second analog-to-digital converter samples and outputs a digital signal according to the second clock;

the second eye monitor collects the digital signals output by the second analog-to-digital converter, and draws a first eye according to the second clock bias signal and the digital signals output by the second analog-to-digital converter.
The method of claim 10, wherein the second clock bias signal comprises a plurality of clock bias signals and the second clock bias signal has a value ranging from-0.5 unit interval UI to 0.5UI.
The method of claim 11, wherein the step size of the second clock bias signal is 0.01UI.
The method according to any one of claims 10 to 12, further comprising:

the first phase interpolator receives a first phase control word output by the first clock data recovery unit;

the first phase interpolator generates a first clock from a first time Zhong Pianzhi signal and the first phase control word; wherein the first timing Zhong Pianzhi signal is determined from the first eye diagram;

the first analog-to-digital converter outputs a digital signal according to the first clock samples.
The method according to any of claims 10 to 13, wherein the second signal path further comprises a second equalizer, the second equalizer being connected to an output of the second analog-to-digital converter; the second eye monitor is also connected with the output end of the second equalizer;

the method further comprises the steps of:

the second equalizer receives the digital signal output by the second analog-to-digital converter and generates an equalized digital signal;

the second eye monitor collects the equalized digital signal output from the second equalizer,

The second eye diagram monitor draws a second eye diagram according to the second clock bias signal and the equalized digital signal;

the second eye monitor compares the first eye pattern with the second eye pattern.