CN116722043A

CN116722043A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN116722043A
Application number: CN202310815319.9A
Authority: CN
Inventors: 张书浩; 汪恒; 杨杰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-07-03
Filing date: 2023-07-03
Publication date: 2023-09-08

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same. Wherein, the semiconductor structure includes: a base structure including a source, a drain, and a channel region; a gate structure on the base structure; the source electrode and the drain electrode are respectively positioned at two sides of the grid structure, and the channel region is positioned below the grid structure; the substrate structure further comprises a first stress layer located at least between the source and the channel region or at least between the drain and the channel region; wherein at least a portion of the first stress layer is located under the gate structure; the upper portion of the first stress layer and the lower portion of the first stress layer are opposite in stress direction to the channel region.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background

With the miniaturization, high density and high integration of semiconductor devices, the size of a memory is continuously reduced, and after the feature size of a transistor in the semiconductor device is reduced to a nanometer scale, the power consumption density, mobility and the like of the transistor reach physical limits, which brings greater challenges to improving the performance of the transistor. The transistors in the related art are limited by physical limits such as power consumption density, transmission speed, etc., and it is difficult to reduce power consumption of the transistors, improve transmission speed of the transistors, etc.

Disclosure of Invention

Accordingly, embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same to solve at least one technical problem existing in the prior art.

According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising: a base structure including a source, a drain, and a channel region; a gate structure on the base structure; the source electrode and the drain electrode are respectively positioned at two sides of the grid structure, and the channel region is positioned below the grid structure; the substrate structure further comprises a first stress layer located at least between the source and the channel region or at least between the drain and the channel region; wherein at least a portion of the first stress layer is located under the gate structure; the upper portion of the first stress layer and the lower portion of the first stress layer are opposite in stress direction to the channel region.

In the above scheme, the channel region comprises a P-type dopant; the stress of the upper part of the first stress layer on the channel region is tensile stress; the stress of the lower part of the first stress layer to the channel region is compressive stress; alternatively, the channel region includes an N-type dopant; the stress of the upper part of the first stress layer to the channel region is compressive stress; the stress of the lower part of the first stress layer to the channel region is tensile stress.

In the above scheme, when the channel region includes the P-type dopant, an average lattice constant of an element included in an upper portion of the first stress layer is smaller than an average lattice constant of an element included in the channel region; the lower portion of the first stress layer includes an element having an average lattice constant greater than an element included in the channel region.

In the above aspect, the upper portion of the first stress layer includes a first element; the lattice constant of the first element is smaller than the lattice constant of the main element of the channel region; the lower part of the first stress layer comprises a second element; the lattice constant of the second element is larger than that of the main element of the channel region; wherein, in the direction that the upper part of the first stress layer points to the lower part of the first stress layer, the atomic percentage of the first element is in gradient decreasing distribution, and the atomic percentage of the second element is in gradient increasing distribution; or the atomic percentage of the first element is distributed in a first increasing and then decreasing way, and the atomic percentage of the second element is distributed in a first increasing and then decreasing way.

In the above scheme, when the channel region includes an N-type dopant, an average lattice constant of an element included in an upper portion of the first stress layer is larger than an average lattice constant of an element included in the channel region; the lower portion of the first stress layer includes an element having an average lattice constant that is less than an average lattice constant of an element included in the channel region.

In the above aspect, the upper portion of the first stress layer includes the second element; the lattice constant of the second element is larger than that of the main element of the channel region; the lower part of the first stress layer comprises a first element; the lattice constant of the first element is smaller than the lattice constant of the main element of the channel region; wherein, in the direction that the upper part of the first stress layer points to the lower part of the first stress layer, the atomic percentage of the second element is in gradient decreasing distribution, and the atomic percentage of the first element is in gradient increasing distribution; or the atomic percentage of the first element is distributed in a first increasing and then decreasing way, and the atomic percentage of the second element is distributed in a first increasing and then decreasing way.

In the above scheme, the first element comprises carbon, the second element comprises germanium, and the main element of the channel region comprises silicon.

In the above aspect, the semiconductor structure further includes a second stress layer located in the base structure; the source electrode, the drain electrode, the first stress layer and the channel region are positioned above the second stress layer, and the horizontal width of the second stress layer is larger than that of the channel region; the channel region comprises a channel layer positioned on the surface of the substrate structure and a doped well layer positioned below the channel layer, the stress directions of the upper parts of the second stress layer and the first stress layer on the channel layer are the same, and the stress directions of the second stress layer on the channel layer are opposite to the stress directions of the second stress layer on the doped well layer;

The first stress layer and/or the source electrode and the drain electrode are/is in contact with the second stress layer in the thickness direction of the substrate structure, or the first stress layer and the source electrode and the drain electrode are separated from the second stress layer.

In the above scheme, the semiconductor structure further comprises a side wall structure located on the side wall of the gate structure; the first stress layer is partially located under the side wall structure and partially located in the substrate structure under the gate structure, or is partially located outside the side wall structure and partially located in the substrate structure under the gate structure.

According to a second aspect of embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor structure, comprising: providing a base structure; forming a gate structure on the base structure; forming a source electrode and a drain electrode in the substrate structures at two sides of the gate structure, and forming a channel region between the source electrode and the drain electrode; forming a first stress layer at least between the source and the channel region or between the drain and the channel region; wherein at least a portion of the first stress layer is located under the gate structure; the upper portion of the first stress layer and the lower portion of the first stress layer are opposite in stress direction to the channel region.

In the above aspect, forming a first stress layer at least between the source and the channel region or between the drain and the channel region includes: ion implantation of a first element is performed on the substrate structure at a first included angle under first energy, ion implantation of a second element is performed on the substrate structure at a second included angle under second energy, the first included angle is larger than the second included angle, and the first energy is smaller than the second energy; or, performing ion implantation of a second element on the substrate structure at a first included angle under the first energy, and performing ion implantation of the first element on the substrate structure at a second included angle under the second energy, wherein the first included angle is larger than the second included angle, and the first energy is smaller than the second energy.

In the above scheme, the method further includes forming a sidewall structure on a sidewall of the gate structure; forming a first stress layer, comprising: before forming the side wall structure, forming a first stress material layer in a substrate structure outside the grid structure by adopting an ion implantation process; after the side wall structure is formed, the first stress material layer is positioned below the side wall structure; annealing the first stress material layer to form a first stress layer which is partially positioned under the side wall structure and partially positioned under the grid structure; or after the side wall structure is formed, forming a first stress material layer in a substrate structure outside the side wall structure by adopting an ion implantation process; the first stress material layer is positioned outside the side wall structure; and annealing the first stress material layer to form a first stress layer which is partially positioned outside the side wall structure, partially positioned below the side wall structure and partially positioned below the grid structure.

In various embodiments of the present disclosure, a first stress layer is disposed at least between a source electrode and a channel region or at least between a drain electrode and the channel region, and stress is introduced into the channel layer of a transistor through the first stress layer, so that carrier mobility of the channel layer is increased, current speed of the channel layer is increased, power consumption of the transistor is reduced, speed of the transistor is increased, and better performance of the transistor is achieved.

Drawings

FIG. 1 is a schematic illustration of an epitaxial process for epitaxially growing a silicon carbide strained material on a silicon substrate;

FIG. 2A is a schematic cross-sectional view of a transistor with source and drain embedded in a silicon carbide strained material to create a stress direction;

FIG. 2B is a schematic top view of the source, drain, and channel regions of FIG. 2A;

fig. 3 is a schematic cross-sectional view of a first semiconductor structure provided in an embodiment of the present disclosure;

fig. 4 is a schematic cross-sectional view of a second semiconductor structure provided in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating the gate control capability of the semiconductor structure of FIG. 3 or FIG. 4;

FIG. 6A is a global stress distribution diagram of an axially pure bend of the semiconductor structure of FIG. 3;

FIG. 6B is a stress distribution diagram of any of the cross sections of FIG. 6A;

fig. 6C is a stress profile of any cross-section of a channel region of the semiconductor structure of fig. 3;

FIG. 7A is a global stress distribution diagram of an axially pure bend of the semiconductor structure of FIG. 4;

FIG. 7B is a stress distribution diagram of any of the cross sections of FIG. 7A;

fig. 7C is a stress profile of any cross-section of a channel region of the semiconductor structure of fig. 4;

FIG. 8 is a schematic diagram of a first distribution of a first element and a second element in a first stress layer;

FIG. 9 is a schematic diagram of a second distribution of a first element and a second element in a first stress layer;

Fig. 10 is a schematic cross-sectional view of a third semiconductor structure provided in an embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional view of a fourth semiconductor structure provided in an embodiment of the present disclosure;

fig. 12 is a schematic cross-sectional view of a fifth semiconductor structure provided by an embodiment of the present disclosure;

fig. 13 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 14A to 14H are schematic cross-sectional views illustrating a semiconductor structure manufacturing process according to an embodiment of the present disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure.

Transistors may be used in various semiconductor devices, for example, a sense amplifier circuit and a word line driver circuit of a dynamic random access memory (DRAM, dynamic Random Access Memory).

As the size of the memory is reduced, the transistor size of the memory area is also continuously reduced, and the smaller the transistor size is, the limitation is that the power consumption density, transmission speed, etc. of the transistor reach physical limits. In particular, some Transistors with ever shrinking dimensions, such as Thin-Film Transistors (TFTs), have a carrier mobility μ (hereinafter μ, μ _e 、μ _h Represented, wherein μ represents carrier mobility, μ _e Represents electron mobility, μ _h Representing hole mobility) can meet the design requirements after the feature size is reduced, but its mu is lower but cannot meet the design requirements, nor the design requirements for reducing leakage current.

Fig. 1 is a schematic diagram of a process for epitaxially growing a silicon carbide strained material on a silicon substrate. Referring to fig. 1, in the related art, silicon carbide (SiC) is epitaxially grown on a silicon (Si) substrate, and a transition region having a material composition mismatch is formed between the Si substrate and the SiC epitaxy by using a difference between a material composition of the Si substrate and a material composition of the SiC epitaxy, and a stress is introduced into the transition region to obtain a strained (hereinafter also referred to as stress) material. The Si substrate is subjected to tensile stress through the transition region with the mismatched material composition, and the SiC epitaxial is subjected to compressive stress through the transition region with the mismatched material composition.

When tensile stress is applied to an N-channel Metal-Oxide-Semiconductor (NMOS) transistor<100>Or alternatively<110>Electron mobility μ of channel layer of NMOS transistor on channel layer of crystal orientation _e Increasing with increasing tensile stress, whereas for compressive stress, the electron mobility μ of the channel layer of an NMOS transistor is exactly opposite _e Decreasing with increasing compressive stress.

When compressive stress is applied to a P-channel Metal-Oxide-Semiconductor (PMOS) transistor<100>Or alternatively<110>Electron mobility μ of channel layer of PMOS transistor on channel layer of crystal orientation _p Increasing with increasing compressive stress, whereas for tensile stress, the electron mobility μ of the channel layer of the PMOS transistor is exactly opposite _p Decreasing with increasing tensile stress.

Stress engineering (including introducing tensile or compressive stress) has evolved therefrom for improving the electrical characteristics of transistors (including NMOS transistors, PMOS transistors), e.g., reducing power consumption of transistors, increasing transmission speed of transistors, etc.

Here and hereinafter, for convenience of description, the first direction and the second direction are represented as two orthogonal directions parallel to a plane of the substrate (or the base structure) in the embodiments of the present disclosure; the third direction is the direction perpendicular to the plane of the substrate (or base structure); wherein a substrate (or base structure) plane may be understood as a plane parallel to the direction of extension of the channel. The first direction may be denoted as X-direction in the drawing; the second direction may be denoted as Y-direction in the drawing; the third direction may be denoted as Z-direction in the drawing.

Fig. 2A is a schematic cross-sectional view of a transistor in the direction of stress created by the embedding of the source and drain into silicon carbide stress material. Fig. 2B is a schematic top view of the source, drain, and channel regions of fig. 2A. Here, the transistor shown in fig. 2A is an NMOS transistor, including a P-well on a P-type substrate, and source, gate, drain and channel layers located in the P-well, wherein the source and the drain are N-type highly doped regions (n+); to facilitate understanding of the direction of stress generated by the source and drain to the channel layer, fig. 2B shows only a schematic top view of the direction of stress generated by the source and drain to the channel layer (generated at a position of the channel region near the gate).

Referring to fig. 2A and 2B, in the related art, a SiC thin film is grown on both sides (source and drain regions) of a channel layer of an NMOS transistor, since the lattice constant of C atoms is 3.57 angstromsAnd the lattice constant of the Si atom is +.>So that the grown SiC can generate tensile stress on the channel layer to improve the electron mobility mu of the channel layer of the NMOS transistor _e The power consumption of the transistor is reduced, and the transmission speed of the transistor is improved.

The transistor in the related art cannot have high carrier mobility mu and low leakage current while having reduced feature size, cannot reduce power consumption of the transistor, cannot increase transmission speed of the transistor, and is difficult to meet the requirement of high performance while increasing integration level.

In order to solve at least one of the above-mentioned problems existing in the related art, embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same.

Fig. 3 is a schematic cross-sectional view of a first semiconductor structure provided in an embodiment of the disclosure. Fig. 4 is a schematic cross-sectional view of a second semiconductor structure provided in an embodiment of the present disclosure. Referring to fig. 3 and 4, based on a first aspect according to an embodiment of the present disclosure, there is provided a semiconductor structure comprising: a base structure including a source S, a drain D, and a channel region; a gate structure G on the base structure; the source electrode S and the drain electrode D are respectively positioned at two sides of the grid structure G, and the channel region is positioned below the grid structure G; the substrate structure further includes a first stress layer 110, where the first stress layer 110 is located at least between the source S and the channel region or at least between the drain D and the channel region; wherein at least a portion of the first stress layer 110 is located under the gate structure G; the upper portion 1102 of the first stress layer and the lower portion 1101 of the first stress layer are opposite in stress direction to the channel region.

Referring to fig. 3, the base structure includes a substrate 100, an active layer AA on the substrate 100, and an isolation structure (not shown in fig. 3). Referring to fig. 4, the base structure includes a substrate 100, an active layer AA and an isolation structure (not shown in fig. 4) on the substrate 100, and a second stress layer 108 located in the active layer AA.

The channel layer CH is formed in a channel region corresponding to the upper portion 1102 of the first stress layer.

The first stress layer 110 includes an upper portion 1102 of the first stress layer and a lower portion 1101 of the first stress layer, and the first stress layer 110 may be a unitary structure or two structures having an interface.

Illustratively, the average lattice constant of the upper portion 1102 of the first stress layer and the average lattice constant of the lower portion 1101 of the first stress layer may have a difference. The first stress layer 110 may be a unitary structure having a lattice constant difference between an upper portion 1102 of the first stress layer and a lower portion 1101 of the first stress layer without an interface. The first stress layer 110 may be two structures having an interface, with a lattice constant difference between an upper portion 1102 of the first stress layer and a lower portion 1101 of the first stress layer, and having an interface.

It should be noted that, the first stress layer 110 is located between the source S and the channel region, or the first stress layer 110 is located between the drain D and the channel region, or the first stress layer 110 is located between the source S and the channel region and between the drain D and the channel region. Here and hereinafter, the first stress layer 110 is illustrated as being located between the source S and the channel region and between the drain D and the channel region.

For an NMOS transistor, a first stress layer 110 is disposed at least between the source S and the channel region or at least between the drain D and the channel region, and stress is introduced into the channel layer of the NMOS transistor through the first stress layer 110, so that the atomic distance in the channel layer of the NMOS transistor is prolonged, the reduction of the number of atoms per unit length is realized, the carrier mobility of the channel layer is increased, the current speed of the channel layer is increased, and the power consumption of the transistor is reduced.

For a PMOS transistor, a first stress layer 110 is disposed at least between the source S and the channel region or at least between the drain D and the channel region, and stress is introduced into the channel layer of the PMOS transistor through the first stress layer 110, so that the atomic distance in the channel layer of the PMOS transistor is shortened, the increase of the number of atoms per unit length is realized, the carrier mobility of the channel layer is increased, the current speed of the channel layer is increased, and the power consumption of the transistor is reduced.

Fig. 5 is a schematic diagram of the gate control capability of the semiconductor structure of fig. 3 or fig. 4. Referring to fig. 5, according to the theory of semiconductors, the closer the capacitance C in the active layer AA is to the surface of the gate structure G _g The larger the gate control capability is, the stronger the on-state conduction current can be formed, and the farther the capacitance C of the surface of the gate structure G is _d The weaker is mainly caused by Leakage Path (LP).

In the embodiment of the disclosure, the first stress layer 110 is disposed at least between the source S and the channel region or at least between the drain D and the channel region, and stress is introduced into the channel layer of the transistor through the first stress layer 110, so that for an NMOS transistor, the compressive stress of the bottom leakage channel LP can be realized, the tensile stress of the top channel CH can be applied, for a PMOS transistor, the tensile stress of the bottom leakage channel LP can be realized, and the compressive stress of the top channel CH can be applied, thereby finally enhancing the on-state current and reducing the off-state current of the transistor.

In some embodiments, the channel region includes a P-type dopant; the upper portion 1102 of the first stress layer is tensile to the stress of the channel region; the stress of the lower portion 1101 of the first stress layer to the channel region is compressive; alternatively, the channel region includes an N-type dopant; the upper portion 1102 of the first stress layer is compressive to the stress of the channel region; the stress of the lower portion 1101 of the first stress layer to the channel region is tensile.

The NMOS transistor is described below as an example.

Fig. 6A is a global stress profile of the semiconductor structure of fig. 3 with pure bending in the axial direction. Fig. 6B is a stress distribution diagram of any cross section of fig. 6A.

Referring to fig. 6A and 6B, an axially pure bending neutral axis is located at the middle of the bending portion of the semiconductor structure, and as shown by the dotted line in fig. 6A, a maximum tensile stress occurs at the surface E1 and a maximum compressive stress occurs at the bottom surface E2.

Fig. 6C is a stress profile of any cross-section of a channel region of the semiconductor structure of fig. 3.

Referring to fig. 6C, the axially pure bending neutral axis is located in the middle of the channel region of the semiconductor structure, and the maximum tensile stress occurs near the gate structure G surface (at the channel layer CH location) and the maximum compressive stress occurs away from the gate structure G surface (at the channel layer CH location) as shown by the dashed line in fig. 6C.

Referring to fig. 3 and 6C in combination, the upper portion 1102 of the first stress layer directly generates tensile stress to the channel layer CH, and the lower portion 1101 of the first stress layer directly generates compressive stress to the corresponding channel region (corresponding to the lower portion 1101 of the first stress layer indirectly generating tensile stress to the channel layer CH), so that the channel layer CH on top of the channel region is subjected to superimposed tensile stress by the upper portion 1102 of the first stress layer and the lower portion 1101 of the first stress layer. Thus, the mobility of the channel layer CH of the NMOS transistor can be further improved, the power consumption of the transistor can be reduced, and the transmission speed of the transistor can be improved.

In some embodiments, when the channel region includes a P-type dopant, the upper portion 1102 of the first stress layer includes an element having an average lattice constant that is less than an average lattice constant of the element included in the channel region; the lower portion 1101 of the first stress layer comprises an element having an average lattice constant that is greater than the average lattice constant of the element comprising the channel region.

Illustratively, the material of the channel region is silicon including a P-type dopant, the element included in the upper portion 1102 of the first stress layer is carbon, and the element included in the lower portion 1101 of the first stress layer is germanium.

Due to lattice constant of C atomsLattice constant smaller than Si atom +.>Lattice constant of Ge atom->Larger than the lattice constant of Si atoms, such that the average lattice constant of the elements contained in the upper portion 1102 of the first stress layer is smaller than the average lattice constant of the elements contained in the channel region, so that SiC grown in the upper portion 1102 of the first stress layer will exert a tensile stress on the channel region; the average lattice constant of the elements contained in the lower portion 1101 of the first stress layer is greater than the average lattice constant of the elements contained in the channel region, so that SiGe grown in the lower portion 1101 of the first stress layer may generate compressive stress on the channel region.

Illustratively, the material of the channel region is silicon germanium including a P-type dopant, the element contained in the upper portion 1102 of the first stress layer is carbon or silicon, and the element contained in the lower portion 1101 of the first stress layer is germanium.

Also, the average lattice constant of the elements contained in the upper portion 1102 of the first stress layer may be made smaller than the average lattice constant of the elements contained in the channel region, so that the upper portion 1102 of the first stress layer may generate tensile stress on the channel region; the lower portion 1101 of the first stress layer may be made to contain elements having an average lattice constant that is greater than the average lattice constant of the elements contained in the channel region, so that the lower portion 1101 of the first stress layer may generate compressive stress to the channel region.

In this way, the upper portion 1102 of the first stress layer directly generates tensile stress to the channel layer CH, and the lower portion 1101 of the first stress layer directly generates compressive stress to the corresponding channel region (corresponding to the lower portion 1102 of the first stress layer indirectly generating tensile stress to the channel layer CH), so that the channel layer CH on top of the channel region is subjected to the superimposed tensile stress generated by the upper portion 1102 of the first stress layer and the lower portion 1101 of the first stress layer.

In some embodiments, an upper portion 1102 of the first stress layer comprises a first element; the lattice constant of the first element is smaller than the lattice constant of the main element of the channel region; the lower portion 1101 of the first stress layer contains a second element; the lattice constant of the second element is larger than that of the main element of the channel region; wherein, in the direction that the upper part 1102 of the first stress layer points to the lower part 1101 of the first stress layer, the atomic percentage of the first element is in gradient decreasing distribution, and the atomic percentage of the second element is in gradient increasing distribution; or the atomic percentage of the first element is distributed in a first increasing and then decreasing way, and the atomic percentage of the second element is distributed in a first increasing and then decreasing way.

For the NMOS transistor, in a direction in which the upper portion 1102 of the first stress layer points to the lower portion 1101 of the first stress layer, the first element (carbon) is located in the upper portion 1102 of the first stress layer, and the atomic percentage of the first element (carbon) is distributed in a gradient decreasing manner; the second element (germanium) is located in the lower portion 1101 of the first stress layer, and the atomic percentage of the second element (germanium) is distributed in a gradient increasing manner.

Fig. 8 is a schematic diagram of a first distribution of a first element and a second element in the first stress layer 110. Referring to fig. 8, for an NMOS transistor, the atomic percentage of the first element (carbon) is distributed first-increment-then-decrement, and the atomic percentage of the second element (germanium) is distributed first-increment-then-decrement.

In some embodiments, when the channel region includes an N-type dopant, the upper portion 1102 of the first stress layer includes an element having an average lattice constant that is greater than an average lattice constant of the element included in the channel region; the lower portion 1101 of the first stress layer contains elements having an average lattice constant that is less than the average lattice constant of the elements contained in the channel region.

Illustratively, for PMOS transistors, the channel region is of silicon including N-type dopants, the upper portion 1102 of the first stress layer comprises the element second element (germanium), and the lower portion 1101 of the first stress layer comprises the element first element (carbon).

Due to lattice constant of C atomsLattice constant smaller than Si atom +.>Lattice constant of Ge atom->The lattice constant of the elements contained in the upper portion 1102 of the first stress layer is greater than the lattice constant of the elements contained in the channel region, so that SiGe grown in the upper portion 1102 of the first stress layer produces compressive stress to the channel region; the average lattice constant of the elements contained in the lower portion 1101 of the first stress layer is larger than the average lattice constant of the elements contained in the channel region, so that the SiC grown in the lower portion 1101 of the first stress layer may generate tensile stress to the channel region.

In this way, the upper portion 1102 of the first stress layer directly generates compressive stress to the channel layer CH, and the lower portion 1101 of the first stress layer directly generates tensile stress to the corresponding channel region (corresponding to the lower portion 1102 of the first stress layer indirectly generating compressive stress to the channel layer CH), so that the channel layer CH on top of the channel region is subjected to the superimposed compressive stress by the upper portion 1102 of the first stress layer and the lower portion 1101 of the first stress layer.

In some embodiments, the upper portion 1102 of the first stress layer comprises a second element; the lattice constant of the second element is larger than that of the main element of the channel region; a lower portion 1101 of the first stress layer contains a first element; the lattice constant of the first element is smaller than the lattice constant of the main element of the channel region; wherein, in the direction that the upper part 1102 of the first stress layer points to the lower part 1101 of the first stress layer, the atomic percentage of the second element is in gradient decreasing distribution, and the atomic percentage of the first element is in gradient increasing distribution; or the atomic percentage of the first element is distributed in a first increasing and then decreasing way, and the atomic percentage of the second element is distributed in a first increasing and then decreasing way.

For PMOS transistors, the first element (carbon) is located in the lower portion 1101 of the first stress layer in a direction in which the upper portion 1102 of the first stress layer is directed to the lower portion 1101 of the first stress layer, and the atomic percentage of the first element (carbon) is distributed in a gradient decreasing manner; the second element (germanium) is located on the upper portion 1102 of the first stress layer, and the atomic percentage of the second element (germanium) is distributed in a gradient increasing manner.

Fig. 9 is a schematic diagram of a second distribution of the first element and the second element in the first stress layer 110. Referring to fig. 9, for a PMOS transistor, the atomic percentage of the first element (carbon) is distributed first-increment-then-decrement, and the atomic percentage of the second element (germanium) is distributed first-increment-then-decrement.

In some embodiments, the first element comprises carbon, the second element comprises germanium, and the primary element of the channel region comprises silicon.

Fig. 10 is a schematic cross-sectional view of a third semiconductor structure provided in an embodiment of the present disclosure. The difference between fig. 10 and fig. 4 is that: the first stress layer 110 and the source S, drain D of the semiconductor structure of fig. 10 are spaced apart from the second stress layer 108, while the first stress layer 110 and/or the source S, drain D of the semiconductor structure of fig. 4 are in contact with the second stress layer 108.

Referring to fig. 4 and 10, in some embodiments, the semiconductor structure further includes a second stress layer 108 located in the base structure; the source electrode S, the drain electrode D, the first stress layer 110 and the channel region are positioned above the second stress layer 108, and the horizontal width of the second stress layer 108 is larger than that of the channel region; the channel region comprises a channel layer positioned on the surface of the substrate structure and a doped well layer positioned below the channel layer, the stress direction of the upper parts of the second stress layer 108 and the first stress layer 110 to the channel layer is the same, and the stress direction of the second stress layer 108 to the channel layer is opposite to the stress direction of the second stress layer 108 to the doped well layer; the first stress layer 110 and/or the source S, drain D are in contact with the second stress layer 108 in the thickness direction of the base structure, or the first stress layer 110 and the source S, drain D are spaced apart from the second stress layer 108.

The NMOS transistor is described below as an example.

Fig. 7A is a global stress profile of the semiconductor structure of fig. 4 in an axially pure bend. Fig. 7B is a stress distribution diagram of any cross section of fig. 7A.

Referring to fig. 7A and 7B, an axially pure bending neutral axis is located at the middle of the bending portion of the semiconductor structure, and as shown by a dotted line in fig. 7A, a maximum tensile stress occurs at the surface E1 and a maximum compressive stress occurs at the bottom surface E2.

Fig. 7C is a stress profile of any cross-section of a channel region of the semiconductor structure of fig. 4.

Referring to fig. 7C, the surface of the channel layer CH of the axially pure bend neutral axially semiconductor structure is offset (compared to the axially pure bend neutral axis of fig. 6C), and the maximum tensile stress occurs near the gate structure G surface (at the channel layer CH location) and the maximum compressive stress occurs away from the gate structure G surface (at the channel layer CH location) as shown by the dashed line in fig. 7C.

Referring to fig. 4 and 7C in combination, the upper portion of the first stress layer 110 directly generates tensile stress to the channel layer CH, and the lower portion 1102 of the first stress layer directly generates compressive stress to the corresponding channel region (corresponding to the lower portion 1102 of the first stress layer indirectly generating tensile stress to the channel layer CH), so that the channel layer CH on top of the channel region is subjected to the superimposed tensile stress by the upper portion 1102 of the first stress layer and the lower portion 1101 of the first stress layer. Meanwhile, the second stress layer 108 directly generates a compressive stress to the corresponding channel region (corresponding to the second stress layer 108 indirectly generating a tensile stress to the channel layer CH), so that the channel layer CH on top of the channel region is subjected to the superimposed tensile stress by the upper portion 1102 of the first stress layer, the lower portion 1101 of the first stress layer, and the second stress layer 108. Thus, the mobility of the channel layer CH of the NMOS transistor can be further improved, the power consumption of the transistor can be reduced, and the transmission speed of the transistor can be improved.

Fig. 11 is a schematic cross-sectional view of a fourth semiconductor structure provided in an embodiment of the present disclosure. Fig. 12 is a schematic cross-sectional view of a fourth semiconductor structure provided in an embodiment of the present disclosure. Fig. 11 and 12 differ from fig. 4 in that: fig. 11 and 12 show a specific location of the sidewall structure 202 on the sidewall of the gate structure G. Referring to fig. 11 and 12, in some embodiments, the semiconductor structure further includes a sidewall structure 202 located on the sidewall of the gate structure G; wherein the first stress layer 110 is partially located in the substrate structure under the sidewall structure 202 and partially located under the gate structure G (shown in fig. 11), or partially located outside the sidewall structure 202 and partially located under the gate structure G (shown in fig. 12).

Referring to fig. 11 and 12, in some embodiments, the depth of the first strained layer is substantially the same as the depth of the source and drain electrodes in the thickness direction (or third direction) of the base structure.

In various embodiments of the present disclosure, a first stress layer is disposed at least between a source and a channel region or at least between a drain and a channel region, and stress is introduced in the channel layer of a transistor (including an NMOS transistor and a PMOS transistor) through the first stress layer, so that carrier mobility of the channel layer is increased, current speed of the channel layer is increased, power consumption of the transistor is reduced, speed of the transistor is increased, and better performance of the transistor is achieved.

The semiconductor structure provided in the embodiments of the present disclosure is similar to a semiconductor structure manufactured by a method for manufacturing a semiconductor structure in the following embodiments, and for technical features that are not disclosed in detail in the embodiments of the present disclosure, reference is made to the semiconductor structure manufactured by the method for manufacturing a semiconductor structure described below for understanding, and details are not repeated here.

Fig. 13 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.

Referring to fig. 13, according to a second aspect of an embodiment of the present disclosure, there is provided a method of manufacturing a semiconductor structure, including the steps of:

step S131, providing a substrate structure;

step S132, forming a grid structure on the substrate structure;

step S133, forming a source electrode and a drain electrode in the substrate structures at two sides of the gate structure, and forming a channel region between the source electrode and the drain electrode;

step S134, forming a first stress layer at least between the source electrode and the channel region or between the drain electrode and the channel region;

wherein at least a portion of the first stress layer is located under the gate structure; the upper portion of the first stress layer and the lower portion of the first stress layer are opposite in stress direction to the channel region.

It should be understood that the steps shown in fig. 13 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 13 may be sequentially adjusted according to actual needs.

Fig. 14A to 14H are schematic cross-sectional views illustrating a semiconductor structure manufacturing process according to an embodiment of the present disclosure. The steps shown in fig. 14A-14H are not exclusive and other steps may be performed before, after, or between any of the illustrated operations; the steps shown in fig. 14A to 14H may be sequentially adjusted according to actual demands. The enlarged views of the P region in fig. 14A to 14H can be understood with reference to the cross-sectional areas of the semiconductor structures shown in fig. 3, 4, 10, 11, and 12.

The method of manufacturing the semiconductor structure provided in the embodiments of the present disclosure is described in detail below with reference to fig. 13 and 14A to 14H. It will be appreciated that the method of fabricating the semiconductor structure described in the embodiments of the present disclosure is not limited to fabricating a particular number of transistors: the method may be a method of manufacturing a single transistor or a method of manufacturing a transistor array. Here and hereinafter, a method for manufacturing a single transistor will be described as an example in the drawings.

Step S131 is performed, referring to fig. 14A to 14E, providing a base structure.

Referring to fig. 14A, a substrate 100 is provided, and a material of the substrate 100 may include silicon (Si), germanium (Ge), silicon germanium (SiGe) substrate, or the like; the substrate 100 may also be Silicon-on-Insulator (SOI) or Germanium-on-Insulator (GOI).

Referring to fig. 14B, a shallow trench isolation process is used to form trenches and a plurality of active regions arranged in an array in a first direction and a second direction in the substrate 100.

Referring to fig. 14C, isolation structures (STI, shallow Trench Isolation) are formed in the trenches between adjacent active regions. The constituent materials of the isolation structures STI include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride. Illustratively, the isolation structure STI includes a silicon oxide layer 102, a silicon nitride layer 104, and a silicon oxide layer 106 stacked in this order in the trench.

Referring to fig. 14D, an active layer AA is formed by doping a material of a certain impurity ion into the top of the substrate 100 using an ion implantation (Implant) process. The impurity ions may be N-type impurity ions or P-type impurity ions. Illustratively, the material of the substrate includes silicon, and P-type doping is performed on top of the substrate to form an active layer AA having P-type doping, the active layer AA serving as a P-well for forming the NMOS transistor.

In some embodiments, the active layer AA may be formed on the substrate 100. In other embodiments, the active layer AA may also be formed on other functional thin film layers.

Thus, the base structure includes the substrate 100, the active layer AA on the substrate 100, and the isolation structure STI.

Referring to fig. 14E, in some embodiments, after forming isolation structures STI in the substrate 100, a second stress layer 108 is formed in the active layer AA of the entire substrate 100. Illustratively, the material of the substrate comprises silicon, the material of the active layer AA comprises boron (B), and the material of the second stress layer 108 comprises carbon.

Thus, the base structure includes the substrate 100, the active layer AA and the isolation structure STI on the substrate 100, and the second stress layer 108 located in the active layer AA.

In step S132, referring to fig. 14F, a gate structure is formed.

A thin film deposition process is used to form a gate material (not shown in fig. 14F) covering the active layer AA and the isolation structures STI.

Here and below, thin film deposition processes include, but are not limited to, physical vapor deposition (PVD, physical Vapor Deposition) processes, chemical vapor deposition (CVD, chemical Vapor Deposition) processes, atomic layer deposition (ALD, atomic Layer Deposition), and the like.

A plurality of gate structures G are formed by etching a gate structure material through a photolithography-Etch process (LE), each gate structure G extending in the second direction and being located on the active layer AA.

In some embodiments, a gate dielectric layer (not shown in fig. 14F) is further included between the gate structure G and the active region. The gate dielectric layer material includes, but is not limited to, silicon oxide. The material of the gate structure G may be a metal material or a semiconductor conductive material, for example, copper, cobalt, nickel, tungsten, molybdenum, doped silicon, polysilicon, or any combination thereof, or the like. In some embodiments, a protective dielectric layer (not shown in fig. 14F) is further formed on the gate structure G, and the protective dielectric layer is used to protect the top surface of the gate structure G. The material of the protective dielectric layer includes, but is not limited to, silicon oxide. In some embodiments, the sidewalls of the gate structure G are further formed with sidewall structures (not shown in fig. 14F, which can be understood with reference to the sidewall structures 202 of fig. 11 and 12 described above) for protecting the sidewalls of the gate structure G. The material of the sidewall structure includes, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride. Illustratively, the sidewall structure includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer sequentially stacked on the sidewall of the gate structure G.

In some embodiments, the gate structure G includes a structure of multiple layers of different conductive material stacked in sequence. In practical applications, the gate structure G includes a semiconductor layer (not shown in fig. 14F), an adhesive layer (not shown in fig. 14F), and a metal layer (not shown in fig. 14F) stacked in order, and illustratively, the gate structure G includes a polysilicon layer, a titanium carbide layer, and a tungsten metal layer stacked in order.

In step S134, referring to fig. 14G, a first stress layer is formed.

After forming the gate structure G on the base structure, a mask (not shown in fig. 14G) covering the base structure is formed, and portions of the active layer AA (not shown in fig. 14G, hereinafter referred to as a first region) adjacent to both sides of the gate structure G are defined and exposed through the mask. Specifically, the mask may be made of a photoresist material, such as photoresist. In some embodiments, the mask also covers the upper surface of the gate structure G;

implanting dopant ions into the exposed first region along an oblique direction of the biasing gate structure G to form an obliquely extending dopant implantation region (not shown in fig. 14G, hereinafter referred to as a first stress material layer) in the active layer AA;

the first stress layer 110 is formed after annealing the first stress material layer.

In one embodiment, after forming the first stress material layer, further comprising: a lightly doped drain (LDD, lightly Doped Drain) region (not shown in fig. 14G) is formed in the surface layer of the first region, the LDD region having a conductivity type opposite to that of the active region AA. Illustratively, the material of the substrate comprises silicon, the material of the active layer AA comprises P-type impurity ions, and the material of the LDD region comprises N-type impurity ions.

In some embodiments, forming the first stress layer 110 at least between the source and the channel region or between the drain and the channel region includes:

ion implantation of a first element is performed on the substrate structure at a first included angle under first energy, ion implantation of a second element is performed on the substrate structure at a second included angle under second energy, the first included angle is larger than the second included angle, and the first energy is smaller than the second energy;

or alternatively, the process may be performed,

and performing ion implantation of a second element on the substrate structure at a first included angle under the first energy, and performing ion implantation of the first element on the substrate structure at a second included angle under the second energy, wherein the first included angle is larger than the second included angle, and the first energy is smaller than the second energy.

Thus, the upper portion of the first stress layer and the lower portion of the first stress layer are opposite in stress direction to the channel region. The channel layer is formed in the channel region corresponding to the upper portion of the first stress layer. Taking the NMOS transistor as an example, the first element includes C, the second element includes Ge, and the material of the base structure includes Si. Since the lattice constant of the C atoms is smaller than that of the Si atoms and the lattice constant of the Ge atoms is larger than that of the Si atoms, the grown SiC will exert a tensile stress on the channel layer, and the grown SiGe will exert a compressive stress on the channel layer.

And carrying out ion implantation of a C element on the substrate structure at a first included angle by adopting an ion implantation process, and carrying out ion implantation of a Ge element on the substrate structure at a second included angle at a second energy, wherein the included angle of the ion implantation of the C element is larger than that of the ion implantation of the Ge element, and the energy of the ion implantation of the C element is smaller than that of the ion implantation of the Ge element. The upper part of the first stress layer is tensile stress to the corresponding channel region, and the lower part of the first stress layer is compressive stress to the corresponding channel region, so that the mobility of the channel layer of the NMOS transistor can be improved, the power consumption of the transistor can be reduced, and the transmission speed of the transistor can be improved.

Taking the PMOS transistor as an example, the first element includes Ge, the second element includes C, an ion implantation process is adopted to perform ion implantation of the C element on the substrate structure at a first included angle under a first energy, and perform ion implantation of the Ge element on the substrate structure at a second included angle under a second energy, wherein the included angle of the ion implantation of the Ge element is larger than the included angle of the ion implantation of the C element, and the energy of the ion implantation of the Ge element is smaller than the energy of the ion implantation of the C element. The upper part of the first stress layer is compressive stress to the corresponding channel region, and the lower part of the first stress layer is tensile stress to the corresponding channel region, so that the mobility of the channel layer of the PMOS transistor can be improved, and the electrical characteristics of the PMOS transistor can be improved.

In step S133, referring to fig. 14H, a source electrode and a drain electrode are formed.

After the first stress layer 110 is formed in the active layer AA, a sidewall structure (not shown in fig. 14G) is formed to cover a sidewall of the gate structure, the sidewall structure covering a top surface of the first stress layer 110. Specifically, the thickness of the sidewall is equal to the width of the first region. A portion of the active layer AA (not shown in fig. 14G, hereinafter referred to as a second region) adjacent to both sides of the first stress layer is defined and exposed by the sidewall structure and the gate structure.

And implanting doping ions into the exposed second region along the vertical direction and annealing to form a source electrode and a drain electrode which extend vertically in the active layer AA.

In some embodiments, the annealing process of the first layer of stressed material may be incorporated into the implantation of dopant ions into the exposed second region and annealing.

In some embodiments, the method further comprises forming a sidewall structure on the sidewall of the gate structure; forming a first stress layer, comprising:

referring to fig. 14H, before forming the sidewall structure, a first stress material layer is formed in the substrate structure other than the gate structure G by using an ion implantation process; after the sidewall structure 202 is formed, the first stress material layer is located under the sidewall structure 202;

Annealing the first stress material layer to form a first stress layer 110 partially under the sidewall structure 202 and partially under the gate structure G;

or alternatively, the process may be performed,

after forming the side wall structure, forming a first stress material layer in a substrate structure outside the side wall structure by adopting an ion implantation process; the first stress material layer is positioned outside the side wall structure;

and annealing the first stress material layer to form a first stress layer which is partially positioned outside the side wall structure, partially positioned below the side wall structure and partially positioned below the grid structure.

In this way, the first stress material layer may be formed before forming the sidewall structure or after forming the sidewall structure, and the resulting first stress material layer may be a first stress layer partially under the sidewall structure and partially under the gate structure, or a first stress layer partially outside the sidewall structure, partially under the sidewall structure and partially under the gate structure.

The semiconductor structure manufactured by the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure is similar to the semiconductor structure in the above embodiments, and for technical features that are not fully disclosed in the embodiments of the present disclosure, reference is made to the above embodiments for understanding, and details are not repeated here.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims

1. A semiconductor structure, comprising:

a base structure comprising a source, a drain, and a channel region;

a gate structure located on the base structure;

the source electrode and the drain electrode are respectively positioned at two sides of the grid structure, and the channel region is positioned below the grid structure;

the base structure further includes a first stress layer located at least between the source and channel region or at least between the drain and channel region;

2. The semiconductor structure of claim 1, wherein,

the channel region includes a P-type dopant; the stress of the upper part of the first stress layer on the channel region is tensile stress; the stress of the lower part of the first stress layer on the channel region is compressive stress;

Or alternatively, the process may be performed,

the channel region includes an N-type dopant; the stress of the upper part of the first stress layer on the channel region is compressive stress; the stress of the lower portion of the first stress layer to the channel region is tensile stress.

3. The semiconductor structure of claim 2, wherein,

when the channel region comprises a P-type dopant, an average lattice constant of an element contained in an upper portion of the first stress layer is smaller than an average lattice constant of an element contained in the channel region; the lower portion of the first stress layer includes an element having an average lattice constant greater than an element included in the channel region.

4. The semiconductor structure of claim 3, wherein,

an upper portion of the first stress layer comprises a first element; the lattice constant of the first element is smaller than the lattice constant of the main element of the channel region; the lower part of the first stress layer comprises a second element; the lattice constant of the second element is greater than the lattice constant of the main element of the channel region;

wherein, in the direction that the upper part of the first stress layer points to the lower part of the first stress layer, the atomic percentage of the first element is in gradient decreasing distribution, and the atomic percentage of the second element is in gradient increasing distribution; or the atomic percentage of the first element is distributed in a first increasing and then decreasing way, and the atomic percentage of the second element is distributed in a first increasing and then decreasing way.

5. The semiconductor structure of claim 2, wherein,

when the channel region comprises an N-type dopant, an average lattice constant of an element contained in an upper portion of the first stress layer is greater than an average lattice constant of an element contained in the channel region; the lower portion of the first stress layer includes an element having an average lattice constant that is less than an average lattice constant of an element included in the channel region.

6. The semiconductor structure of claim 5, wherein,

the upper part of the first stress layer comprises a second element; the lattice constant of the second element is greater than the lattice constant of the main element of the channel region; the lower part of the first stress layer comprises a first element; the lattice constant of the first element is smaller than the lattice constant of the main element of the channel region;

wherein, in the direction that the upper part of the first stress layer points to the lower part of the first stress layer, the atomic percentage of the second element is distributed in a gradient decreasing way, and the atomic percentage of the first element is distributed in a gradient increasing way; or the atomic percentage of the first element is distributed in a first increasing and then decreasing way, and the atomic percentage of the second element is distributed in a first increasing and then decreasing way.

7. The semiconductor structure of claim 4 or 6, wherein the first element comprises carbon, the second element comprises germanium, and the main element of the channel region comprises silicon.

8. The semiconductor structure of claim 1, further comprising a second stress layer in the base structure; the source electrode, the drain electrode, the first stress layer and the channel region are positioned above the second stress layer, and the horizontal width of the second stress layer is larger than that of the channel region;

the channel region comprises a channel layer positioned on the surface of the substrate structure and a doped well layer positioned below the channel layer, the stress directions of the upper parts of the second stress layer and the first stress layer on the channel layer are the same, and the stress directions of the second stress layer on the channel layer and the stress directions of the second stress layer on the doped well layer are opposite;

the first stress layer and/or the source electrode and the drain electrode are/is in contact with the second stress layer in the thickness direction of the base structure, or the first stress layer and the source electrode and the drain electrode are/is separated from the second stress layer.

9. The semiconductor structure of claim 1, further comprising a sidewall structure on a sidewall of the gate structure;

the first stress layer is partially located under the side wall structure and partially located in the substrate structure under the gate structure, or is partially located outside the side wall structure and partially located in the substrate structure under the gate structure.

10. A method of fabricating a semiconductor structure, comprising:

providing a base structure;

forming a gate structure on the base structure;

forming a source electrode and a drain electrode in the substrate structures at two sides of the gate structure, and forming a channel region between the source electrode and the drain electrode;

forming a first stress layer at least between the source and the channel region or between the drain and the channel region;

11. The method of claim 10, wherein forming a first stress layer at least between the source and the channel region or between the drain and the channel region comprises:

Performing ion implantation of a first element on the substrate structure at a first included angle under first energy, and performing ion implantation of a second element on the substrate structure at a second included angle under second energy, wherein the first included angle is larger than the second included angle, and the first energy is smaller than the second energy;

or alternatively, the process may be performed,

and performing ion implantation of a second element on the substrate structure at a first included angle under first energy, performing ion implantation of the first element on the substrate structure at a second included angle under second energy, wherein the first included angle is larger than the second included angle, and the first energy is smaller than the second energy.

12. The method of claim 10, further comprising forming a sidewall structure on a sidewall of the gate structure; the forming a first stress layer includes:

before forming the side wall structure, forming a first stress material layer in a substrate structure outside the grid structure by adopting an ion implantation process; after the side wall structure is formed, the first stress material layer is positioned below the side wall structure;

forming the first stress layer which is partially positioned under the side wall structure and partially positioned under the grid structure after annealing the first stress material layer;

Or alternatively, the process may be performed,

after the side wall structure is formed, forming the first stress material layer in a substrate structure outside the side wall structure by adopting an ion implantation process; the first stress material layer is positioned outside the side wall structure;

and forming the first stress layer which is partially positioned outside the side wall structure, partially positioned below the side wall structure and partially positioned below the grid structure after annealing the first stress material layer.