CN116722041A

CN116722041A - Semiconductor device, method of manufacturing the same, and semiconductor apparatus including the same

Info

Publication number: CN116722041A
Application number: CN202310457778.4A
Authority: CN
Inventors: 季明华
Original assignee: GTA Semiconductor Co Ltd
Current assignee: GTA Semiconductor Co Ltd
Priority date: 2023-04-25
Filing date: 2023-04-25
Publication date: 2023-09-08
Anticipated expiration: 2043-04-25
Also published as: CN116722041B

Abstract

The present disclosure relates to a semiconductor device, a method of manufacturing the same, and an apparatus including the device. Provided is a semiconductor device including: a substrate comprising an active region, the active region comprising at least a first region; a RESURF structure disposed over a first portion of the first region, the RESURF structure including a 2D material layer including a 2D material; a gate structure comprising a gate layer comprising at least a portion adjacent to the 2D material layer, and the portion of the gate layer is isolated from the 2D material layer by an isolation insulating layer, wherein a property of at least the portion of the 2D material layer adjacent to the gate layer varies with a potential of the gate layer.

Description

Semiconductor device, method of manufacturing the same, and semiconductor apparatus including the same

Technical Field

The present disclosure relates to a semiconductor device and a method of manufacturing the same, and an apparatus including the device, and more particularly, to an LDMOS device and a method of manufacturing the same, and an apparatus including the device.

Background

Laterally Diffused MOS (LDMOS) transistors are of great interest. In the LDMOS device of the prior art, a reduced surface field (Reduced Surface Field, RESURF) technology is widely used. For LDMOS devices, it is desirable to obtain a low On-resistance Ron in the On (On) state and to achieve a high breakdown voltage (Breakdown Voltage, BV) in the Off (Off) state. In the LDMOS device in the prior art, an N-type LDMOS (NLDMOS) transistor is mainly used; p-type LDMOS (PLDMOS) transistors also exist, but are not commonly used.

The present disclosure proposes a novel LDMOS device and a method of manufacturing the same.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate comprising an active region, the active region comprising at least a first region; a RESURF structure disposed over a first portion of the first region, the RESURF structure including a 2D material layer including a 2D material; a gate structure comprising a gate layer comprising at least a portion adjacent to the 2D material layer, and the portion of the gate layer is isolated from the 2D material layer by an isolation insulating layer, wherein a property of at least the portion of the 2D material layer adjacent to the gate layer varies with a potential of the gate layer.

According to another aspect of the present disclosure, there is also provided a method of manufacturing a semiconductor device, including: providing a substrate, wherein the substrate comprises an active region, and a first region is formed in the active region; forming a second region in the active region; forming a RESURF structure over a first portion of the first region, the RESURF structure including at least a 2D material layer comprising a 2D material, the 2D material layer being formed over the first portion of the first region; forming a gate structure comprising a gate dielectric layer and a gate layer, the gate dielectric layer overlying at least a second portion of the first region and a portion of the second region, the gate layer comprising a first portion overlying the gate dielectric layer and a second portion adjacent to the 2D material layer, and the gate layer being formed to be electrically insulated from the 2D material layer, wherein a property of at least a portion of the 2D material layer adjacent to the gate layer varies with a potential of the gate layer.

According to yet another aspect of the present disclosure, there is also provided a semiconductor apparatus comprising a semiconductor device as described in any of the embodiments disclosed herein.

Other features of the present disclosure and its advantages will become apparent from the following detailed description of exemplary embodiments of the disclosure, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 shows a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure;

fig. 1A shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;

fig. 1B shows a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure;

fig. 1C shows a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure;

fig. 2 shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;

fig. 3 shows a schematic cross-sectional view of a semiconductor device according to a further embodiment of the present disclosure;

fig. 4A-4J illustrate schematic cross-sectional views in partial process steps during the fabrication of a semiconductor device according to one embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram of a vulcanization (annealing) process of a two-dimensional (2D) material layer according to one embodiment of the present disclosure;

fig. 6 illustrates a flow chart of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure; and

fig. 7A-7F show schematic cross-sectional views in partial process steps in the fabrication of a semiconductor device according to one embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same parts or parts having the same functions, and a repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.

For ease of understanding, the positions, dimensions, ranges, etc. of the respective structures shown in the drawings and the like may not represent actual positions, dimensions, ranges, etc. Accordingly, the disclosed invention is not limited to the disclosed positions, dimensions, ranges, etc. as illustrated in the drawings.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. Note that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise. In addition, techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.

It should be appreciated that the following description of at least one exemplary embodiment is merely illustrative, and is not intended to limit the present disclosure, application or uses thereof. It should also be appreciated that any implementation illustratively described herein is not necessarily indicative of a preferred or advantageous embodiment over other implementations. The disclosure is not to be limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

In addition, certain terminology may be used in the following description for the purpose of reference only and is therefore not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.

It should also be understood that references to "semiconductor device" (which may also sometimes be referred to simply as "device") in the context of the present application mean any device in which semiconductor material is contained, including, but not limited to, for example: a die (die) or wafer (wafer) containing semiconductor material, a chip (chip) or package (package) containing a die, and any device containing the aforementioned die, wafer, chip or package. The term "semiconductor device" in the context of the present application means any device comprising semiconductor material.

Some exemplary embodiments according to the present disclosure are described below with reference to the accompanying drawings.

Fig. 1 shows a schematic cross-sectional view of a semiconductor device 100 according to one embodiment of the present disclosure. In some embodiments, semiconductor device 100 may be a laterally diffused N-type MOS (NLDMOS) device.

As shown in fig. 1, a semiconductor device 100 may include a substrate 101. The substrate 101 may be, for example, but is not limited to, a silicon (Si) substrate, such as a bulk silicon substrate or a silicon-on-Semiconductor (SOI) substrate, or a silicon carbide (SiC) substrate. The substrate 101 comprises an active region comprising at least a first region 111. In some embodiments, the first region 111 may be an N-well (N-well); however, the present disclosure is not limited thereto. As an example, trench isolation STI between devices is also shown in fig. 1.

The semiconductor device 100 may further comprise a (first) RESURF structure comprising a layer 121 of 2D material comprising a two-dimensional (2D) material. As shown in fig. 1, a 2D material layer 121 is disposed over a first portion (not shown) of the first region 111. Here, the first portion of the first region 111 operates as a diffusion drift region or as a part of a diffusion drift region.

The 2D material may also be referred to as a topological insulator (Topological Insulator, TI). In the context of this document, these two concepts are equivalent and interchangeable. Topological insulators are materials with spin-orbit coupling strengths sufficient to reverse the order of the bulk bands around the insulator gap. Although the bulk properties of these materials are not very different from any other insulating material, their surfaces are in a peculiar state. These surface electrons appear as mass-free relativistic particles that obey dirac dynamics, which locks their spin degrees of freedom to momentum, thereby halving their phase space relative to any other fermi state. Furthermore, the spin-spin texture associated with its dirac properties greatly limits scattering of surface states as long as the time-reversal symmetry is maintained. In particular it inhibits backscatter and protects the topological surface electrons from localization.

Thus, in short, a 2D material or topological insulator may appear to be conductive or insulating depending on the external action (e.g., electric field) applied thereto.

In some embodiments, the 2D material may include, for example, but is not limited to, any of the following: molybdenum (Mo) sulfide, tin (Sn) sulfide, selenium (Se) sulfide, tungsten (W) and selenium (Se) compounds, and graphene.

In some embodiments, the thickness of the 2D material layer may be a few nanometers (nm) to a few tens of nanometers, any particular value or range of values within that range of values should be considered as referred to herein, e.g., 5nm-50nm, 5nm-30nm, 8nm-25nm, 10nm-20nm, 7nm, 9nm, 11nm, 15nm, 18nm, 22nm, 35nm, 40nm, 45nm, 55nm, 60nm, 70nm, 80nm, etc. The material, thickness, and fabrication process of the 2D material layer can be easily selected according to actual needs by those skilled in the art.

The semiconductor device 100 may further include a first insulating layer 131. A first insulating layer 131 overlies the RESURF structure. The first insulating layer 131 may be any suitable material, such as, but not limited to, an oxide including silicon (e.g., siO ₂ ). In some embodiments, the thickness of the first insulating layer 131 may be in the range of, for example, several hundred nm to several thousand nm, such as 500nm-8000nm, 500nm-6000nm, 800nm-5500nm, 600nm-5000nm, 1000nm-3000nm, and the like. The thickness of the first insulating layer is largely dependent on the voltage rating used by the device. Any particular value or range of values within the numerical ranges described above should be considered as being referred to herein.

In some embodiments, the (first) RESURF structure may optionally further comprise an interface layer 123. An interface layer 123 is disposed over the 2D material layer 121 and between the 2D material layer and the first insulating layer 131. The thickness of the interface layer 123 may be a few nanometers (nm) to hundreds of nanometers, any specific number or range of numbers within this range of numbers should be considered as mentioned herein, e.g., 3nm/5nm/7nm/10nm-200nm, 15nm-150nm, 20nm-100nm, 30nm-80nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 70nm, 80nm, 90nm, 120nm, 140nm, 250nm, 300nm, etc. Here, "/" indicates or. The thickness of the interfacial layer is largely determined by the fabrication and material properties of the 2D material layer.

In some embodiments, the 2D material layer 121 may include any of the sulfides or selenides previously described, and the interface layer 123 may be used to further vulcanize the 2D material layer 121, for example, by an annealing process in a sulfur-containing atmosphere to compensate for sulfur defects in the 2D material and to increase crystallinity. Thus, the on mobility of the 2D material layer may be enhanced. As an example, the interface layer 123 may include hafnium oxide (HfO ₂ ) Layers and/or alumina (Al ₂ O ₃ ) Layers or a stack thereof.

By annealing the sulfide-containing 2D material layer under a sulfur-containing atmosphere, crystallinity can be improved, and hall effect mobility of the 2D material layer thin film can be improved.

The semiconductor device 100 may further include a gate structure (not labeled in the figures). The gate structure includes a gate layer 143, the gate layer 143 including at least a portion adjacent to the 2D material layer 121, and the portion of the gate layer being isolated from the 2D material layer. In other words, an insulating layer is interposed between the portion of the gate layer and the 2D material layer. Here, for example, a first insulating layer 131 is interposed between the gate layer and the 2D material layer.

Those skilled in the art will readily appreciate that in other embodiments, it is also contemplated that an additional or alternative insulating layer may be provided between the gate layer 143 (or the portion thereof) and the 2D material layer 121; in other words, there is no particular limitation on the isolation insulating layer that isolates both the gate layer and the 2D material layer. For example, there are many different implementations of the isolation insulating layer that isolates the gate layer from the 2D material layer, as shown or described in other embodiments that will be described later. Those skilled in the art will readily be able to configure the implementation of the isolation insulating layer according to the needs of the actual application, including but not limited to the number of layers, the materials and thicknesses of the layers, the manner of formation, etc.

The properties of at least the portion of the 2D material layer 121 adjacent to the gate layer 143 may vary with the potential of the gate layer 143, thereby exhibiting conductive or insulating (non-conductive) properties.

In this embodiment, it is contemplated to form a 2D material layer on a portion of the active region (which may correspond to the lateral diffusion region or a portion thereof) as a new RESURF structure. Using 2D materials (e.g. MoS ₂ Graphene, etc.) as a new RESURF structure, the on-resistance of the LDMOS device in the on-state can be reduced, and the Breakdown Voltage (BV) in the off-state can be increased.

In addition, as shown in fig. 1, the active region may further include a second region 112. In some embodiments, the second region 112 may be a P-well (P-well), and the second region 112 may be disposed in the first region 111. However, it should be understood that the present disclosure is not limited thereto. The active region may further include a third region 113. In some embodiments, the third region 113 may be an N-type (e.g., n+) doped region, which may serve as the drain of the device; however, the present disclosure is not limited thereto. The third region 113 may be disposed in the first region 111 (here, an N-well), and the third region 113 may have a higher doping concentration than the first region 111.

In a top view, the first region 111 and the second region 112 may be laterally adjacent to each other, and the third region and the first region may be laterally adjacent to each other. Furthermore, the 2D material layer 121 may be disposed between the second region 112 and the third region 113 when seen in a top view.

The new RESURF structure according to embodiments of the present application can replace the conventional RESURF structure with a smaller layout (layout) and superior performance (low Ron and high BV). Alternatively, the new RESURF structure according to embodiments of the application may also be used in conjunction with conventional RESURF structures.

For example, as shown in fig. 1, the active region may also include a fourth region 114. In some embodiments, the fourth region 114 is disposed in the first region 111 and is disposed in contact with or adjacent to the 2D material layer 121. In other words, the fourth region 114 may be disposed at the surface of the first region 111. The doping type of the fourth region 114 may be the same as the doping type of the first region 111, and may be highly doped, and the doping concentration may be higher than that of the first region 111. In this case, the fourth region 114 is also referred to as an N-top layer. Those skilled in the art will readily understand that the fourth region 114 may function as a (third) RESURF structure.

The active region may also include a fifth region 115. In some embodiments, the fifth region 115 is disposed in the first region 111 and spaced apart from the 2D material layer 121. The doping type (P-type) of the fifth region 115 is opposite to that of the first region 111. Here, the fifth region 115 is disposed below and adjacent to the fourth region 114. The fifth region 115 is often referred to as a P buried layer. Those skilled in the art will readily appreciate that the fifth region 115 may also function as a (fourth) RESURF structure. Here, the fifth region 115, which is a P buried layer, may be used for charge compensation of the fourth region 114 (N-top layer), so that the fourth region 114 may be more heavily doped to achieve a lower on-resistance Ron in an on-state and complete depletion in an off-state, increasing breakdown voltage.

Although in the embodiment shown in fig. 1, both the fourth region 114 (third RESURF structure) and the fifth region 115 (fourth RESURF structure) are employed, in some other embodiments, the fifth region 115 may be omitted, or both the fourth and fifth regions may be omitted.

In addition, as shown in fig. 1, the gate structure further includes a gate dielectric layer 141, the gate dielectric layer 141 being disposed between at least a portion of the gate layer and the active region. Here, the gate dielectric layer 141 is shown formed over a portion of the first region 111 and a portion of the second region 112 of the active region. However, the present disclosure is not limited thereto. The configuration of the gate dielectric may also vary depending on the method of preparing the gate dielectric layer. For example, in some embodiments, gate dielectric layer 141 may also extend onto first dielectric layer 131 as gate layer 143, as shown in fig. 1A (described in more detail later).

In some embodiments, as shown in fig. 1, the gate layer 143 may include a portion over the gate dielectric layer 141 and a portion over the first insulating layer 131, such that the 2D material layer partially overlaps (e.g., in a normal direction) with a portion of the gate layer. However, the present disclosure is not limited thereto as long as the gate layer is adjacent to the 2D material layer such that a potential of the gate layer can act on the 2D material layer such that its conductive property is changed. Further, it will be readily understood by those skilled in the art that the gate layer 143 overlapping the first insulating layer 131 (which may correspond to a field insulating layer) may be a (second) RESURF structure. That is, the overlapping portion of the gate layer 143 and the first insulating layer 131 serves as a field plate (field plate).

As shown in fig. 1, the 2D material layer 121 extends between the gate dielectric layer 141 and the third region 113 over a first portion of the first region 112 and is spaced apart from the gate dielectric layer 141 and the third region 113, respectively.

The active region may further include sixth and seventh regions 116 and 117 disposed in the second region 112, the sixth and seventh regions 116 and 117 having doping types opposite to each other. Alternatively, the doping type of the sixth region 116 may be the same as that of the first region 111, and the doping type of the seventh region may be opposite to that of the first region 111. The sixth and seventh regions 116 and 117 may serve as sources of the LDMOS.

The active region may further include an eighth region 118 disposed in or under the second region 112 and having the same doping type as the second region 112.

In some embodiments, the semiconductor device may further include an additional second insulating layer 105. The second insulating layer 105 may be formed in the same material layer with the first insulating layer 131 in the same process step to simplify the manufacturing process flow. Alternatively, the second insulating layer 105 may be formed in a different step from the first insulating layer 131 to optimize the thickness each.

In some embodiments, the semiconductor device may further include an electrode 145, the electrode 145 being disposed over the first insulating layer 131 and partially overlapping the 2D material layer 121. The electrode 145 may be formed in the same layer as the gate layer. The electrode 145 may be electrically connected to an electrode (e.g., drain electrode, not shown in fig. 1) connected to, for example, the third region 113, thereby carrying the same low potential as the drain electrode. In this manner, when device 100 is in the Off state, portions of the 2D material layer adjacent electrode 145 and/or the drain electrode (e.g., 209 of fig. 4J) may be better maintained in an insulating state, such that the breakdown field may be ensured or further improved.

Fig. 1A shows a schematic cross-sectional view of a semiconductor device 100A according to another embodiment of the present disclosure. In fig. 1A, the same reference numerals are used to designate the same or similar components or elements. The structural configuration of the semiconductor device 100A is substantially the same as that of the semiconductor device 100 shown in fig. 1, except that the two gate dielectric layers 141 are configured differently.

The gate dielectric layer 141 in fig. 1A is shown formed under the gate layer 143 (and electrode 145). For example, gate dielectric layer 141 may be formed by, for example, deposition (and other steps, such as subsequent etching), or by thermal oxidation plus deposition (and other steps, such as subsequent etching). And the gate dielectric layer 141 shown in fig. 1A may be formed by, for example, thermal oxidation (as well as other steps, such as subsequent etching).

Other components of the semiconductor device 100A and their configurations are substantially the same as the corresponding components of the semiconductor device 100 shown in fig. 1, and the above description with respect to fig. 1 may be equally or adaptively applied thereto. Therefore, a repetitive description thereof is omitted here.

Fig. 1B shows a schematic cross-sectional view of a semiconductor device 100B according to yet another embodiment of the present disclosure. In fig. 1B, the same reference numerals are used to designate the same or similar components or elements. The structural configuration of the semiconductor device 100B is substantially the same as that of the semiconductor device 100A shown in fig. 1A, except that the first insulating layers 131 of the two are configured differently.

The first insulating layer 131 in fig. 1B is shown formed over the RESURF structure (layer 121 and optional layer 123) without covering the sides of the RESURF structure. Here, the gate dielectric layer 141 is formed to be in direct contact with a side of the RESURF structure.

Other components of the semiconductor device 100B and their configurations are substantially the same as the corresponding components of the semiconductor device 100 shown in fig. 1 or 1A, and the descriptions above with respect to fig. 1 or 1A may be equally or adaptively applied thereto. Therefore, a repetitive description thereof is omitted here.

Fig. 1C shows a schematic cross-sectional view of a semiconductor device 100C according to yet another embodiment of the present disclosure. In fig. 1C, the same reference numerals are used to designate the same or similar components or elements. The structural configuration of the semiconductor device 100C is substantially the same as that of the semiconductor device shown in fig. 1A and 1B, except that the aforementioned first insulating layer 131 is not formed in the semiconductor device 100C.

Also here, the gate dielectric layer 141 is formed to be in direct contact with the side of the RESURF structure and partially covers over the interface layer 123.

Also shown in fig. 1C is an additional insulating layer 107 that overlies the substrate. An insulating layer 107 overlies the gate structure and RESURF structure and may be formed with openings to expose portions of the surface of the active region for forming contacts (e.g., plugs of tungsten or copper) or electrodes. The insulating layer 107 may be, for example, an interlayer dielectric (ILD).

Other components of the semiconductor device 100C and their configurations are substantially the same as the corresponding components of the semiconductor device 100 shown in fig. 1 or 1A, and the descriptions above with respect to fig. 1 or 1A may be equally or adaptively applied thereto. Therefore, a repetitive description thereof is omitted here.

Fig. 2 shows a schematic cross-sectional view of a semiconductor device 200 according to another embodiment of the present disclosure. In fig. 2, the same reference numerals are used to designate the same or similar components or elements, and thus the descriptions of the same or similar components or elements as previously described may be equally or adaptively applied thereto, and the description will not be repeated.

The semiconductor device 200 differs from the previously described devices 100 and 100A primarily in the insulating layer 105, and thus in some of the differences. In this embodiment, the insulating layer 105 may correspond to the field oxide layer in the LDMOS of the prior art, but the field oxide over the first portion of the first region 111 is removed to form an opening, thereby exposing the surface of the first portion of the first region 111. A RESURF structure comprising a layer 121 of 2D material (and optionally an interface layer 123) is formed on said first portion of the first region 111 and a first insulating layer 131 is formed overlying the RESURF structure. Here, the first insulating layer 131 is shown to fill in the openings in the field oxide layer 105 and to be substantially flush with the field oxide layer 105; it should be understood that this is by way of example only and not by way of limitation. The first insulating layer 131 and the insulating layer 105 may each be manufactured by different methods and optimized thicknesses.

It is further noted that embodiments of the present application also contemplate that the surface of the first portion of the first region 111 (i.e., the portion on which the RESURF structure is formed) is disposed lower than the surface of at least some other portion of the active region. For example, the surface of the first portion is lower than the surface of a portion (second portion) of the first region 111 under the gate dielectric layer 121, or lower than the surface of a portion of the second region 112 under the gate dielectric layer 121. In this way, the breakdown field (BV) and/or on-resistance (Ron) of the device may be further improved.

It should also be understood that the insulating layer 105 in this embodiment is merely exemplary as field oxide, and the locations of the openings shown are also exemplary; those skilled in the art can readily apply the teachings and principles of this disclosure as appropriate to the actual needs in light of this disclosure. For example, in some embodiments, the insulating layer 105 may be any suitable insulating layer or sacrificial insulating layer, so long as openings may be formed therein for forming the RESURF structure of the present application comprising a 2D material layer on a substrate. The sacrificial layer is removed in a subsequent process. In some embodiments, for example, the insulating layer 105 may be a sacrificial layer comprising a silicon oxide layer and a silicon nitride layer, which may have an opening to expose a portion of the active region for forming a 2D material layer thereon; and the insulating layer 105 may also act as an etch stop layer for etching the 2D material layer.

Fig. 3 shows a schematic cross-sectional view of a semiconductor device 300 according to yet another embodiment of the present disclosure. In fig. 3, the same reference numerals are used to designate the same or similar components or elements, and thus the descriptions of the same or similar components or elements previously described herein may be equally or adaptively applied thereto, and the description thereof will not be repeated.

The semiconductor device 300 differs from the device 200 in that the active region between the field oxide 105 on the left and right sides is substantially planar. Thus, what has been described above with respect to fig. 1 and 1A can be readily adapted to this embodiment. It should also be appreciated that although in the embodiment shown in fig. 3, field oxide 105 may be used to isolate devices from one another, in other embodiments, other ways of isolating devices from one another may be used, such as by trench isolation (STI), for example (not shown).

Fig. 4A-4J illustrate schematic cross-sectional views in partial process steps in the fabrication of a semiconductor device according to one embodiment of the present disclosure. Fig. 6 illustrates a flow chart of a method 600 of manufacturing a semiconductor device according to some embodiments of the present disclosure. The following is a description of FIGS. 4A-4J and 6.

First, in step S601, a substrate is provided as shown in fig. 4A. The substrate may be, for example, the substrate 101 in any of the embodiments described above. As previously described, the substrate 101 may include an active region.

In step S603, the first region 111 is formed in the active region, as shown in fig. 4B. As an example, the first region 111 may be, for example, an N-well. In step S605, the second region 112 is formed in the active region, as shown in fig. 4B. For example, the second region 112 may be a P-well. The formation of fourth region 114 and/or the formation of fifth region 115 is also shown in fig. 4B. In addition, although not shown in fig. 4A and 4B (and subsequent figures), a device isolation structure, such as an STI (see fig. 1) or a field oxide isolation structure (see fig. 2 and 3), may be formed in the substrate 101.

In some embodiments, a dielectric layer (e.g., a silicon oxide layer, or a silicon oxide and silicon nitride layer, or a silicon oxynitride layer) may be formed on the substrate, a patterned photoresist mask is formed over the dielectric layer, and ion implantation is performed using the mask to form doped regions as the first regions. The photoresist mask may then be removed and the dielectric layer removed at the appropriate time.

The regions of the active region of the present application may also be formed by ion implantation or other doping methods, similarly using a photoresist mask or other hard mask. After the formation of the corresponding regions, these masks may be removed.

It will be appreciated that in practice, the method may further comprise the step of forming a plurality of doped regions (e.g. some other regions) as required. And the steps of forming the first region, the second region, and/or the other regions may be performed in a different order, in a different method. The present disclosure is not limited in this regard. Only steps closely related to the technical idea of the embodiment of the present application are focused on here and are described by way of illustration.

In step S407, a RESURF structure is formed over the first portion of the first region 111, as shown in fig. 4C and 4D. The RESURF structure includes at least a 2D material layer 121,2D material layer 121 comprising a 2D material formed over a first portion of the first region 111. As previously mentioned, the 2D material may include (but is not limited to) any of the following: sulfides of Mo, sulfides of Sn, sulfides of Se, compounds of W and Se, and graphene.

As an example, as shown in fig. 4C, forming the RESURF structure may include: in step S6071, an initial 2D material layer 201 is formed on the substrate by, for example, sputtering, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), transfer process, or any other suitable process. Optionally, forming the RESURF structure may include: in step S6073, the interface material layer 203 is formed on the initial 2D material layer 201 using an ALD, CVD, PVD or the like process.

As an example, the 2D material layer 121 may include a sulfide of molybdenum (Mo) (e.g., moS ₂ ). Forming the RESURF structure may further include: optionally, in step S6075, the initial 2D material layer 201 is subjected to a sulfur (S) -containing atmosphere through the interface material layer 203And (5) annealing treatment. For example, rapid thermal annealing may be performed under a sulfur (S) atmosphere at a temperature of 400 ℃ to 700 ℃ for 30 seconds. Fig. 5 shows a schematic diagram of an annealing process of a 2D material layer under a sulfur atmosphere according to one embodiment of the present disclosure. As shown in FIG. 5, by the annealing treatment under the sulfur atmosphere, S species (atoms or ions) can be generated by, for example, al ₂ O ₃ Or HfO ₂ Is to MoS ₂ The layer is sulfur-compensated to reduce defects, improve crystallinity, and improve MoS ₂ Hall effect mobility of the layers.

Forming the RESURF structure may further include: in step S6077, a patterning process is performed such that portions of the initial 2D material layer 201 and the interface material layer 203 formed over the first portion of the first region 111 are left, thereby forming a RESURF structure.

It should be noted that although the interface material layer 203 and the interface layer 123 formed thereof are shown in fig. 4C and 4D, it should be understood that the interface material layer 203 and the interface layer 123 are preferred, and in some embodiments, the formation of the interface material layer 203 and the interface layer 123 may be omitted.

As another example, forming the RESURF structure may include: step S6071, forming an initial 2D material layer (e.g., a sulfide layer of Mo) 201 on the substrate by, for example, sputtering, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), transfer process, or any other suitable process; and, at step 6077, a patterning process is performed such that a portion of the initial 2D material layer formed over the first portion of the first region 111 is left, thereby forming a 2D material layer 121.

As an example, forming the initial 2D material layer may include: forming an oxide layer of Mo (e.g., moO 3) on a substrate; the oxide layer of Mo is subjected to a vulcanization treatment in a sulfur (S) atmosphere, thereby forming a sulfide layer of Mo.

As an example, forming the initial 2D material layer may include: forming an oxide layer of tungsten (W) on a substrate (e.g., WO 3); the oxide layer of W is subjected to a selenization treatment in a selenium (Se) atmosphere, thereby forming a selenide layer of W.

As an example, metal organic and organic compound components, such as molybdenum hexacarbonyl (molybdenum hexacarbonyl) Mo (CO) 6 and diethyl sulfide (diethyl sulfide) C4H10S, may be used to form MoS by CVD or PVD processes ₂ A layer.

As an example, a large area of single and few-layer MoS can be grown using the reaction of a metal halide MoCl5 precursor with S ₂ And (3) a film.

In other embodiments, the 2D material may include graphene. As an example, a graphene layer may be formed at a first portion of the first region 111 by Chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE) growth using, for example, an ethylene (C2H 4) precursor.

As an example, the patterning step may include: a mask, such as a photoresist mask or a hard mask, is formed over the target layer, and the target layer is etched using a corresponding etchant. For example, conventional fluorine (F) or chlorine (Cl) containing plasma etches may be utilized to etch the 2D material layer and/or the interface layer. Those skilled in the art will appreciate that the corresponding etchant may be selected for different materials to be etched.

The method 600 further comprises: optionally, in step S609, an insulating layer (e.g., the aforementioned first insulating layer 131) is formed. The insulating layer may be formed to cover at least the RESURF structure as shown in fig. 1, 1A, 1B, or 4E and 4F. As an example, as shown in fig. 4E, an insulating material layer 205 is formed on the substrate on which the RESURF structure is formed. The insulating material layer 205 may be, for example, silicon oxide or BSG or BPSG, or the like, or any combination thereof. Next, as shown in fig. 4F, the insulating material layer 205 is patterned, thereby forming the first insulating layer 131. A first insulating layer 131 overlies the RESURF structure.

In addition, it should be noted that while other portions of layer 205 are shown removed in fig. 4F, it should be understood that some other portions of layer 205 may be retained if desired.

The method 600 further comprises: in step S611, a gate structure is formed, as shown in fig. 4G. The gate structure may comprise a gate dielectric layer and a gate layer, for example, according to any of the embodiments described above. Here, the gate dielectric layer 141 covers over the active region (a portion (second portion) of the first region and a portion of the second region 112 will be formed later), and the gate layer 143 includes a first portion over the gate dielectric layer 141 and a second portion adjacent to the 2D material layer 121. The first insulating layer 131 is interposed between the second portion of the gate layer 143 and the 2D material layer 121. The properties of at least the portion of the 2D material layer 121 adjacent to the gate layer 143 change with the potential of the gate layer 143. In some embodiments, the second portion of the gate layer may include a portion that overlaps the 2D material layer 121 in a top view, as shown in fig. 4G.

As an example, forming the gate structure may include: forming a gate dielectric material layer and a gate material layer on a substrate at step S6111; in step S6113, the gate dielectric material layer and the gate material layer are patterned, thereby forming the gate dielectric layer and the gate layer (and optionally the electrode 145). Thereafter, in step S6115, the spacer 207 for the gate is formed. The gate layer, gate dielectric layer and spacers may be readily prepared by those skilled in the art using materials and processes known in the art, and thus will not be described in further detail.

In some embodiments, the method 600 further comprises: optionally, at step 613, one or more other regions (e.g., doped regions) are formed in the active region. For example, as shown in fig. 4H, the aforementioned third region 113, sixth region 1176, and seventh region 117 are formed in the active region, respectively. In alternative embodiments, more or fewer doped regions may be formed. It will be appreciated that the steps of forming these regions separately in the active region may be performed in separate steps, or some of the steps may be performed in a single step, or may be performed at any suitable timing in the flow as desired; and is not limited to the manner shown in fig. 6.

Optionally, at step S615, an additional insulating layer 209 is formed on the substrate, as shown in fig. 4I. The insulating layer 209 may be an interlayer Insulating Layer (ILD) that may be formed of any suitable insulating material such as, but not limited to, silicon oxide, BSG, BPG, and the like, or any combination thereof. The insulating layer 209 may have a plurality of openings for forming contacts to the active layer.

In step S617, a contact and electrode layer is formed, as shown in fig. 4J. As an example, a drain electrode 211 to a drain (e.g., the third region 113) and a source electrode 213 to a source (e.g., the sixth and seventh regions 116 and 117) are shown. Those skilled in the art will readily appreciate that silicide to the active region (source or drain region) may be formed to reduce contact resistance. In some implementations, a plug (e.g., a tungsten (W) plug or a copper (Cu) plug) may also be formed first to fill the opening in the insulating layer 209 (as shown in fig. 4I); after which an electrode layer is formed. Since this is not the focus of the present application, it is considered herein collectively as an electrode.

In addition, optionally, according to various embodiments, an insulating layer (e.g., without limitation, insulating layer 105 shown in fig. 2 and 3) may be formed on the substrate, which may include openings to expose at least a first portion of first region 111 and at least a portion of second region 112, at step S606.

As such, a semiconductor device according to one embodiment of the present disclosure is prepared. The semiconductor device may be a Lateral Diffused MOS (LDMOS) device. The first portion of the first region 111 may operate as or as part of a diffusion drift region.

Fig. 7A-7F show schematic cross-sectional views in partial process steps in the fabrication of a semiconductor device according to another embodiment of the present disclosure.

As shown in fig. 7A, an initial 2D material layer 701 for forming RESURF structures is formed on a substrate 101. Optionally, an interface material layer 703 may also be formed, as well as an insulating material layer 705. One or more of the aforementioned regions in the active region may be formed in the substrate 101. As an example, the first region 111, the second region 112, the fourth region 114, the fifth region 115, and the eighth region 118 are shown in the figure. However, it should be understood that one or more of these regions may be formed in a preceding step, or in a subsequent step, or may be omitted.

Thereafter, as shown in fig. 7B, a patterning process is performed such that the initial 2D material layer 701 and portions of the interface material layer 703 and the insulating material layer 705 (if any) formed over the first portion of the first region 111 are left, thereby forming a RESURF structure. As previously described, the RESURF structure may include a 2D material layer 121, an optional interfacial layer 123 thereon, and a first insulating layer 131.

Thereafter, as shown in fig. 7C, a gate structure is formed. The gate structure may include a gate dielectric layer 141 and a gate layer 143. Here, a gate dielectric layer 141 overlies the active region (a portion of the first region (second portion) and a portion of the second region 112 that will be formed later) and covers the sides of the layer 121 and layers 123 and 131, if any. The gate layer 143 includes a first portion over the gate dielectric layer 141 and a second portion adjacent to the 2D material layer 121. A gate dielectric layer 141 is interposed between the gate layer 143 and the 2D material layer 121. Also shown in fig. 7C are spacers 707 for the gate.

Optionally, as shown in fig. 7D, one or more other regions (e.g., doped regions) are formed in the active region. For example, the aforementioned third region 113, sixth region 1176, and seventh region 117 are formed in the active region, respectively. In alternative embodiments, more or fewer doped regions may be formed. It will be appreciated that the steps of forming these regions separately in the active region may be performed in separate steps, or some of the steps may be performed in a single step, or may be performed at any suitable timing in the flow, as desired.

Thereafter, as shown in fig. 7E, an additional insulating layer 709 is formed over the substrate. The insulating layer 709 may be an interlayer Insulating Layer (ILD) that may be formed of any suitable insulating material such as, but not limited to, silicon oxide, BSG, BPG, etc., or any combination thereof. The insulating layer 709 may have a plurality of openings for forming contacts to the active layer.

After that, as shown in fig. 7F, a contact and electrode layer 713 is formed.

As such, a semiconductor device according to another embodiment of the present disclosure is prepared. As previously described, the semiconductor device may be a Lateral Diffused MOS (LDMOS) device. The first portion of the first region 111 may operate as or as part of a diffusion drift region. It should be understood that what has been described above with respect to other figures or embodiments may be equally or adaptively applied to the embodiments shown in fig. 7A-7F, and detailed descriptions are not repeated here.

According to the LDMOS device disclosed by the embodiment of the invention, in the on state:

the gate may be biased at a high voltage (e.g., 10v-20 v), the drain may be biased at a low voltage (e.g.,<1 v). Thus, the LDMOS device is turned on. The 2D material layer has conductivity and low resistance due to the positive bias of the gate. 2D material layer (e.g. MoS ₂ Layer) is higher below the gate or near the gate edge and is lower near the drain. The electron flow may flow not only through the usual channels (through the first region 111 (e.g., N-well) and/or the fourth region 114 (e.g., N-top layer, if any) but also through the 2D material layer, thereby resulting in a lower on-resistance Ron.

According to the LDMOS device disclosed by the embodiment of the application, in the off state:

the drain may be at a high voltage (typically >20v, or higher, such as tens of volts (v) or higher, e.g. 100-700 v) for device use, and the gate may be at a low voltage (typically 0v or a suitable negative bias, e.g. -5 v). Thus, the 2D material layer is non-conductive (or insulating), having a high breakdown voltage (higher than that of silicon or bulk silicon). While the surface of the first region (N-well) or N-top layer (if any) is also more depleted, the overall breakdown voltage BV of the device is further enhanced.

According to embodiments of the present disclosure, 2D material (e.g., moS ₂ Etc.) as the new RESURF structure proposed by the present application, excellent performance in mobility, breakdown field and thermal conduction can be achieved. Thus a lower on-resistance Ron can be achieved with superior electron mobility of the 2D material layer (which may be several times that of silicon) and a higher click can be achieved with the 2D material layer A field-through (breakdown voltage), which may be several times the breakdown field of silicon, and better thermal conductivity. Further, at the same rated power level, the device size may be further reduced. While the better thermal conductivity may also enable simple cooling of the power package. The novel RESURF structure provided by the application can also be applied to SiC power ICs, and can realize excellent performance and high reliability.

Preferably, the LDMOS device according to an embodiment of the present disclosure is configured as an N-type LDMOS device; however, the present disclosure is not limited thereto and may be configured as a P-type LDMOS device. When turned on, the mobility of the carrier (electron) of the N-type LDMOS device is several times better than that of the carrier (hole) of the P-type LDMOS device, and therefore, correspondingly, the on-resistance Ron of the PLDMOS is several times higher than that of the NLDMOS.

The present disclosure also contemplates the following items, aspects, or embodiments:

item 1. A semiconductor device includes: a substrate comprising an active region, the active region comprising at least a first region; a RESURF structure disposed over a first portion of the first region, the RESURF structure including a 2D material layer including a 2D material; a gate structure comprising a gate layer comprising at least a portion adjacent to the 2D material layer, and the portion of the gate layer is isolated from the 2D material layer by an isolation insulating layer, wherein a property of at least the portion of the 2D material layer adjacent to the gate layer varies with a potential of the gate layer.

The semiconductor device according to item 1, wherein: the 2D material includes any one of the following: sulfides of Mo, sulfides of Sn, sulfides of Se, compounds of W and Se, and graphene.

The semiconductor device according to item 1, wherein: the isolation insulating layer comprises a first insulating layer at least covering the RESURF structure, a portion of the first insulating layer being interposed between the portion of the gate layer and the 2D material layer; the 2D material layer partially overlaps a portion of the gate layer in a normal direction.

The semiconductor device according to item 3, wherein: the gate structure further includes a gate dielectric layer disposed at least between at least a portion of the gate layer and the active region; the gate layer includes a portion over the gate dielectric layer and a portion over the first insulating layer.

Item 5. The semiconductor device of item 1, wherein: the gate structure further includes a gate dielectric layer disposed between the portion of the gate layer and the 2D material layer, and a portion disposed between another portion of the gate layer and the active region; the isolation insulating layer includes the gate dielectric layer; the 2D material layer partially overlaps a portion of the gate layer in a normal direction across the gate dielectric layer.

The semiconductor device according to item 3, wherein: the gate structure further includes a gate dielectric layer disposed between the portion of the gate layer and the 2D material layer, and a portion disposed between another portion of the gate layer and the active region; the isolation insulating layer includes the gate dielectric layer; the 2D material layer partially overlaps a portion of the gate layer in a normal direction across the gate dielectric layer.

Item 7. The semiconductor device of item 1, the RESURF structure further comprising: an interfacial layer disposed over the 2D material layer.

The semiconductor device according to item 1, wherein: the 2D material includes any one of the following: sulfide of Mo, sulfide of Sn, sulfide of Se, the RESURF structure further comprising: and an interface layer disposed over the 2D material layer and between the 2D material layer and the first insulating layer, the interface layer being capable of being used for a vulcanization treatment of the 2D material layer.

Item 9. The semiconductor device of any one of items 1-8, wherein: the semiconductor device is a lateral diffusion MOS device; the first portion of the first region operates as or as part of a diffusion drift region; the active region further includes a second region and a third region, wherein the first and second regions are laterally adjacent to each other and the third region and the first region are laterally adjacent to each other in a top view; the gate dielectric layer is formed over at least a portion of the first region and a portion of the second region; the 2D material layer extends between the gate dielectric layer and the third region over a first portion of the first region and is spaced apart from the gate dielectric layer and the third region, respectively; the 2D material layer is between the second region and the third region when seen in a top view.

The semiconductor device of item 9, wherein one or more of the following: the surface of the first portion of the first region is lower than the surface of the portion of the second region; the isolation insulating layer further comprises an additional insulating layer.

Item 11. The semiconductor device of item 9, wherein: the first region is one of an N-type region and a P-type region, the second region is the other of the N-type region and the P-type region, and the third region has the same conductivity type as the first region and has a higher doping concentration than the first region; the active region further comprises one or more of the following: i) A fourth region disposed in the first region and in contact with or adjacent to the 2D material layer, the fourth region having a doping type that is the same as a doping type of the first region; ii) a fifth region disposed in the first region and spaced apart from the 2D material layer, the fifth region having a doping type opposite to the doping type of the first region; iii) A sixth region and a seventh region having opposite doping types, the sixth region and the seventh region being disposed in the second region, and the doping type of the sixth region being the same as that of the first region and the doping type of the seventh region being opposite to that of the first region; iv) an eighth region disposed in or below the second region and having a doping type identical to that of the second region.

The semiconductor device according to item 11, further comprising: a first electrode disposed over the first insulating layer and partially overlapping the 2D material layer; a second electrode electrically connected to the sixth region and the seventh region; and a third electrode electrically connected to the third region and electrically connected to the first electrode.

Item 13. A method of manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate comprises an active region, and a first region is formed in the active region; forming a second region in the active region; forming a RESURF structure over a first portion of the first region, the RESURF structure including at least a 2D material layer comprising a 2D material, the 2D material layer being formed over the first portion of the first region; forming a gate structure comprising a gate dielectric layer and a gate layer, the gate dielectric layer overlying at least a second portion of the first region and a portion of the second region, the gate layer comprising a first portion overlying the gate dielectric layer and a second portion adjacent to the 2D material layer, and the gate layer being formed to be electrically insulated from the 2D material layer, wherein a property of at least a portion of the 2D material layer adjacent to the gate layer varies with a potential of the gate layer.

The method of item 14, further comprising, prior to forming the gate structure, forming a first insulating layer overlying at least the RESURF structure, a portion of the first insulating layer interposed between the gate layer and the 2D material layer; the 2D material layer partially overlaps a portion of the gate layer in a normal direction.

The method of item 15, the method of item 13, further comprising, prior to forming the RESURF structure: a second insulating layer is formed over the substrate, the second insulating layer including a first opening exposing at least a first portion of the first region and at least a portion of the second region.

Item 16. The method of item 13, wherein: the second portion of the gate layer includes: and a portion overlapping with the 2D material layer in a plan view.

Item 17. The method of item 13, wherein: the gate dielectric layer also includes a portion formed between the gate layer and the 2D material layer.

The method of item 14, wherein: the gate dielectric layer also includes a portion formed between the gate layer and the 2D material layer.

The method of any one of items 13 to 18, wherein: the 2D material includes any one of the following: sulfides of Mo, sulfides of Sn, sulfides of Se, compounds of W and Se, and graphene.

Item 20. The method of any one of items 13 to 18, wherein the RESURF structure further comprises an interface layer on the 2D material layer.

The method of any one of items 13 to 18, wherein: the 2D material layer includes a sulfide of molybdenum (Mo); forming the RESURF structure includes: forming a sulfide layer of Mo on a substrate; and performing a patterning process such that a portion of the Mo sulfide layer formed over the first portion of the first region is retained.

The method of any one of items 13 to 18, wherein: the 2D material layer includes a sulfide of molybdenum (Mo), and forming the RESURF structure includes: forming an oxide layer of Mo on a substrate; vulcanizing the oxide layer of Mo in a sulfur (S) -containing atmosphere to form a sulfide layer of Mo; and performing a patterning process such that a portion of the Mo sulfide layer formed over the first portion of the first region is retained.

Item 23. The method of item 20, wherein forming the RESURF structure comprises: forming an initial 2D material layer on a substrate; forming an interface material layer on the initial 2D material layer; and annealing the initial 2D material layer through the interface material layer in a sulfur (S) -containing atmosphere; and performing a patterning process such that portions of the initial 2D material layer and the interface material layer formed over the first portion of the first region are preserved, thereby forming the RESURF structure.

The method of any one of items 13-18, wherein: the semiconductor device is a Lateral Diffusion MOS (LDMOS) device; the first portion of the first region operates as or as part of a diffusion drift region, the method further comprising: forming a third region in the active region, wherein the first and second regions laterally abut each other in a top view, the third region and the first region laterally abut each other; the first region is one of an N-type region and a P-type region, the second region is the other of the N-type region and the P-type region, and the third region has the same conductivity type as the first region and higher doping concentration than the first region; the 2D material layer is between the second region and the third region when seen in a top view.

The method of item 24, further comprising one or more of: i) Forming a fourth region in the active region, the fourth region being disposed in the first region and in contact with or adjacent to the 2D material layer, the fourth region having a doping type that is the same as a doping type of the first region; ii) forming a fifth region in the active region, the fifth region being disposed in the first region and spaced apart from the 2D material layer, the fifth region having a doping type opposite to a doping type of the first region; iii) Forming a sixth region in the active region and a seventh region in the active region, the sixth and seventh regions being disposed in the second region and having a doping type that is the same as the first region and a doping type that is opposite to the first region; iv) forming an eighth region in the active region, the eighth region being formed in or below the second region and having the same doping type as the second region.

Item 26. A semiconductor device comprising the semiconductor device of any one of items 1-12.

Those skilled in the art will recognize that the boundaries between the operations (or steps) described in the above embodiments are merely illustrative. The operations may be combined into a single operation, the single operation may be distributed among additional operations, and the operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in other various embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

It should also be understood that only the main steps of the method embodiments of the present disclosure have been described in the above embodiments to reveal the gist of the invention. Those skilled in the art will readily appreciate that the above-described methods may also include other steps, such as washing, drying, etc., during actual manufacturing; the description thereof is omitted here to avoid obscuring the gist of the invention.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The embodiments disclosed herein may be combined in any desired manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications might be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A semiconductor device, comprising:

a substrate comprising an active region, the active region comprising at least a first region;

a RESURF structure disposed over a first portion of the first region, the RESURF structure including a 2D material layer including a 2D material;

a gate structure including a gate layer including at least a portion adjacent to the 2D material layer, the portion of the gate layer being isolated from the 2D material layer by an isolation insulating layer,

wherein a property of at least a portion of the 2D material layer adjacent to the gate layer varies with a potential of the gate layer.

2. The semiconductor device according to claim 1, wherein:

the 2D material includes any one of the following:

sulfides of Mo, sulfides of Sn, sulfides of Se, compounds of W and Se, and graphene.

3. The semiconductor device according to claim 1, wherein:

the isolation insulating layer comprises a first insulating layer which at least covers the RESURF structure,

a portion of the first insulating layer is interposed between the portion of the gate layer and the 2D material layer;

The 2D material layer partially overlaps a portion of the gate layer in a normal direction.

4. The semiconductor device according to claim 3, wherein:

the gate structure further includes a gate dielectric layer disposed at least between at least a portion of the gate layer and the active region;

the gate layer includes a portion over the gate dielectric layer and a portion over the first insulating layer.

5. The semiconductor device according to claim 1, wherein:

the gate structure further includes a gate dielectric layer,

a gate dielectric layer disposed between the portion of the gate layer and the 2D material layer, and a portion disposed between another portion of the gate layer and the active region;

the isolation insulating layer includes the gate dielectric layer;

the 2D material layer partially overlaps a portion of the gate layer in a normal direction across the gate dielectric layer.

6. The semiconductor device according to claim 3, wherein:

the gate structure further includes a gate dielectric layer,

The isolation insulating layer includes the gate dielectric layer;

7. The semiconductor device of claim 1, wherein the RESURF structure further comprises:

an interfacial layer disposed over the 2D material layer.

8. The semiconductor device according to claim 1, wherein:

the 2D material includes any one of the following: sulfides of Mo, sulfides of Sn, sulfides of Se,

the RESURF structure further includes:

and an interface layer disposed over the 2D material layer and between the 2D material layer and the first insulating layer, the interface layer being capable of being used for a vulcanization treatment of the 2D material layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein:

the semiconductor device is a lateral diffusion MOS device;

the first portion of the first region operates as or as part of a diffusion drift region;

the active region further includes a second region and a third region, wherein the first and second regions are laterally adjacent to each other and the third region and the first region are laterally adjacent to each other in a top view;

The gate dielectric layer is formed over at least a portion of the first region and a portion of the second region;

the 2D material layer extends between the gate dielectric layer and the third region over a first portion of the first region and is spaced apart from the gate dielectric layer and the third region, respectively;

the 2D material layer is between the second region and the third region when seen in a top view.

10. The semiconductor device of claim 9, wherein one or more of the following:

the surface of the first portion of the first region is lower than the surface of the portion of the second region;

the isolation insulating layer further comprises an additional insulating layer.

11. The semiconductor device according to claim 9, wherein:

the first region is one of an N-type region and a P-type region, the second region is the other of the N-type region and the P-type region, and the third region has the same conductivity type as the first region and has a higher doping concentration than the first region;

the active region further comprises one or more of the following:

i) A fourth region disposed in the first region and in contact with or adjacent to the 2D material layer, the fourth region having a doping type that is the same as a doping type of the first region;

ii) a fifth region disposed in the first region and spaced apart from the 2D material layer, the fifth region having a doping type opposite to the doping type of the first region;

iii) A sixth region and a seventh region having opposite doping types, the sixth region and the seventh region being disposed in the second region, and the doping type of the sixth region being the same as that of the first region and the doping type of the seventh region being opposite to that of the first region;

iv) an eighth region disposed in or below the second region and having a doping type identical to that of the second region.

12. The semiconductor device according to claim 11, further comprising:

a first electrode disposed over the first insulating layer and partially overlapping the 2D material layer;

a second electrode electrically connected to the sixth region and the seventh region; and

and a third electrode electrically connected to the third region and electrically connected to the first electrode.

13. A method of manufacturing a semiconductor device, comprising:

providing a substrate, the substrate comprising an active region,

Forming a first region in the active region;

forming a second region in the active region;

forming a RESURF structure over a first portion of the first region, the RESURF structure including at least a 2D material layer comprising a 2D material, the 2D material layer being formed over the first portion of the first region;

forming a gate structure comprising a gate dielectric layer and a gate layer, the gate dielectric layer overlying at least a second portion of the first region and a portion of the second region, the gate layer comprising a first portion overlying the gate dielectric layer and a second portion adjacent to the 2D material layer, and the gate layer being formed to be electrically insulated from the 2D material layer,

14. The method as recited in claim 13, further comprising:

forming a first insulating layer, which at least covers the RESURF structure,

a portion of the first insulating layer is interposed between the gate layer and the 2D material layer;

15. The method of claim 13, further comprising, prior to forming the RESURF structure:

a second insulating layer is formed over the substrate, the second insulating layer including a first opening exposing at least a first portion of the first region and at least a portion of the second region.

16. The method as recited in claim 13, wherein:

the second portion of the gate layer includes: and a portion overlapping with the 2D material layer in a plan view.

17. The method as recited in claim 13, wherein:

the gate dielectric layer also includes a portion formed between the gate layer and the 2D material layer.

18. The method as recited in claim 14, wherein:

19. The method of any one of claims 13 to 18, wherein:

the 2D material includes any one of the following: sulfides of Mo, sulfides of Sn, sulfides of Se, compounds of W and Se, and graphene.

20. The method of any one of claims 13 to 18, wherein the RESURF structure further comprises an interface layer on the 2D material layer.

21. The method of any one of claims 13 to 18, wherein:

the 2D material layer includes a sulfide of molybdenum (Mo);

forming the RESURF structure includes:

forming a sulfide layer of Mo on a substrate; and

a patterning process is performed such that a portion of the Mo sulfide layer formed over the first portion of the first region is retained.

22. The method of any one of claims 13 to 18, wherein:

the 2D material layer comprises a sulfide of molybdenum (Mo),

forming the RESURF structure includes:

forming an oxide layer of Mo on a substrate;

vulcanizing the oxide layer of Mo in a sulfur (S) -containing atmosphere to form a sulfide layer of Mo; and

23. The method of claim 20, wherein forming the RESURF structure comprises:

forming an initial 2D material layer on a substrate;

Forming an interface material layer on the initial 2D material layer; and

annealing the initial 2D material layer through the interfacial material layer in a sulfur (S) -containing atmosphere; and

patterning is performed such that portions of the initial 2D material layer and the interface material layer formed over the first portion of the first region are preserved, thereby forming the RESURF structure.

24. The method of any one of claims 13-18, wherein:

the semiconductor device is a Lateral Diffusion MOS (LDMOS) device;

the first portion of the first region operates as or as part of a diffusion drift region,

the method further comprises the steps of:

forming a third region in the active region, wherein the first and second regions laterally abut each other in a top view, the third region and the first region laterally abut each other;

the first region is one of an N-type region and a P-type region, the second region is the other of the N-type region and the P-type region, and the third region has the same conductivity type as the first region and higher doping concentration than the first region;

25. The method of claim 24, further comprising one or more of:

i) Forming a fourth region in the active region, the fourth region being disposed in the first region and in contact with or adjacent to the 2D material layer, the fourth region having a doping type that is the same as a doping type of the first region;

ii) forming a fifth region in the active region, the fifth region being disposed in the first region and spaced apart from the 2D material layer, the fifth region having a doping type opposite to a doping type of the first region;

iii) Forming a sixth region in the active region and a seventh region in the active region, the sixth and seventh regions being disposed in the second region and having a doping type that is the same as the first region and a doping type that is opposite to the first region;

iv) forming an eighth region in the active region, the eighth region being formed in or below the second region and having the same doping type as the second region.

26. A semiconductor apparatus comprising the semiconductor device according to any one of claims 1 to 12.