CN116721684A - Ternary content addressing memory, addressing method and chip thereof - Google Patents

Ternary content addressing memory, addressing method and chip thereof Download PDF

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CN116721684A
CN116721684A CN202311006281.7A CN202311006281A CN116721684A CN 116721684 A CN116721684 A CN 116721684A CN 202311006281 A CN202311006281 A CN 202311006281A CN 116721684 A CN116721684 A CN 116721684A
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tcam
matching
key
matched
written
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CN116721684B (en
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萧启阳
黄宇明
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Shenzhen Yunbao Intelligent Co ltd
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Shenzhen Yunbao Intelligent Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Storage Device Security (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The application relates to a ternary content addressing memory and an addressing method, medium, device and chip thereof, comprising: the signal processing unit receives the key, the key length and the external address, generates f sub-keys according to the key, the key length and the TCAM unit bit width, determines a TACM unit for storing the f sub-keys and a corresponding internal address according to the external address, the key length and the TCAM unit bit width and depth, generates f write signals according to the f sub-keys, the f TCAM units and the corresponding internal address, and sends the f write signals to the f TCAM units respectively; the key length is greater than or equal to the bit width value of the TCAM unit; the TCAM unit receives the writing signal, obtains the corresponding sub key and the internal address, and writes the sub key into the internal address for storage. The application can improve the resource utilization rate of the three-state content addressing memory.

Description

Ternary content addressing memory, addressing method and chip thereof
Technical Field
The application relates to the technical field of memories, in particular to a ternary content addressable memory, an addressing method and a chip thereof.
Background
The ternary content addressable memory (TCAM, ternary content addressable memory) is mainly used for fast searching of entries such as ACL and route. As shown in fig. 1, the ternary content addressable memory includes a plurality of interfaces for inputting different signals, wherein, compare_req is a match enable signal, compare_key [ n:0] is a key to be matched, compare_mask [ n:0] indicates that bits to be masked are matched, for example, only bits [ m:0] are matched, compare_mask [ n:m+1] =0, compare_mask [ m:0] =1; key search of different lengths can be realized through the Compare_mask [ n:0], and Compare_result is the output search result (address).
When the difference of different key lengths is large, resources of the TCAM are wasted; when designing, the bit width of the ternary content addressing memory is required to be equal to the maximum length of the key, and for the unit with smaller key length, a single key occupies the whole bit width of the ternary content addressing memory, and the bit width is wasted; particularly when there are more cells with small key lengths, the utilization of the ternary content addressable memory will be very low.
Disclosure of Invention
The application aims to provide a ternary content addressing memory, an addressing method and a chip thereof, so as to improve the resource utilization rate of the ternary content addressing memory.
In order to achieve the above objective, an embodiment of the present application provides a ternary content addressable memory, as shown in fig. 2, where the ternary content addressable memory includes a signal processing unit, j TCAM storage units, and j is greater than or equal to 2;
the signal processing unit is used for receiving a key to be written, a key length to be written and an external address to be written, generating f sub-keys to be written according to the key to be written, the key length to be written and the TCAM unit bit width, determining a TACM unit for storing the f sub-keys to be written and a corresponding internal address according to the external address, the key length to be written and the TCAM unit bit width and depth, generating f write signals according to the f sub-keys to be written, the f TCAM units and the corresponding internal address, and respectively sending the f write signals to the f TCAM units; f is greater than or equal to 1 and less than or equal to j, and the length of the key to be written is greater than or equal to the bit width value of the TCAM unit;
the TCAM unit is used for receiving the writing signal, obtaining the corresponding sub key to be written and the internal address, and writing the sub key to be written into the internal address for storage.
In some schemes, the signal processing unit is specifically configured to group j TCAM units according to the length of the key to be written and the bit width of the TCAM storage unit, where each group has f TCAM units; and determining TACM units for storing the f sub-keys to be written and depth values thereof according to the depth of each group of TCAM units and the external address, wherein the depth values are used as internal addresses.
In some schemes, the signal processing unit is further configured to receive a key to be matched and a key length to be matched, generate i sub-keys to be matched according to the key length to be matched, TCAM unit bit width and the key to be matched, and group j TCAM units, where each group has i TCAM units; outputting the i sub-keys to be matched to each group of TCAM units; i is 1 or more and j or less;
the TCAM unit is further used for matching the i sub-keys to be matched with the sub-keys stored in the TCAM unit to obtain a matching result, and outputting the matching result to the signal processing unit; when the matching is successful, the matching result comprises matching success information and a matched TCAM unit internal address; when the matching fails, the matching result comprises matching failure information;
the signal processing unit is further configured to receive the matching results output by the j TCAM units, obtain an external address to be output according to the matching results of the j TCAM units, and output the external address to be output.
In some schemes, the bit width of the ternary content addressable memory is M, the depth is K, and the writing and matching of keys with the lengths of N-M are supported; the bit width of the TCAM unit is N, and j is equal to M divided by N; wherein M, K, N is a preset value, and N is smaller than M.
In some schemes, the signal processing unit is specifically configured to determine that the matching is successful if the matching results of the i TCAM units are all successful and the internal addresses of the matched TCAM units are all consistent when the key length to be matched is M, and determine that the matching is failed if the matching results are not the same.
In some schemes, the signal processing unit is specifically configured to, when the key length to be matched is greater than N and less than M, determine that the matching is successful if i matching results in the matching results of the j TCAM units are all successful and the internal addresses of the matched TCAM units are consistent, and convert the internal addresses of the TCAM units that are consistent in matching into corresponding external addresses to be output, otherwise, determine that the matching is failed.
In some embodiments, when the key length to be matched is N, if one of the matching results of the i TCAM units is matching success, the signal processing unit determines that the matching is successful, and converts an internal address of the TCAM unit included in the one matching result into a corresponding external address to be output, otherwise, determines that the matching is failed.
The embodiment of the application also provides an addressing method of the three-state content addressing memory, which comprises the following steps:
the signal processing unit receives a key to be written, a key length to be written and an external address to be written, generates f sub-keys to be written according to the key to be written, the key length to be written and the TCAM unit bit width, determines a TACM unit for storing the f sub-keys to be written and a corresponding internal address according to the external address, the key length to be written and the TCAM unit bit width and depth, generates f write signals according to the f sub-keys to be written, the f TCAM units and the corresponding internal address, and sends the f write signals to the f TCAM units respectively; f is greater than or equal to 1 and less than or equal to j, and the length of the key to be written is greater than or equal to the bit width value of the TCAM unit;
the TCAM unit is used for receiving the writing signal, obtaining the corresponding sub key to be written and the internal address, and writing the sub key to be written into the internal address for storage.
In some aspects, the method specifically includes:
the signal processing unit groups j TCAM units according to the length of the key to be written and the bit width of the TCAM storage unit, and each group has f TCAM units; and determining TACM units for storing the f sub-keys to be written and depth values thereof according to the depth of each group of TCAM units and the external address, wherein the depth values are used as internal addresses.
In some aspects, the method further comprises:
the signal processing unit receives a key to be matched and a key length to be matched, generates i sub-keys to be matched according to the key length to be matched, the TCAM unit bit width and the key to be matched, and groups j TCAM units, wherein each group has i TCAM units; outputting the i sub-keys to be matched to each group of TCAM units; i is 1 or more and j or less;
the TCAM unit matches the i sub-keys to be matched with the sub-keys stored in the TCAM unit to obtain a matching result, and outputs the matching result to the signal processing unit; when the matching is successful, the matching result comprises matching success information and a matched TCAM unit internal address; when the matching fails, the matching result comprises matching failure information;
and the signal processing unit receives the matching results output by the j TCAM units, obtains corresponding external addresses to be output according to the matching results of the j TCAM units, and outputs the external addresses to be output.
In some schemes, the bit width of the ternary content addressable memory is M, the depth is K, and the writing and matching of keys with the lengths of N-M are supported; the bit width of the TCAM unit is N, and j is equal to M divided by N; wherein M, K, N is a preset value, and N is smaller than M.
In some aspects, the signal processing unit receives the matching results output by the j TCAM units, and obtains the external address to be output according to the matching results of the j TCAM units, which specifically includes:
when the length of the key to be matched is M, if the matching results of the i TCAM units are successful and the internal addresses of the matched TCAM units are consistent, the signal processing unit determines that the matching is successful, and determines the internal address of the matched TCAM unit as the external address to be output, otherwise, the signal processing unit determines that the matching is failed.
In some aspects, the signal processing unit receives the matching results output by the j TCAM units, and obtains the external address to be output according to the matching results of the j TCAM units, which specifically includes:
and when the length of the key to be matched is greater than N and less than M, if i matching results in the matching results of the j TCAM units are all successful in matching and the internal addresses of the matched TCAM units are consistent, the signal processing unit determines that the matching is successful, converts the internal addresses of the matched TCAM units into corresponding external addresses to be output, and otherwise, the signal processing unit determines that the matching is failed.
In some aspects, the signal processing unit receives the matching results output by the j TCAM units, and obtains the external address to be output according to the matching results of the j TCAM units, which specifically includes:
when the length of the key to be matched is N, if one of the matching results of the i TCAM units is successful, the signal processing unit determines that the matching is successful, and converts the internal address of the TCAM unit contained in the one matching result into the corresponding external address to be output, otherwise, the signal processing unit determines that the matching is failed.
Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a processor, implements an addressing method as described above.
The embodiment of the application also provides electronic equipment, which comprises a processor, a memory and a computer program stored on the memory and capable of running on the processor, wherein the addressing method is realized when the processor executes the program.
The embodiment of the application also provides a chip comprising the three-state content addressing memory.
The tri-state content addressing memory and the addressing method, medium, equipment and chip thereof provided by the embodiment of the application have the following beneficial effects:
the three-state content addressing memory is designed to form a memory space by j TCAM units, a signal processing unit is arranged, the memory and addressing of keys with different lengths can be supported, the bit width of each TCAM unit is consistent with the length of the key with the minimum length, one internal address of each TCAM unit can store the key with the minimum length, meanwhile, the key with the length greater than the minimum length can be divided into at least two parts, the at least two parts are respectively stored in the at least two TCAM units, and based on the scheme, when the matching of the specific key length (the key length is an integer multiple of the bit width of the TCAM unit) is realized, the resource utilization rate of the three-state content addressing memory can reach 100 percent; meanwhile, the key with the common length (the key length is not an integer multiple of the TCAM unit bit width) is divided into at least two parts and stored in at least two TCAM units, so that the resource utilization rate of the ternary content addressable memory can be greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a ternary content addressable memory according to the background art;
FIG. 2 is a simplified schematic diagram of a ternary content addressable memory in accordance with one embodiment of the application;
FIG. 3 is a schematic diagram of a ternary content addressable memory according to one embodiment of the present application.
Detailed Description
The detailed description of the drawings is intended as an illustration of some embodiments of the application and is not intended to represent the only forms in which the application may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the application.
One embodiment of the application provides a ternary content addressable memory, which comprises a signal processing unit and j TCAM memory units, wherein j is more than or equal to 2;
the signal processing unit is configured to receive a write enable signal, a to-be-written key length, and an external address to be written, determine whether to perform a write operation according to the write enable signal, if yes, generate f to-be-written sub-keys according to the to-be-written key, the to-be-written key length, and a TCAM unit bit width, determine a TACM unit for storing the f to-be-written sub-keys and a corresponding internal address according to the external address, the to-be-written key length, and the TCAM storage unit bit width and depth, and generate f write signals according to the f to-be-written sub-keys, the f TCAM units, and the corresponding internal address, where the write signals include a write enable signal, the to-be-written sub-key, and the corresponding internal address, and send the f write signals to the f TCAM units, respectively; f=the length of a key to be written/the bit width of a TCAM unit, wherein the value of the f=the length of the key to be written/the bit width of the TCAM unit is more than or equal to 1 and less than or equal to j, and the length of the key to be written is more than or equal to the bit width value of the TCAM unit;
the TCAM unit is used for receiving a write signal, obtaining a corresponding sub key to be written and an internal address, and writing the sub key to be written into the internal address for storage; specifically, any TCAM unit, in response to receiving a write signal, parses the write signal to obtain a corresponding sub-key to be written, a write enable signal, and an internal address, and when the write enable signal is 1, writes the sub-key to be written into the internal address to store the sub-key.
As can be seen from the above description, the ternary content addressable memory of the present embodiment is designed to form a storage space by j TCAM units, and is provided with a signal processing unit, so that storage and addressing of keys with different lengths can be supported, the bit width of each TCAM unit is consistent with the length of the key with the minimum length, an internal address of each TCAM unit can store a key with the minimum length, and at the same time, a key with a length greater than the minimum length can be divided into at least two parts, and the at least two parts are respectively stored in at least two TCAM units. Meanwhile, the key with the common length (the key length is not an integer multiple of the TCAM unit bit width, for example, the to-be-written key length is 7 and the TCAM unit bit width is 4) is divided into at least two parts and stored in at least two TCAM units, so that the resource utilization rate of the ternary content addressable memory can be greatly improved.
In some embodiments, the signal processing unit is specifically configured to group j TCAM cells according to the key length to be written and the bit width of the TCAM storage unit, where each group has f TCAM cells; and determining TACM units for storing the f sub-keys to be written and depth values thereof according to the depth of each group of TCAM units and the external address, wherein the depth values are used as internal addresses.
Specifically, the external address refers to a storage address presented to the outside of the ternary content addressable memory, one ternary content addressable memory with depth of K comprises j TCAM units, the depth of each TCAM unit is K, namely each TCAM unit comprises K internal addresses, and a minimum-length key can be stored in a space of each internal address; when the write enabling signal is 1, the signal processing unit splits the to-be-written key into f to-be-written sub-keys according to the length of the to-be-written key and the bit width of the TCAM unit, wherein the number of f depends on the internal addresses of the TCAM unit which the to-be-written key needs to occupy, and the bit width of the TCAM unit is a known fixed value; it should be noted that, during splitting, splitting is performed according to the bit height of key data from low to high; for example, if the length of the key to be written is 8 and the bit width of the TCAM unit is 4, the internal address of 2 TCAM units needs to be occupied (the internal address of one TCAM unit stores the lower sub-key with the length of 4 and the internal address of the other TCAM unit stores the upper sub-key with the length of 4), that is, f is equal to 2; for another example, if the length of the key to be written is 7 and the bit width of the TCAM unit is 4, the internal address of 2 TCAM units is also required to be occupied (the internal address of one TCAM unit stores a low-order partial sub-key with the length of 4 and the internal address of the other TCAM unit stores a high-order partial sub-key with the length of 3), that is, f is equal to 2; further, the internal addresses of the TCAM units have a one-to-one correspondence with the external addresses, so that the internal addresses of f TCAM units for storing the f sub-keys to be written can be determined according to the external addresses, corresponding f write signals are generated according to the f sub-keys to be written, the write enable signals and the internal addresses of the f TCAM units, and the f write signals are respectively sent to the f TCAM units, so that the f TCAM units respectively execute corresponding storage tasks.
In some embodiments, the signal processing unit is further configured to receive a key to be matched and a length of the key to be matched, generate i sub-keys to be matched according to the length of the key to be matched, a TCAM cell bit width, and the key to be matched, and group j TCAM cells, where each group has i TCAM cells; outputting the i sub-keys to be matched to each group of TCAM units; i is 1 or more and j or less;
specifically, the signal processing unit receives a matching enabling signal, a key to be matched and a key length to be matched, which are input by external equipment, when the matching enabling signal is 1, the signal processing unit splits the key to be matched into i sub-keys to be matched according to the key length to be matched and the bit width of a TCAM unit, wherein the number of i depends on the internal addresses of the TCAM units which are required to be occupied by the key to be matched, and the bit width of the TCAM unit is a known fixed value; it should be noted that, during splitting, splitting is performed according to the bit height of key data from low to high; for example, if the length of the key to be matched is 8 and the bit width of the TCAM unit is 4, the internal address of 2 TCAM units needs to be occupied (i.e., i is equal to 2, i.e., one TCAM unit stores the lower sub-key with the internal address of 4 and the other TCAM unit stores the upper sub-key with the internal address of 4); for another example, if the length of the key to be matched is 7 and the bit width of the TCAM unit is 4, the internal address of 2 TCAM units is also required to be occupied (i is equal to 2, i.e., the internal address of one TCAM unit stores the lower sub-key with the length of 4 and the internal address of the other TCAM unit stores the upper sub-key with the length of 3).
The TCAM unit is further used for matching the i sub-keys to be matched with the sub-keys stored in the TCAM unit to obtain a matching result, and outputting the matching result to the signal processing unit; when the matching is successful, the matching result comprises matching success information and a matched TCAM unit internal address; when the matching fails, the matching result comprises matching failure information;
specifically, any TCAM unit is configured to, in response to receiving the i sub-keys to be matched and the match enable signal, match the i sub-keys to be matched with the sub-keys stored in the TCAM unit when the match enable signal is 1, determine whether there is a sub-key in the TCAM unit that is the same as any one of the i sub-keys to be matched, if so, succeed in matching, and output an internal address where the same sub-key is located and match success information to the signal processing unit, if not, fail in matching, and output match failure information to the signal processing unit.
The signal processing unit is further configured to receive the matching results output by the j TCAM units, obtain an external address to be output according to the matching results of the j TCAM units, and output the external address to be output;
specifically, the signal processing unit completes aggregation processing of signals output by different TCAM units, and outputs the aggregated signals to an external device, judges whether the matching is successful according to the matching results of the j TCAM units, and if the matching is successful, obtains an external address according to an internal address in the matching results output by the j TCAM units, and outputs the external address to the external device.
In some embodiments, the ternary content addressable memory has a bit width of M, a depth of K, and supports writing and matching of keys with lengths of N-M; the bit width of the TCAM unit is N, and j is equal to M divided by N; wherein M, K, N is a preset value, and N is smaller than M.
In some embodiments, the signal processing unit is specifically configured to determine that the matching is successful if the matching results of the i TCAM units are all successful and the internal addresses of the matched TCAM units are all consistent when the key length to be matched is M, and determine that the matching is failed if the matching results are not the same, and determine that the internal address of the matched TCAM unit is the external address to be output.
As shown in fig. 3, the following describes the embodiment in detail, and the total specification of the ternary content addressable memory is width m=48, depth k=8, the supported key length is 12-48, the minimum key length is 12, and the maximum key length is 48; therefore, in this example, the number of TCAM units is M/n=4, the number of 4 TCAM units is TCAM0, TCAM1, TCAM2, TCAM3, the TCAM unit specification is width n=12, and depth k=8; when the length of the key matched with the storage is 48, the storage space of the three-state content addressing memory is 8, and the corresponding external address is 0-7; the procedure for writing key a of length 48 to address 5 and then performing key a matching is as follows:
step1.1, interface incoming write signal, comprising: write enable signal=1, key=a to be written, key length to be written=48, external address=5;
step1.2, the signal processing unit splits the key according to the length 12 into 4 sub-keys to be written, namely A [47:36], A [35:24], A [23:12] and A [11:0], and sends the 4 sub-keys to be written to TCAM0, TCAM1, TCAM2 and TCAM3, wherein the writing internal addresses of TCAM0, TCAM1, TCAM2 and TCAM3 are all 5;
step1.3, each TCAM unit writes the received sub key to be written into the address 5;
step1.4, interface incoming match signal, comprising: match enable signal=1, key to be matched=a, key length to be matched=48;
step1.5, the signal processing unit splits the key A to be matched into 4 sub-keys to be matched according to the length 12, namely A [47:36], A [35:24], A [23:12] and A [11:0], and sends the 4 sub-keys to be matched to TCAM0, TCAM1, TCAM2 and TCAM3 for matching;
step1.6, TCAM0, TCAM1, TCAM2 and TCAM3 return the matching result to the signal processing unit, the signal processing unit judges whether the matching result of each TCAM unit is consistent, if so, the matching result is internal address 5, so the matching result of key A is internal address 5, and the external address is equal to internal address 5;
step1.7, output external address 5 to external device.
In some embodiments, the signal processing unit is specifically configured to, when the key length to be matched is greater than N and less than M, determine that the matching is successful if i matching results in the matching results of the j TCAM units are all successful and the internal addresses of the matched TCAM units are consistent, and convert the internal addresses of the TCAM units that are consistent in matching into corresponding external addresses to be output, otherwise, determine that the matching is failed.
As shown in fig. 3, the following describes the embodiment in detail, and the total specification of the ternary content addressable memory is width m=48, depth k=8, the supported key length is 12-48, the minimum key length is 12, and the maximum key length is 48; therefore, in this example, the number of TCAM units is M/n=4, the number of 4 TCAM units is TCAM0, TCAM1, TCAM2, TCAM3, the TCAM unit specification is width n=12, and depth k=8; when the length of the key matched with the storage is 24, the storage space of the three-state content addressing memory is 16, and the corresponding external address is 0-15; the flow of writing a length 24 key b to address 12 and then performing a key b match is as follows:
step2.1, interface incoming write signal, comprising: write enable signal=1, key=b to be written, key length to be written=24, external address=12;
step2.2, the signal processing unit splits the key B according to the length 12 into 2 keys to be written, namely B23:12 and B11:0, because the external address is 12, the number of keys with the length of 24 being TCAM0+TCAM1 can be stored is 8, the external address corresponds to 0-7, the number of keys with the length of 24 being TCAM2+TCAM3 can be stored is 8, the external address corresponds to 8-15, the signal processing unit respectively sends two molecular keys to TCAM2 and TCAM3, and the internal address corresponding to TCAM2 and TCAM3 is 4;
step2.3, TCAM2, TCAM3 writes the received child key into the internal address 4;
step2.4, interface incoming match signal, comprising: match enable signal=1, key to be matched=b, key length to be matched=24;
step2.5, the signal processing unit splits the key B according to the length 12 into 2 sub-keys to be matched, namely B23:12 and B11:0, and sends the 2 sub-keys to be matched to TCAM0, TCAM1, TCAM2 and TCAM3 for matching;
step2.6, TCAM0, TCAM1, TCAM2, TCAM3 return match result to the signal processing unit, the signal processing unit judges whether TCAM0 matches result and TCAM1 match result match and match TCAM unit internal address match, TCAM2 matches result and match TCAM unit internal address match, wherein, a group of match success and match TCAM unit internal address match is match success, B [23:12], B [11:0] store in TCAM2, TCAM3 internal address 4 respectively, therefore, here TCAM2 and TCAM3 match result are match success and match TCAM unit internal address bit 4, because TCAM2+ TCAM3 external address is 8-15, so finally output external address is 12.
step2.7, output external address 12.
In some embodiments, the signal processing unit is specifically configured to, when the key length to be matched is N, determine that the matching is successful if one of the matching results of the i TCAM units is successful, and convert an internal address of the TCAM unit included in the one matching result into a corresponding external address to be output, otherwise determine that the matching is failed.
As shown in fig. 3, the following describes the embodiment in detail, and the total specification of the ternary content addressable memory is width m=48, depth k=8, the supported key length is 12-48, the minimum key length is 12, and the maximum key length is 48; therefore, in this example, the number of TCAM units is M/n=4, the number of 4 TCAM units is TCAM0, TCAM1, TCAM2, TCAM3, the TCAM unit specification is width n=12, and depth k=8; when the length of the key matched with the storage is 12, the storage space of the three-state content addressing memory is 32, and the corresponding external address is 0-31; the flow of writing a length 12 key c to address 12 and then performing a key c match is as follows:
step3.1, interface incoming write signal, comprising: write enable signal=1, key=c to be written, key length to be written=12, external address=12;
step3.2, the signal processing unit splits the to-be-written key C according to the length 12, and the to-be-written key C is not required to be split because the length of the to-be-written key C is 12, because the external address is 12, the number of the TCAM0 storable key length 12 is 8, the external address corresponds to 0-7, the TCAM1 storable key length 12 is 8, the external address corresponds to 8-15, and the signal processing unit sends the to-be-written key C to the TCAM1, and the TCAM1 corresponds to the internal address of 4;
step3.3, the TCAM1 writes the received key C to be written into the address 4;
step3.4, interface incoming match signal, comprising: match enable signal=1, key to be matched=c, key length to be matched=12;
step3.5, the signal processing unit splits the key C to be matched according to the length 12, and because the key is 12 in length, the key does not need to be split, and the key C to be matched is respectively sent to TCAM0, TCAM1, TCAM2 and TCAM3 for matching;
step3.6, TCAM0, TCAM1, TCAM2 and TCAM3 return the matching result to the signal processing unit, the signal processing unit identifies whether each TCAM unit is successfully matched, if any matching is successful, the TCAM1 is successfully matched, and the internal address of the TCAM unit obtained by matching is 4, so that the matching result is successful, and the external address of the TCAM1 is 8-15, so that the finally output external address is 12;
step3.7, output external address 12.
Another embodiment of the present application provides a method for addressing a ternary content addressable memory according to the above embodiment, the method comprising the steps of:
step S100, the signal processing unit receives a key to be written, a key length to be written and an external address to be written, generates f sub-keys to be written according to the key to be written, the key length to be written and the TCAM unit bit width, determines a TACM unit for storing the f sub-keys to be written and a corresponding internal address according to the external address, the key length to be written and the TCAM unit bit width and depth, generates f write signals according to the f sub-keys to be written, the f TCAM units and the corresponding internal address, and sends the f write signals to the f TCAM units respectively; f is greater than or equal to 1 and less than or equal to j, and the length of the key to be written is greater than or equal to the bit width value of the TCAM unit;
step S200, the TCAM unit is configured to receive a write signal, obtain a corresponding sub-key to be written and an internal address, and write the sub-key to be written into the internal address for storage.
In some embodiments, the step S100 specifically includes:
the signal processing unit groups j TCAM units according to the length of the key to be written and the bit width of the TCAM storage unit, and each group has f TCAM units; and determining TACM units for storing the f sub-keys to be written and depth values thereof according to the depth of each group of TCAM units and the external address, wherein the depth values are used as internal addresses.
In some embodiments, the method further comprises:
step S300, the signal processing unit receives a key to be matched and a key length to be matched, generates i sub-keys to be matched according to the key length to be matched, the TCAM unit bit width and the key to be matched, and groups j TCAM units, wherein each group has i TCAM units; outputting the i sub-keys to be matched to each group of TCAM units; i is 1 or more and j or less;
step S400, the TCAM unit matches the i sub-keys to be matched with the sub-keys stored in the TCAM unit to obtain a matching result, and outputs the matching result to the signal processing unit; when the matching is successful, the matching result comprises matching success information and a matched TCAM unit internal address; when the matching fails, the matching result comprises matching failure information;
step S500, the signal processing unit receives the matching results output by the j TCAM units, obtains corresponding external addresses to be output according to the matching results of the j TCAM units, and outputs the external addresses to be output.
In some embodiments, the ternary content addressable memory has a bit width of M, a depth of K, and supports writing and matching of keys with lengths of N-M; the bit width of the TCAM unit is N, and j is equal to M divided by N; wherein M, K, N is a preset value, and N is smaller than M.
In some embodiments, the step S500 specifically includes:
when the length of the key to be matched is M, if the matching results of the i TCAM units are successful and the internal addresses of the matched TCAM units are consistent, the signal processing unit determines that the matching is successful, and determines the internal address of the matched TCAM unit as the external address to be output, otherwise, the signal processing unit determines that the matching is failed.
In some embodiments, the step S500 specifically includes:
and when the length of the key to be matched is greater than N and less than M, if i matching results in the matching results of the j TCAM units are all successful in matching and the internal addresses of the matched TCAM units are consistent, the signal processing unit determines that the matching is successful, converts the internal addresses of the matched TCAM units into corresponding external addresses to be output, and otherwise, the signal processing unit determines that the matching is failed.
In some embodiments, the step S500 specifically includes:
when the length of the key to be matched is N, if one of the matching results of the i TCAM units is successful, the signal processing unit determines that the matching is successful, and converts the internal address of the TCAM unit contained in the one matching result into the corresponding external address to be output, otherwise, the signal processing unit determines that the matching is failed.
It should be noted that, the addressing method of the foregoing embodiment corresponds to the ternary content addressable memory of the foregoing embodiment, so that a portion of the addressing method of the foregoing embodiment, which is not described in detail, may be referred to the content of the ternary content addressable memory of the foregoing embodiment, and will not be described herein.
Another embodiment of the present application also proposes a computer-readable storage medium storing a computer program which, when executed by a processor, implements an addressing method as described in the above embodiments.
In particular, the computer-readable storage medium may include: any entity or recording medium, a USB flash disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, etc. capable of carrying the computer program instructions.
Another embodiment of the present application provides an electronic device, including a processor, a memory, and a computer program stored on the memory and executable on the processor, where the processor implements the addressing method described in the above embodiment when executing the program.
The electronic device may also include a bus that connects the different components, including the memory and the processor. The memory may include computer-readable media in the form of volatile memory, such as Random Access Memory (RAM) and/or cache memory. The memory may also include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the application. The electronic device may also communicate with one or more external devices (e.g., keyboard, pointing device, display, etc.), with one or more devices that enable a user to interact with the electronic device, and/or with any device (e.g., network card) that enables the electronic device to communicate with one or more other computing devices, such communication may be through an input/output (I/O) interface, and the electronic device may also communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) through a network adapter.
Another embodiment of the present application provides a chip comprising the ternary content addressable memory described in the previous embodiment.
The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (15)

1. The ternary content addressing memory is characterized by comprising a signal processing unit and j TCAM storage units, wherein j is more than or equal to 2;
the signal processing unit is used for receiving a key to be written, a key length to be written and an external address to be written, generating f sub-keys to be written according to the key to be written, the key length to be written and the TCAM unit bit width, determining a TACM unit for storing the f sub-keys to be written and a corresponding internal address according to the external address, the key length to be written and the TCAM unit bit width and depth, generating f write signals according to the f sub-keys to be written, the f TCAM units and the corresponding internal address, and respectively sending the f write signals to the f TCAM units; f is greater than or equal to 1 and less than or equal to j, and the length of the key to be written is greater than or equal to the bit width value of the TCAM unit;
the TCAM unit is used for receiving the writing signal, obtaining the corresponding sub key to be written and the internal address, and writing the sub key to be written into the internal address for storage.
2. The ternary content addressable memory of claim 1, wherein the signal processing unit is specifically configured to:
grouping j TCAM units according to the length of the key to be written and the bit width of the TCAM storage unit, wherein each group has f TCAM units; and determining TACM units for storing the f sub-keys to be written and depth values thereof according to the depth of each group of TCAM units and the external address, wherein the depth values are used as internal addresses.
3. The ternary content addressable memory of claim 1 or 2, wherein,
the signal processing unit is further used for receiving a key to be matched and a key length to be matched, generating i sub-keys to be matched according to the key length to be matched, the TCAM unit bit width and the key to be matched, and grouping j TCAM units, wherein each group has i TCAM units; outputting the i sub-keys to be matched to each group of TCAM units; i is 1 or more and j or less;
the TCAM unit is further used for matching the i sub-keys to be matched with the sub-keys stored in the TCAM unit to obtain a matching result, and outputting the matching result to the signal processing unit; when the matching is successful, the matching result comprises matching success information and a matched TCAM unit internal address; when the matching fails, the matching result comprises matching failure information;
the signal processing unit is further configured to receive the matching results output by the j TCAM units, obtain an external address to be output according to the matching results of the j TCAM units, and output the external address to be output.
4. The ternary content addressable memory of claim 3, wherein the ternary content addressable memory has a bit width of M, a depth of K, and supports writing and matching of keys of length N-M; the bit width of the TCAM unit is N, and j is equal to M divided by N; wherein M, K, N is a preset value, and N is smaller than M.
5. The ternary content addressable memory of claim 4, wherein the signal processing unit is specifically configured to, when the key length to be matched is M, determine that the matching is successful if the matching results of the i TCAM units are all successful and the internal addresses of the matched TCAM units are all consistent, and determine that the internal addresses of the matched TCAM units are external addresses to be output, otherwise, determine that the matching is failed.
6. The ternary content addressable memory of claim 4, wherein the signal processing unit is specifically configured to, when the key length to be matched is greater than N and less than M, determine that the matching is successful if i matching results in the matching results of the j TCAM units are all successful and the internal addresses of the matched TCAM units are consistent, and convert the internal addresses of the TCAM units that are consistent in matching into corresponding external addresses to be output, otherwise, determine that the matching is failed.
7. The ternary content addressable memory of claim 4, wherein the signal processing unit is specifically configured to, when the key length to be matched is N, determine that one of the matching results of the i TCAM units is successful, if the matching result is successful, determine that the matching is successful, and convert an internal address of the TCAM unit included in the one matching result into a corresponding external address to be output, otherwise determine that the matching is failed.
8. A method of addressing a ternary content addressable memory according to claim 1, the method comprising:
the signal processing unit receives a key to be written, a key length to be written and an external address to be written, generates f sub-keys to be written according to the key to be written, the key length to be written and the TCAM unit bit width, determines a TACM unit for storing the f sub-keys to be written and a corresponding internal address according to the external address, the key length to be written and the TCAM unit bit width and depth, generates f write signals according to the f sub-keys to be written, the f TCAM units and the corresponding internal address, and sends the f write signals to the f TCAM units respectively; f is greater than or equal to 1 and less than or equal to j, and the length of the key to be written is greater than or equal to the bit width value of the TCAM unit;
the TCAM unit is used for receiving the writing signal, obtaining the corresponding sub key to be written and the internal address, and writing the sub key to be written into the internal address for storage.
9. Addressing method according to claim 8, characterized in that it comprises in particular:
the signal processing unit groups j TCAM units according to the length of the key to be written and the bit width of the TCAM storage unit, and each group has f TCAM units; and determining TACM units for storing the f sub-keys to be written and depth values thereof according to the depth of each group of TCAM units and the external address, wherein the depth values are used as internal addresses.
10. An addressing method according to claim 8 or 9, characterized in that the method further comprises:
the signal processing unit receives a key to be matched and a key length to be matched, generates i sub-keys to be matched according to the key length to be matched, the TCAM unit bit width and the key to be matched, and groups j TCAM units, wherein each group has i TCAM units; outputting the i sub-keys to be matched to each group of TCAM units; i is 1 or more and j or less;
the TCAM unit matches the i sub-keys to be matched with the sub-keys stored in the TCAM unit to obtain a matching result, and outputs the matching result to the signal processing unit; when the matching is successful, the matching result comprises matching success information and a matched TCAM unit internal address; when the matching fails, the matching result comprises matching failure information;
and the signal processing unit receives the matching results output by the j TCAM units, obtains corresponding external addresses to be output according to the matching results of the j TCAM units, and outputs the external addresses to be output.
11. The addressing method of claim 10 wherein said ternary content addressable memory has a bit width of M, a depth of K, and supports writing and matching of keys of length N-M; the bit width of the TCAM unit is N, and j is equal to M divided by N; wherein M, K, N is a preset value, and N is smaller than M.
12. The addressing method of claim 11, wherein said signal processing unit receives the matching results output by said j TCAM cells, and obtains an external address to be output according to the matching results of said j TCAM cells, specifically comprising:
when the length of the key to be matched is M, if the matching results of the i TCAM units are successful and the internal addresses of the matched TCAM units are consistent, the signal processing unit determines that the matching is successful, and determines the internal address of the matched TCAM unit as the external address to be output, otherwise, the signal processing unit determines that the matching is failed.
13. The addressing method of claim 11, wherein said signal processing unit receives the matching results output by said j TCAM cells, and obtains an external address to be output according to the matching results of said j TCAM cells, specifically comprising:
and when the length of the key to be matched is greater than N and less than M, if i matching results in the matching results of the j TCAM units are all successful in matching and the internal addresses of the matched TCAM units are consistent, the signal processing unit determines that the matching is successful, converts the internal addresses of the matched TCAM units into corresponding external addresses to be output, and otherwise, the signal processing unit determines that the matching is failed.
14. The addressing method of claim 11, wherein said signal processing unit receives the matching results output by said j TCAM cells, and obtains an external address to be output according to the matching results of said j TCAM cells, specifically comprising:
when the length of the key to be matched is N, if one of the matching results of the i TCAM units is successful, the signal processing unit determines that the matching is successful, and converts the internal address of the TCAM unit contained in the one matching result into the corresponding external address to be output, otherwise, the signal processing unit determines that the matching is failed.
15. A chip comprising the ternary content addressable memory of any one of claims 1-7.
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