CN116720981A

CN116720981A - Virtual loop checking method and device, terminal equipment and storage medium

Info

Publication number: CN116720981A
Application number: CN202310627488.XA
Authority: CN
Inventors: 梁玮琪; 孔德深; 叶欣; 史志强; 蒋海辉; 黄雄
Original assignee: CYG Sunri Co Ltd
Current assignee: CYG Sunri Co Ltd
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2023-09-08

Abstract

The application is suitable for the technical field of loop checking, and provides a virtual loop checking method, a virtual loop checking device, terminal equipment and a storage medium, wherein the virtual loop checking method comprises the following steps: determining a virtual circuit to be checked and target information corresponding to the virtual circuit to be checked according to an SCD file, wherein the SCD file comprises identification information of virtual terminals and topology information of the virtual terminals, the virtual circuit to be checked is formed by connecting virtual terminals corresponding to the identification information of at least two virtual terminals, the target information comprises the topology information of each virtual terminal in the virtual circuit to be checked, the target information is input into a trained checking model for checking, and a checking result output by the checking model is obtained and used for indicating whether the connection relation between the virtual terminals in the virtual circuit to be checked is correct or not. The application can improve the accuracy of virtual loop checking.

Description

Virtual loop checking method and device, terminal equipment and storage medium

Technical Field

The application belongs to the technical field of loop checking, and particularly relates to a virtual loop checking method, a virtual loop checking device, terminal equipment and a computer readable storage medium.

Background

The total station system configuration file (substation configuration description, SCD) fully describes the information of the primary and secondary systems of the intelligent substation, the instance configuration and communication parameters of all intelligent electronic devices (Intelligent Electronic Device, IEDs), and the communication configuration between the intelligent electronic devices. The correctness of SCD file configuration is critical to the safe operation of the intelligent substation, and especially virtual terminals (namely virtualized connection interfaces) in the SCD file and virtual loops reflecting the connection relation of the virtual terminals can directly influence the tripping and closing of the intelligent substation, the connection relation of sampling loops and secondary loops and the like, and whether the virtual loops are correct or not directly influences the relay protection function and the safe and stable operation of a power grid.

At present, when checking the correctness of the virtual circuit in the SCD file, the checking is usually performed manually, but the number of virtual terminals in the SCD file is large, the connection relationship between the virtual terminals is complex, a great amount of labor and time cost are required for manual checking, and the checking difficulty is high.

Disclosure of Invention

The embodiment of the application provides a virtual circuit checking method, a virtual circuit checking device, terminal equipment and a storage medium, which can improve the accuracy of virtual circuit checking.

In a first aspect, an embodiment of the present application provides a virtual circuit checking method, including:

determining a virtual circuit to be checked and target information corresponding to the virtual circuit to be checked according to an SCD file, wherein the SCD file comprises identification information of virtual terminals and topology information of the virtual terminals, the virtual circuit to be checked is formed by connecting virtual terminals corresponding to the identification information of at least two virtual terminals, and the target information comprises the topology information of each virtual terminal in the virtual circuit to be checked;

and inputting the target information into a trained checking model for checking, and obtaining a checking result output by the checking model, wherein the checking result is used for indicating whether the connection relationship between the virtual terminals in the virtual circuit to be checked is correct.

In a possible implementation manner of the first aspect, the checking model includes a preprocessing network and a classification model, the inputting the target information into a trained checking model for checking, to obtain a checking result output by the checking model, includes:

vectorizing the target information based on the preprocessing network to obtain characteristics to be checked;

And inputting the features to be checked into the classification model to obtain a checking result output by the classification model.

In another possible implementation manner of the first aspect, the topology information includes a signal description of the virtual terminal and a name of an intelligent electronic device corresponding to the virtual terminal;

the vectorizing processing is carried out on the target information based on the preprocessing network to obtain the feature to be checked, and the vectorizing processing comprises the following steps:

performing word segmentation processing on the signal description in the target information to obtain a word segmentation result;

splitting the name in the target information to obtain a splitting result;

vectorizing the word segmentation result and the splitting result respectively to obtain signal characteristics and name characteristics;

and splicing the signal characteristics and the name characteristics to obtain the characteristics to be checked.

In another possible implementation manner of the first aspect, the checking model is determined by:

obtaining a sample set, wherein the sample set comprises at least one virtual loop with a label;

vectorizing target information corresponding to the labeled virtual loop in the sample set based on the constructed preprocessing network to obtain a first characteristic;

Training a pre-constructed classification model based on the first characteristics until the classification model meets preset requirements, wherein the classification model is used for checking whether the connection relation of the virtual terminals is correct according to the input characteristics of the virtual circuits;

and determining the check model according to the preprocessing network and the classification model meeting the requirements.

In another possible implementation manner of the first aspect, the classification model includes a plurality of base learners and a classifier, and training a pre-constructed classification model based on the first feature until the classification model meets a preset requirement includes:

determining a training set and a verification set according to the first characteristics of each virtual loop in the sample set;

training each base learner according to the first characteristics in the training set by adopting a K-fold cross verification mode to obtain each trained base learner and a first predicted value output by each base learner;

inputting the first features in the verification set into each trained base learner respectively to obtain second predicted values output by the base learners;

Determining a second feature according to the first predicted value, and determining a third feature according to the second predicted value;

training the classifier according to the second characteristic and the third characteristic until the classifier meets the preset requirement.

In another implementation manner of the first aspect, before the training of the pre-constructed classification model based on the first feature, the method further includes:

calculating a variance of each of the first features for each of the first features of the virtual circuit in the sample set;

determining a target first feature from the variance;

the training the pre-constructed classification model based on the first feature comprises the following steps:

training the pre-constructed classification model based on the target first feature.

In a second aspect, an embodiment of the present application provides a virtual circuit checking apparatus, including:

the target information acquisition module is used for determining a virtual circuit to be checked and target information corresponding to the virtual circuit to be checked according to an SCD file, wherein the SCD file comprises identification information of virtual terminals and topology information of the virtual terminals, the virtual circuit to be checked is formed by connecting at least two virtual terminals, and the target information comprises the topology information of each virtual terminal in the virtual circuit to be checked;

And the checking module is used for inputting the target information into a trained checking model to check, so as to obtain a checking result output by the checking model, wherein the checking result is used for indicating whether the connection relationship between the virtual terminals in the virtual circuit to be checked is correct.

In a third aspect, an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the steps of the virtual circuit checking method described in the first aspect are implemented when the processor executes the computer program.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which when executed by a processor, implements the steps of the virtual circuit checking method described in the first aspect.

In a fifth aspect, an embodiment of the present application provides a computer program product, which when run on a terminal device, causes the terminal device to perform the virtual circuit checking method according to any one of the first aspects.

Compared with the prior art, the embodiment of the application has the beneficial effects that:

In the embodiment of the application, the target information of the virtual circuit to be checked, which is acquired according to the SCD file, comprises the topology information of each virtual terminal in the virtual circuit to be checked, and the topology information of the virtual terminals can reflect the connection relation of the virtual terminals, so that the target information of the virtual circuit to be checked is used as the input of a trained checking model for checking, and whether the connection between the virtual terminals in the virtual circuit to be checked is correct or not can be detected based on the connection relation of the virtual terminals reflected by the target information, thereby realizing the automatic checking of the virtual circuit, reducing the cost and the time cost and improving the checking accuracy of the virtual circuit.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.

Fig. 1 is a schematic flow chart of a virtual circuit checking method according to an embodiment of the application;

FIG. 2 is a naming convention table of names of intelligent electronic devices provided by an embodiment of the present application;

fig. 3 is a schematic structural diagram of a virtual circuit checking device according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise.

Embodiment one:

fig. 1 shows a schematic flow chart of a virtual circuit checking method according to an embodiment of the present application, which is described in detail below:

step S101, determining a virtual circuit to be checked and target information corresponding to the virtual circuit to be checked according to an SCD file, wherein the SCD file comprises identification information of virtual terminals and topology information of the virtual terminals, the virtual circuit to be checked is formed by connecting virtual terminals corresponding to the identification information of at least two virtual terminals, and the target information comprises the topology information of each virtual terminal in the virtual circuit to be checked.

The SCD file refers to a total station system configuration file of the intelligent substation, describes example configuration and communication parameters of all intelligent electronic devices (Intelligent Electronic Device, IEDs), communication configuration among the intelligent electronic devices and a primary system structure of the substation, and is usually completed by a system integrator. The SCD file includes at least an identification of the virtual terminal (unique identification may be set according to a device number of the intelligent electronic device corresponding to the virtual terminal) and topology information of the virtual terminal, which is communication connection configuration information of the virtual terminal.

The virtual terminal refers to a virtualized connection interface of intelligent electronic equipment (such as transformer protection, measurement and control devices and the like) and is used for defining the connection relation between the intelligent electronic equipment of the digital transformer substation, and the virtual circuit is a communication connection formed by connecting two or more virtual terminals.

Specifically, since the SCD file records the instance configuration, the communication parameters and the communication configuration among all intelligent electronic devices of the intelligent substation, after the SCD file is parsed, a virtual circuit preset by a user such as a system integrator can be determined according to the communication configuration among the intelligent electronic devices recorded in the SCD file, the virtual circuit determined according to the SCD file is taken as a virtual circuit to be checked, the information of the virtual terminal corresponding to the identification information recorded in the SCD file is determined according to the identification information of each virtual terminal in the virtual circuit to be checked, so that the topology information of the virtual terminal is obtained, and the obtained topology information of each virtual terminal in the virtual circuit to be checked is taken as the target information corresponding to the virtual circuit to be checked.

Optionally, in order to reduce the complexity of checking, when determining the virtual circuit to be checked according to the SCD file, the communication connection formed by connecting two virtual terminals may be used as the virtual circuit to be checked, that is, the virtual circuit formed by two or more virtual terminals in the SCD file is split, so as to obtain one or more groups of virtual circuits to be checked formed by two virtual terminals with connection relationships, so that the virtual circuit to be checked only contains one connection relationship (two virtual terminals), thereby reducing the checking complexity and improving the checking efficiency and accuracy.

In the embodiment of the application, because the topology information of the virtual terminals in the SCD file can reflect the connection relation of the virtual terminals, when the virtual circuit to be checked is determined according to the SCD file, the topology information of each virtual terminal in the virtual circuit to be checked is determined at the same time and is used as the target information of the virtual circuit to be checked, so that whether the virtual circuit to be checked has a connection error can be checked according to the target information reflecting the connection relation of each virtual terminal in the virtual circuit to be checked.

Step S102, inputting the target information into a trained checking model for checking, and obtaining a checking result output by the checking model, wherein the checking result is used for indicating whether the connection relationship between the virtual terminals in the virtual circuit to be checked is correct.

Specifically, because the target information includes topology information of each virtual terminal in the virtual circuit to be checked, and the topology information of the virtual terminal can reflect the connection relationship of the virtual terminal, in the embodiment of the application, the target information of the virtual circuit to be checked is used as the input of a trained checking model, and whether the connection relationship of the virtual terminal in the virtual circuit is correct or not is automatically checked according to the topology information of the virtual terminal reflected by the target information through the checking model, so that a checking result corresponding to the virtual circuit to be checked, which is output by the checking model, is obtained.

When the virtual circuit to be checked contains three or more virtual terminals, the virtual terminals do not have a connection relationship (for example, when the virtual circuit to be checked has A, B, C three virtual terminals, the virtual terminal A and the virtual terminal B have a connection relationship, and the virtual terminal B and the virtual terminal C have a connection relationship, wherein the virtual terminal A and the virtual terminal C do not have a connection relationship), so that when the virtual circuit to be checked is checked, each pair of virtual terminals with a connection relationship in the virtual circuit to be checked checks whether the connection relationship is correct, thereby obtaining a checking result of the virtual circuit to be checked.

In the embodiment of the application, because the SCD file comprises the identification information and the topology information of the virtual terminals, when the virtual circuit to be checked is determined according to the SCD file, the target information comprising the topology information of each virtual terminal in the virtual circuit is obtained from the SCD file, and the topology information of the virtual terminals can reflect the connection relation of the virtual terminals, the target information of the virtual circuit to be checked is used as the input of a trained checking model to check, and whether the connection between the virtual terminals in the virtual circuit to be checked is correct or not can be checked automatically by the checking model, thereby realizing the automatic checking of the virtual circuit, without manual participation, reducing the labor cost and the time cost, and improving the accuracy of virtual circuit checking.

In some embodiments, before the step S101, a model to be checked is acquired, where the check model is determined by the following steps:

a1, acquiring a sample set, wherein the sample set comprises at least one virtual loop with a label.

Alternatively, the sample set may be an obtained public data set as the sample set, or may be a manually labeled data set. The sample set uses a virtual circuit as a training sample, wherein the virtual circuit in the sample set can be a communication connection formed by connecting two virtual terminals or a communication connection formed by connecting a plurality of virtual terminals, and the label is used for indicating whether the connection relation of the virtual terminals in the virtual circuit is correct or not. To reduce the cost of manual labeling and the complexity of model training, each virtual circuit in the sample set may be formed by only two virtual terminal connections.

A2, vectorizing target information corresponding to the marked virtual loop in the sample set based on the constructed preprocessing network to obtain a first characteristic.

A3, training a pre-constructed classification model based on the first features until the classification model meets preset requirements, wherein the classification model is used for checking whether the connection relation of the virtual terminals is correct according to the input features of the virtual circuits.

A4, determining the checking model according to the preprocessing network and the classification model meeting the requirements.

Specifically, because the target information of the virtual circuit describes the topology information of each virtual terminal in the virtual circuit, in the embodiment of the application, the virtual circuit is used as a training sample to train a checking model, and the connection relation of the virtual terminals in the virtual circuit is automatically checked by the checking model on the topology information reflected by the target information corresponding to the virtual circuit, so that the automatic checking of the virtual circuit is realized. Before training the classification model, because the target information is text information and the model cannot better process the text information, vectorizing the target information of the virtual circuit in the acquired sample set to obtain the first feature in a corresponding vector form, and training the obtained first feature as training data of the classification model until the classification model meets the preset requirement (for example, the accuracy reaches 0.98), so as to obtain the classification model capable of being used for checking the connection relation of the virtual terminal based on the target information of the virtual circuit. Finally, because the target information is text information, the classification model cannot be directly input for checking, and therefore, the preprocessing network and the classification model meeting the requirements are used as a final checking model for checking the virtual loop.

In the embodiment of the application, before training the classification model according to the target information of the virtual circuit, the target information is vectorized through the preprocessing network to obtain the first characteristic in a vector form, and then the first characteristic is used as the input of the classification model for training, so that the classification model capable of automatically checking the connection relation of the virtual terminal according to the characteristic information of the virtual circuit is obtained, the automatic checking of the virtual circuit is realized, the manual checking is not needed, the labor cost and the time cost are reduced, and meanwhile, the automatic checking can avoid misjudgment caused by experience difference and other reasons of a user during the manual checking, and the checking accuracy is improved.

In some embodiments, the classification model includes a plurality of base learners and a classifier, and the step A3 includes:

a31, determining a training set and a verification set according to the first characteristics of each virtual loop in the sample set.

A32, training each base learner according to the first characteristics in the training set by adopting a K-fold cross validation mode to obtain each trained base learner and a first predicted value output by each base learner.

The K-fold cross validation refers to dividing a data set into K subsets with the same size, traversing the K subsets in sequence, taking the current subset as a validation set each time, taking the rest subsets as training sets, and training and evaluating a model.

A33, inputting the first features in the verification set into each trained base learner to obtain second predicted values output by the base learners.

A34, determining a second characteristic according to the first predicted value, and determining a third characteristic according to the second predicted value.

A35, training the classifier according to the second characteristic and the third characteristic until the classifier meets the preset requirement.

Specifically, because the connection relation of virtual terminals in the virtual loop is complex, and a single model is difficult to fit complex data, in order to reduce model training difficulty and improve generalization capability and anti-interference capability of a subsequently obtained check model, in the embodiment of the application, a pre-constructed classification model comprises a plurality of base learners (i.e. individual learners, such as a support vector machine, a convolutional neural network and the like, which can be used as the base learners) and a classifier (such as a Bayesian classifier, a multi-layer perception classifier and the like), and the generalization capability of the classification model is improved by integrating the plurality of base learners.

When training the classification model, firstly determining a training set and a verification set of the classification model according to the first characteristics of each virtual loop in the sample set, and then training the classification model by adopting the training set. That is, the first features of the virtual circuits in the sample set are used as training data of the classification model, and are directly input into the classification model for training.

In order to prevent the situation of over fitting, when training is performed on the base learner in the classification model by adopting a training set, the training set is divided into K (for example, 5,K is at least 2) sub-training sets with the same size by adopting a K-fold cross validation mode, each base learner is trained by adopting K-1 sub-training sets as the training set of the base learner, and the other remaining sub-training sets are adopted as the test set of the base learner. After training the base learner by adopting K-1 sub training sets, taking each first characteristic in the test set corresponding to the base learner as the input of the trained base learner to obtain a first predicted value output by the base learner. Alternatively, when training each base learner, each round of training the base learner may use different K-1 sub-training sets as its training sets, and the remaining one sub-training set is used as its test set, and K rounds of training are performed on the base learner, where the test set (i.e., the sub-training set) of each round of training is different. In each round of training of the base learner, after the current K-1 sub-training sets are adopted to train the base learner, the corresponding test set is used as the input of the base learner, so as to obtain first predicted values output by the base learner, and K first predicted values output by the base learner are obtained in total.

And after the training of the base learner is completed, taking the first characteristics in the verification set obtained according to the sample set as the input of each trained base learner to obtain a second predicted value output by each base learner.

After the first predicted value and the second predicted value corresponding to each base learner are obtained, determining second features according to each first predicted value, determining third features according to each second predicted value, and training the second features and the third features serving as training data of the classifier until the classifier meets preset requirements (such as classification accuracy reaching 0.98). Alternatively, when the second feature is determined according to the first predicted value, one first predicted value output by each base learner may be spliced or stacked to obtain a second feature, and when the third feature is determined according to the second predicted value, one second predicted value output by each base learner may be spliced or stacked to obtain the third feature. Alternatively, the first predicted values obtained by the same first feature in each base learner may be spliced or stacked to obtain a second feature, and the label of the virtual loop corresponding to the first feature is used as the label of the second feature.

In the embodiment of the application, because a single model is difficult to fit complex data, the model is difficult to train and the model accuracy is low, in the embodiment of the application, the constructed classification model comprises a plurality of base learners and a classifier, the characteristics of target information are respectively learned through the plurality of base learners, and the prediction results of the plurality of base learners are integrated as training data of the classifier for training, so that the generalization capability of the obtained checking model is improved, and the checking accuracy of the checking model is further improved.

It should be noted that, in the actual situation, the classification model in the checking model and the training step of the classification model may be determined according to the actual application scenario, for example, a random forest may be directly adopted as the classification model, the random forest may be trained, or a plurality of base learners may be directly adopted as the classification model, each base learner may be trained (for example, each base learner is trained by the above K-fold cross validation method, or each base learner is directly trained by the training set), and then the final checking result is determined according to the prediction result of each base learner (for example, the average value of the prediction result of each base learner is used as the final checking result of the checking model), which will not be described herein.

In some embodiments, before the step A3, the method further includes:

for each of the first features of the virtual circuit in the sample set, calculating a variance of each of the first features.

And determining a target first characteristic according to the variance.

Correspondingly, the step A3 includes:

Specifically, the variance can reflect the discrete degree of the data, and the sparsity of the training data can better improve the generalization capability of the model, so that in order to improve the accuracy of a subsequently obtained checking model, before training the classification model, the target first features for training the classification model are selected according to the variances of the first features of each virtual loop in the sample set, and then the target first features are directly adopted for training the classification model when the classification model is trained. Alternatively, since a larger variance of the data represents a larger degree of dispersion of the data, after calculating the variance of the first features of each virtual circuit, the pre-constructed classification model may be trained based on the determined first features according to a specified number of first features (e.g., 30% of the total number of first features) with a larger variance as the target first features. In other embodiments, the first feature with the variance greater than the preset threshold (e.g. 2.5) may be used as the target first feature, so as to ensure that the target first feature has a certain sparsity.

For example, assuming that the sample set includes 10 ten thousand virtual loops, that is, 10 ten thousand first features are obtained after processing, after variances of the first features are calculated respectively, 2 ten thousand first features with larger variances (that is, first features with the first 2 ten thousand being arranged in order of the variances from large to small) are determined, the 2 ten thousand first features are used as target first features, and the 2 ten thousand target first features (that is, first features) are used as training data of the classification model for training.

In the embodiment of the application, the variance can reflect the discrete degree of the data, so that the target first feature for training the classification model is determined according to the variance of each first feature before training the classification model, and the first feature with larger discrete degree can be acquired for training, thereby improving the generalization capability of the classification model obtained by training and further improving the accuracy of the check model obtained subsequently. It should be noted that in actual cases, the target first feature may be determined based on a standard deviation or a value of standard deviation or the like of each first feature, which can reflect the degree of dispersion of the first feature, without limitation.

In some embodiments, the checking model includes a preprocessing network and a classification model, and the step S102 includes:

And B1, carrying out vectorization processing on the target information based on the preprocessing network to obtain the characteristics to be checked.

And B2, inputting the features to be checked into the classification model to obtain a checking result output by the classification model.

Specifically, since the target information is text information and the model cannot process the text information well, before the target information is input into the classification model, vectorization processing is performed on the target information through a pre-constructed preprocessing network, the target information is converted into characteristics to be checked in a vector form, and then the characteristics to be checked in the vector form are used as input of the classification model to be classified, so that a checking result output by the classification model is obtained.

It should be noted that, since the target information includes topology information of each virtual terminal in the virtual circuit to be checked, when checking the connection relationship between the virtual terminals in the virtual circuit to be checked, checking is performed according to the topology information of each virtual terminal, that is, when preprocessing the target information to obtain the feature to be checked, vectorizing processing is performed on the topology information of each virtual terminal in the target information, and then checking the feature information of each vectorized virtual terminal is used as the feature to be checked.

According to the embodiment of the application, the vectorization preprocessing is carried out on the target information in the text form, so that the model can better check the connection relation of the virtual terminals according to the target information.

In some embodiments, the topology information includes a signal description of the virtual terminal and a name of the intelligent electronic device corresponding to the virtual terminal, and the step B1 includes:

and B11, performing word segmentation on the signal description in the target information to obtain a word segmentation result.

Optionally, the information of the connection device of the intelligent electronic device corresponding to the virtual terminal is recorded in the signal description, and the information includes one or more of voltage level, primary device interval name, device protection, device type and device model.

Specifically, as the signal description in the target information records the information such as the voltage level, the primary equipment interval name and the like of the intelligent electronic equipment corresponding to the virtual terminal, in order to better detect different characteristic information of the virtual terminal and improve the accuracy of virtual loop checking, before vectorization is carried out on the signal description, word segmentation processing is carried out on the signal description, and each word in the signal description is segmented to obtain the segmented signal description (namely a word segmentation result).

Optionally, because the descriptions of the information such as the signal descriptions of the virtual terminals may be different for the manufacturers of different intelligent electronic devices, and some information irrelevant to the connection of the virtual terminals may exist in the word segmentation result obtained after word segmentation, in order to improve the checking efficiency and accuracy of the virtual circuit, the word segmentation result of the signal descriptions is cleaned, and key information relevant to the connection of the virtual terminals (i.e. the information such as the voltage level and the primary device interval name recorded by the signal descriptions) is reserved.

Optionally, when the signal description is subjected to word segmentation, the signal description can be subjected to jieba word segmentation, further, the signal description can be subjected to jieba word segmentation in a full decomposition mode, all words which can be segmented in the signal description are rapidly scanned, and then the scanned words are cleaned, so that the words in the obtained word segmentation result are all information related to connection of virtual terminals, and the word segmentation efficiency and the accuracy of the word segmentation result are improved. For example, assuming that the virtual circuit to be checked consists of a virtual terminal A and a virtual terminal B with connection relation, and assuming that the signal of the virtual terminal A is described as "220kV mountain high B line main two protection CSC-103A2-DG-N-Z" and the signal of the virtual terminal B is described as "220kV mountain high B line B set intelligent terminal CSD-601ILB-DG-N", the signal descriptions of the virtual terminal A and the virtual terminal B are respectively subjected to jieba word segmentation processing of a full decomposition mode to obtain word segmentation results corresponding to the virtual terminal A: [ '220kV', 'mountain high', 'line B', 'main two', 'protection', 'CSC103A2DGNZ', 'virtual terminal B' corresponding word segmentation result: [ '220kV', 'mountain high', 'line B', 'sleeve B', 'smart terminal', 'CSD-601ILB-DG-N' ].

And B12, splitting the names in the target information to obtain splitting results.

The names in the target information refer to the names of the intelligent electronic devices corresponding to the virtual terminals described in the target information, and the names of the intelligent electronic devices are standardized. For example, as shown in fig. 2, the name length of the intelligent electronic device is 8 characters, wherein the 1 st and 2 nd characters are device types, the 3 rd character is the type of the home device of the intelligent electronic device, the 4 th and 5 th characters are voltage levels of the intelligent electronic device, the 6 th and 7 th characters are the home device numbers of the intelligent electronic device, and the 8 th character is the device number of the intelligent electronic device.

Specifically, the names of the intelligent electronic devices are named according to the specific rules, so that the names of the intelligent electronic devices in the target information can be split according to the naming rules of the names of the intelligent electronic devices, and the split results of various information accurately describing the intelligent electronic devices can be obtained. For example, as shown in fig. 2, when the name of the intelligent electronic device named according to the naming table is split, the 1 st and 2 nd characters of the name are split into one piece of information (device type), the 3 rd character is split into one piece of information (type of home device of the intelligent electronic device), and the 4 th, 5 th, 6 th, 7 th and 8 th characters are split to obtain the corresponding pieces of information, respectively.

And B13, respectively carrying out vectorization processing on the word segmentation result and the splitting result to obtain signal characteristics and name characteristics.

Specifically, since the obtained word segmentation result and the obtained splitting result are text data, and the model cannot process the text data well, before checking according to the word segmentation result and the splitting result corresponding to the target information, vectorizing the word segmentation result to obtain signal characteristics in a vector form, and vectorizing the splitting result to obtain name characteristics in the vector form.

Optionally, because one or more words are included in the Word segmentation result, the Word segmentation result may be subjected to Word vectorization (e.g., word2vec based on Word distributed expression), each Word in the Word segmentation result may be converted into a vector with a fixed dimension, and a proper manner may be selected to perform weighting processing, so as to finally obtain a signal feature corresponding to the Word segmentation result. Optionally, because the name in the target information is a discrete feature, in order to calculate the distance between the features more reasonably, when vectorizing the splitting result, the splitting result and/or the splitting result may be subjected to single-hot encoding, and the value of the discrete feature is expanded to the euclidean space to calculate the feature distance.

And B14, splicing the signal characteristics and the name characteristics to obtain the characteristics to be checked.

Specifically, in order to evaluate the distinguishing degree of the virtual terminals more accurately, after the signal features and the name features are obtained, the signal features and the name features in the vector form are spliced together to obtain the features to be checked, wherein the features comprise the signal features and the name features. Alternatively, when the vectorization processing is performed on the segmentation result and the splitting result, two-dimensional signal features and name features are generated, and when the signal features and the name features are spliced, the signal features and the name features can be spliced in the length (row) direction or in the width (column) direction.

In some embodiments, the topology information of the virtual terminal in the target information further includes virtual terminal information including one or more of a terminal type, a terminal direction, an access point, a manufacturer, a version, and a year, and data information including one or more of an object index, a data base type, and a data composite type. When vectorization processing is carried out on the target information, independent thermal coding processing is carried out on the virtual terminal information and the data information contained in the target information respectively to obtain corresponding virtual terminal characteristics and data characteristics, all characteristic information such as signal characteristics, name characteristics, virtual terminal characteristics, data characteristics and the like of each virtual terminal in the target information are spliced respectively to obtain characteristic matrixes corresponding to each virtual terminal, and then the characteristics to be checked are determined according to the obtained characteristic matrixes.

Optionally, because the features to be checked obtained by preprocessing include features of different types such as word vectors, and the effects of different models on processing different types of data are different (such as a regression model is more suitable for processing word vectors), five base learners and one classifier are arranged in the classification model, the five base learners in the classification model can adopt a support vector machine, an adaboost, a push ladder model Gboost, a random forest and a multi-layer perceptron network, the classifier in the classification model can adopt a random forest, and the classification result of the plurality of base learners is determined based on the classification result of the plurality of base learners by adopting the random forest model after classifying the features to be checked through the different base learners respectively, so that the final classification result is output.

In the embodiment of the application, when the target information is subjected to vectorization processing based on the preprocessing network, the target information is subjected to different processing according to the characteristics of the information contained in the target information so as to better express the characteristic information of each information, and finally, each characteristic is spliced together, and the to-be-checked characteristic obtained by combining all the information of the target information can better express the topology information of the virtual terminal, so that the accuracy of subsequent checking is improved.

In some embodiments, the types of connection errors between the virtual terminals mainly include logic errors, voltage class errors, signal repetition, AB set pull errors, interval errors, and the like, and when the classification model in the checking model checks whether the connection relationship between the virtual terminals in the virtual circuit to be checked is normal according to the characteristics to be checked, different types of connection errors between the virtual terminals are checked differently. For example, for the voltage class error of the virtual terminals, judging whether the voltage classes of the virtual terminals are matched according to the voltage class characteristic information corresponding to the virtual terminals with the connection relation in the characteristics to be checked, if the voltage classes of the virtual terminals are matched, the virtual terminals with the connection relation are not in error, and for the interval error, judging whether the intervals of the virtual terminals with the connection relation in the virtual circuit to be checked are identical, namely, whether the attribution equipment numbers in the name characteristics of the corresponding virtual terminals are identical, and if the attribution equipment numbers of the virtual terminals with the connection relation are identical, the interval error is not in between the virtual terminals with the connection relation. Correspondingly, when the checking model outputs a checking result, the checking result can indicate the virtual terminal with the connection error and the specific error type in the virtual circuit to be checked, so that a user can quickly and accurately correct the virtual circuit to be checked with the connection error according to the checking result.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.

Embodiment two:

corresponding to the virtual circuit checking method described in the above embodiments, fig. 3 shows a block diagram of the virtual circuit checking device provided in the embodiment of the present application, and for convenience of explanation, only the portion relevant to the embodiment of the present application is shown.

Referring to fig. 3, the apparatus includes: a target information acquisition module 31 and a check module 32. Wherein, the liquid crystal display device comprises a liquid crystal display device,

the target information acquisition module is used for determining a virtual circuit to be checked and target information corresponding to the virtual circuit to be checked according to an SCD file, wherein the SCD file comprises identification information of virtual terminals and topology information of the virtual terminals, the virtual circuit to be checked is formed by connecting at least two virtual terminals, and the target information comprises the topology information of each virtual terminal in the virtual circuit to be checked.

In some embodiments, the virtual circuit checking apparatus further includes:

and the sample acquisition module is used for acquiring a sample set, wherein the sample set comprises at least one virtual loop with a label.

And the vectorization processing module is used for vectorizing target information corresponding to the marked virtual loop in the sample set by using a preprocessing network constructed to obtain a first characteristic.

The training module is used for training a pre-constructed classification model based on the first characteristics until the classification model meets preset requirements, and the classification model is used for checking whether the connection relation of the virtual terminals is correct according to the input characteristics of the virtual circuits.

And the check model acquisition module is used for determining the check model according to the preprocessing network and the classification model meeting the requirements.

In some embodiments, the classification model includes a preprocessing network and a classification model, and the training module includes:

and the training data determining unit is used for determining a training set and a verification set according to the first characteristics of each virtual loop in the sample set.

And the first predicted value acquisition unit is used for training each base learner according to the first characteristics in the training set by adopting a K-fold cross validation mode to obtain each trained base learner and a first predicted value output by each base learner.

And a second predicted value obtaining unit configured to input the first features in the verification set to each of the base learners after training, respectively, to obtain second predicted values output by the base learners.

And the feature acquisition unit is used for determining a second feature according to the first predicted value and determining a third feature according to the second predicted value.

The training unit is used for training the classifier according to the second characteristic and the third characteristic until the classifier meets the preset requirement.

In some embodiments, the training module further comprises:

and a variance calculating unit configured to calculate variances of the first features for the first features of the virtual circuits in the sample set.

And the target first feature acquisition unit is used for determining the target first feature according to the variance.

Correspondingly, the training unit is used for training the pre-constructed classification model based on the target first feature.

In some embodiments, the check model includes a preprocessing network and a classification model, and the check module includes:

and the feature extraction unit is used for carrying out vectorization processing on the target information based on the preprocessing network to obtain features to be checked.

And the checking unit is used for inputting the checking characteristics into the classification model to obtain a checking result output by the classification model.

In some embodiments, the topology information includes a signal description of the virtual terminal and a name of the intelligent electronic device corresponding to the virtual terminal, and the checking module further includes:

and the word segmentation unit is used for carrying out word segmentation on the signal description in the target information to obtain a word segmentation result.

And the splitting unit is used for splitting the names in the target information to obtain splitting results.

And the vectorization processing unit is used for vectorizing the word segmentation result and the splitting result respectively to obtain signal characteristics and name characteristics.

And the characteristic splicing unit is used for splicing the signal characteristic and the name characteristic to obtain the characteristic to be checked.

It should be noted that, because the content of information interaction and execution process between the above devices/units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein.

Embodiment III:

fig. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in fig. 4, the terminal device 4 of this embodiment includes: at least one processor 40 (only one processor is shown in fig. 4), a memory 41 and a computer program 42 stored in the memory 41 and executable on the at least one processor 40, the processor 40 implementing the steps in any of the various method embodiments described above when executing the computer program 42.

The terminal device 4 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, etc. The terminal device may include, but is not limited to, a processor 40, a memory 41. It will be appreciated by those skilled in the art that fig. 4 is merely an example of the terminal device 4 and is not meant to be limiting as to the terminal device 4, and may include more or fewer components than shown, or may combine certain components, or different components, such as may also include input-output devices, network access devices, etc.

The processor 40 may be a central processing unit (Central Processing Unit, CPU), the processor 40 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 41 may in some embodiments be an internal storage unit of the terminal device 4, such as a hard disk or a memory of the terminal device 4. The memory 41 may in other embodiments also be an external storage device of the terminal device 4, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the terminal device 4. Further, the memory 41 may also include both an internal storage unit and an external storage device of the terminal device 4. The memory 41 is used for storing an operating system, application programs, boot loader (BootLoader), data, other programs, etc., such as program codes of the computer program. The memory 41 may also be used for temporarily storing data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

The embodiment of the application also provides a network device, which comprises: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, which when executed by the processor performs the steps of any of the various method embodiments described above.

Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a processor, implements steps for implementing the various method embodiments described above.

Embodiments of the present application provide a computer program product enabling a terminal device to carry out the steps of the method embodiments described above when the computer program product is run on the terminal device.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing device/terminal apparatus, recording medium, computer Memory, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other manners. For example, the apparatus/network device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. A virtual circuit checking method, comprising:

2. The virtual circuit checking method according to claim 1, wherein the checking model includes a preprocessing network and a classification model, the inputting the target information into the trained checking model for checking, and obtaining the checking result output by the checking model includes:

3. The virtual circuit checking method of claim 2, wherein the topology information includes a signal description of the virtual terminal and a name of an intelligent electronic device corresponding to the virtual terminal;

Splitting the name in the target information to obtain a splitting result;

4. The virtual circuit verification method of claim 1, wherein the verification model is determined by:

5. The virtual circuit verification method of claim 4, wherein the classification model comprises a plurality of basis learners and a classifier, the training of the pre-constructed classification model based on the first feature until the classification model meets a preset requirement comprises:

6. The virtual circuit verification method of claim 4, wherein prior to the training of the pre-constructed classification model based on the first feature, further comprising:

determining a target first feature from the variance;

7. A virtual circuit checking device, comprising:

8. The virtual circuit verification apparatus of claim 7, wherein the verification model comprises a preprocessing network and a classification model, the verification module comprising:

the feature extraction unit is used for carrying out vectorization processing on the target information based on the preprocessing network to obtain features to be checked;

9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 6 when executing the computer program.

10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 6.