CN116720468A - Method for constructing unit library time sequence model by combining neural network - Google Patents

Method for constructing unit library time sequence model by combining neural network Download PDF

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CN116720468A
CN116720468A CN202310695252.XA CN202310695252A CN116720468A CN 116720468 A CN116720468 A CN 116720468A CN 202310695252 A CN202310695252 A CN 202310695252A CN 116720468 A CN116720468 A CN 116720468A
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CN116720468B (en
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郭静静
宁雪洁
蔡志匡
王子轩
刘璐
谢祖帅
郭宇锋
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Nanjing University of Posts and Telecommunications
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Abstract

The application discloses a method for constructing a unit library time sequence model by combining a neural network, and belongs to the technical field of calculation, calculation or counting. The method comprises the following steps: providing a unit time sequence library modeling method based on a current source model, and simultaneously overcoming delay calculation errors caused by multiport input; in combination with neural network training prediction models, model predictions are used instead of traditional look-up table forms. And combining the unit time sequence library model with the neural network to perform static time sequence analysis, and performing delay calculation, so that the time sequence analysis precision and the operation efficiency are improved.

Description

Method for constructing unit library time sequence model by combining neural network
Technical Field
The application belongs to the field of integrated circuit EDA (Electronics Design Automation, electronic design automation), and particularly discloses a method for constructing a unit library time sequence model by combining a neural network, belonging to the technical field of calculation, calculation or counting.
Background
Static timing analysis is an exhaustive analysis method that calculates and checks whether the setup time and hold time of each flip-flop in the circuit and other path-based delay requirements are met, according to the requirements of the synchronous circuit design and the topology of the circuit netlist. The static timing analysis is based on the premise that a designer firstly requests the static timing analysis, and then a timing analysis tool analyzes the static timing analysis according to a specific timing model to give a correct timing report. In static timing analysis, the unit delay refers to the delay inside the unit, i.e. the delay information from the input port to the output port of the unit.
The timing check is calculated from the delay values of internal timing arcs in a cell library, typically a look-up table model, by which the delay of the cell is obtained. The first proposed look-up table model is a nonlinear delay model (Non-linear Delay Model, NLDM), and the delay of the unit is obtained by looking up the index values of various combinations of the input switching time of the unit input pins and the total output capacitance of the unit output pins. The cell output load includes capacitance and interconnect resistance, but NLDM assumes the output load is purely capacitive and ignores the interconnect resistance. With the development of advanced technology, the characteristic size of the transistor is further reduced, the nonlinear phenomenon of the output waveform of the unit gate is serious, and the output load of the unit also needs to comprise an interconnection line resistor, so that the NLDM model precision is poor, and the requirement of accurately modeling the output waveform of the unit gate cannot be met. Under the advanced technology, the modeling of the output waveform of the unit gate by using the current source model (Current Source Model, CSM) is more accurate, and the static time sequence analysis is more accurate. The CSM consists of a driving model and a receiving model, wherein the driving model is a nonlinear current source based on time and voltage, and the driving resistance of the nonlinear current source is infinite, so that the CSM can accurately model the output waveform of the unit even if the driving resistance of the unit gate is far smaller than the interconnection resistance.
The conventional unit library timing modeling technology can solve the timing library modeling problem of single-input-port units such as inverters and the like, and can characterize the timing information of the single-input-port units. When dealing with a multiple input port unit such as a nand gate, nor gate, etc., it is generally assumed that there is only one input switch during transmission, while the other inputs of the gate remain fixed, but in practice the multiple input delay is different from the single input delay, which assumption may lead to timing violations. Therefore, existing cell library timing modeling techniques are unable to accurately analyze the static timing of multiport input cells.
The CSM-based cell library can obtain the time sequence information of cell delay and cell output signal conversion, and meanwhile, the model takes various factors causing delay errors into consideration to perform output signal modeling more accurately, wherein the various factors causing the delay errors comprise nonlinear loads, complex input waveforms, coupling capacitors and the like. The time sequence model based on the current source is time-varying, and the output drive of the unit is modeled by controlling the current source through voltage, so that the model precision is improved. However, the existing simulation and signing tools are based on the combination of closed expression and lookup tables for driving modeling, when circuits with more than billions of transistors are processed, the calculation complexity is high, the lookup time of the lookup tables is long, and therefore the static time sequence analysis time is long, the chip design period is long, and the design cost is high.
In summary, the present application proposes a method for building a cell library timing model in combination with a neural network to overcome the above-mentioned drawbacks.
Disclosure of Invention
The application aims to overcome the defects of the prior art, and provides a method for constructing a unit library time sequence model by combining a neural network, which aims to solve the technical problems that delay calculation errors are caused by the fact that a multi-port is assumed to be a single port by the prior unit library time sequence modeling technology and running time is long by using a neural network training prediction model to replace a traditional lookup table form by applying the unit time sequence model by combining the neural network to static time sequence analysis in consideration of the fact that components of the multi-port input unit time sequence library model are related to voltage values of all ports.
The application adopts the following technical scheme for realizing the purposes of the application:
a method for constructing a unit library time sequence model combined with a neural network comprises the following steps:
step one, building a unit model, presetting port voltages, and obtaining current values of all ports under different preset port voltages;
calculating unit model component data according to different preset port voltages;
thirdly, constructing a data set by taking the port voltage as an index in a mode that the port voltage is matched with the corresponding unit model component data, and training a neural network by using the data set;
inputting the input port voltage as a characteristic value of the neural network, and acquiring unit model component data and an output port voltage predicted value;
fitting the output port voltage waveform according to the unit model component data and the output port voltage predicted value.
As a further optimization scheme of the unit library time sequence model construction method combined with the neural network, the method for constructing the unit model comprises the following steps:
modeling each input port of the unit model to obtain an internal equivalent circuit of each input port, wherein the input port equivalent circuit comprises: the input port capacitor, the input port calibration capacitor and the miller capacitor are connected with the input port, the input port capacitor positive plate, the input port calibration capacitor positive plate and the miller capacitor positive plate are grounded, and the miller capacitor negative plate is used as a connection point of an equivalent circuit in the input port;
modeling the output port of the unit model to obtain an internal equivalent circuit of the output port, wherein the equivalent circuit of the output port comprises: the output port current source and the output port capacitor are connected, the negative electrode of the output port current source is used as a connection point of an internal equivalent circuit of the output port, the positive electrode of the output port current source is grounded, the positive electrode of the output port capacitor is connected with the negative electrode of the output port current source and the output port, and the connection point of the internal equivalent circuit of the output port is connected with the connection point of the internal equivalent circuit of the input port.
As a still further optimization scheme of the cell library timing model construction method combined with the neural network, the cell model component data in the second step includes: input port capacitance, miller capacitance, input port calibration capacitance, output port current source equivalent current, output port capacitance.
As a still further optimization scheme of the unit library timing model construction method combined with the neural network, when the unit is a two-input AND gate unit, the unit model comprises: the first input port internal equivalent circuit, the second input port internal equivalent circuit and the output port internal equivalent circuit are composed of a first input port capacitor, a first input port calibration capacitor and a first miller capacitor, the second input port internal equivalent circuit is composed of a second input port capacitor, a second input port calibration capacitor and a second miller capacitor, and the output port internal equivalent circuit connection point is connected with the first input port internal equivalent circuit connection point and the second input port internal equivalent circuit connection point.
As a further optimization scheme of the unit library time sequence model construction method combined with the neural network, the specific method for calculating the unit model component data according to different preset port voltages comprises the following steps: first input port capacitance C 1 From the following componentsObtaining the capacitance value C of the second input port 2 By->Obtaining the capacitance value C of the output port o By->Obtaining a first Miller capacitance value C m1 Second Miller capacitance value C m2 By->Obtaining the equivalent current I of the current source of the output port o From i o +I o Obtain the input port calibration capacitance value from its linear correlation with the input port capacitance value, where i =0 1 、i 2 、i o The current values of the first input port, the second input port and the output port are V 1 、V 2 、V o C is the preset voltage value of the first input port, the second input port and the output port mi I=1, 2 for the ith miller capacitance value.
As a further optimization scheme of the unit library time sequence model construction method combined with the neural network, the fifth step is to fit the expression of the output port voltage waveform according to the unit model component data and the output port voltage predicted value as follows:
wherein V is o (t)、V o (t+Δt) is the output voltage value at time t and t+Δt, respectively, C m1 (t)、C m2 (t) is the first and second Miller capacitance values at time t, V 1 (t)、V 1 (t+Deltat) is the voltage value of the first input port at the time t and the time t+Deltat respectively, V 2 (t)、V 2 (t+Deltat) is the voltage value of the second input port at the moment t and the moment t+Deltat respectively, I o (t) is the output port voltage value at the moment t, delta t is the time interval, C o (t) is the capacitance value of the output port at the moment t, C calb1 (t)、C calb2 (t) calibrating capacitance values of the first input port and the second input port respectively at the moment t and the moment t+delta t, C i* And (t) is the capacitance value of the input port of the next AND gate unit, wherein the output of the last AND gate unit is connected to the next AND gate unit at the moment t.
A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the above method.
The application adopts the technical scheme and has the following beneficial effects:
(1) The application provides a modeling method of a unit time sequence library based on a current source model, which models each input port of a unit by constructing an input branch comprising input port capacitance and Miller capacitance, and adds calibration capacitance to all ports in order to more accurately represent output port voltage.
(2) The application combines the neural network, replaces the traditional form of relying on a lookup table stored in a memory with model prediction, replaces lookup with calculation, predicts the component parameters and the output port voltage according to the input port voltage through the neural network model, calculates the unit delay by the prediction result, combines the neural network with the unit time sequence library model based on the current source model, improves the precision operation speed of static time sequence analysis and improves the efficiency.
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The accompanying drawings are included to provide a further understanding of the application and together with the description serve to explain and do not limit the application.
FIG. 1 is a flow chart of a method of building a cell library timing model in conjunction with a neural network of the present application.
Fig. 2 is a schematic diagram of the current source based cell internal model of the present application.
FIG. 3 is a schematic diagram of a neural network model incorporating the present application.
The reference numerals in the figures illustrate: c (C) 1 First input port capacitance, C 2 Second input port capacitance, C o Output port capacitance, C m1 First Miller capacitance, C m2 Second Miller capacitance, C calb1 First, theAn input port for calibrating capacitance, C calb2 Calibrating capacitance at second input port, I o Output port current source.
Detailed Description
The technical scheme of the application is further described in detail below with reference to the accompanying drawings and examples.
In order that the objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, in which some, but not all embodiments of the application are illustrated. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on embodiments of the present application, are intended to be within the scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
The application is further described below with reference to the accompanying drawings. The method for constructing the unit library time sequence library model combined with the neural network can carry out time sequence modeling on the circuit standard unit under the 45nm process of the OpenTimer. The method for constructing a timing model according to the present application will be described by way of example with reference to a two-input and gate unit. The time sequence model construction method is shown in fig. 1 and comprises S1-S5.
S1, constructing a two-input AND gate model, presetting port voltages, wherein the voltages of the two input ports are the same, V 1 ＝V 2 The input port voltage is a rising voltage of-0.05V to 1.15V, and the output port voltage V o And obtaining each port current value under the condition of preset port voltage by HSPICE simulation for the actual output voltage under the excitation of the input port voltage.
S2, as shown in FIG. 2, it is assumed that the two-input AND gate unit model is internally provided with a first input port capacitor C 1 Second input port capacitance C 2 Output port capacitance C o First Miller capacitance C m1 Second Miller capacitance C m2 First input port calibration capacitance C calb1 Second input port calibration capacitance C calb2 And output port current source I o These components are composed of a first input port capacitor C 1 Positive plate, first input port calibration capacitance C calb1 Positive plate, first Miller capacitance C m1 The positive plate is connected with a first input port in1, a first input port capacitor C 1 Negative plate, first input port calibration capacitance C calb1 The negative plates are all grounded, the first Miller capacitance C m1 The negative plate is used as a connection point of an equivalent circuit in the first input port in1, and the second input port capacitor C 2 Positive plate, second input port calibration capacitance C calb2 Positive plate, second miller capacitance C m2 The positive plate is connected with a second input port in2, and a second input port capacitor C 2 Negative plate, second input port calibration capacitance C calb2 The negative plates are all grounded, and the second Miller capacitance C m2 The negative plate is used as a connection point of an equivalent circuit in the second input port in2, and the current source I of the output port o The negative electrode is used as a connection point of an equivalent circuit in an output port Out, and the output port current source I o Positive electrode is grounded, and output port capacitor C o Positive plate and output port current source I o The negative electrode and the output port Out are connected. Considering the property of capacitor isolation direct current, when HSPICE simulation is performed, the input port voltage is considered to be a direct current signal or a ramp signal according to specific conditions, component data under different voltage values can be calculated according to the port voltage, and the first input port capacitor C 1 A second input port C 2 The result is obtained by the method (1),
output port capacitance C o The result is obtained by the step (2),
first Miller capacitance C m1 Second Miller C m2 The result is obtained by the step (3),
output port current source I o The result is obtained by the step (4),
i o +I o ＝0 (4)
the input port calibration capacitance is linearly related to the input port capacitance.
In the formulae (1) to (4), i 1 、i 2 、i o The current values of the first input port, the second input port and the output port are V 1 、V 2 、V o The preset voltage values of the first input port, the second input port and the output port are I o C is the equivalent current of the current source of the output port mi I=1, 2 for the ith miller capacitance value.
And S3, taking the port voltage as an index, constructing a data set in a mode of matching the port voltage with the corresponding component numerical value one by one, and training a neural network model by using the constructed data set.
As shown in fig. 3, the application sets the hidden layer of the neural network model as a single layer, and the prediction formula of the neural network is as follows (5):
wherein D is the number of neurons of an input layer, H is the number of neurons of a hidden layer, w is the weight of a neural network, x is an input value, y is an output value, sigma is an activation function sigmoid, the sigmoid function can better fit a curve in machine learning, and i is the sequence number of the neurons.
S4, inputting the input port voltage as a characteristic value of the neural network, and predicting the characteristic value by the trained neural network to comprise a first input port capacitor C 1 Second input port capacitance C 2 Output port capacitance C o First Miller capacitance C m1 Second Miller capacitance C m2 First input port calibration capacitance C calb1 Second input port calibration capacitance C calb2 And output port current source I o Model component data of (a) and output port voltage V o 。
S5, after model training is completed, the input port voltage enters a neural network model, and component data under the input port voltage is predicted, so that an output voltage value can be calculated, and further an output voltage waveform is obtained through iterative calculation according to a formula (6). The cell transfer delay is calculated from the waveforms of the input voltage and the output voltage.
In the formula (6), C i* The output of the upper AND gate unit is connected to the input port capacitance of the lower AND gate unit, delta t is the time interval, and the output port capacitance C o (t), first Miller capacitance C m1 (t), a second Miller capacitance C m2 (t), first input port calibration capacitance C calb1 (t), second input port calibration capacitance C calb2 (t) and output port current source I o The model component data of (t) is a value corresponding to time t.
The above specific embodiments and examples are specific support for the technical idea proposed by the present application, and the scope of protection of the present application is not limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical scheme according to the technical idea proposed by the present application still belong to the scope of protection of the technical scheme of the present application.

Claims (7)

1. The method for constructing the unit library time sequence model by combining the neural network is characterized by comprising the following steps of:
step one, building a unit model, presetting port voltages, and obtaining current values of all ports under different preset port voltages;
calculating unit model component data according to different preset port voltages;
thirdly, constructing a data set by taking the port voltage as an index in a mode that the port voltage is matched with the data of the corresponding unit model component, and training a neural network by using the data set;
inputting the input port voltage as a characteristic value of the neural network, and acquiring unit model component data and an output port voltage predicted value;
fitting the output port voltage waveform according to the unit model component data and the output port voltage predicted value.
2. The method for building a cell library timing model in combination with a neural network according to claim 1, wherein the method for building a cell model in the step one is as follows:
modeling each input port of the unit model to obtain an internal equivalent circuit of each input port, wherein the input port equivalent circuit comprises: the input port capacitor, the input port calibration capacitor and the miller capacitor are connected with the input port, the input port capacitor positive plate, the input port calibration capacitor positive plate and the miller capacitor positive plate are grounded, and the miller capacitor negative plate is used as a connection point of an equivalent circuit in the input port;
modeling the output port of the unit model to obtain an internal equivalent circuit of the output port, wherein the equivalent circuit of the output port comprises: the output port current source and the output port capacitor are connected, the negative electrode of the output port current source is used as a connection point of an internal equivalent circuit of the output port, the positive electrode of the output port current source is grounded, the positive electrode of the output port capacitor is connected with the negative electrode of the output port current source and the output port, and the connection point of the internal equivalent circuit of the output port is connected with the connection point of the internal equivalent circuit of the input port.
3. The method for building a time sequence model of a cell library in combination with a neural network according to claim 2, wherein the cell model component data in the step two comprises: input port capacitance, miller capacitance, input port calibration capacitance, output port current source equivalent current, output port capacitance.
4. The method for building a cell library timing model in combination with a neural network according to claim 2, wherein when the cell is a two-input and gate cell, the cell model comprises: the first input port internal equivalent circuit, the second input port internal equivalent circuit and the output port internal equivalent circuit are composed of a first input port capacitor, a first input port calibration capacitor and a first miller capacitor, the second input port internal equivalent circuit is composed of a second input port capacitor, a second input port calibration capacitor and a second miller capacitor, and the output port internal equivalent circuit connection point is connected with the first input port internal equivalent circuit connection point and the second input port internal equivalent circuit connection point.
5. The method for building a cell library timing model in combination with a neural network according to claim 4, wherein the specific method for calculating cell model component data according to different preset port voltages in the second step is as follows: first input port capacitance C 1 From the following componentsObtaining the capacitance value of the second input port>Obtaining the capacitance value C of the output port o By->Obtaining a first Miller capacitance value C m1 Second Miller capacitance value C m2 By->Obtaining the equivalent current I of the current source of the output port o From i o +I o Obtain the input port calibration capacitance value from its linear correlation with the input port capacitance value, where i =0 1 、i 2 、i o The current values of the first input port, the second input port and the output port are V 1 、V 2 、V o C is the preset voltage value of the first input port, the second input port and the output port mi I=1, 2 for the ith miller capacitance value.
6. The method for building a cell library timing model in combination with a neural network according to claim 5, wherein the fifth step fits the expression of the output port voltage waveform according to the cell model component data and the output port voltage predicted value to:
wherein V is o (t)、V o (t+Δt) is the output voltage value at time t and t+Δt, respectively, C m1 (t)、C m2 (t) is the first and second Miller capacitance values at time t, V 1 (t)、V 1 (t+Deltat) is the voltage value of the first input port at the time t and the time t+Deltat respectively, V 2 (t)、V 2 (t+Deltat) is the voltage value of the second input port at the moment t and the moment t+Deltat respectively, I o (t) is the output port voltage value at the moment t, delta t is the time interval, C o (t) is the capacitance value of the output port at the moment t, C calb1 (t)、C calb2 (t) calibrating capacitance values of the first input port and the second input port respectively at the moment t and the moment t+delta t, C i* And (t) is the capacitance value of the input port of the next AND gate unit, wherein the output of the last AND gate unit is connected to the next AND gate unit at the moment t.
7. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method of claim 1.
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