CN116719565A - Method, device, equipment and medium for starting chip - Google Patents

Method, device, equipment and medium for starting chip Download PDF

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Publication number
CN116719565A
CN116719565A CN202310700101.9A CN202310700101A CN116719565A CN 116719565 A CN116719565 A CN 116719565A CN 202310700101 A CN202310700101 A CN 202310700101A CN 116719565 A CN116719565 A CN 116719565A
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China
Prior art keywords
chip
program
digest value
verified
value
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CN202310700101.9A
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Chinese (zh)
Inventor
熊子涵
贾学强
丁微微
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Priority to CN202310700101.9A priority Critical patent/CN116719565A/en
Publication of CN116719565A publication Critical patent/CN116719565A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575Secure boot
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Storage Device Security (AREA)

Abstract

The application provides a method, a device, equipment and a medium for starting a chip, wherein the method for starting the chip comprises the following steps: calculating a first digest value of a program to be verified according to a preset digest algorithm; writing the program to be verified and the segment storage address number of the first digest value into a memory of a chip; responding to the power-on of a chip, and acquiring the program to be verified and the segment storage address number from the memory; the segmented storage address numbers are sequenced according to the number sequence to obtain corresponding storage addresses, the first digest value is read from the storage addresses, and the corresponding second digest value is calculated for the program to be verified according to the preset digest algorithm; and judging whether the first abstract value is the same as the second abstract value, and determining whether to start the chip according to a judging result. The scheme disclosed by the application increases the safety in the starting process of the chip.

Description

Method, device, equipment and medium for starting chip
Technical Field
The present application relates to the field of communications, and in particular, to a method, an apparatus, a device, and a medium for starting a chip.
Background
Before the chip is started, the corresponding software program needs to be loaded into the chip, whether the program software loaded into the chip is correct needs to be determined to ensure that the chip can be normally started, and the chip can execute normal functions only by loading the correct software program, if the wrong software program is loaded, the chip can be caused to have abnormal functions and even be damaged.
In the related technology of chip starting, when the chip is started, whether the condition of chip starting is met or not is judged by judging whether the check value of the software program written into the chip is consistent with a preset value, safety protection is lacked in the check process, and error writing can occur in the process of transmitting the check value, so that the safety of chip starting is not facilitated to be improved.
Disclosure of Invention
In view of this, the present application provides a method, apparatus, device and medium for chip start, which at least solves the above-mentioned problems in the related art of chip start, in which, when a chip is started, whether the condition of chip start is met is judged by whether the verification value of the software program written into the chip is consistent with the preset value, the safety protection is lacking in the verification process, and the verification error may occur due to the erroneous writing in the verification value transmission process, which is not beneficial to improving the safety of chip start.
Based on the above objects, an aspect of an embodiment of the present application provides a method for chip start-up, including: calculating a first digest value of a program to be verified according to a preset digest algorithm; writing the program to be verified and the segment storage address number of the first digest value into a memory of a chip; responding to the power-on of a chip, and acquiring the program to be verified and the segment storage address number from the memory; the segmented storage address numbers are sequenced according to the number sequence to obtain corresponding storage addresses, the first digest value is read from the storage addresses, and the corresponding second digest value is calculated for the program to be verified according to the preset digest algorithm; and judging whether the first abstract value is the same as the second abstract value, and determining whether to start the chip according to a judging result.
In some embodiments, the step of writing the segment storage address number of the program to be verified and the first digest value into the memory of the chip comprises: the storage addresses corresponding to the first abstract value are segmented and then arranged in disorder, so that segmented storage address numbers of the first abstract value are obtained; and writing the program to be verified and the segment address number into a memory of a chip.
In some embodiments, the step of segmenting the storage address corresponding to the first digest value and then arranging the segmented storage address in an out-of-order manner to obtain the segmented storage address number of the first digest value includes: converting the first abstract value into an authentication tag with a preset length through a preset encryption algorithm; and grouping the authentication tags according to a preset grouping unit and arranging the authentication tags according to disorder to obtain the segmented storage address numbers of the first abstract value.
In some embodiments, the step of grouping the authentication tags according to a preset grouping unit and arranging the authentication tags according to an out-of-order, and obtaining the segment storage address number of the first digest value includes: grouping the authentication tags according to a preset grouping unit; and the random address generator is used for scrambling the sequence after grouping and recording the scrambled numbers to obtain the segmented storage address numbers of the first abstract value.
In some embodiments, the step of writing the program to be verified and the segment address number into a memory of a chip comprises: encrypting the segment address number and the program to be verified through the preset encryption algorithm, and writing the encrypted segment address number and the program to be verified into a memory of the chip; writing the public key of the preset encryption algorithm into the memory of the chip.
In some embodiments, the pre-digest algorithm comprises a secure hash algorithm.
In some embodiments, the step of determining whether the first digest value and the second digest value are the same, and determining whether to perform the chip start according to the determination result includes: and responding to the fact that the first digest value and the second digest value are the same, and starting the chip by sending a starting signal to a pin of the chip.
In another aspect of the embodiment of the present application, there is also provided a device for starting a chip, including: the first module is used for calculating a first digest value of the program to be verified according to a preset digest algorithm; the second module is used for writing the program to be verified and the segment storage address number of the first digest value into the memory of the chip; the third module is used for responding to the power-on of the chip and acquiring the program to be verified and the segment storage address number from the memory; a fourth module, configured to sort the segment storage address numbers according to a number sequence to obtain corresponding storage addresses, read the first digest value from the storage addresses, and calculate a corresponding second digest value for the program to be verified according to the preset digest algorithm; and a fifth module, configured to determine whether the first digest value and the second digest value are the same, and determine whether to perform chip start according to a determination result.
In another aspect of the embodiment of the present application, there is also provided an electronic device including at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor performing the steps of the method described above.
In another aspect of the embodiments of the present application, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The application has at least the following beneficial effects: when the chip is electrified, the method firstly reads the program to be verified and the segmented storage address number of the first abstract value, and obtains the storage address of the first abstract value and reads the first abstract value after reordering the segmented address numbers in hardware, wherein the disordered address number is known in the chip but not known by a third party, the disordered address number generated by software is random each time, and then the disordered address number is stored in a memory in the chip, so that the safety in the chip starting process can be effectively improved, and the problem of verification errors caused by misoperation of a verification value in the transmission process is avoided.
Further, when the software program is written into the chip, the corresponding first digest value is calculated by the software program, the storage addresses corresponding to the first digest value are segmented and then arranged in disorder to obtain segmented storage address numbers, the segmented storage address numbers are written into the memory, the segmented address numbers are arranged in disorder, the safety of the first digest value in the transmission process is improved, the storage address numbers of the first digest value of the program to be verified are different each time, the safety of the first digest value of the software program written into the memory is improved, and the method is simple to operate and easy to expand.
Further, the digest value of the program to be verified is calculated through a preset digest algorithm, the digest value is further encrypted through an encryption algorithm to obtain an authentication tag, the authentication tag is arranged in disorder after being grouped according to a grouping unit to obtain segmented storage address numbers and written into a memory, and the first digest value is further encrypted and then the disorder address numbers are sent into the memory, so that the security of the program to be verified in the transmission process can be further improved.
Further, the segmented addresses after grouping are subjected to disordered sequencing through a random address generator to obtain storage address numbers, the sequence of each generated disordered address number is random, and then the random address numbers are written into a memory in the chip through an interface, only the inside of the chip is known but not known by a third party, so that the randomness of the storage address numbers and the safety of a transmission process are improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the solutions of the prior art, the drawings which are necessary for the description of the embodiments or the prior art will be briefly described, it being evident that the drawings in the following description are only some embodiments of the application and that other embodiments can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for starting a chip according to an embodiment of the present application;
fig. 2 is a schematic diagram of a software architecture for chip start provided in an embodiment of the present application;
fig. 3 is a schematic diagram of a chip-initiated hardware architecture according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a chip-starting apparatus according to an embodiment of the present application;
fig. 5 shows a schematic diagram of an electronic device according to an embodiment of the present application;
fig. 6 shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various alternative forms.
Furthermore, it should be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
One or more embodiments of the present application will be described below with reference to the accompanying drawings.
Based on the above objects, a first aspect of the embodiments of the present application proposes an embodiment of a method for chip activation. Fig. 1 shows a flowchart of a method for starting a chip according to an embodiment of the present application, where, as shown in fig. 1, the method for starting a chip includes:
s1, calculating a first digest value of a program to be verified according to a preset digest algorithm;
s2, writing the program to be verified and the segmented storage address number of the first digest value into a memory of a chip;
s3, responding to the power-on of the chip, and acquiring the program to be verified and the segmented storage address number from the memory;
s4, sorting the segment storage address numbers according to the number sequence to obtain corresponding storage addresses, reading the first digest value from the storage addresses, and calculating a corresponding second digest value for the program to be verified according to the preset digest algorithm;
and S5, judging whether the first abstract value is the same as the second abstract value, and determining whether to start the chip according to a judging result.
According to several embodiments of the present application, the step of writing the program to be verified and the segmented memory address number of the first digest value into the memory of the chip comprises: the storage addresses corresponding to the first abstract value are segmented and then arranged in disorder, so that segmented storage address numbers of the first abstract value are obtained; writing the program to be verified and the segment address number into the memory of the chip.
According to several embodiments of the present application, the step of obtaining the segment storage address number of the first digest value by sequentially segmenting and then arranging the storage addresses corresponding to the first digest value in an out-of-order manner includes: converting the first abstract value into an authentication tag with a preset length through a preset encryption algorithm; grouping the authentication tags according to a preset grouping unit and arranging the authentication tags according to disorder, and obtaining the segmented storage address numbers of the first abstract value.
According to several embodiments of the present application, the step of grouping authentication tags according to a preset grouping unit and arranging the authentication tags according to an out-of-order, and obtaining a segment storage address number of a first digest value includes: grouping the authentication tags according to a preset grouping unit; and the random address generator is used for scrambling the sequence after grouping and recording the scrambled numbers to obtain the segmented storage address numbers of the first abstract value.
According to several embodiments of the present application, the step of writing the program to be verified and the segment address number into the memory of the chip comprises: encrypting the segment address number and the program to be verified through a preset encryption algorithm, and writing the encrypted segment address number and the program to be verified into a memory of the chip; writing a public key of a preset encryption algorithm into a memory of the chip.
According to several embodiments of the present application, the pre-set digest algorithm comprises a secure hash algorithm.
According to several embodiments of the present application, the step of determining whether to perform chip start according to the determination result includes: in response to the first digest value and the second digest value being the same, the chip is booted by sending a boot signal to a pin of the chip.
The following is another embodiment of a method for starting a chip.
Fig. 2 is a schematic diagram of a software architecture for starting a chip provided in an embodiment of the present application, as shown in fig. 2, a program to be verified is first written directly into a corresponding position of a memory inside the chip through a second interface of the chip, then the program to be verified is calculated by a digest value calculation unit in the software architecture to obtain a first digest value, the first digest value is encrypted by an encryption algorithm of a first encryption calculation unit to obtain a corresponding authentication tag, and preferably, the authentication tag is further encrypted by the encryption algorithm and then written into the memory inside the chip through a third interface of the chip. Meanwhile, the storage addresses corresponding to the authentication tags are grouped according to a preset grouping unit and are arranged in a disordered manner to obtain segmented storage address numbers. Preferably, in this embodiment, the storage addresses of the authentication tags are grouped by a random address generator and then arranged in a disordered manner to obtain segmented storage address numbers, specifically, the first digest value is encrypted according to a 1024-bit encryption algorithm to obtain 1024-bit authentication tags, the storage addresses of the 1024-bit authentication tags are divided into 32 groups in units of 32 bits, and the numbers are 0 to 31, and the 32 groups of data are stored in an address space in a memory inside the chip in a random arrangement manner. Preferably, the 32 numbers can be disordered through a random number generator, and the data generated by the random number generator each time are random, so that the security performance can be improved, 1 random number is generated within the range of 0-31, for example, the generated random number is 19, and the data with the 19 numbers is written into the 0 position of the address space of the memory inside the chip; renumbering the remaining 30 sets of data to 0-30, and continuing to generate a random number in the range of 0-30 by a random number generator, for example, the generated random number is 8, which writes the new data with the number of 8 into the address space 1; and so on until the 32 address spaces are all full, and the 32 random numbers are recorded. In order to further improve the security, the 32 random numbers can be written into the corresponding position of the memory inside the chip through the first interface as the address storage number after being encrypted by the second encryption computing unit, and the authentication tag is written into the corresponding position of the memory through the second interface after being encrypted by the second encryption computing unit.
Fig. 3 is a schematic diagram of a hardware architecture of chip start provided in an embodiment of the present application, where, as shown in fig. 3, the hardware architecture for chip start includes: the memory (including a pre-written program to be authenticated, an encrypted authentication tag, and an encrypted segment storage address number), the first interface, the second interface, and the third interface, the calculation unit (a calculation unit that calculates a digest value by the same digest algorithm as that calculates the first digest value, such as a secure hash algorithm), the decryption unit (a calculation unit that performs decryption), the internal storage unit (a public key for storing decryption by the decryption unit), the verification unit, and the startup control unit. When the chip is powered on, the decryption unit reads the encrypted segment storage address number from the memory through the first interface and simultaneously obtains a public key for decrypting the encrypted segment storage address number from the internal storage unit, the encrypted segment storage address number is decrypted through the public key to obtain the segment storage address number, the segment storage address number is an disordered address number stored by an authentication tag of a first digest value which is calculated in advance through software of a program to be verified, the disordered address number is rearranged according to a serial number sequence (generally from a small number sequence to a large number sequence) to obtain a storage address of the authentication tag of the first digest value, then the encrypted authentication tag of the first digest value is read from the address of the memory through the second interface, simultaneously obtains a public key from the internal storage unit, decrypts the encrypted authentication tag of the first digest value through the public key to obtain the authentication tag of the first digest value, and then converts the authentication tag of the first digest value into a corresponding first digest value and sends the corresponding authentication tag to the verification unit. The computing unit reads the program to be verified from the memory through the third interface, calculates the program to be verified through a digest algorithm which is the same as that used for calculating the first digest value, obtains a second digest value, and sends the obtained second digest value to the verification unit. The verification unit compares the received first digest value with the second digest value and sends a comparison result to the starting control unit, when the first digest value is the same as the second digest value, the starting control unit outputs a starting signal to a pin of the chip to start the chip, and when the first digest value is different from the second digest value, the starting control unit does not output a control signal. The method increases the safety in the process of starting the chip, and can effectively avoid the problem of starting failure caused by misoperation.
In a second aspect of the embodiment of the present application, a device for starting a chip is provided, and fig. 4 shows a schematic diagram of a device for starting a chip provided in the embodiment of the present application, as shown in fig. 4, including: a first module 011, configured to calculate a first digest value of a program to be verified according to a preset digest algorithm; a second module 012, configured to write the program to be verified and the segment storage address number of the first digest value into a memory of the chip; a third module 013, configured to obtain the program to be verified and the segment storage address number from the memory in response to power-on of the chip; a fourth module 014, configured to sort the segment storage address numbers according to a number sequence to obtain a corresponding storage address, read the first digest value from the storage address, and calculate a corresponding second digest value for the program to be verified according to the preset digest algorithm; and a fifth module 015, configured to determine whether the first digest value and the second digest value are the same, and determine whether to perform chip start according to a determination result.
In some embodiments, the second module 012 is further to: the storage addresses corresponding to the first abstract value are segmented and then arranged in disorder, so that segmented storage address numbers of the first abstract value are obtained; writing the program to be verified and the segment address number into the memory of the chip.
In some embodiments, the second module 012 is further to: converting the first abstract value into an authentication tag with a preset length through a preset encryption algorithm; grouping the authentication tags according to a preset grouping unit and arranging the authentication tags according to disorder, and obtaining the segmented storage address numbers of the first abstract value.
In some embodiments, the second module 012 is further to: grouping the authentication tags according to a preset grouping unit; and the random address generator is used for scrambling the sequence after grouping and recording the scrambled numbers to obtain the segmented storage address numbers of the first abstract value.
In some embodiments, the second module 012 is further to: encrypting the segment address number and the program to be verified through a preset encryption algorithm, and writing the encrypted segment address number and the program to be verified into a memory of the chip; writing a public key of a preset encryption algorithm into a memory of the chip.
In some embodiments, the pre-digest algorithm comprises a secure hash algorithm.
In some embodiments, the fifth module 015 is further to: in response to the first digest value and the second digest value being the same, the chip is booted by sending a boot signal to a pin of the chip.
In a third aspect of the embodiment of the present application, an electronic device is provided, and fig. 5 is a schematic diagram of an electronic device provided in the embodiment of the present application. As shown in fig. 5, an electronic device provided by an embodiment of the present application includes the following modules: at least one processor 021; and a memory 022, the memory 022 storing computer instructions 023 executable on the processor 021, the computer instructions 023 when executed by the processor 021 implementing the steps of the method as described above, wherein the method comprises: calculating a first digest value of a program to be verified according to a preset digest algorithm; writing the program to be verified and the segment storage address number of the first digest value into a memory of a chip; responding to the power-on of a chip, and acquiring the program to be verified and the segment storage address number from the memory; the segmented storage address numbers are sequenced according to the number sequence to obtain corresponding storage addresses, the first digest value is read from the storage addresses, and the corresponding second digest value is calculated for the program to be verified according to the preset digest algorithm; and judging whether the first abstract value is the same as the second abstract value, and determining whether to start the chip according to a judging result.
The application also provides a computer readable storage medium. Fig. 6 is a schematic diagram of a computer-readable storage medium according to an embodiment of the present application. As shown in fig. 6, the computer-readable storage medium 031 stores a computer program 032 which, when executed by a processor, performs the steps of the method as described above.
Finally, it should be noted that, as will be understood by those skilled in the art, implementing all or part of the above-described methods in the embodiments may be implemented by a computer program to instruct related hardware, and the program of the method for setting system parameters may be stored in a computer readable storage medium, where the program may include the flow of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
Furthermore, the method disclosed according to the embodiment of the present application may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. The above-described functions defined in the methods disclosed in the embodiments of the present application are performed when the computer program is executed by a processor.
Furthermore, the above-described method steps and system units may also be implemented using a controller and a computer-readable storage medium storing a computer program for causing the controller to implement the above-described steps or unit functions.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or general purpose or special purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, D0L, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present application has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the application, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the application, and many other variations of the different aspects of the embodiments of the application as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present application.

Claims (10)

1. A method for chip activation, comprising:
calculating a first digest value of a program to be verified according to a preset digest algorithm;
writing the program to be verified and the segment storage address number of the first digest value into a memory of a chip;
responding to the power-on of a chip, and acquiring the program to be verified and the segment storage address number from the memory;
the segmented storage address numbers are sequenced according to the number sequence to obtain corresponding storage addresses, the first digest value is read from the storage addresses, and the corresponding second digest value is calculated for the program to be verified according to the preset digest algorithm;
and judging whether the first abstract value is the same as the second abstract value, and determining whether to start the chip according to a judging result.
2. The method of claim 1, wherein the step of writing the segmented storage address number of the program to be authenticated and the first digest value into the memory of the chip comprises:
the storage addresses corresponding to the first abstract value are segmented and then arranged in disorder, so that segmented storage address numbers of the first abstract value are obtained;
and writing the program to be verified and the segment address number into a memory of a chip.
3. The method of claim 2, wherein the step of segmenting the storage address corresponding to the first digest value and then arranging the segmented storage address to obtain the segmented storage address number of the first digest value comprises:
converting the first abstract value into an authentication tag with a preset length through a preset encryption algorithm;
and grouping the authentication tags according to a preset grouping unit and arranging the authentication tags according to disorder to obtain the segmented storage address numbers of the first abstract value.
4. The method of claim 3, wherein the step of grouping the authentication tags in a preset grouping unit and arranging the authentication tags in an out-of-order manner to obtain the segment storage address number of the first digest value comprises:
grouping the authentication tags according to a preset grouping unit;
and the random address generator is used for scrambling the sequence after grouping and recording the scrambled numbers to obtain the segmented storage address numbers of the first abstract value.
5. The method of claim 4, wherein the step of writing the program to be verified and the segment address number into a memory of a chip comprises:
encrypting the segment address number and the program to be verified through the preset encryption algorithm, and writing the encrypted segment address number and the program to be verified into a memory of the chip;
writing the public key of the preset encryption algorithm into the memory of the chip.
6. The method of claim 1, wherein the pre-digest algorithm comprises a secure hash algorithm.
7. The method of claim 1, wherein the step of determining whether the first digest value and the second digest value are the same, and determining whether to perform the chip start-up according to the determination result comprises:
and responding to the fact that the first digest value and the second digest value are the same, and starting the chip by sending a starting signal to a pin of the chip.
8. A chip-enabled device, comprising:
the first module is used for calculating a first digest value of the program to be verified according to a preset digest algorithm;
the second module is used for writing the program to be verified and the segment storage address number of the first digest value into the memory of the chip;
the third module is used for responding to the power-on of the chip and acquiring the program to be verified and the segment storage address number from the memory;
a fourth module, configured to sort the segment storage address numbers according to a number sequence to obtain corresponding storage addresses, read the first digest value from the storage addresses, and calculate a corresponding second digest value for the program to be verified according to the preset digest algorithm;
and a fifth module, configured to determine whether the first digest value and the second digest value are the same, and determine whether to perform chip start according to a determination result.
9. An electronic device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-7.
10. A computer readable storage medium storing a computer program which when executed by a processor performs the steps of the method of any one of claims 1-7.
CN202310700101.9A 2023-06-13 2023-06-13 Method, device, equipment and medium for starting chip Pending CN116719565A (en)

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CN202310700101.9A CN116719565A (en) 2023-06-13 2023-06-13 Method, device, equipment and medium for starting chip

Applications Claiming Priority (1)

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CN202310700101.9A CN116719565A (en) 2023-06-13 2023-06-13 Method, device, equipment and medium for starting chip

Publications (1)

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CN116719565A true CN116719565A (en) 2023-09-08

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