CN116710902A

CN116710902A - Flash memory device, memory control method and electronic equipment

Info

Publication number: CN116710902A
Application number: CN202080108185.1A
Authority: CN
Inventors: 马崇良; 丁强; 刘江卫
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2023-09-05
Also published as: WO2022140933A1

Abstract

A flash memory device (700), a memory control method and an electronic apparatus, the device comprising a control module (710) and a flash memory module (720), the control module (710) being configured to: when a data reading command is received, determining a physical address of the first data in the flash memory module (720) from an address mapping table according to a logical address of the first data to be read; the first data is read from the flash memory module (720) according to the physical address, wherein the flash memory module (720) comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, and the address mapping table is generated by the control module (710) according to the address and the configuration information of each physical page in the at least one physical page. The address mapping table can be quickly generated according to the address and the configuration information of each physical page in at least one physical page, and the processing efficiency can be improved.

Description

Flash memory device, memory control method and electronic equipment

Technical Field

The present application relates to the field of storage technologies, and in particular, to a flash memory device, a storage control method, and an electronic apparatus.

Background

The data stored in the nonvolatile memory will not disappear after the current is turned off and can be stored. Flash Memory (Flash Memory) is widely used as a type of nonvolatile Memory. Compared with other nonvolatile memories, the flash memory has the advantages of large capacity, high storage efficiency per unit area and the like, but has the defects of relatively time consumption for establishing address mapping, slower speed for dynamically updating and using information, requirement for setting management pages and the like.

Disclosure of Invention

In view of this, a flash memory device, a method and an electronic apparatus are provided.

In a first aspect, an embodiment of the present application provides a flash memory device, the device including a control module and a flash memory module, the control module configured to:

when a data reading command is received, determining a physical address of first data in the flash memory module from an address mapping table according to a logic address of the first data to be read; reading the first data from the flash memory module according to the physical address,

The flash memory module comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, the configuration information comprises a logical address of the data stored in the data field, and the address mapping table is generated by the control module according to the address and the configuration information of each physical page in the at least one physical page.

According to an embodiment of the application, the flash memory module comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, and the configuration information comprises a logical address of the data stored in the data field. By storing the configuration information in the information field of the physical pages, the control module can quickly generate an address mapping table according to the address and the configuration information of each physical page in at least one physical page, so that the generation speed of the address mapping table can be improved, the processing efficiency is improved, and pages for managing the configuration information are not required to be set, thereby saving the storage space. When the flash memory device receives the data reading command, the control module can directly determine the physical address of the data to be read in the flash memory module through the address mapping table according to the logical address of the data to be read, and the data reading is carried out according to the physical address, so that the data reading efficiency can be improved.

In a first possible implementation manner of the flash memory device according to the first aspect, the control module is further configured to: when the address mapping signal is valid, respectively reading configuration information from the information domain of each physical page according to the address of each physical page in the at least one physical page; and generating an address mapping table according to the addresses of the physical pages and the configuration information.

When the address mapping signal is effective, the address of each physical page in at least one physical page in the flash memory module is taken as an index, configuration information is respectively read from the information domain of each physical page, and an address mapping table is generated according to the address of each physical page and the configuration information thereof, so that the generation speed of the address mapping table can be improved simply and quickly, and the processing efficiency is improved.

In a second possible implementation manner of the flash memory device according to the first aspect or the first possible implementation manner of the first aspect, the configuration information stored in the information field of each physical page in the at least one physical page further includes a state of the physical page to which the configuration information belongs, and the state of the physical page to which the configuration information belongs is used.

By the method, the address mapping table can be generated for the used physical page in the selected state, so that the number of mapping relations in the address mapping table can be reduced, the generation speed of the address mapping table can be increased, the data access speed can be increased, and the usability can be improved.

In a third possible implementation manner of the flash memory device according to the first possible implementation manner of the first aspect or the second possible implementation manner of the first aspect, the reading, according to an address of each physical page in the at least one physical page, configuration information from an information field of each physical page includes: and reading configuration information from the information fields of the physical pages in turn according to the order of the addresses of the physical pages in the at least one physical page. In this way, the reading efficiency of the configuration information can be improved.

In a fourth possible implementation form of the flash memory device according to the first possible implementation form of the first aspect as such or according to the third possible implementation form of the first aspect, the flash memory module further comprises a further physical page than the at least one physical page, the control module is further configured to: and when the flash memory device is powered on or the configuration information of any physical page in the flash memory module is changed, setting the address mapping signal to be valid.

When the flash memory device is powered on (namely initialized), the address mapping signal is set to be effective, and the mapping from the logical address to the physical address is triggered, so that the address mapping speed can be improved, the operation can be performed in parallel with other operations, and the initialization time is effectively saved.

When the configuration information of any physical page of the flash memory module changes, the address mapping signal is set to be effective, and the process of regenerating the address mapping table is triggered, so that the speed is high, the dynamic management efficiency of the address mapping can be improved, and the service performance is further improved.

In a fifth possible implementation manner of the flash memory device according to the fourth possible implementation manner of the first aspect, the configuration information stored in the information field of each physical page in the flash memory module further includes a number of erasures of the physical page, and the control module is further configured to: when a write data command is received, determining whether a logic address of second data to be written exists in the address mapping table; when the logical address of the second data does not exist in the address mapping table, selecting at least one first target page with idle state from other physical pages except the at least one physical page of the flash memory module; selecting a second target page from the at least one first target page according to the erasing times of each first target page and preset conditions; and writing the second data into the second target page, and updating configuration information of the second target page.

When writing data into the flash memory device, it can determine if there is a logic address of the second data to be written in the address mapping table, when there is no logic address of the second data in the address mapping table, it can select one physical page from other physical pages except at least one physical page of the flash memory module according to the idle state and erasing times, and write data, and update the configuration information of the physical page, so that when writing data, the written target page can be selected according to the state and erasing times of the physical page, realizing erasing balance, and improving the reliability of the flash memory device.

In a sixth possible implementation manner of the flash memory device according to the fifth possible implementation manner of the first aspect, the control module is further configured to: when the logical address of the second data exists in the address mapping table, determining the physical address of the second data in the flash memory module from the address mapping table according to the logical address of the second data; judging whether the residual storage space of the third target page corresponding to the physical address is larger than or equal to the storage space required by the second data; and when the remaining storage space of the third target page is larger than or equal to the storage space required by the second data, writing the second data into the third target page.

In this way, not only the writing efficiency of the second data but also the utilization rate of the storage space of the flash memory device can be improved.

In a seventh possible implementation manner of the flash memory device according to the sixth possible implementation manner of the first aspect, the control module is further configured to: when the remaining storage space of the third target page is smaller than the storage space required by the second data, selecting a fourth target page which is free and has the erasing times meeting the preset condition from other physical pages except the at least one physical page of the flash memory module; and writing the second data and the effective data in the third target page into the fourth target page, and respectively updating the configuration information of the third target page and the fourth target page.

By the method, when the storage space is insufficient, one physical page can be selected from other physical pages except at least one physical page of the flash memory module according to the idle state and the erasing times of the physical pages, data writing is performed, and configuration information of the physical page is updated at the same time, so that when the physical page corresponding to a logical address of data is replaced, a target page can be selected according to the state and the erasing times of the physical page, erasing balance is realized, and the reliability of the flash memory device is improved.

In a fifth possible implementation manner of the first aspect, in an eighth possible implementation manner of the flash memory device, the selecting, according to the number of times of erasing each first target page and a preset condition, a second target page from the at least one first target page includes: and determining the page with the least erasing times in the at least one first target page as a second target page. In this way, the page with the least erasing times can be selected every time data is written, so that erasing and writing balance is realized.

In a ninth possible implementation manner of the flash memory device according to the first aspect or one or more of the multiple possible implementation manners of the first aspect, the control module includes a cache sub-module, configured to store an address mapping table and a state of each physical page in the flash memory module.

The address mapping table and the states of pages read from the information fields of all physical pages of the flash memory module are stored in the cache sub-module, so that the control module is convenient to use, the frequency of reading configuration information from the flash memory module can be reduced, and the use efficiency is improved.

In a second aspect, an embodiment of the present application provides a memory control method, where the method is applied to a control module in a flash memory device, the flash memory device includes the control module and the flash memory module, and the method includes: when a data reading command is received, determining a physical address of first data in the flash memory module from an address mapping table according to a logic address of the first data to be read; reading the first data from the flash memory module according to the physical address,

According to an embodiment of the application, the flash memory module comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, and the configuration information comprises a logical address of the data stored in the data field. By storing the configuration information in the information field of the physical pages, the control module can quickly generate the address mapping table according to the address and the configuration information of each physical page in at least one physical page, so that the generation speed of the address mapping table can be increased, the processing efficiency is improved, and the page for managing the configuration information is not required to be arranged, thereby saving the storage space. When the flash memory device receives the data reading command, the control module can directly determine the physical address of the data to be read in the flash memory module through the address mapping table according to the logical address of the data to be read, and the data reading is carried out according to the physical address, so that the data reading efficiency can be improved.

In a first possible implementation manner of the storage control method according to the second aspect, the method further includes: when the address mapping signal is valid, respectively reading configuration information from the information domain of each physical page according to the address of each physical page in the at least one physical page; and generating an address mapping table according to the addresses of the physical pages and the configuration information.

In a second possible implementation manner of the second aspect or the first possible implementation manner of the second aspect, the configuration information stored in the information field of each physical page in the at least one physical page further includes a state of the physical page, and the state of the physical page is used.

In a third possible implementation manner of the storage control method according to the first possible implementation manner of the second aspect or the second possible implementation manner of the second aspect, the reading, according to an address of each physical page in the at least one physical page, configuration information from an information field of each physical page includes: and reading configuration information from the information fields of the physical pages in turn according to the order of the addresses of the physical pages in the at least one physical page. In this way, the reading efficiency of the configuration information can be improved.

In a fourth possible implementation manner of the memory control method according to one or more of the first possible implementation manner of the second aspect to the third possible implementation manner of the second aspect, the flash memory module further includes other physical pages than the at least one physical page, and the method further includes: and when the flash memory device is powered on or the configuration information of any physical page in the flash memory module is changed, setting the address mapping signal to be valid.

When the configuration information of any physical page of the flash memory module changes, the address mapping signal is set to be effective, the process of regenerating the address mapping table is triggered, the processing speed is high, the dynamic management efficiency of address mapping can be improved, and the service performance is further improved.

In a fifth possible implementation manner of the storage control method according to the fourth possible implementation manner of the second aspect, the configuration information stored in the information field of each physical page in the flash memory module further includes a number of erasures of the physical page, and the method further includes: when a write data command is received, determining whether a logic address of second data to be written exists in the address mapping table; when the logical address of the second data does not exist in the address mapping table, selecting at least one first target page with idle state from other physical pages except the at least one physical page of the flash memory module; selecting a second target page from the at least one first target page according to the erasing times of each first target page and preset conditions; and writing the second data into the second target page, and updating configuration information of the second target page.

In a sixth possible implementation manner of the storage control method according to the fifth possible implementation manner of the second aspect, the method further includes: when the logical address of the second data exists in the address mapping table, determining the physical address of the second data in the flash memory module from the address mapping table according to the logical address of the second data; judging whether the residual storage space of the third target page corresponding to the physical address is larger than or equal to the storage space required by the second data; and when the remaining storage space of the third target page is larger than or equal to the storage space required by the second data, writing the second data into the third target page.

In a seventh possible implementation manner of the storage control method according to the sixth possible implementation manner of the second aspect, the method further includes: when the remaining storage space of the third target page is smaller than the storage space required by the second data, selecting a fourth target page which is free and has the erasing times meeting the preset condition from other physical pages except the at least one physical page of the flash memory module; and writing the second data and the effective data in the third target page into the fourth target page, and respectively updating the configuration information of the third target page and the fourth target page.

According to a fifth possible implementation manner of the second aspect, in an eighth possible implementation manner of the storage control method, the selecting, according to the number of erasures and a preset condition of each first target page, a second target page from the at least one first target page includes: and determining the page with the least erasing times in the at least one first target page as a second target page. In this way, the page with the least erasing times can be selected every time data is written in early time, so that erasing and writing balance is realized.

In a ninth possible implementation manner of the storage control method according to the second aspect or one or several possible implementation manners of the first aspect, the control module includes a cache sub-module, configured to store an address mapping table and a state of each physical page in the flash memory module.

In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a flash memory device connected to the processor, the flash memory device being as described in the first aspect or one or more of the many possible implementations of the first aspect.

These and other aspects of the application will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Drawings

Fig. 1 shows a schematic diagram of an access architecture of a flash memory.

Fig. 2 shows a schematic diagram of page partitioning of a flash memory.

Fig. 3 is a schematic diagram of an application scenario of a flash memory device according to an embodiment of the application.

Fig. 4 is a schematic diagram of an application scenario of a flash memory device according to an embodiment of the application.

Fig. 5 shows an application scenario of a flash memory device according to an embodiment of the application.

Fig. 6 shows a schematic structural diagram of a terminal device according to an embodiment of the present application.

Fig. 7 shows a block diagram of a flash memory device according to an embodiment of the present application.

Fig. 8 shows a schematic diagram of partitioning of physical pages of a flash memory device according to an embodiment of the present application.

Fig. 9 is a schematic diagram of an address mapping table of a flash memory device according to an embodiment of the application.

Fig. 10 is a schematic diagram illustrating an application scenario of a flash memory device according to an embodiment of the application.

Fig. 11 is a schematic diagram illustrating a processing procedure of a control module of a flash memory device according to an embodiment of the application.

Fig. 12 is a schematic diagram illustrating a processing procedure of a control module of a flash memory device according to an embodiment of the application.

Fig. 13 shows a flowchart of a memory control method according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the application will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following description in order to provide a better illustration of the application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present application.

Flash Memory (Flash Memory) is widely used as a non-volatile Memory in electronic devices such as mobile phones, digital cameras, computers, and single-chip computers.

Fig. 1 shows a schematic diagram of an access architecture of a flash memory. As shown in fig. 1, the flash memory 20 is applied to a System on Chip (SoC) 10, and the System on Chip 10 includes a CPU (Central Processing Unit ) 11, a RAM (Random Access Memory, random access memory) 12, a controller 13, and the flash memory 20.

Wherein the CPU 11 is configured to execute processing such as system control or general-purpose computation; the RAM 12 is used for storing instructions, intermediate data, calculation results, etc. in the CPU processing, and the RAM 12 includes an address management module; the controller 13 is configured to manage and control the flash memory 20, for example, to control configuration parameters, access modes, address management, etc. of the flash memory 20, and the controller 13 includes a page table cache (Translation Lookaside Buffer, TLB for short) for storing address mapping tables.

Typically, the flash memory 20 may be divided into a plurality of physical PAGEs (PAGE), and the size of the physical PAGEs may be set according to practical situations, for example 512B, 1KB, 2KB, etc. Flash memory manufactured by different manufacturers may vary in physical page size.

Fig. 2 shows a schematic diagram of the physical page partitioning of a flash memory. As shown in fig. 2, assuming that each physical PAGE is 1KB in size and the memory space of the flash memory 20 is 1MB, the flash memory 20 may be divided into 1024 physical PAGEs, PAGE0, PAGE1, PAGE2, PAGE3, …, PAGE1023 in sequence.

Since a logical Address (VA) is used when the CPU accesses the flash memory, the CPU cannot directly access the flash memory, and the CPU needs to convert the logical Address (VA) into a Physical Address (PA) of the flash memory before accessing the flash memory. That is, address management from logical address to physical address (VA-PA) is required.

At present, a CPU is usually used to perform address management on a flash memory by executing a software program, and when this method is adopted, several dedicated management pages need to be set in the flash memory to record usage information, bad block information and the like of the flash memory at any time, when the usage information (for example, the state of a page) of the flash memory, the bad block information and the like change, the CPU needs to execute the software program to write the changed information into the set management pages, and if the logical address to the physical address need to be mapped again, the CPU needs to read the usage information of each page in the flash memory from the management pages by the software program, so as to regenerate the address mapping table.

However, when address management is performed in the above manner, not only a dedicated space is required to be set for recording and maintaining information required by VA-PA mapping, but also usage information of the flash memory is read and VA-PA mapping is established through a software program, which is relatively time-consuming, and when dynamic management of VA-PA mapping is required, the speed is relatively slow, and the usability is affected.

In addition, during the use of the flash memory, some pages of data may be discarded and not used; multiple read-write operations may also cause Bit errors or unusable Bit cells (Bit cells) in certain pages of the flash memory, and thus unusable whole pages, where the usage information of the flash memory needs to be dynamically updated, but the speed is relatively slow when updated by software. And in some cases, a page may be continuously erased, but the operation may affect the service life of the flash memory, and reduce the reliability of the flash memory.

Therefore, in the use process of the flash memory, there are problems that the address mapping is relatively time-consuming to establish, the speed of dynamically updating the information is slow, and the reliability caused by unbalanced erasing is relatively low.

In order to solve the above technical problems, the present application provides a flash memory device. The flash memory device of the embodiment of the application can rapidly complete the mapping from the logical address to the physical address; the flash memory device of the embodiment of the application can also perform use balance according to the erasing times of the page when writing data. The flash memory device can be applied to the electronic equipment, so that the use performance of the flash memory in the electronic equipment is improved.

Fig. 3 is a schematic diagram of an application scenario of a flash memory device according to an embodiment of the application. As shown in fig. 3, the flash memory device 30 is built in a chip 50 of the electronic apparatus 40, and is connected to a processor 51 of the chip 50, and the processor 51 can perform operations such as reading and writing on the flash memory device 30.

Fig. 4 is a schematic diagram of an application scenario of a flash memory device according to an embodiment of the application. As shown in fig. 4, the flash memory device 30 is built in the electronic apparatus 40, but is external to the chip 50, and the flash memory device 30 is connected to the processor 51 of the chip 50, and the processor 51 can perform operations such as reading and writing on the flash memory device 30.

Fig. 5 shows an application scenario of a flash memory device according to an embodiment of the application. As shown in fig. 5, the flash memory device 30 is externally arranged on the electronic apparatus 40, and is connected to the electronic apparatus 40 in a pluggable manner, and the processor 41 of the electronic apparatus 40 can perform operations such as reading and writing on the flash memory device 30.

The electronic device of the present application may include a terminal device and a server, where the terminal device may be a smart phone, a netbook, a tablet computer, a notebook computer, a wearable electronic device (e.g., a smart bracelet, a smart watch, etc.), a TV, a virtual reality device, a sound, etc.

Fig. 6 shows a schematic structural diagram of a terminal device according to an embodiment of the present application. Taking the example that the terminal device is a mobile phone, fig. 6 shows a schematic structural diagram of the mobile phone 200.

The handset 200 may include a processor 210, an external memory interface 220, an internal memory 221, a usb interface 230, a charge management module 240, a power management module 241, a battery 242, an antenna 1, an antenna 2, a mobile communication module 251, a wireless communication module 252, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an earphone interface 270D, a sensor module 280, keys 290, a motor 291, an indicator 292, a camera 293, a display 294, a SIM card interface 295, and the like. The sensor module 280 may include a gyroscope sensor 280A, an acceleration sensor 280B, a proximity sensor 280G, a fingerprint sensor 280H, and a touch sensor 280K (of course, the mobile phone 200 may also include other sensors such as a temperature sensor, a pressure sensor, a distance sensor, a magnetic sensor, an ambient light sensor, an air pressure sensor, a bone conduction sensor, etc., which are not shown).

It should be understood that the structure illustrated in the embodiment of the present application is not limited to the specific embodiment of the mobile phone 200. In other embodiments of the application, the handset 200 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

Processor 210 may include one or more processing units such as, for example: the processor 210 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a memory, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a Neural network processor (Neural-network Processing Unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors. The controller may be a neural center or a command center of the mobile phone 200. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 210 for storing instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. The memory may hold instructions or data that the processor 210 has just used or recycled. If the processor 210 needs to reuse the instruction or data, it may be called directly from the memory. Repeated accesses are avoided and the latency of the processor 210 is reduced, thereby improving the efficiency of the system.

The display 294 is used to display images, videos, and the like. The display 294 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED) or an active-matrix organic light-emitting diode (matrix organic light emitting diode), a flexible light-emitting diode (flex), a mini, a Micro led, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the cell phone 200 may include 1 or N displays 294, N being a positive integer greater than 1. The display 294 may be used to display information entered by a user or provided to a user as well as various graphical user interfaces (graphical user interface, GUI). For example, the display 294 may display photographs, videos, web pages, or files, etc. For another example, the display 294 may display a graphical user interface. The graphical user interface includes status bars, hidden navigation bars, time and weather gadgets (widgets), and icons of applications, such as browser icons, etc. The status bar includes the name of the operator (e.g., chinese mobile), the mobile network (e.g., 4G), time, and the remaining power. The navigation bar includes a back (back) key icon, a home screen (home) key icon, and a forward key icon. Further, it is to be appreciated that in some embodiments, bluetooth icons, wi-Fi icons, external device icons, etc. may also be included in the status bar. It will also be appreciated that in other embodiments, a Dock may be included in the graphical user interface, a commonly used application icon may be included in the Dock, and the like. When the processor 210 detects a touch event of a user's finger (or a stylus, etc.) for a certain application icon, a user interface of the application corresponding to the application icon is opened in response to the touch event, and the user interface of the application is displayed on the display 294.

In the embodiment of the present application, the display 294 may be an integral flexible display, or a tiled display formed of two rigid screens and a flexible screen located between the two rigid screens may be used.

The camera 293 (front camera or rear camera, or one camera may be used as either a front camera or a rear camera) is used to capture still images or video. In general, the camera 293 may include a photosensitive element such as a lens group including a plurality of lenses (convex lenses or concave lenses) for collecting optical signals reflected by an object to be photographed and transmitting the collected optical signals to an image sensor. The image sensor generates an original image of the object to be photographed according to the optical signal.

Internal memory 221 may be used to store computer executable program code that includes instructions. The processor 210 executes various functional applications of the cellular phone 200 and data processing by executing instructions stored in the internal memory 221. The internal memory 221 may include a storage program area and a storage data area. The storage program area may store, among other things, code for an operating system, an application program (e.g., a camera application, a WeChat application, etc.), and so on. The storage data area may store data created during use of the handset 200 (e.g., images, video, etc. captured by the camera application), etc. In one possible implementation, the internal memory 221 may be a flash memory device.

In addition, the internal memory 221 may include a high-speed random access memory, and may further include a nonvolatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like.

The function of the sensor module 280 is described below.

The gyro sensor 280A may be used to determine the motion gesture of the cell phone 200. In some embodiments, the angular velocity of the cell phone 200 about three axes (i.e., x, y, and z axes) may be determined by the gyro sensor 280A. I.e., gyro sensor 280A may be used to detect the current motion state of the handset 200, such as shaking or being stationary.

When the display screen in the embodiment of the present application is a foldable screen, the gyro sensor 280A may be used to detect a folding or unfolding operation acting on the display screen 294. The gyro sensor 280A may report the detected folding operation or unfolding operation to the processor 210 as an event to determine the folding state or unfolding state of the display screen 294.

The acceleration sensor 280B can detect the magnitude of acceleration of the mobile phone 200 in various directions (typically three axes). I.e., gyro sensor 280A may be used to detect the current motion state of the handset 200, such as shaking or being stationary. When the display screen in the embodiment of the present application is a foldable screen, the acceleration sensor 280B may be used to detect a folding or unfolding operation acting on the display screen 294. The acceleration sensor 280B may report the detected folding operation or unfolding operation as an event to the processor 210 to determine the folding state or unfolding state of the display screen 294.

Proximity light sensor 280G may include, for example, a Light Emitting Diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The mobile phone emits infrared light outwards through the light emitting diode. The cell phone uses a photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object in the vicinity of the handset. When insufficient reflected light is detected, the handset may determine that there is no object in the vicinity of the handset. When the display screen in the embodiment of the present application is a foldable screen, the proximity light sensor 280G may be disposed on a first screen of the foldable display screen 294, and the proximity light sensor 280G may detect a folding angle or an unfolding angle of the first screen and the second screen according to an optical path difference of the infrared signal.

The gyro sensor 280A (or the acceleration sensor 280B) may transmit detected motion state information (such as angular velocity) to the processor 210. The processor 210 determines whether it is currently in a handheld state or a foot rest state based on the motion state information (e.g., when the angular velocity is not 0, it is indicated that the mobile phone 200 is in a handheld state).

The fingerprint sensor 280H is used to collect a fingerprint. The mobile phone 200 can utilize the collected fingerprint characteristics to realize fingerprint unlocking, access an application lock, fingerprint photographing, fingerprint incoming call answering and the like.

The touch sensor 280K, also referred to as a "touch panel". The touch sensor 280K may be disposed on the display screen 294, and the touch sensor 280K and the display screen 294 form a touch screen, which is also referred to as a "touch screen". The touch sensor 280K is used to detect a touch operation acting on or near it. The touch sensor may communicate the detected touch operation to the application processor to determine the touch event type. Visual output related to touch operations may be provided through the display 294. In other embodiments, the touch sensor 280K may also be disposed on the surface of the mobile phone 200 at a different location than the display 294.

Illustratively, the display 294 of the handset 200 displays a main interface that includes icons of a plurality of applications (e.g., camera applications, weChat applications, etc.). The user clicks on the icon of the camera application in the main interface by touching the sensor 280K, triggering the processor 210 to launch the camera application, opening the camera 293. The display 294 displays an interface of the camera application, such as a viewfinder interface.

The wireless communication function of the mobile phone 200 can be implemented by the antenna 1, the antenna 2, the mobile communication module 251, the wireless communication module 252, a modem processor, a baseband processor, and the like.

The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the handset 200 may be used to cover a single or multiple communication bands. Different antennas may also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 251 may provide a solution including 2G/3G/4G/5G wireless communication applied to the cell phone 200. The mobile communication module 251 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), etc. The mobile communication module 251 may receive electromagnetic waves from the antenna 1, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to the modem processor for demodulation. The mobile communication module 251 can amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna 1 to radiate. In some embodiments, at least some of the functional modules of the mobile communication module 251 may be provided in the processor 210. In some embodiments, at least some of the functional modules of the mobile communication module 251 may be disposed in the same device as at least some of the modules of the processor 210.

The modem processor may include a modulator and a demodulator. The modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used for demodulating the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low frequency baseband signal to the baseband processor for processing. The low frequency baseband signal is processed by the baseband processor and then transferred to the application processor. The application processor outputs sound signals through an audio device (not limited to speaker 270A, receiver 270B, etc.), or displays images or video through display screen 294. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be provided in the same device as the mobile communication module 251 or other functional module, independent of the processor 210.

The wireless communication module 252 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc. applied to the handset 200. The wireless communication module 252 may be one or more devices that integrate at least one communication processing module. The wireless communication module 252 receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 210. The wireless communication module 252 may also receive a signal to be transmitted from the processor 210, frequency modulate it, amplify it, and convert it to electromagnetic waves for radiation via the antenna 2. In the embodiment of the present application, the wireless communication module 252 is configured to transmit data with other terminal devices under the control of the processor 210.

In addition, the mobile phone 200 may implement audio functions through an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an earphone interface 270D, an application processor, and the like. Such as music playing, recording, etc. The handset 200 may receive key 290 inputs, generating key signal inputs related to user settings and function control of the handset 200. The cell phone 200 may use the motor 291 to generate a vibration alert (e.g., an incoming call vibration alert). The indicator 292 in the mobile phone 200 may be an indicator light, which may be used to indicate a state of charge, a change in power, an indication message, a missed call, a notification, etc. The SIM card interface 295 in the handset 200 is used to connect to a SIM card. The SIM card may be inserted into the SIM card interface 295 or removed from the SIM card interface 295 to allow contact and separation from the handset 200.

It should be understood that in practical applications, the mobile phone 200 may include more or fewer components than shown in fig. 6, and embodiments of the present application are not limited. The illustrated cell phone 200 is only one example, and cell phone 200 may have more or fewer components than shown in the figures, may combine two or more components, or may have a different configuration of components. The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

Fig. 7 shows a block diagram of a flash memory device according to an embodiment of the present application. As shown in fig. 7, the flash memory device 700 includes a control module 710 and a flash memory module 720. The control module 710 may be a processor, and the flash memory module 720 may be a flash memory.

The flash memory module 720 may include a plurality of physical pages, each physical page including a data field for storing data and an information field for storing configuration information of the physical page. The configuration information may include a logical address of data stored in a data field of the physical page.

In one possible implementation, the configuration information stored in the information field of each physical page may also include the status of the belonging physical page and/or the number of erasures of the belonging physical page.

In one possible implementation, the status of each physical page in the flash memory module may include free, used, discarded, and corrupted. Wherein, free (free) indicates that the physical page is not written with data and can be directly used; use (clean) indicates that the data stored on the physical page is still in use and is not erasable; discarding (dirty) means that the data stored in the physical page is no longer used and can be erased; corruption (error) indicates that a physical page has errors (e.g., bit cells are not available, etc.) and cannot be used.

In the using process of the flash memory module, the state of each physical page can be changed according to actual operation. For example, after writing data in a physical page whose state is idle, the state of the physical page becomes used; when the data in the physical page with the state being used is not used any more, the state of the physical page is changed into abandoned; after the physical page with the abandoned state is erased, the state of the physical page becomes idle; when there is an error in a physical page, for example, when there is an unusable bit cell in the physical page, the state of the physical page may be set to corrupt. In one possible implementation, the state of the physical page and its transitions may be implemented by a state machine.

It should be appreciated that the above is merely illustrative of the state of a physical page and its transitions. Those skilled in the art may set the transition conditions of the states of the physical page and between the states according to actual situations, and the present application is not limited thereto.

Fig. 8 shows a schematic diagram of partitioning of physical pages of a flash memory device according to an embodiment of the present application. As shown in fig. 8, any physical page 800 in the flash memory module includes a data field 810 and an information field 820. The data field 810 is used to store data, and the information field 820 is used to store the state of the physical page 800, the number of erasures, and the logical address of the data stored in the data field of the physical page 800. A reserved field is also included in the information field 820 to be configured according to actual usage requirements.

In one possible implementation, the address mapping table needs to be generated during power-up of the flash memory device. In this case, the control module may enable the address mapping signal such that the address mapping signal is active. Wherein the address mapping signal may be used to indicate whether an address mapping table is generated. When the address mapping signal is valid, the control module can trigger the process of generating an address mapping table; after the trigger is successful, the address mapping signal becomes invalid.

The address mapping signal can be realized by hardware such as a register, a trigger and the like, and the specific hardware realization mode of the address mapping signal is not limited by the application.

In one possible implementation, the address mapping table needs to be regenerated when the configuration information of any physical page in the flash memory module changes. In this case, the control module may enable the address mapping signal such that the address mapping signal is active.

Wherein the change in the configuration information of the physical page may include at least one of a change in a state of the physical page from space to use, a change in a state from use to other state, and a change in a logical address of data stored in the physical page. The configuration information of the physical page may also include other changes related to the address mapping table, which is not limited by the present application.

In one possible implementation, when the address mapping signal is valid, the control module may select at least one physical page whose status is used from all physical pages of the flash memory module according to the status of the physical pages stored in the configuration information of each physical page in the flash memory module, and generate the address mapping table according to the address and the configuration information of each physical page in the at least one physical page. The address mapping table is used for storing the mapping relation between the logical address and the physical address of the data stored in the flash memory module.

Since the configuration information stored in the information field of each physical page in the at least one physical page includes the logical address of the stored data, when the address mapping signal is valid, the control module may read the configuration information from the information field of each physical page in a hardware manner such as a circuit according to the address of each physical page in the at least one physical page, that is, with the address PA of each physical page in the at least one physical page as an Index (Index). For example, the configuration information may be sequentially read from the information fields of the respective physical pages in order of the addresses of the respective physical pages from small to large or from large to small. In this way, the reading efficiency of the configuration information can be improved.

After the configuration information of each physical page in at least one physical page is read, the control module can generate an address mapping table according to the address and the configuration information of each physical page. Because each physical page of the flash memory module has an address, after the configuration information of each physical page in at least one physical page is read, the control module can extract a logic address from the configuration information according to the address of each physical page, namely, the address PA of the physical page is used as an index, the logic address VA is used as content, and information extraction is carried out to obtain the mapping relation (PA-VA) from the physical address to the logic address; and then the mapping relation from the physical address to the logical address is flipped to obtain the mapping relation (VA-PA) from the logical address to the physical address, and an address mapping table is established according to the mapping relation from the logical address to the physical address. In the address mapping table, the logical address VA is an index and the physical address PA is a content.

Fig. 9 is a schematic diagram of an address mapping table of a flash memory device according to an embodiment of the application. As shown in fig. 9, in the address mapping table, the logical address VA is an index and the physical address PA is a content. The physical address corresponding to the logical address VA10 is PA0, the physical address corresponding to the logical address VA28 is PA1, and the physical address corresponding to the logical address VA57 is PA2047.

In one possible implementation, the control module may include a cache sub-module for storing the address mapping table and the state of each physical page. The cache sub-module may be a TLB. The address mapping table and the states of the pages read from the information fields of the physical pages of the flash memory module can be stored in the cache sub-module, so that the control module can be conveniently used, the number of times of reading configuration information from the flash memory module can be reduced, and the use efficiency is improved.

Fig. 10 is a schematic diagram illustrating an application scenario of a flash memory device according to an embodiment of the application. As shown in fig. 10, the flash memory device 1010 is built in the SOC chip 1000, and the SOC chip 1000 includes a CPU 1020, a RAM 1030, and the flash memory device 1010.

Wherein, the CPU 1020 is the main control, and most of the instructions and data in the execution process of the CPU 1020 are stored in the flash memory 1010; the flash memory device 1010 includes a control module 1040 and a flash memory module 1050, where the control module 1040 includes a cache sub-module 1041. The cache sub-module may be a TLB.

The CPU 1020 completes the initialization of the flash memory device 1010 (including generating an address mapping table) before accessing the flash memory device 1010. The initialization process of flash memory device 1010 may be exemplified as follows:

in the power-on and power-up process of the flash memory device 1010, when an address mapping table needs to be generated, the control module 1040 enables the address mapping signal, so that the address mapping signal is valid, and the process of generating the address mapping table is triggered specifically as follows:

the control module reads its configuration information from the information fields of each physical page according to the address of each physical page in the flash memory module 1050; then, according to the configuration information of each physical page, at least one physical page whose status is "used" is selected from all physical pages of the flash memory module 1050, and then, according to the address of each physical page in the at least one physical page and the logical address in the configuration information thereof, an address mapping table is generated and stored in the cache submodule 1041, and at the same time, information such as the status of the page extracted from the configuration information of each physical page may also be stored in the cache submodule 1041.

After the flash memory device 1010 is initialized, when the CPU 1020 accesses the flash memory device 1010, it can directly send the logical address, and determine the corresponding physical address through the address mapping table, so as to realize the fast access to the flash memory device 1010.

In this embodiment, when the flash memory device is powered on and initialized, mapping from a logical address to a physical address can be completed by combining hardware, so that not only can the address mapping speed be improved, but also the mapping can be performed in parallel with other operations, and the initialization time is effectively saved. In addition, the configuration information is stored in the information field of each physical page, the page for managing the configuration information is not required to be set, and the storage space can be saved.

Fig. 11 is a schematic diagram illustrating a processing procedure of a control module of a flash memory device according to an embodiment of the application. As shown in fig. 11, when data is read from the flash memory device, the control module processes:

in step S1110, when a read data command is received, a physical address of the first data in the flash memory module is determined from the address mapping table according to a logical address of the first data to be read.

For example, when the flash memory device receives a command for reading data sent by the CPU, the control module may search in the address mapping table according to the logical address of the first data to be read, that is, with the logical address of the first data to be read as an index, and determine the physical address corresponding to the logical address of the first data in the first mapping table as the physical address of the first data in the flash memory module.

After determining the physical address of the first data in the flash memory module, in step S1120, the first data may be read from the flash memory module according to the physical address.

In this embodiment, when data is read from the flash memory device, the physical address of the data to be read in the flash memory module can be directly determined through the address mapping table according to the logical address of the data to be read, and the data reading is performed according to the physical address, so that the data reading efficiency can be improved.

Fig. 12 is a schematic diagram illustrating a processing procedure of a control module of a flash memory device according to an embodiment of the application. As shown in fig. 12, when writing data into the flash memory device, the control module processes:

in step S1210, upon receiving the write data command, it is determined whether there is a logical address of the second data to be written in the address mapping table.

For example, when the flash memory device receives a write data command of the CPU, the control module may search in the address mapping table according to the logical address of the second data to be written, that is, with the logical address of the second data to be written as an index, to determine whether the logical address exists in the address mapping table.

When there is no logical address of the second data to be written in the address mapping table, in step S1220, at least one first target page with a free state may be selected from other physical pages except the at least one physical page of the flash memory module.

After the first target pages are determined, in step S1230, a second target page may be selected from at least one first target page according to the number of erasures of each first target page and the preset condition. The predetermined condition may be, for example, minimum number of erasures, number of erasures less than or equal to a predetermined threshold, etc.

For example, when the preset condition is that the number of erasures is less than or equal to a preset threshold, at least one page with the number of erasures less than or equal to the preset threshold may be selected from the first target pages, and one page is randomly selected from the at least one page and is used as the second target page.

It should be understood that the preset conditions and the preset threshold values can be set by those skilled in the art according to the actual situation, which is not limited by the present application.

In one possible implementation, the page with the least number of erasures in the at least one first target page may be determined as the second target page. When the number of the pages with the minimum erasing times in the first target page is multiple, one page can be randomly selected from the pages with the minimum erasing times and used as the second target page. In this way, the physical page with the least erasing times can be selected every time data is written, so that erasing and writing balance is realized.

After the second target page is determined, in step S1240, the second data to be written may be written into the second target page, and the configuration information of the second target page may be updated. When the configuration information is updated, the logical address of the second data can be written into the information field of the second target page, and the state of the second target page is updated from idle to use. After the configuration information of the second target page is updated, the control module sets the address mapping signal to be effective, and triggers the process of generating the address mapping table, so that the dynamic management of the physical page and the dynamic update of the address mapping table are realized.

When the logical address of the second data exists in the address mapping table, in step S1250, the physical address of the second data in the flash memory module is determined from the address mapping table according to the logical address of the second data, and in step S1260, it is determined whether the remaining storage space of the third target page corresponding to the physical address is greater than or equal to the storage space required by the second data; when the remaining storage space of the third target page is greater than or equal to the storage space required by the second data, that is, when the storage space of the third target page is sufficient, the second data may be written into the third target page in step S1270.

And when the remaining storage space of the third target page is smaller than the storage space required by the second data, step S1280 may be executed to select a fourth target page with idle state and the number of erasures satisfying the preset condition from other physical pages except the at least one physical page of the flash memory module, and in step S1290, the second data and the valid data in the third target page are written into the fourth target page, and the configuration information of the third target page and the fourth target page is updated respectively.

That is, when the storage space of the third target page is insufficient, a new physical page needs to be updated for the logical address of the second data, and one page that is idle and meets the preset condition (for example, the number of erasures is the minimum) can be selected from other physical pages except at least one physical page of the flash memory module as the fourth target page, then the valid data (i.e., the data still needed to be used) and the second data in the third target page are written into the fourth target page, and the configuration information of the third target page and the fourth target page is updated. Specifically, the state of the third target page may be updated from use to discard, the logical address of the second data may be written into the information field of the fourth target page, and the state of the fourth target page may be updated from idle to use.

After the configuration information of the third target page and the fourth target page is updated, the control module sets the address mapping signal to be effective, and triggers the process of generating the address mapping table, so that the dynamic management of the physical page and the dynamic update of the address mapping table are realized.

In this embodiment, when writing data into the flash memory device, it may be determined whether there is a logical address of the second data to be written in the address mapping table, and when there is no logical address of the second data in the address mapping table, one physical page may be selected from other physical pages except at least one physical page of the flash memory module according to the idle state and the erasing times of the physical page, and data writing may be performed, and meanwhile configuration information of the physical page may be updated, so that when writing data, a written target page may be selected according to the state and the erasing times of the physical page, so as to implement erasing balance, and improve reliability of the flash memory device;

when the logical address of the second data exists in the address mapping table, the physical address of the second data in the flash memory module can be determined from the address mapping table, and whether the storage space of the page corresponding to the physical address is sufficient or not can be judged. When the storage space is sufficient, the second data is written into the page, so that the writing efficiency of the second data can be improved, and the utilization rate of the storage space of the flash memory device can be improved. When the storage space is insufficient, one physical page can be selected from other physical pages except at least one physical page of the flash memory module according to the idle state and the erasing times of the physical pages, data writing is performed, and configuration information of the physical page is updated at the same time, so that when the physical page corresponding to a logical address of data is replaced, a target page can be selected according to the state and the erasing times of the physical page, erasing balance is realized, and the reliability of the flash memory device is improved.

The flash memory device of the embodiment of the application comprises a control module and a flash memory module, wherein the flash memory module comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, and the configuration information comprises a logic address of the data stored in the data field; the configuration information may also include the status of the belonging physical page and/or the number of erasures of the belonging physical page.

In the process of powering on (i.e. initializing) the flash memory device, the address of each physical page in at least one physical page in the flash memory module is taken as an index, the configuration information of each physical page is automatically obtained, and the address mapping table is automatically established according to the address of each physical page and the configuration information thereof, so that the address mapping speed can be improved, and the initialization time can be saved. When the configuration information of each physical page of the flash memory module changes, the processing of reading and generating the address mapping table can be triggered, so that the dynamic management of the physical pages and the dynamic update of the address mapping table are realized.

In addition, when the flash memory device executes a data writing command, when the logical address of writing data does not exist in the address mapping table, or when the physical page corresponding to the logical address of the data is replaced, the physical page can be selected according to the idle state and the erasing times of the physical page, the data writing can be performed, and meanwhile, the configuration information of the physical page is updated, so that erasing and writing balance can be realized when the data is written, the probability that some physical pages are continuously erased is reduced, and the reliability of the flash memory device is improved.

Fig. 13 shows a flowchart of a memory control method according to an embodiment of the present application. As shown in fig. 13, the method is applied to a control module in a flash memory device, the flash memory device includes a control module and a flash memory module, and the memory control method includes:

step S1310, when a data reading command is received, determining a physical address of the first data in the flash memory module from an address mapping table according to a logical address of the first data to be read;

step S1320, according to the physical address, reads the first data from the flash memory module,

wherein the flash memory module comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, the configuration information comprises a logic address of the data stored in the data field,

the address mapping table is generated by the control module according to the address and configuration information of each physical page in the at least one physical page.

In one possible implementation, the method further includes: when the address mapping signal is valid, respectively reading configuration information from the information domain of each physical page according to the address of each physical page in the at least one physical page; and generating an address mapping table according to the addresses of the physical pages and the configuration information.

In one possible implementation, the configuration information stored in the information field of each physical page of the at least one physical page further includes a state of the physical page to which the configuration information belongs, and the state of the physical page to which the configuration information belongs is used.

In one possible implementation manner, the reading configuration information from the information domain of each physical page according to the address of each physical page in the at least one physical page includes: and reading configuration information from the information fields of the physical pages in turn according to the order of the addresses of the physical pages.

In one possible implementation, the flash memory module further includes other physical pages than the at least one physical page, and the method further includes: and when the flash memory device is powered on or the configuration information of any physical page in the flash memory module is changed, setting the address mapping signal to be valid.

In a possible implementation manner, the configuration information stored in the information domain of each physical page in the flash memory module further includes the number of erasures of the physical page, and the method further includes: when a write data command is received, determining whether a logic address of second data to be written exists in the address mapping table; when the logical address of the second data does not exist in the address mapping table, selecting at least one first target page with idle state from other physical pages except the at least one physical page of the flash memory module; selecting a second target page from the at least one first target page according to the erasing times of each first target page and preset conditions; and writing the second data into the second target page, and updating configuration information of the second target page.

In one possible implementation, the method further includes: when the logical address of the second data exists in the address mapping table, determining the physical address of the second data in the flash memory module from the address mapping table according to the logical address of the second data; judging whether the residual storage space of the third target page corresponding to the physical address is larger than or equal to the storage space required by the second data; and when the remaining storage space of the third target page is larger than or equal to the storage space required by the second data, writing the second data into the third target page.

In one possible implementation, the method further includes: when the remaining storage space of the third target page is smaller than the storage space required by the second data, selecting a fourth target page which is free and has the erasing times meeting the preset condition from other physical pages except the at least one physical page of the flash memory module; and writing the second data and the effective data in the third target page into the fourth target page, and respectively updating the configuration information of the third target page and the fourth target page.

In one possible implementation manner, the selecting, according to the number of times of erasing each first target page and a preset condition, a second target page from the at least one first target page includes: and determining the page with the least erasing times in the at least one first target page as a second target page.

In one possible implementation, the control module includes a cache sub-module configured to store an address mapping table and a status of each physical page in the flash memory module.

An embodiment of the present application provides an electronic apparatus including: the device comprises a processor and a flash memory device connected with the processor, wherein the flash memory device comprises a control module and a flash memory module.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by hardware (e.g., circuits or ASICs (Application Specific Integrated Circuit, application specific integrated circuits)) which perform the corresponding functions or acts, or combinations of hardware and software, such as firmware, etc.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

A flash memory device, the device comprising a control module and a flash memory module, the control module configured to:

when a data reading command is received, determining a physical address of first data in the flash memory module from an address mapping table according to a logic address of the first data to be read;

reading the first data from the flash memory module according to the physical address,

wherein the flash memory module comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, the configuration information comprises a logic address of the data stored in the data field,

the address mapping table is generated by the control module according to the address and configuration information of each physical page in the at least one physical page.
The apparatus of claim 1, wherein the control module is further configured to:

when the address mapping signal is valid, respectively reading configuration information from the information domain of each physical page according to the address of each physical page in the at least one physical page;

And generating the address mapping table according to the addresses of the physical pages and the configuration information.
The apparatus according to claim 1 or 2, wherein the configuration information stored in the information field of each of the at least one physical page further comprises a state of the belonging physical page, and the state of the belonging physical page is used.
A device according to claim 2 or 3, wherein said reading configuration information from the information fields of the respective physical pages according to the addresses of the respective physical pages in said at least one physical page, respectively, comprises:

and reading configuration information from the information fields of the physical pages in turn according to the order of the addresses of the physical pages in the at least one physical page.
The apparatus of any of claims 2-4, wherein the flash memory module further comprises physical pages other than the at least one physical page,

the control module is further configured to:

and when the flash memory device is powered on or the configuration information of any physical page in the flash memory module is changed, setting the address mapping signal to be valid.
The apparatus of claim 5, wherein the configuration information stored in the information field of each physical page in the flash memory module further comprises a number of erasures of the physical page to which the configuration information belongs,

the control module is further configured to:

when a write data command is received, determining whether a logic address of second data to be written exists in the address mapping table;

when the logical address of the second data does not exist in the address mapping table, selecting at least one first target page with idle state from other physical pages except the at least one physical page of the flash memory module;

selecting a second target page from the at least one first target page according to the erasing times of each first target page and preset conditions;

and writing the second data into the second target page, and updating configuration information of the second target page.
The apparatus of claim 6, wherein the control module is further configured to:

when the logical address of the second data exists in the address mapping table, determining the physical address of the second data in the flash memory module from the address mapping table according to the logical address of the second data;

Judging whether the residual storage space of the third target page corresponding to the physical address is larger than or equal to the storage space required by the second data;

and when the remaining storage space of the third target page is larger than or equal to the storage space required by the second data, writing the second data into the third target page.
The apparatus of claim 7, wherein the control module is further configured to:

when the remaining storage space of the third target page is smaller than the storage space required by the second data, selecting a fourth target page which is free and has the erasing times meeting the preset condition from other physical pages except the at least one physical page of the flash memory module;

and writing the second data and the effective data in the third target page into the fourth target page, and respectively updating the configuration information of the third target page and the fourth target page.
The apparatus of claim 6, wherein selecting the second target page from the first target pages according to the number of erasures of the at least one first target page and a preset condition comprises:

And determining the page with the least erasing times in the at least one first target page as a second target page.
The apparatus of any of claims 1-9, wherein the control module includes a cache sub-module to store an address mapping table and a status of each physical page in the flash memory module.
A memory control method, wherein the method is applied to a control module in a flash memory device, the flash memory device comprising a control module and a flash memory module, the method comprising:

when a data reading command is received, determining a physical address of first data in the flash memory module from an address mapping table according to a logic address of the first data to be read;

reading the first data from the flash memory module according to the physical address,

wherein the flash memory module comprises at least one physical page, each physical page in the at least one physical page comprises a data field and an information field, the data field is used for storing data, the information field is used for storing configuration information of the physical page, the configuration information comprises a logic address of the data stored in the data field,

The address mapping table is generated by the control module according to the address and configuration information of each physical page in the at least one physical page.
The method of claim 11, wherein the method further comprises:

when the address mapping signal is valid, respectively reading configuration information from the information domain of each physical page according to the address of each physical page in the at least one physical page;

and generating an address mapping table according to the addresses of the physical pages and the configuration information.
The method of claim 11 or 12, wherein the configuration information stored in the information field of each of the at least one physical page further comprises a state of the belonging physical page, and the state of the belonging physical page is used.
The method according to claim 12 or 13, wherein reading configuration information from the information fields of the respective physical pages according to the address of the respective physical pages in the at least one physical page, respectively, comprises:

and reading configuration information from the information fields of the physical pages in turn according to the order of the addresses of the physical pages in the at least one physical page.
The method of any of claims 12-14, wherein the flash memory module further comprises physical pages other than the at least one physical page,

the method further comprises the steps of:

and when the flash memory device is powered on or the configuration information of any physical page in the flash memory module is changed, setting the address mapping signal to be valid.
The method of claim 15, wherein the configuration information stored in the information field of each physical page in the flash memory module further comprises a number of erasures of the physical page to which the configuration information belongs,

the method further comprises the steps of:

when a write data command is received, determining whether a logic address of second data to be written exists in the address mapping table;

when the logical address of the second data does not exist in the address mapping table, selecting at least one first target page with idle state from other physical pages except the at least one physical page of the flash memory module;

selecting a second target page from the at least one first target page according to the erasing times of each first target page and preset conditions;

And writing the second data into the second target page, and updating configuration information of the second target page.
The method of claim 16, wherein the method further comprises:

when the logical address of the second data exists in the address mapping table, determining the physical address of the second data in the flash memory module from the address mapping table according to the logical address of the second data;

judging whether the residual storage space of the third target page corresponding to the physical address is larger than or equal to the storage space required by the second data;

and when the remaining storage space of the third target page is larger than or equal to the storage space required by the second data, writing the second data into the third target page.
The method of claim 17, wherein the method further comprises:

when the remaining storage space of the third target page is smaller than the storage space required by the second data, selecting a fourth target page which is free and has the erasing times meeting the preset condition from other physical pages except the at least one physical page of the flash memory module;

And writing the second data and the effective data in the third target page into the fourth target page, and respectively updating the configuration information of the third target page and the fourth target page.
The method of claim 16, wherein selecting a second target page from the at least one first target page according to the number of erasures of each first target page and a preset condition comprises:

and determining the page with the least erasing times in the at least one first target page as a second target page.
The method of any of claims 11-19, wherein the control module includes a cache sub-module for storing an address mapping table and a status of each physical page in the flash memory module.
An electronic device, comprising:

a processor;

a flash memory device connected to the processor, the flash memory device being as claimed in any one of claims 1 to 10.