CN116707316B - Control method of asymmetric half-bridge power supply - Google Patents

Control method of asymmetric half-bridge power supply Download PDF

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Publication number
CN116707316B
CN116707316B CN202310961429.6A CN202310961429A CN116707316B CN 116707316 B CN116707316 B CN 116707316B CN 202310961429 A CN202310961429 A CN 202310961429A CN 116707316 B CN116707316 B CN 116707316B
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China
Prior art keywords
time
arm switch
switching
signal
zvs
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CN202310961429.6A
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Chinese (zh)
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CN116707316A (en
Inventor
沈逸伦
黄于芸
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Agco Microelectronics Shenzhen Co ltd
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Agco Microelectronics Shenzhen Co ltd
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33571—Half-bridge at primary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The present disclosure provides a control method of an asymmetric half-bridge power supply, which relates to the technical field of electronics, and the power supply includes a first arm switch and a second arm switch which form a half-bridge and are used for controlling a resonant circuit and are controlled by a controller, and the control method includes: providing a cluster mode, wherein the controller generates two groups of switch operation periods, the first group of switch operation periods and the second group of switch operation periods respectively comprise at least one switch period, the first arm switch and the second arm switch are only turned on once in each switch period, and the controller enables the first arm switch and the second arm switch to be turned off continuously for a neglect time from the end of the first group of switch operation periods until the start of the second group of switch operation periods. And adjusting a second opening time of the second arm switch relative to the opening in the first switching period according to whether the first arm switch realizes ZVS when the first switching period is opened. In this way, the energy transmitted to the secondary side can be effectively reduced and the switching losses can be reduced.

Description

Control method of asymmetric half-bridge power supply
Technical Field
The disclosure relates to the field of electronic technology, and in particular, to a control method of an asymmetric half-bridge power supply.
Background
The power supply is used for converting the input voltage into one or more output voltages, and the output voltages are used as input voltages of the electronic product. With the wide use of portable electronic products, power supplies are required to have high power, high efficiency and small volume.
One type of power supply is an asymmetric half-bridge (AHB) power supply with a transformer, which is simple in construction and can provide more than 100W of power. This power supply has upper and lower arm switches (high-side and low-side switches) on the primary side of the transformer configured in a half-bridge configuration, while providing different pulse width modulation (pulse width modulation, PWM) signals for the upper and lower arm switches, and is therefore referred to as asymmetric. The transformer in the AHB power supply is also connected with an oscillating capacitor on the primary side to form a resonant circuit (resonance circuit).
When the load supplied by the AHB power supply is heavy, the upper arm switch and the lower arm switch are substantially complementary during a switching cycle. The resonant circuit is charged and discharged and resonated, so that the upper arm and the lower arm can achieve zero-voltage switching (zero voltage switching, ZVS) with low switching loss (low switching loss) and have excellent conversion efficiency.
One way to reduce switching losses when the load being powered is medium or light is to increase the switching period, i.e., reduce the switching frequency. However, as the switching cycle of the AHB power supply increases, maintaining ZVS for the upper and lower arm switches becomes a technical challenge.
One technique is taught in the publication CN111010036 a. When the load is light, the lower arm switch of the AHB power supply is turned on only once (in an on state for a period of time) in a switching cycle of a discontinuous conduction mode (Discontinuous Conduction Mode, DCM), and the upper arm switch is turned on twice (one time after the lower arm switch is turned on and the other time before the lower arm switch in the next switching cycle is turned on).
Another technique is taught in the patent application publication No. CN104779806 a. In one switching cycle, the lower arm switch of the AHB power supply is turned on only once, and the upper arm switch is turned on only once. When the load is heavy, the upper arm switch is on approximately immediately after the lower arm switch is off, the upper and lower switches are approximately complementary; when the load is light, the switching period becomes longer, i.e. the upper arm switch is not turned on immediately after the lower arm switch is turned off, but is turned on until the end of the switching period. In other words, the upper arm switch is turned on approximately before the start of the next switching cycle.
Disclosure of Invention
According to an aspect of the disclosed embodiments, a control method for an asymmetric half-bridge power supply is provided, where the asymmetric half-bridge power supply includes a first arm switch and a second arm switch that are configured to form a half-bridge, the first arm switch and the second arm switch are used to control a resonant circuit, the first arm switch and the second arm switch are controlled by a controller, and the resonant circuit includes a transformer and an oscillating capacitor, and the control method includes: providing a cluster mode in which the controller generates a first set of switching periods and a second set of switching periods, the first set of switching periods and the second set of switching periods each including at least one switching cycle in which the first arm switch and the second arm switch are turned on only once, the controller causing the first arm switch and the second arm switch to be turned off continuously for an ignore time from the end of the first set of switching periods until the second set of switching periods; detecting whether zero voltage switching ZVS is realized when the first arm switch is started in a first switching period; and adjusting a second on time of the second arm switch for opening in the first switching period according to whether the first arm switch realizes ZVS when the first switching period is opened, so as to assist the first arm switch to realize ZVS when a second switching period after the first switching period is opened.
In the embodiment of the present disclosure, the controller may control the first arm switch and the second arm switch constituting the half bridge and provide the cluster mode. In the cluster mode, the controller generates at least one or a plurality of consecutive switching cycles, each of which is turned on only once for both the upper arm switch and the lower arm switch. After the switching cycles and before the other switching cycles begin, the controller may cause the first arm switch and the second arm switch to be continuously turned off for an ignored time, thereby effectively reducing the energy transferred to the secondary side when the load changes from heavy load to medium load or from medium load to light load. In addition, in each switching period in the cluster mode, the controller can detect whether the first arm switch realizes ZVS or not to adjust the on time of the second arm switch, so that the first arm switch can realize ZVS when the next switching period starts, thereby reducing switching loss and improving conversion efficiency.
The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 shows an AHB power supply according to the present invention.
Fig. 2 shows signal waveforms of the AHB power supply of fig. 1 operating at CRM.
Fig. 3 shows signal waveforms of an AHB power supply according to the present invention operating in a burst mode.
Fig. 4 shows an AHB controller implemented in accordance with the present invention.
FIG. 5 shows the lower arm on time T ON_GL And compensation signal V COMP A target number N and a compensation signal V COMP And ignoring time T SKIP And compensation signal V COMP Relationship to each other.
FIG. 6A shows the compensation signal V COMP Exceeding the reference voltage V REF1 The AHB power supply of FIG. 1 is now operating on the CRM signal waveform.
FIG. 6B shows the compensation signal V COMP Between reference voltage V REF1 And V is equal to REF3 While the AHB power supply of FIG. 1 is operating in CRM and cluster mode.
Fig. 7 shows the signal converter, lower arm controller, and upper arm controller of fig. 4.
FIG. 8 shows four switching periods TCYC of the AHB power supply of FIG. 1 in steady state 01 ~TCYC 04 Is provided.
Fig. 9 shows signal waveforms of the AHB power supply of fig. 1 operating in CRM and cluster modes.
Fig. 10 shows an AHB controller implemented in accordance with the present invention.
Fig. 11 and 12 show signal waveforms generated when the AHB power supply of fig. 1 employs the AHB controller of fig. 10.
Fig. 13 shows another AHB power supply according to the present invention.
Fig. 14 shows another AHB controller implemented in accordance with the present invention.
Fig. 15 shows an upper arm controller and a lower arm controller of the AHB controller in fig. 14.
Fig. 16 shows yet another AHB controller implemented in accordance with the present invention.
Symbol description:
16. a load;
100 An AHB power supply;
110. 110A, 110B AHB controller;
112. a synchronous rectification controller;
114. an optical coupler;
120. a lower arm controller;
121. a signal converter;
122. a target number generator;
124. a counter and a comparator;
126. neglecting the time generator;
128. an upper arm controller;
160. a triangular wave generator;
162. a comparator;
210 ZVS reference bit recorder;
212. a comparator;
213 ZVS detection circuitry;
214. a counter;
216. a digital-to-analog converter;
218. opening a time controller;
220. a comparator;
222. a longest dead time timer;
224. or gate;
226. opening a time controller;
302. an operational amplifier;
304 An NMOS switch;
310. a local legend;
600 An AHB power supply;
610. 610A, 610B AHB controller;
620. a lower arm controller;
628. an upper arm controller;
712. 720 a comparator;
A CCOM compensation capacitor;
CIN input capacitance;
CM current mirror;
CNT counting;
a CO output capacitor;
cr oscillation capacitance;
dV1 and dV2 default values;
an ER error amplifier;
GH. A GL control signal;
GNDI input ground;
GNDO outputs a ground line;
GR 1 ~GR1 2 during the switching operation;
GSR synchronous rectification control signal;
I DIS a discharge current;
I Lr leakage inductance current;
I Tr exciting current;
I RT mirror current;
I VS controlling the current;
an LA auxiliary winding;
lm parallel leakage inductance;
an LP main winding;
lr series leakage inductance;
LS secondary side winding;
n target number;
PLS pre-magnetic pulses;
a PRM primary side;
r1 and R2 resistances;
a RES resonant circuit;
RH resistance;
R PULL a pull-up resistor;
an RT resistor;
SEC secondary side;
S GO a start signal;
SH upper arm switch;
a SL lower arm switch;
S SKIP ignoring the signal;
SSR synchronous rectification switch;
t1 01 、t2 01 、t3 01 、t0 02 、t2 02 、t3 02 、t0 03 a time point;
TCYC、TCYC 1 ~TCYC N 、TCYC 01 ~TCYC 04 a switching period;
T DLH 、T DHL 、T DHL01 、T DHL02 、T DHL03 dead time;
T ON_GH 、T ON_GH01 、T ON_GH02 、T ON_GH03 the upper arm opening time;
T ON_GL lower arm on time;
T ON_GL_MIN minimum on time;
a Tr transformer;
T SKIP neglecting time;
U/D comparison results;
V AUX winding voltage;
V COMP compensating the signal;
V DSL switching voltage across;
V DSL_IN detecting a signal;
V DSR switching voltage across;
V IN an input voltage;
VIN input power line;
V O outputting a voltage;
V ON_H simulating a voltage;
VOUT output power line;
V REF 、V REF1 、V REF2 、V REF3 A reference voltage;
V RO a fixed voltage;
V S 、V S_IN detecting a signal;
V S_IN_ZVS ZVS reference bits;
V SAW triangular wave signals.
Detailed Description
In the description, the same reference numerals are used to designate components having the same or similar structures, functions, principles, and will be understood by those having ordinary skill in the art based on the teachings of the present specification. For simplicity of the description, the same reference numerals will not be repeated.
In an AHB power supply according to the present invention, a controller on the primary side can control a lower arm switch (i.e., a first arm switch) constituting a half bridge to keep pace with an arm switch (i.e., a second arm switch) and provide a Burst Mode. In the cluster mode, the controller generates at least one or a plurality of continuous switching cycles, the upper arm switch and the lower arm switch are turned on only once in each switching cycle, and after the plurality of switching cycles, the controller keeps turning off the upper arm switch and the lower arm switch for an neglect time before other switching cycles are started. During each switching cycle in the cluster mode, the controller detects whether the lower arm switch achieves ZVS to adjust the upper arm on time (i.e., the second on time) of the upper arm switch, and expects that the lower arm switch can achieve ZVS at the beginning of the next switching cycle. The goal is to have the AHB power supply operate approximately in Critical Mode (CRM). Each switching cycle may be regarded as a first switching cycle and the next switching cycle after each switching cycle may be regarded as a second switching cycle.
The power supply generally has three operation modes, namely, continuous-Conduction Mode (CCM), CRM, and DCM. The inductive element of the power supply, which is used for energy storage and conversion, may be an inductor or a transformer. At the end of one switching cycle, CCM refers to the fact that the excitation current in the inductive element does not return to 0 and the next switching cycle begins. In contrast, DCM means that the next switching cycle begins after the excitation current is maintained approximately equal to 0 for a period of time. CRM can be regarded as a special case between CCM and DCM, and the next switching cycle starts approximately shortly after the excitation current equals 0.
Fig. 1 shows an AHB power supply 100 according to the present invention. On the primary side PRM, an input capacitance CIN is provided across the input power line VIN and the input ground line GNDI, and provides an input voltage V IN . The transformer Tr and the oscillating capacitor Cr may form a resonant circuit RES, and are connected to the upper arm switch SH and the lower arm switch SL. The upper arm switch SH and the lower arm switch SL form a half bridge (half bridge) connected in series between the input power line VIN and the input ground line GNDI, and control the resonant circuit RES. The transformer Tr includes a primary winding LP, a secondary winding (secondary winding) LS, and an auxiliary winding (auxiliary winding) LA that are inductively coupled to each other. In fig. 1, the series leakage inductance Lr and the parallel leakage inductance Lm represent inductances connected in series and parallel to the main winding LP, respectively, and having no inductance coupled with other windings. The series leakage inductance Lr and the parallel leakage inductance Lm may be separate electronic components, or may be parasitic inductance parasitic in the transformer Tr. The main winding LP is electrically connected to the oscillating capacitor Cr. According to the winding voltage V AUX The resistors R1 and R2 in series provide the detection signal VS to the AHB controller 110.AHB controller 110 detects signal V S Detecting the winding voltage V of the auxiliary winding LA AUX And provides control signals GH and GL to control the upper arm switch SH and the lower arm switch SL, respectively. The synchronous rectification switch SSR located on the secondary side SEC is connected between the secondary side winding LS and the output capacitor CO, and is controlled by the synchronous rectification controller 112. In one embodiment, the synchronous rectification controller 112 and the synchronous rectification switch SSR may be replaced by a rectification diode. The AHB controller 110 controls the switching of the upper arm switch SH and the lower arm switch SL so that the resonant circuit RES is powered by the input power V IN The synchronous rectification controller 112 draws power to achieve a rectification function, causing the transformer Tr to charge the output capacitor CO, establishing an output voltage V across the output power line VOUT and the output ground GNDO O Power is supplied to the load 16.
The AHB power supply 100 shown in fig. 1 is merely illustrative of one type of AHB power supply and is not intended to limit the present invention. For example, in another AHB power supply implemented in accordance with the present invention, the resonant circuit RES may be connected between the input ground GNDI and the junction between the upper arm switch SH and the lower arm switch SL. In another embodiment, the series order of the main winding LP and the oscillating capacitor Cr in the resonant circuit RES may be reversed.
Input voltage V IN The output voltage provided by the PFC power converter of the previous stage can be the output voltage obtained by rectifying the commercial power through the bridge rectifier.
As shown in fig. 1, the output voltage V O Regulating primary PRM versus input voltage V through feedback control provided by optocoupler 114 IN The electrical energy drawn. Error amplifier ER at secondary side SEC, can compare output voltage V O With reference voltage V REF And can control the compensation signal V on the compensation capacitor CCOM of the primary side PRM by driving the optocoupler 114 COMP . The pull-up resistor R in the AHB controller 110 is illustrated in fig. 1 PULL Pull-up resistor R PULL Is connected between the high voltage power supply and the compensation capacitor CCOM. In FIG. 1, when the output voltage V O Greater than reference voltage V REF When the diode in the optocoupler 114 emits stronger light, the current flowing to the input ground GNDI increases to compensate the signal V COMP Over time, the resonant circuit RES is powered by the input power V IN Drawing less electrical energy, the transformer Tr charges the output capacitance CO less, thereby causing the output voltage V to be O Reducing the reference voltage V REF Approximation. Thereby, the output power V is stabilized approximately O At reference voltage V REF . On the other hand, the current I drawn by the load OUT The change may also indirectly affect the compensation signal V COMP . When the load draws current I OUT When decreasing, the output voltage V O May also rise with the rise of the compensation signal V COMP Will decrease over time. When the load draws current I OUT When increasing, the output voltage V O May also fall with the compensation signal V COMP And increases over time.
FIG. 2 shows the AHB power supply 100 of FIG. 1 operating in CRMSome of the signal waveforms. From top to bottom, FIG. 2 shows the control signals GL, GH and I Tr With leakage inductance current I flowing through series leakage inductance Lr Lr Detection signal V S Switch voltage V at the junction between upper arm switch SH and lower arm switch SL DSL Synchronous rectification control signal GSR, switch voltage across the junction between synchronous rectification switch SSR and secondary side winding LS DSR The secondary winding LS charges the output capacitor CO with a discharge current I DIS . Switch voltage across V DSL The channel voltage across the equivalent lower arm switch SL. FIG. 2 shows two successive switching cycles, each beginning at approximately the excitation current I Tr About 0A, and are all switching cycles when the AHB power supply 100 is operating in CRM.
As shown in the switching cycle TCYC of fig. 2, the AHB controller 110 starts the lower arm switch SL for a lower arm on time T according to the control signal GL ON_GL While the lower arm is open for time T ON_GL Can be determined by the length of the compensation signal V COMP And (3) determining. At the lower arm opening time T ON_GL After the end, there is a dead time (dead time) T DLH In this period of dead time T DLH In this case, both the upper arm switch SH and the lower arm switch SL are turned off at the same time. At dead time T DLH After that, the control signal GH turns on the upper arm switch SH for an upper arm on time T ON_GH . Upper arm open time T ON_GH The length of (2) is based on the previous lower arm opening time T ON_GL Initially, the lower arm switch SL is automatically adjusted if ZVS is reached. Upper arm on time T ON_GH After ending there is a dead time T DHL In this period of dead time T DLH In this case, both the upper arm switch SH and the lower arm switch SL are turned off at the same time. In one embodiment, dead time T DHL Can be adjusted by AHB controller 110 depending on whether lower arm switch SL is ZVS enabled. Next switching period, at dead time T DHL After the end, it starts as shown in fig. 2.
Fig. 3 shows some signal waveforms for an AHB power supply 100 according to the present invention operating in a burst mode. As shown in fig. 3, AHB controlThe processor 110 may provide a cluster pattern. In cluster mode, the AHB controller 110 is configured to generate GR during switching operations 1 And during the switch operation GR 2 . During the switch operation GR 1 With GR 2 Each of the switching periods includes at least one switching period, and the lower arm switch SL and the upper arm switch SH are turned on only once in each switching period. As illustrated in fig. 3, during the switching operation GR 1 Comprising N switching periods TCYC 1 ~TCYC N . The AHB controller 110 is internally provided with an ignore signal S SKIP For ending a switching operation period and starting a skip time T SKIP As shown in fig. 3. From the switching operation period GR 1 At the end, the AHB controller 110 is configured to cause the upper arm switch SH and the lower arm switch SL to ignore the time T SKIP Continuously turned off until the switch is operated by GR 2 Starting. In each switching cycle of FIG. 3, the AHB controller 110 will determine the lower arm on time T ON_GL Initially, the lower arm switch SL automatically adjusts the upper arm on time T if ZVS is reached ON_GH Such that at the beginning of the next switching cycle the lower arm switch SL achieves ZVS. In other words, the AHB controller 110 automatically adjusts the upper arm on time T ON_GH Such that the lower arm switch SL approximately achieves ZVS during each switching cycle in fig. 3. In each switching cycle in fig. 3, the AHB power supply 100 operates at approximately CRM, as previously described in fig. 2.
Fig. 4 shows an AHB controller 110A. The AHB controller 110A shown in fig. 4 may be referred to as the AHB controller 110 of fig. 1. The AHB controller 110A includes a signal converter 121, a lower arm controller 120, a target number generator 122, a counter and comparator 124, an ignore time generator 126, and an upper arm controller 128. FIG. 5 shows the lower arm on time T ON_GL And compensation signal V COMP Relationship between the target number N and the compensation signal V COMP Relationships between, and ignore time T SKIP And compensation signal V COMP The relationships between these may all be used in the AHB controller 110A.
Fig. 5 also shows the compensation signal V COMP Is not equal to (1)Similarly, the AHB controller 110A causes the AHB power supply 100 to operate in a different mode. When compensating signal V COMP Exceeding the reference voltage V REF1 When the load is considered to be a heavy load (i.e., the first predetermined reference value), the AHB power supply 100 is substantially operated in CRM (i.e., the AHB controller 110A provides the critical mode). When compensating signal V COMP Between reference voltage V REF1 With reference voltage V REF3 Between (i.e., the third predetermined reference value), the AHB power supply 100 operates substantially in CRM and cluster modes (i.e., the AHB controller 110A provides a combination of critical and cluster modes (crm+burst)). When compensating signal V COMP Below the reference voltage V REF3 When the load 16 is not present, or referred to as an unloaded state, the AHB power supply 100 operates in a Sleep Mode (i.e., the AHB controller 110A provides the Sleep Mode), and the upper and lower arm switches are kept off. In FIG. 5, reference voltage V REF2 (i.e. the second preset reference value) is between the reference voltage V REF1 With reference voltage V REF3 Between them.
The signal converter 121 of fig. 4 may be at the winding voltage V AUX When the current is negative, a detection current I is provided VS Will detect the signal V S Limited to 0V to provide an internally used detection signal V S_IN . For example, the detection signal V S_IN May be proportional to the detected current I VS Is set in the voltage range.
The lower arm controller 120 in fig. 4 is based on the detection signal V S_IN Indicated winding voltage V AUX At dead time T DHL During the descent, a control signal GL is provided to start the lower arm opening time T ON_GL . The lower arm controller 120 can be based on the compensation signal V COMP To end the lower arm opening time T ON_GL As shown in fig. 5, the compensation signal V COMP Determines the lower arm opening time T ON_GL Is a length of (c). Compensation signal V COMP The higher the lower arm opening time T ON_GL The longer. Compensation signal V COMP Below the reference voltage V REF2 Time of opening lower arm T ON_GL For not following compensation signal V COMP A variable fixed value, which can The minimum opening time T defined by the lower arm controller 120 ON_GL_MIN 。
The target number generator 122 generates a compensation signal V according to the compensation signal V COMP The target number N is determined and provided to the counter and comparator 124, as shown in fig. 5. In cluster mode, i.e. compensation signal V COMP Between reference voltage V REF1 With reference voltage V REF3 Between which the output voltage V O Increase, compensate signal V COMP Falling (i.e. compensating signal V COMP The intensity of (c) decreases), the target number N decreases, and the minimum value of the target number N is 1. In sleep mode, i.e. compensation signal V COMP Less than the reference voltage V REF3 Since the target number N is 0, both the upper arm switch SH and the lower arm switch SL are kept in the off state.
The counter and comparator 124 counts the number of switching cycles existing during the current switching operation according to the control signal GL. When the number of switching cycles in the current switching period is greater than or equal to the target number N (e.g., the target number N may be greater than or equal to 2), the counter and comparator 124 triggers the ignore time generator 126 to generate the ignore signal S SKIP The time T can be largely ignored SKIP 。
According to the compensation signal V COMP Ignoring the signal S SKIP So that the lower arm controller 120 is fixedly turned off for an ignore time T SKIP After that, another switching period is started, the lower arm controller 120 is caused to start a new switching cycle, and the counter of the comparator 124 are reset. Basically, the compensation signal V COMP The larger the neglected time T SKIP The shorter. As shown in fig. 5, when the compensation signal V COMP Exceeding the reference voltage V REF1 When the time T is ignored SKIP 0, no cluster mode. Output voltage V O Increase, compensate signal V COMP Fall, neglect time T SKIP Growth.
FIG. 6A shows the compensation signal V COMP Exceeding the reference voltage V REF1 The AHB power supply 100 is then approximately operating on the signal waveform of the CRM. As described earlier, the compensation signal V COMP Exceeding the reference voltage V REF1 When the time T is ignored SKIP For 0, the AHB controller 110A does not provide the ignore time T SKIP . So, regardless of the target number N, one switching cycle follows one switching cycle in FIG. 6A, each switching cycle, the transformer Tr is approximately operated at CRM, and the lower arm on time T in each switching cycle ON_GL Substantially all along with the compensation signal V COMP But vary. Upper arm on time T in each switching cycle ON_GH Is adjusted depending on whether the lower arm switch SL has reached ZVS.
FIG. 6B shows the compensation signal V COMP Between reference voltage V REF1 And V is equal to REF3 In between, the AHB power supply 100 generally operates as a CRM and provides a cluster mode. As described earlier, the compensation signal V COMP Below the reference voltage V REF1 When the time T is ignored SKIP And not 0 at the beginning. As shown in FIG. 6B, therefore, after the number of switching cycles in the switching operation period GR3 is the same as the target number N, the neglect time T is rested SKIP The switching operation period GR4 is started. Each switching cycle is approximately operating at CRM. Lower arm on time T in each switching cycle ON_GL Substantially all along with the compensation signal V COMP But vary. Upper arm on time T in each switching cycle ON_GH The length is adjusted depending on whether the lower arm switch SL has reached ZVS.
Fig. 7 shows the signal converter 121, the lower arm controller 120, and the upper arm controller 128 of fig. 4 for illustrating the upper arm on time T ON_GH With dead time T DHL How to automatically adjust depending on whether the lower arm switch SL implements ZVS.
The signal converter 121 detects the signal V S Detecting winding voltage V AUX Indirectly detecting switch voltage across V DSL To provide the detection signal V S_IN . As shown in fig. 7, the signal converter 121 controls the detection signal V by the operational amplifier 302 and the NMOS switch 304 S Not less than 0V. When the winding voltage V AUX Less than 0V, NMOS switch 304 provides a control current I VS Flows out from the signal converter 121 to the auxiliary winding LA,to maintain the detection signal Vs at 0V. Thus, the current I is controlled VS About equal to |V AUX I/R1, wherein R1 is the resistance of the divider resistor R1. The current mirror CM provides a control current I approximately proportional to VS Mirror current I of (2) RT Flows through a resistor RT to generate a detection signal V S_IN . So that the detection signal V S_IN May correspond approximately to the winding voltage V of the transformer Tr AUX May also represent the switch voltage V of the lower arm switch SL DSL (switch Cross-over voltage V) DSL I.e. the pressure difference across the lower arm switch SL). When the switch is in a voltage V DSL The closer to 0V from a positive value, the winding voltage V AUX The more negative, the control current I VS The larger the detection signal V S_IN The higher.
In fig. 7, ZVS reference bit recorder 210 is on for lower arm on time T ON_GL At a predetermined time point, sampling the detection signal V S_IN To generate ZVS reference bit V S_IN_ZVS . For example, at the lower arm opening time T ON_GL Minimum on time T after start ON_GL_MIN At this time, ZVS reference bit recorder 210 samples detection signal V S_IN As ZVS reference bit V S_IN_ZVS . In other words, the ZVS reference bit recorder 210 records that the lower arm switch SL is stably turned on, and the switch voltage V is across DSL When equal to 0V, detect signal V S_IN Is a stable value of (c). Briefly, the switch is voltage V DSL About proportional to the detection signal V S_IN With ZVS reference bit V S_IN_ZVS Is a difference between (a) and (b).
In FIG. 7, the upper arm controller 128 may automatically adjust the upper arm on time T depending on whether the lower arm switch SL is ZVS enabled ON_GH . The upper arm controller 128 includes a ZVS detection circuit 213 and an on-time controller 218.ZVS detection circuit 213 includes a comparator 212, a counter 214, and a digital-to-analog converter (DAC) 216. For example, ZVS detection circuit 213 may include a recorder. The recorder may include a counter 214 and a digital-to-analog converter 216.
ZVS detection circuit 213 may provide a top on time T reflecting the top switch SH in the previous switching cycle ON_GH And detect when the control signal GL is switchedWhether the lower arm switch SL implements ZVS or not, and adjusts the length parameter in the current switching cycle accordingly, for example, the counter 214 counts up or down in the previous switching cycle to obtain a counted number, which is a digital form of the length parameter, reflecting the upper arm on time T of the upper arm switch SH in the previous switching cycle ON_GH The method comprises the steps of carrying out a first treatment on the surface of the The length parameter in digital form is passed through a digital-to-analog converter (DAC) 216 to obtain a length parameter in analog form, i.e., an analog voltage V obtained by the DAC 216 ON_H . For example, the recorder in the ZVS detection circuit 213 can determine the adjusted length parameter according to the comparison result U/D when the signal edge of the control signal GL occurs. The on-time controller 218 starts to turn on the upper arm switch SH at an appropriate time after the control signal GL turns off the lower arm switch SL, and the upper arm on-time T ON_GH Is based on the adjusted length parameter (e.g. the adjusted analog voltage V ON_H ) To determine.
For example, in the case of providing a length parameter reflecting the upper arm on time ton_gh of the upper arm switch SH in the previous switching cycle, if the lower arm switch SL implements ZVS in the current switching cycle, the provided length parameter may be reduced (i.e., the upper arm on time ton_gh of the upper arm switch SH in the current switching cycle may be shortened); if the ZVS is not achieved by the lower arm switch SL during the current switching cycle, the provided length parameter may be increased (i.e., the upper arm on time ton—gh of the upper arm switch SH during the current switching cycle may be shortened).
It should be understood that the above-mentioned "previous switching period" means a switching period previous to each current switching period, i.e., the upper arm on time T reflecting the upper arm switch SH in the previous switching period is provided for each current switching period ON_GH Length parameter of (c) is provided.
It should be noted that, in providing the upper arm on time T reflecting the upper arm switch SH in the previous switching cycle ON_GH In the case of the length parameter of (2), the detection of whether the lower arm switch SL is ZVS is achieved in the current switching cycle can be performed on the basis of the provided length parameterStepwise fine tuning (e.g. stepwise counting) to determine a more suitable upper arm opening time T ON_GH Directly setting the upper arm on time T of the upper arm switch SH with respect to detecting whether the lower arm switch SL achieves ZVS in each switching cycle ON_GH Can more accurately determine the upper arm on time T of the upper arm switch SH that is required to be reached in the current switching cycle that enables the lower arm switch SL in the next switching cycle to achieve ZVS ON_GH Thereby effectively reducing switching loss and improving conversion efficiency.
Comparator 212 compares the detection signal V S_IN With ZVS reference bit V S_IN_ZVS To produce a comparison result U/D. For example, when detecting the signal V S_IN With ZVS reference bit V S_IN_ZVS About equal, for example: detection signal V S_IN The sum with the default value dV1 is not less than the ZVS reference bit V S_IN_ZVS When the comparison result U/D is logically "0", the switch voltage V of the lower arm switch SL is shown DSL Should be close to 0V. Conversely, when detecting the signal V S_IN Below ZVS reference bit V S_IN_ZVS Very much time (detection signal V S_IN The sum with the default value dV1 is smaller than the ZVS reference bit V S_IN_ZVS ) The comparison result U/D is logically "1", indicating the switch voltage V across the lower arm switch SL DSL Should be quite obvious.
The counter 214 takes the edge of the control signal GL for turning on the lower arm switch SL as the frequency, and counts up or down the counter 214 according to the comparison result U/D, and outputs the count CNT. The control signal GL is used to turn on the signal edge of the lower arm switch SL, which turns on the lower arm switch SL, thereby causing the main winding LP to start being inputted with the voltage V IN Energizing by charging, also resulting in an auxiliary winding voltage V AUX Is controlled at a relatively negative voltage and causes a detection signal V S_IN Up to a high point, about ZVS reference bit V S_IN_ZVS . However, due to the signal transfer delay, the lower arm switch SL is turned on from the control signal GL signal edge to the winding voltage V AUX When actually controlled, there is a time difference. However, the counter 214 can know about the lower arm from the comparison result U/D and the control signal GLBefore the switch SL is turned on (before the time difference), both ends of the lower arm switch SL are cross-pressed (switch cross-voltage V DSL ) Whether or not it is about 0 (i.e. the detection signal V S_IN With ZVS reference bit V S_IN_ZVS The difference between them is not greater than the default value dV 1), which is equal to the judgment as to whether the lower arm switch SL achieves ZVS. Accordingly, counter 214 changes count CNT depending on whether lower arm switch SL implements ZVS. The count CNT can be used to determine the upper arm on time T ON_GH Is a length of (c).
The digital-to-analog converter 216 converts the count CNT to output an analog voltage V ON_H Which determines the upper arm opening time T ON_GH Is a length of (c).
For example, if the comparison result U/D is "0" at the moment when the lower arm switch SL is turned on (when the signal edge of the control signal GL occurs), indicating that the lower arm switch SL has achieved ZVS, the count CNT is reduced and the analog voltage V is reduced ON_H Reduced, resulting in a subsequent upper arm opening time T ON_GH Shortening. Conversely, if at the instant the lower arm switch SL is turned on, the comparison result U/D is "1", indicating that the lower arm switch SL has not yet achieved ZVS, the count CNT is incremented, simulating the voltage V ON_H Increase, resulting in a subsequent upper arm opening time T ON_GH Growth.
In fig. 7, the lower arm controller 120 may automatically determine the dead time T DHL The control signal GL is provided in due time to start to turn on the lower arm switch SL. The lower arm controller 120 includes a comparator 220, a maximum dead time timer 222, an OR gate 224, and an on time controller 226.
Like the comparator 212, the comparator 220 also compares the detection signal V S_IN With ZVS voltage V S_IN_ZVS To generate the start signal SGO. In design, if ZVS is implemented at the moment the lower arm switch SL is turned on, the comparison result U/D output by the comparator 212 will be changed from "1" to "0" before the lower arm switch SL is actually turned on, and the comparator 220 should be configured to make the time point of the logic change of the start signal SGO earlier than the time point of the logic change of the comparison result U/D. For example, in FIG. 8, the default value dV1 is 0.1V and the default dV2 is 0.2V. Thus, at dead time T DHL In, winding voltage V AUX Gradually decrease to detect the signal V S_IN During the gradual increase, the logic change of the comparison result U/D is later than the logic change of the start signal SGO.
The start time controller 226 triggers the start of the lower arm switch SL to start the lower arm start time T after a predetermined delay time after the logic change of the start signal SGO ON_GL And according to the compensation signal V COMP To determine the lower arm opening time T ON_GL Is a length of (c).
The longest dead time timer 222 is started from the upper arm on time T ON_GH Starting to time after finishing, providing the longest dead time T DEAD_MAX . The longest dead time timer 222 may be set at the longest dead time T if the start signal SGO has not triggered the on-time controller 226 DEAD_MAX After the lapse of time, the trigger on time controller 226 starts the lower arm on time T ON_GL . The longest dead time timer 222 can prevent the dilemma that the start signal SGO of the comparator 220 has not changed logically when the ZVS is not achieved by the lower arm switch SL, and the switching period cannot be ended. In other words, the longest dead time timer 222 causes the dead time T DHL Not greater than the maximum dead time T DEAD_MAX 。
As shown in fig. 7, ZVS reference bit recorder 210 is on for a lower arm on time T ON_GL At a predetermined time point, sampling the detection signal V S_IN To generate ZVS reference bit V S_IN_ZVS ZVS reference bit V S_IN_ZVS Is a fixed value obtained by sampling. Namely, the detection signal V S_IN Is a voltage V reflecting the winding voltage AUX To obtain a reflected winding voltage V without the additional step of "sampling the winding voltage at a set sampling time point" and storing an analog value AUX Is a signal of (a). Thus, the detection signal V possibly introduced by the early or over-completion of the sampling time point can be avoided S_IN Is a function of the error of (a).
In addition, the comparator 212, the comparator 220, and the counter 214 are digital circuits. After the counter 214 is triggered by the signal edge of the control signal GL to read the output value (i.e. 0 or 1) of the comparator 212, the following digital addition and subtraction operation is performed. In this way, the digital circuit is used to determine whether the lower arm switch SL in the current switching period achieves ZVS, and compared with the analog circuit which is used to determine whether the lower arm switch SL in the current switching period achieves ZVS through an analog signal, interference caused by fluctuation of the analog signal (for example, a voltage signal) can be reduced, so that the anti-interference effect in the power supply circuit can be greatly improved.
FIG. 8 shows four possible switching cycles TCYC when the AHB controller 110A is used in the AHB power supply 100, in steady state (after the load 16 has been maintained for a sufficient period of time) 01 ~TCYC 04 Is a function of the signal waveform of the signal. The waveforms in FIG. 8 represent the control signal GL, the control signal GH, and the exciting current I, respectively, from top to bottom Tr Detection signal V S Switch voltage across V DSL And a detection signal V inside the AHB controller 110A S_IN 。
Please refer to fig. 8 and fig. 7 at the same time. With a switching period TCYC 01 For example, ZVS reference bit recorder 210 is at time point t1 01 Sampling the detection signal V S_IN To generate ZVS reference bit V S_IN_ZVS . Whether in the switching period TCYC 01 Initially, the lower arm switch SL has ZVS, and the upper arm controller 128 can determine the upper arm on time T based on the current count CNT ON_GH01 Is a length of (c). Dead time T DHL01 From time point t2 01 Beginning to time t0 02 And (5) ending. From time point t2 01 Initially, switch voltage across V DSL Detection signal V S And starts to descend. When detecting signal V S When the voltage is controlled to 0V by the signal converter 121, the signal V is detected S_IN And starts to rise. Detection signal V S_IN The rising speed substantially follows the arm opening time T ON_GH01 And (5) correlation. Generally, upper arm on time T ON_GH01 Longer dead time T DHL01 The detection signal V in S_IN The faster the rise, the higher the peak can be.
FIG. 8 is a partial viewExample 310 amplifies about time point t0 02 (switching period TCYC) 02 Start point of (V) near the detection signal V S_IN . At time point t3 01 When the comparator 220 detects the detection signal V S_IN Has been very close to the ZVS reference bit V S_IN_ZVS Since the gap is less than the default dV2, the start signal SGO logic begins to change, triggering the on-time controller 226 at time t3 01 After a predetermined delay time, the lower arm switch SL is started to be turned on by the control signal GL, and the dead time T is ended DHL01 。
As can be seen from the local legend 310, at time point t3 01 By time point t0 02 In the period between, detect signal V S_IN Has been closer to the ZVS reference bit V S_IN_ZVS The difference is less than the default dV1. Therefore, at time point t0 02 Previously, the comparison result U/D, i.e., the output of comparator 212, would be logically "0" indicating that the voltage across the lower arm switch SL should be approximately 0V, and the next switching cycle (i.e., switching cycle TCYC 02 ) The lower arm switch SL will achieve ZVS. Thus, at time point t0 02 The count CNT recorded by the counter 214 is decremented. Switch voltage across V in fig. 8 DSL The waveform of (2) also shows that the lower arm switch SL is in the switching period TCYC 02 Is at the beginning (time t0 02 ) The lower arm switch SL has a ZVS.
As shown in the enlarged partial legend 310, detecting whether the first arm switch realizes ZVS when the signal edge of the control signal occurs, does not represent the time point t3 when the signal edge of the first control signal GL occurs 01 And compare the detection signal V S_IN With ZVS reference bit V S_IN_ZVS Time point t0 of difference between the two 02 At the same time, there may be several delay time differences between the two, for example. That is, in the present invention, "the signal edge in response to the first control signal" may be "when the signal edge of the first control signal occurs" or "within a period of time after the signal edge of the first control signal occurs".
During the switching period TCYC 02 In the ZVS reference bit recorder 210 oneSampling detection signal V of sampling in good time S_IN To generate ZVS reference bit V S_IN_ZVS . The upper arm controller 128 determines the upper arm on time T based on the current count CNT ON_GH02 Is a length of (c). Because the count CNT is now greater than the count CNT in the switching period TCYC 01 The count CNT in (C) is small, so the upper arm on time T ON_GH02 Compared with the upper arm opening time T ON_GH01 Short in the future.
Dead time T DHL02 From time point t2 02 Beginning to time point t0 03 . From time point t2 02 Initially, switch voltage across V DSL Detection signal V S And starts to descend. Compared with dead time T DHL01 The detection signal V in S_IN Because of the upper arm opening time T ON_GH02 Relatively short, so the dead time T DHL02 The detection signal V in S_IN The rate of rise is relatively slow and the highest point possible is also relatively low. Relatively slow detection signal V S_IN Rising speed also results in dead time T DHL02 Will be compared with dead time T DHL01 Long.
The partial legend 312 in FIG. 8 is enlarged approximately at time point t0 03 (switching period TCYC) 03 Start point of (V) near the detection signal V S_IN . At time point t3 02 When the comparator 220 detects the detection signal V S_IN Has been very close to the ZVS reference bit V S_IN_ZVS However, the gap is less than the default value dV2, so the start signal SGO logic begins to change. Time point t3 02 After a predetermined delay time, i.e. time t0 03 The on-time controller 226 starts to turn on the lower arm switch SL with the control signal GL, ending the dead time T DHL02 。
As can be seen from the local legend 312, because of dead time T DHL02 The detection signal V in S_IN The rising speed is relatively slow, so at time t3 02 By time point t0 03 In a period between, although the detection signal V S_IN Closer to ZVS reference bit V S_IN_ZVS But still differ from each other by more than the default value dV1. Therefore, at time point t0 03 Previously, compare knotsThe result U/D will be a logical "1" indicating the switch voltage V across the lower arm switch SL DSL Is not close enough to 0V, and at the same time represents the next switching period (i.e., switching period TCYC 03 ) The lower arm switch SL does not achieve ZVS. Thus, the count CNT recorded by the counter 214 is incremented. Switch voltage across V in fig. 8 DSL The waveform of (2) also shows that the lower arm switch SL is in the switching period TCYC 03 The lower arm switch SL achieves ZVS at a little bit.
During the switching period TCYC 03 In this, the upper arm controller 128 determines the upper arm on time T according to the current count CNT ON_GH03 Is a length of (c). Because of the current count CNT, relative to the current count CNT in the switching period TCYC 02 The count CNT in (a) is increased, so the upper arm on time T ON_GH03 Compared with the upper arm opening time T ON_GH02 Long, also results in dead time T DHL03 Will be compared with dead time T DHL02 Short.
Thus, as shown in FIG. 8, at steady state, the upper arm on time T for each switching cycle ON_GH There will be some variation depending on whether the lower arm switch SL is ZVS enabled at the beginning of the switching cycle. Upper arm open time T ON_GH Is maintained at about a length just sufficient for the lower arm switch SL to achieve ZVS at the beginning of the next switching cycle. Furthermore, dead time T per switching period DHL And the lower arm switch SL can be timely ended to realize ZVS.
In one case, if the AHB controller 110A always finds that the lower arm switch SL has ZVS implemented, the count CNT will gradually decrease with each switching cycle, slowly shortening the upper arm on time T ON_GH The lower arm controller 120 will also automatically and slowly increase the dead time T DHL . The AHB controller 110A does not maintain the upper arm on time T approximately until the lower arm switch SL is found to begin not achieving ZVS ON_GH With dead time T DHL Is a length of (c).
If the upper arm is open for a time T ON_GH Initially very short, resulting in the lower arm switch SL not achieving ZVS, and even in the detection signal V S_IN Failure to climb to ZVS reference bitV S_IN_ZVS dV2, let alone climb to ZVS reference V S_IN_ZVS -dV1. The longest dead time timer 222 in fig. 7 causes the dead time T DHL About equal to the default maximum dead time T DEAD_MAX And the count CNT recorded by the counter 214 is incremented such that the upper arm on time T of the next switching cycle ON_GH And (3) increasing. With each switching cycle, the count CNT is gradually increased, and the upper arm opening time T is increased ON_GH The length of (2) gradually increases, the dead time T DHL About always equal to the longest dead time T DEAD_MAX Only dead time T DHL Internal detection signal V S_IN Will climb higher and higher. Once at dead time T DHL In, detect signal V S_IN Climb beyond ZVS reference bit V S_IN_ZVS dV2, dead time T DHL Will automatically end early, not longer being the longest dead time T DEAD_MAX . Upper arm open time T ON_GH The length of (a) increases gradually with each switching period until the dead time T DHL In, detect signal V S_IN Climb beyond ZVS reference bit V S_IN_ZVS dV1, the lower arm switch SL has achieved ZVS. Thereafter, the upper arm opening time T ON_GH The length of (c) remains approximately unchanged as shown in fig. 8.
Thus, as described above, the upper arm opening time T ON_GH With dead time T DHL The proper length is automatically adjusted according to whether the lower arm switch SL realizes ZVS. Upper arm open time T ON_GH The power stored in the transformer Tr is not wasted due to too long, nor is the lower arm switch SL too short to achieve ZVS. Dead time T DHL It also ends up in time when the lower arm switch SL can achieve ZVS.
Counter 214 digitally records count CNT, which is equal to about the upper arm on time T ON_GH Due length, in cluster mode, at neglect time T SKIP After the past, counter 214 may immediately provide an upper arm on time T of about the length ON_GH Let the lower arm switch SL in the following switching cycle achieve ZVS as much as possible.
In the cluster mode, embodiments of the present invention are not limited to only one or a few switching cycles per switching operation period. In another embodiment, each switching period further comprises a pre-magnetic pulse PLS before at least one switching cycle begins. Fig. 9 shows a signal waveform in another embodiment. As shown in fig. 9 and fig. 6B, it can be seen from the foregoing description, and the description will not be repeated. However, in FIG. 6B, the rest is ignored for a time T SKIP Thereafter, a new switching cycle is directly initiated by the lower arm controller 120 during the switching operation. In contrast, in FIG. 9, at the time T is ignored SKIP Thereafter, the switching operation period starts when the upper arm controller 128 supplies the pre-magnetic pulse PLS before the lower arm controller 120 starts a plurality of switching cycles. As shown in fig. 9, the switching operation periods GR7 and GR8 each have a pre-magnetic pulse PLS at the beginning. For example, when the ignore time generator 126 in FIG. 4 ignores the signal S SKIP Notifying the ignore time T SKIP When it is to be ended, the upper arm controller 128 causes the on-time controller 218 to fire the pre-magnetic pulse PLS in accordance with the current count CNT. The pre-magnetic pulse PLS shown in fig. 9 may first energize the transformer Tr and make it possible for the lower arm switch SL to achieve ZVS during the first switching cycle during a switching operation.
Fig. 10 illustrates an AHB controller 110B, which includes a lower arm controller 120, a triangular wave generator 160, a comparator 162, and an upper arm controller 128, as well as implementing cluster mode and CRM operations. Fig. 11 shows some of the signal waveforms that may be generated when the AHB power supply 100 of fig. 1 employs the AHB controller 110B. From top to bottom, FIG. 11 shows the control signals GL, GH, V in one embodiment SAW And compensation signal V COMP And ignore signal S SKIP 。
The operation and function of the lower arm controller 120 and the upper arm controller 128 may be known from the previous description of the AHB controller 110A, and will not be further described.
In one embodiment of the present invention, triangular wave generator 160 provides a periodic threeAngular wave signal V SAW With a maximum value approximately equal to the reference voltage V REF1 The minimum value is approximately equal to the reference voltage V REF3 As shown in fig. 11. Comparator 162 compares the triangular wave signal V SAW And compensation signal V COMP Thereby generating an ignore signal S SKIP . When compensating signal V COMP Above the triangular wave signal V SAW When ignore signal S SKIP Is logically "0" so that the lower arm controller 120 and the upper arm controller 128 can alternately turn on the lower arm switch SL and the upper arm switch SH, resulting in individual switching cycles, each approximately at CRM. As described previously, in each switching cycle, the lower arm controller 120 is responsive to the compensation signal V COMP Determining the lower arm opening time T ON_GL Is a length of (c). The upper arm controller 128 adjusts the upper arm on time T based on whether the lower arm switch SL achieves ZVS at the beginning of a switching cycle ON_GH The length is made approximately just to allow the lower arm switch SL to achieve ZVS. When compensating signal V COMP Below the triangular wave signal V SAW When ignore signal S SKIP Is logically "1" such that the lower arm controller 120 no longer turns on the lower arm switch SL, as shown in fig. 11. In general, when the signal S is ignored SKIP When the logic value is 0, the switching operation period is defined as a switching operation period; when ignoring signal S SKIP When logically "1", the time T is ignored approximately SKIP . In fig. 11, each of the switching operation periods GR9 and GR10 has 5 switching cycles. For example, a triangular wave signal V SAW Is about 400Hz, and the switching frequency of the control signal GH and the control signal GL may be as high as 100kHz.
FIG. 12 shows a control signal GL, a control signal GH, a triangular wave signal V in another embodiment SAW And compensation signal V COMP And ignore signal S SKIP . Fig. 12 is substantially the same as fig. 11. Unlike fig. 11, the control signal GH is provided with the pre-magnetic pulse PLS at the beginning of the switching operation periods GR11 and GR12 in fig. 12, and then the subsequent switching cycle is started. As previously described, the pre-magnetic pulse PLS may cause the lower arm switch SL to achieve ZVS during the first switching cycle during switching operation.
As described above, the AHB power supply according to the embodiment of the invention is directed to the compensation signal V COMP The reflected load provides different modes of operation. When compensating signal V COMP When the display load is heavy, the AHB power supply is based on the compensation signal V COMP Modulating lower arm on time T ON_GL And the transformer is operated at approximately continuous CRM. When compensating signal V COMP When the display load is medium, the AHB power supply still depends on the compensation signal V COMP Modulating lower arm on time T ON_GL The transformer is made to operate substantially at CRM, but provides a cluster mode that allows switching periods to alternate with neglected times. When compensating signal V COMP When the load is no-load, the AHB power supply enters a sleep mode, and the upper and lower arm switches SH and SL are both fixed off. Thus, the benefits of ZVS can be enjoyed during heavy and medium loads, while switching losses can be reduced during medium loads, possibly improving conversion efficiency.
In the embodiment of fig. 1, the AHB controller 110 is configured to detect the signal V S Detecting winding voltage V AUX Indirectly detecting switch voltage across V DSL To determine whether the lower arm switch SL achieves ZVS, but the present invention is not limited thereto. Fig. 13 shows another AHB power supply 600 implemented in accordance with the present invention, which is identical or similar to the AHB power supply 100 of fig. 1, and will not be repeated as will be apparent from the previous description. The AHB power supply 600 may also provide a cluster mode, and may also automatically adaptively adjust the upper arm on time T ON_GH With dead time T DHL Let the lower arm switch SL reach approximately ZVS.
In the AHB power supply 600, the AHB controller 610 additionally directly detects the switch voltage V across the switch via the resistor RH DSL To determine whether the lower arm switch SL achieves ZVS. When the current flowing through the resistor RH is negligible, the detection signal V at the junction between the AHB controller 610 and the resistor RH DSL_IN The voltage is approximately equal to the switch voltage V DSL . In another embodiment, the detection signal V DSL_IN About switch voltage across V DSL Is a partial pressure result of (a).
Fig. 14 shows an AHB controller 610A as an example of the AHB controller 610 in fig. 13. The AHB controller 610A of fig. 14 corresponds to the AHB controller 110A of fig. 4, being identical or similar to each other, as can be appreciated from the previous teachings, and will not be repeated. Like the AHB controller 110A of fig. 4, the AHB controller 610A of fig. 14 also provides a cluster mode. Compared to the AHB controller 110A of FIG. 4, the AHB controller 610A does not have the signal converter 121, and the lower arm controller 620 and the upper arm controller 628 directly receive the detection signal V DSL_IN . Practically, switch is across voltage V DSL Will be limited by the body diode (body diode) in the lower arm switch SL, which is generally positive, and the lowest value is a slight negative value very close to 0V, as in the switch voltage across V of FIG. 8 DSL The waveform is shown. Thus, the detection signal V DSL_IN The signal converter 121 is not required.
Fig. 15 illustrates an upper arm controller 628 and a lower arm controller 620 in the AHB controller 610A. Fig. 15 corresponds to fig. 7, identical or similar to each other, as can be appreciated from the previous teachings, and will not be repeated. As described earlier with respect to fig. 7, the AHB controller 610A of fig. 15 may automatically adaptively adjust the upper arm on time T ON_GH With dead time T DHL Letting the lower arm switch SL approximately achieve ZVS, also letting each switching cycle approximately operate at CRM. In comparison with fig. 7, fig. 15 does not have the signal converter 121 and ZVS reference bit recorder 210 of fig. 7. The AHB controller 610A does not need to record the detection signal V when the arm switch SL is on DSL_IN Because the switch voltage V is across the switch when the lower arm switch SL is on DSL Detection signal V DSL_IN Should be 0V. In fig. 15, the comparator 712 detects the detection signal V DSL_IN Whether the voltage drops to a default value dV1 (i.e., a first default value) very close to 0V, and uses the signal edge of the control signal GL as the frequency of the counter 214 to determine whether the ZVS is achieved by the lower arm switch GL. In fig. 15, the comparator 720 detects the detection signal V DSL_IN Whether the detected signal V falls to a default value dV2 (i.e. a second default value) very close to 0V or not DSL_IN Whether or not low enough, it is already about to let the lower arm switchGL implements the ZVS reference bit to control the dead time T DHL . As described previously, in practice, when detecting signal V DSL_IN At dead time T DHL When dropped, the output logic of comparator 720 should change earlier than the output logic of comparator 712. For example, the default values dV1 and dV2 are 0.1V and 0.2V, respectively.
Fig. 16 shows an AHB controller 610B as an example of the AHB controller 610 in fig. 13. The AHB controller 610A of fig. 16 corresponds to the AHB controller 110B of fig. 10, and is identical or similar to each other, as can be appreciated from the previous teachings, and will not be repeated. Like the AHB controller 110B of FIG. 10, the AHB controller 610B of FIG. 16 utilizes a comparison triangle wave signal V SAW And compensation signal V COMP To provide a cluster pattern. The AHB controller 610B can also automatically and adaptively regulate the upper arm opening time T ON_GH With dead time T DHL Let the lower arm switch SL reach approximately ZVS.
An embodiment 1 is a control method for an asymmetric half-bridge power supply, the asymmetric half-bridge power supply includes a first arm switch and a second arm switch configured to form a half-bridge, the first arm switch and the second arm switch are used for controlling a resonant circuit, the first arm switch and the second arm switch are controlled by a controller, the resonant circuit includes a transformer and an oscillating capacitor, the control method includes:
Providing a cluster mode in which the controller generates a first set of switching periods and a second set of switching periods, the first set of switching periods and the second set of switching periods each including at least one switching cycle in which the first arm switch and the second arm switch are turned on only once, the controller causing the first arm switch and the second arm switch to be turned off continuously for an ignore time from the end of the first set of switching periods until the second set of switching periods;
detecting whether zero voltage switching ZVS is realized when the first arm switch is started in a first switching period; and
and adjusting a second opening time of the second arm switch for opening in the first switching period according to whether the first arm switch realizes ZVS when the first switching period is opened or not so as to assist the first arm switch to realize ZVS when a second switching period after the first switching period is opened.
In this way, the controller can control the first arm switch and the second arm switch that constitute the half bridge, and provide a cluster mode. In the cluster mode, the controller generates at least one or a plurality of consecutive switching cycles, each of which is turned on only once for both the upper arm switch and the lower arm switch. After the switching cycles and before the other switching cycles begin, the controller may cause the first arm switch and the second arm switch to be continuously turned off for an ignored time, thereby effectively reducing the energy transferred to the secondary side when the load changes from heavy load to medium load or from medium load to light load. In addition, in each switching period in the cluster mode, the controller can detect whether the first arm switch realizes ZVS or not to adjust the on time of the second arm switch, so that the first arm switch can realize ZVS when the next switching period starts, thereby reducing switching loss and improving conversion efficiency.
Embodiment 2. The method of embodiment 1 wherein the first switching period and the second switching period are two consecutive switching periods belonging to the first set of switching operation periods;
the controller automatically adjusts a start time point of the second switching period according to whether the first arm switch achieves ZVS in the first switching period.
Embodiment 3. The method of embodiment 1 or 2 wherein the controller determines a first on-time of the first arm switch during each switching cycle in the burst mode based on a compensation signal, the compensation signal being controlled by an output voltage of the asymmetric half-bridge power supply.
Embodiment 4. The method of any of the above embodiments, wherein in the cluster mode, the controller determines a target number according to a compensation signal, counts a number of switching cycles during the first set of switching operations, and starts the ignore time when the number is equal to the target number, the compensation signal being controlled by an output voltage of the asymmetric half-bridge power supply, the target number being equal to or greater than 2.
Embodiment 5. The method of any of the above embodiments, wherein the compensation signal correspondingly decreases and the target number correspondingly decreases as the output voltage increases.
Embodiment 6. The method of any of the above embodiments, wherein in the cluster mode, the controller determines the length of the ignore time based on a compensation signal, the compensation signal being controlled by an output voltage of the asymmetric half-bridge power supply.
Embodiment 7. The method of any of the above embodiments, wherein the compensation signal correspondingly decreases and the length of the ignore time correspondingly increases as the output voltage increases.
Embodiment 8. The method of any of the embodiments above, further comprising:
when the compensation signal is higher than a first preset reference value, the controller provides a critical mode so that the second group of switch operation periods are continuous with the first group of switch operation periods, and the compensation signal is controlled by the output voltage of the asymmetric half-bridge power supply.
Embodiment 9. The method of any of the embodiments above, further comprising:
when the compensation signal is greater than a third preset reference value and lower than the first preset reference value, the controller provides a combined mode of a critical mode and a cluster mode so that the neglect time is greater than 0.
Embodiment 10. The method of any of the embodiments above, further comprising:
when the compensation signal is lower than a second preset reference value, the first opening time of the first arm switch is not shortened along with the decrease of the compensation signal, and the second preset reference value is larger than a third preset reference value and smaller than the first preset reference value.
Embodiment 11. The method of any of the embodiments above, further comprising:
when the compensation signal is lower than a third preset reference value, the controller provides a sleep mode to continuously turn off the first arm switch and the second arm switch until the asymmetric half-bridge power supply is separated from the sleep mode, wherein the third preset reference value is smaller than the first preset reference value.
Embodiment 12. The method of any of the above embodiments, wherein each switching period comprises a pre-magnetic pulse that energizes the transformer, the pre-magnetic pulse being prior to a start of the at least one switching cycle.
Embodiment 13. The method of any of the embodiments above, further comprising:
generating a triangular wave signal; and
comparing the triangular wave signal with a compensation signal to determine the neglect time;
The compensation signal is controlled by the output voltage of the asymmetric half-bridge power supply.
Embodiment 14. The method of any of the embodiments above, further comprising:
providing a first control signal to turn on the first arm switch for a first turn-on time;
providing a detection signal to represent the real-time change of the switch voltage across the first arm switch; and
and in response to the signal edge of the first control signal, comparing the detection signal with a first default value to detect whether the first arm switch realizes ZVS.
Embodiment 15. The method of any of the embodiments above, further comprising:
comparing the detection signal with a second default value to determine a dead time continuing the second on time.
Embodiment 16. The method of any of the embodiments above, further comprising:
providing a first control signal to turn on the first arm switch for a first turn-on time;
providing a detection signal to represent real-time variation of winding voltage of the transformer;
sampling the detection signal as a ZVS reference bit during the first on time; and
and comparing the detection signal with the ZVS reference bit in response to a signal edge of the first control signal to detect whether the first arm switch achieves ZVS.
Embodiment 17. The method of any of the embodiments above, further comprising:
comparing the detection signal with the ZVS reference bit to determine a dead time subsequent to the second on time.
Embodiment 18. The method of any of the embodiments above, further comprising:
decreasing the second on time when the first arm switch is determined to achieve ZVS when it is on during the second switching period such that the second on time during the second switching period is shorter than the second on time during the first switching period; and
the second on-time is increased such that the second on-time in the second switching period is longer than the second on-time in the first switching period when the first arm switch is determined to not achieve ZVS when it is on for the second switching period.
Embodiment 19. a control method for an asymmetric half-bridge power supply including a first arm switch and a second arm switch forming a half-bridge, the asymmetric half-bridge power supply including a resonant circuit connected to the half-bridge, the resonant circuit including a transformer and an oscillating capacitor, the method comprising:
Providing a length parameter reflecting a second on time of the second arm switch in a previous switching cycle;
providing a control signal to turn on the first arm switch for a first on time in a current switching period;
detecting whether the first arm switch realizes ZVS or not in response to the signal edge of the control signal, and adjusting the length parameter according to the detection result;
determining a second opening time of the second arm switch in the current switching period according to the adjusted length parameter; and
after the first on time, the second arm switch is turned on according to the determined second on time.
In this way, the length parameter reflecting the second opening time of the second arm switch in the previous switching period is provided, and the length parameter is adjusted by detecting whether the first arm switch realizes ZVS in the current switching period, so that the opening time of the second arm switch in the current switching period is determined according to the adjusted length parameter, the opening time of the second arm switch in the current switching period can be controlled more accurately, the first arm switch can realize ZVS more easily when the next switching period starts, switching loss is further effectively reduced, and conversion efficiency is improved.
Embodiment 20. The method of embodiment 19 wherein the transformer provides a winding voltage, the method further comprising:
providing a detection signal to represent the real-time variation of the winding voltage; and
in response to the signal edge, the detection signal is compared with a first default value to detect whether the first arm switch achieves ZVS.
Therefore, the detection signal is a continuous analog signal capable of reflecting real-time change of the winding voltage, so that the winding voltage is not required to be sampled through an additional step of setting a sampling time point and an analog value is stored to obtain a signal reflecting the winding voltage, and further, errors of the detection signal possibly caused by early or over-completion of the setting of the sampling time point can be avoided.
Embodiment 21. The method of any of the embodiments above, further comprising:
sampling the detection signal when the first arm switch is turned on for the previous time, and generating a ZVS reference bit; and
in response to the signal edge, comparing the detection signal to the ZVS reference bit to detect whether the first arm switch achieves ZVS.
Embodiment 22. The method of any of the above embodiments, wherein comparing the detection signal with the ZVS reference bit in response to the signal edge to detect whether the first arm switch achieves ZVS comprises:
Determining a first difference between the ZVS reference bit and the detection signal in response to the signal edge;
determining that the first arm switch has achieved ZVS if the first difference is less than or equal to the first default value;
and determining that the first arm switch does not achieve ZVS if the first difference is greater than the first default value.
Embodiment 23. The method of any of the embodiments above, further comprising:
starting to turn on the first arm switch according to the detection signal and the ZVS reference bit.
Embodiment 24. The method of any of the embodiments above, further comprising:
and comparing the detection signal with a second default value to start to turn on the first arm switch, wherein the second default value is larger than the first default value.
An embodiment 25 of the method according to any of the preceding embodiments, wherein comparing the detection signal with a second default value to start turning on the first arm switch comprises:
sampling the detection signal when the first arm switch is turned on for the previous time, and generating a ZVS reference bit;
determining a second difference between the ZVS reference bit and the detection signal;
And determining to start to turn on the first arm switch when the second difference value is greater than or equal to the two default values.
Embodiment 26. The method of any of the above embodiments, wherein comparing the detection signal with a first default value in response to the signal edge to detect whether the first arm switch achieves ZVS comprises:
comparing the detection signal with a first default value in response to the signal edge to generate a comparison result; and
and counting the up number or the down number according to the comparison result to obtain a counted number, wherein the counted number is used as the adjusted length parameter.
Embodiment 27. The method of any of the embodiments above, further comprising:
directly detecting the switch cross voltage of the first arm switch; and
and judging whether the first arm switch realizes ZVS or not according to the switch cross voltage.
Embodiment 28. A controller for an asymmetric half-bridge power supply, wherein the asymmetric half-bridge power supply includes a first arm switch and a second arm switch forming a half-bridge and configured to control a resonant circuit, the resonant circuit including a transformer and an oscillating capacitor, the controller configured to control the first arm switch and the second arm switch, the controller comprising:
The first arm controller is used for providing a first control signal for starting the first arm switch for a first starting time; and
a second arm controller for providing a second control signal for turning on the second arm switch for a second on time, comprising:
a ZVS detection circuit for providing a length parameter reflecting a second on-time of the second arm switch in a previous switching cycle, detecting whether the first arm switch implements ZVS in response to a signal edge of the first control signal, and adjusting the length parameter accordingly; and
and the starting time controller is used for determining the second starting time in the current switching period according to the adjusted length parameter.
Embodiment 29. The method of any of the embodiments above, wherein the ZVS detection circuit includes:
the comparator is used for comparing the detection signal with a default value to generate a comparison result; and
a recorder, configured to determine the adjusted length parameter according to the comparison result in response to the signal edge;
the detection signal represents real-time change of switch cross voltage of the first arm switch.
Therefore, the detection signal is a continuous analog signal capable of reflecting real-time change of the switch voltage across, so that the step of sampling the switch voltage across by an additional set sampling time point and storing an analog value is not needed to obtain the signal reflecting the switch voltage across, and further, the error of the detection signal possibly introduced by the early or over-completion of the set sampling time point can be avoided.
Embodiment 30. The method of any of the embodiments above, wherein the recorder comprises:
the counter is used for counting the up number or the down number by taking the first control signal as a clock signal according to the comparison result so as to obtain a counted number; and
and the digital-analog converter is used for generating the adjusted length parameter according to the counted number.
Therefore, as the comparator and the counter are both digital circuits, whether the first arm switch in the current switching period realizes ZVS is judged through the digital circuits, and compared with the mode that an analog circuit is adopted to judge whether the first arm switch in the current switching period realizes ZVS through an analog signal, the interference caused by fluctuation of the analog signal (such as a voltage signal) and the like can be reduced, and thus the anti-interference effect in the power supply circuit can be greatly improved.
Embodiment 31. The method of any of the above embodiments, wherein the transformer comprises a main winding and an auxiliary winding, the main winding being electrically connected to the oscillating capacitor, the controller further comprising:
a signal converter electrically connected to the auxiliary winding through a resistor for providing a detection signal representative of a real-time change in winding voltage of the auxiliary winding; and
A ZVS reference bit recorder for sampling the detection signal to generate ZVS reference bits;
the ZVS detection circuit is used for responding to the signal edge and comparing the detection signal with the ZVS reference bit to determine the adjusted length parameter.
An embodiment 32 of the method according to any of the preceding embodiments, wherein the second arm controller is electrically connected to the first arm switch to provide a detection signal, the detection signal representing a real-time change in a switch cross-over voltage of the first arm switch, the second arm controller being configured to compare the detection signal with a first default value to determine the adjusted length parameter.
Embodiment 33. The method of any of the embodiments above, wherein the first arm controller comprises:
the comparator is used for comparing the detection signal with a second default value to generate an initial signal; and
and the starting time controller is used for receiving the starting signal and determining dead time immediately after the second starting time.
Embodiment 34. The method of any of the above embodiments wherein the first arm controller further comprises a longest dead time timer for providing a longest dead time such that the dead time is not greater than the longest dead time.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (17)

1. The control method for an asymmetric half-bridge power supply, wherein the asymmetric half-bridge power supply comprises a first arm switch and a second arm switch which are arranged to form a half-bridge, the first arm switch and the second arm switch are used for controlling a resonant circuit, the first arm switch and the second arm switch are controlled by a controller, the resonant circuit comprises a transformer and an oscillating capacitor, and the control method comprises the following steps:
providing a cluster mode in which the controller generates a first set of switching periods and a second set of switching periods, the first set of switching periods and the second set of switching periods each including at least one switching cycle in which the first arm switch and the second arm switch are turned on only once, the controller causing the first arm switch and the second arm switch to be turned off continuously for an ignore time from the end of the first set of switching periods until the second set of switching periods;
Detecting whether zero voltage switching ZVS is realized when the first arm switch is started in a first switching period;
adjusting a second on time of the second arm switch for opening in the first switching period according to whether the first arm switch realizes ZVS when the first switching period is opened or not, so as to assist the first arm switch to realize ZVS when a second switching period after the first switching period is opened;
providing a first control signal to turn on the first arm switch for a first turn-on time;
providing a detection signal to represent the real-time change of the switch voltage across the first arm switch; and
ending dead time continuing the second on time and providing the first control signal once the difference between the detection signal and the ZVS reference bit is less than a second default value;
wherein in response to a signal edge of the first control signal, detecting whether the first arm switch achieves ZVS by determining whether a difference between the detection signal and the ZVS reference bit is less than a first default value.
2. The method of claim 1, wherein the first switching period and the second switching period are two consecutive switching periods that fall within the first set of switching operation periods;
The controller automatically adjusts a start time point of the second switching period according to whether the first arm switch achieves ZVS in the first switching period.
3. The method of claim 1, wherein the controller determines the first on-time of the first arm switch in each switching cycle in the cluster mode based on a compensation signal, the compensation signal being controlled by an output voltage of the asymmetric half-bridge power supply.
4. The method of claim 1, wherein in the cluster mode, the controller determines a target number according to a compensation signal, counts a number of switching cycles during the first set of switching operations, and starts the ignore time when the number is equal to the target number, the compensation signal being controlled by an output voltage of the asymmetric half-bridge power supply, the target number being equal to or greater than 2.
5. The method of claim 4, wherein the compensation signal correspondingly decreases and the target number correspondingly decreases as the output voltage increases.
6. The method of claim 1, wherein in the burst mode, the controller determines the length of the ignore time based on a compensation signal, the compensation signal being controlled by an output voltage of the asymmetric half-bridge power supply.
7. The method of claim 6, wherein the compensation signal correspondingly decreases and the length of the ignore time correspondingly increases as the output voltage increases.
8. The method of claim 1, further comprising:
when the compensation signal is higher than a first preset reference value, the controller provides a critical mode so that the second group of switch operation periods are continuous with the first group of switch operation periods, and the compensation signal is controlled by the output voltage of the asymmetric half-bridge power supply.
9. The method of claim 8, further comprising:
when the compensation signal is greater than a third preset reference value and lower than the first preset reference value, the controller provides a combined mode of a critical mode and a cluster mode so that the neglect time is greater than 0.
10. The method of claim 8, further comprising:
when the compensation signal is lower than a second preset reference value, the first opening time of the first arm switch is not shortened along with the decrease of the compensation signal, and the second preset reference value is larger than a third preset reference value and smaller than the first preset reference value.
11. The method of claim 8, further comprising:
When the compensation signal is lower than a third preset reference value, the controller provides a sleep mode to continuously turn off the first arm switch and the second arm switch until the asymmetric half-bridge power supply is separated from the sleep mode, wherein the third preset reference value is smaller than the first preset reference value.
12. The method of claim 1, wherein each switching operation period comprises a pre-magnetic pulse energizing a transformer, the pre-magnetic pulse being prior to a start of the at least one switching cycle.
13. The method of claim 1, further comprising:
generating a triangular wave signal; and
comparing the triangular wave signal with a compensation signal to determine the neglect time;
the compensation signal is controlled by the output voltage of the asymmetric half-bridge power supply.
14. The method of claim 1, further comprising:
providing a longest dead time;
wherein the dead time is not greater than the longest dead time.
15. The method of claim 1, wherein the second default value is greater than the first default value.
16. The method of claim 1, further comprising:
providing the detection signal by detecting a real-time change in winding voltage of the transformer;
During the first on time, the detection signal is sampled as the ZVS reference bit.
17. The method of claim 1, further comprising:
decreasing the second on time when the first arm switch is determined to achieve ZVS when it is on during the second switching period such that the second on time during the second switching period is shorter than the second on time during the first switching period; and
the second on-time is increased such that the second on-time in the second switching period is longer than the second on-time in the first switching period when the first arm switch is determined to not achieve ZVS when it is on for the second switching period.
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