CN116705854A - Super junction MOSFET device and manufacturing method thereof - Google Patents

Super junction MOSFET device and manufacturing method thereof Download PDF

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Publication number
CN116705854A
CN116705854A CN202310686122.XA CN202310686122A CN116705854A CN 116705854 A CN116705854 A CN 116705854A CN 202310686122 A CN202310686122 A CN 202310686122A CN 116705854 A CN116705854 A CN 116705854A
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field plate
epitaxial layer
super junction
mosfet device
junction mosfet
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祁金伟
张耀辉
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Suzhou Huatai Electronics Co Ltd
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Suzhou Huatai Electronics Co Ltd
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The application provides a super junction MOSFET device and a manufacturing method thereof. The super junction MOSFET device comprises a substrate and a plurality of field plate structures, wherein the substrate comprises a laminated substrate and a first epitaxial layer; the field plate structures comprise an oxide layer and vertical field plates, the oxide layer is in contact with the first epitaxial layer, the vertical field plates are located in the oxide layer, the extending direction of the vertical field plates is the same as the thickness direction of the first epitaxial layer, the distance between two adjacent field plate structures is larger than the width of the field plate structures, and the width is perpendicular to the thickness direction of the field plate structures. The super junction MOSFET device has the advantages that the through-current capability of the super junction MOSFET device is good, and the voltage withstand capability of the super junction MOSFET device is good due to the existence of the field plate structure, so that the performance of the super junction MOSFET device is good.

Description

Super junction MOSFET device and manufacturing method thereof
Technical Field
The application relates to the field of semiconductors, in particular to a super junction MOSFET device and a manufacturing method thereof.
Background
In order to improve the voltage-withstanding capability of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor ) device, a super junction device is introduced, however, since a P column structure in the super junction does not contribute to conduction in the device, the utilization rate of an epitaxial layer is lower in the super junction MOSFET device, so that the current-passing capability of the device is weaker, and the performance of the device is further affected.
Disclosure of Invention
The application mainly aims to provide a super junction MOSFET device and a manufacturing method thereof, which are used for solving the problem of poor performance caused by weak current passing capability of the super junction device in the prior art.
To achieve the above object, according to one aspect of the present application, there is provided a super junction MOSFET device comprising a base and a plurality of field plate structures, wherein the base comprises a stacked substrate and a first epitaxial layer; the field plate structures are arranged in the first epitaxial layer at intervals, each field plate structure comprises an oxide layer and a vertical field plate, each oxide layer is in contact with the corresponding first epitaxial layer, each vertical field plate is located in the corresponding oxide layer, the extending direction of each vertical field plate is identical to the thickness direction of the corresponding first epitaxial layer, the distance between two adjacent field plate structures is larger than the width of each field plate structure, and the width is perpendicular to the thickness direction of each field plate structure.
Optionally, the super junction MOSFET device further includes a plurality of gate structures, the gate structures being located on a side of the field plate structure remote from the substrate, a projection of each gate structure in the first epitaxial layer being located between two adjacent field plate structures.
Optionally, the super junction MOSFET device further includes a second epitaxial layer on a surface of the first epitaxial layer remote from the substrate, and the gate structure extends through the second epitaxial layer.
Optionally, the super junction MOSFET device further includes a plurality of sources, where the sources are located in the second epitaxial layer, one of the gate structures corresponds to two sources, and the two sources are located on two sides of the corresponding gate structure, and the sources are in contact with the gate structure.
Optionally, the doping types of the substrate and the first epitaxial layer are N-type, and the doping type of the second epitaxial layer is P-type.
Optionally, the gate structure includes a trench gate oxide layer and a trench gate, the trench gate oxide layer penetrates through the second epitaxial layer into the first epitaxial layer, and the trench gate oxide layer contacts with the second epitaxial layer; the trench gate is located in the corresponding trench gate oxide layer, penetrates through the second epitaxial layer to the first epitaxial layer, and is in contact with the trench gate oxide layer.
Optionally, the trench gate is the same material as the vertical field plate.
Optionally, a ratio of a distance between two adjacent field plate structures to the width of the field plate structures is greater than or equal to 5.
According to another aspect of the present application, there is provided a method of fabricating any one of the super junction MOSFET devices, the method comprising: providing a base comprising a stacked substrate and a first epitaxial layer; removing part of the first epitaxial layer to form a plurality of first grooves which are arranged at intervals, wherein the distance between two adjacent first grooves is larger than the width of the first grooves, and the width is perpendicular to the thickness direction of the first grooves; and forming a field plate structure in the first groove, wherein the field plate structure comprises an oxide layer and a vertical field plate, the oxide layer covers the side wall and the bottom of the first groove, and the vertical field plate is positioned in the rest first groove.
Optionally, forming a field plate structure in the first groove includes: performing high-temperature oxidation on the side wall and the bottom of the first groove to form an oxide layer; and forming the vertical field plates in the remaining first grooves.
By applying the technical scheme of the application, the super junction MOSFET device comprises a substrate and a plurality of field plate structures, wherein the substrate comprises a laminated substrate and a first epitaxial layer; the field plate structures are arranged in the first epitaxial layer at intervals, each field plate structure comprises an oxide layer and a vertical field plate, each oxide layer is in contact with the corresponding first epitaxial layer, each vertical field plate is located in the corresponding oxide layer, the extending direction of each vertical field plate is identical to the thickness direction of the corresponding first epitaxial layer, the distance between two adjacent field plate structures is larger than the width of each field plate structure, and the width is perpendicular to the thickness direction of each field plate structure. Compared with the problem of poor performance caused by weak current passing capability of the super junction MOSFET device in the prior art, the super junction MOSFET device has the advantages that the distance between two adjacent field plate structures is larger than the preset width of the field plate structures, so that the distance between the adjacent field plate structures is larger than the width of the field plate structures, the width of the first epitaxial layer between the adjacent field plate structures is ensured to be larger, the current passing space of the first epitaxial layer is ensured to be larger, the better current passing capability of the super junction MOSFET device is ensured, and the better voltage withstand capability of the super junction MOSFET device is ensured due to the existence of the field plate structures, thereby solving the problem of poor performance caused by weak current passing capability of the super junction MOSFET device in the prior art, and ensuring the better performance of the super junction MOSFET device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
fig. 1 shows a schematic structure of a super junction MOSFET device according to an embodiment of the application;
fig. 2 shows a flow diagram of a method of fabricating a superjunction MOSFET device according to an embodiment of the present application;
FIG. 3 shows a schematic structural view of a substrate according to an embodiment of the present application;
fig. 4 shows a schematic structural view after forming a first trench according to an embodiment of the present application;
fig. 5 shows a schematic structure after forming a gate structure according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. a field plate structure; 30. a gate structure; 40. a second epitaxial layer; 50. a source electrode; 60. a first groove; 101. a substrate; 102. a first epitaxial layer; 201. an oxide layer; 202. a vertical field plate; 301. a trench gate oxide layer; 302. a trench gate.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the problem of poor performance caused by weak current capability of the super junction device in the prior art is solved, and in order to solve the above problem, the embodiment of the application provides a super junction MOSFET device and a manufacturing method thereof.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
According to an embodiment of the present application, there is provided a super junction MOSFET device, as shown in fig. 1, the super junction MOSFET device includes a base 10 and a plurality of field plate structures 20, wherein the base 10 includes a stacked substrate 101 and a first epitaxial layer 102; the plurality of field plate structures 20 are arranged in the first epitaxial layer 102 at intervals, the field plate structures 20 comprise an oxide layer 201 and a vertical field plate 202, the oxide layer 201 is in contact with the first epitaxial layer 102, surfaces of the vertical field plate 202 and the oxide layer 201, which are far away from the substrate 101, are all flush with surfaces of the first epitaxial layer 102, which are far away from the substrate 101, the vertical field plate 202 is arranged in the oxide layer 201, the extending direction of the vertical field plate 202 is the same as the thickness direction of the first epitaxial layer 102, and the distance between two adjacent field plate structures 20 is larger than the width of the field plate structures 20, wherein the width is the width of the field plate structures 20, which is perpendicular to the thickness direction.
The super junction MOSFET device comprises a substrate and a plurality of field plate structures, wherein the substrate comprises a laminated substrate and a first epitaxial layer; the field plate structures are arranged in the first epitaxial layer at intervals, each field plate structure comprises an oxide layer and a vertical field plate, the oxide layer is in contact with the first epitaxial layer, the surfaces of the vertical field plates, which are far away from the substrate, of the oxide layer are all flush with the surfaces of the first epitaxial layer, which are far away from the substrate, the vertical field plates are arranged in the oxide layer, the extending direction of the vertical field plates is the same as the thickness direction of the first epitaxial layer, the distance between two adjacent field plate structures is larger than the width of the field plate structures, and the width is the width, which is perpendicular to the thickness direction, of the field plate structures. Compared with the problem of poor performance caused by weak current passing capability of the super junction device in the prior art, the super junction MOSFET device of the application ensures that the first epitaxial layer between the adjacent field plate structures is larger in width due to the fact that the distance between the two adjacent field plate structures is larger than the preset width of the field plate structures, ensures that the current passing space of the first epitaxial layer is larger, ensures that the current passing capability of the super junction MOSFET device is better, and ensures that the voltage withstanding capability of the super junction MOSFET device is better due to the existence of the field plate structures. The application solves the problem of poor performance caused by weak current passing capability of the super junction device in the prior art, and ensures better performance of the super junction MOSFET device.
In the prior art, the super junction structure can improve the voltage endurance capability through charge balance, so that the resistance and conduction loss can be reduced and the voltage endurance of the MOSFET can be maintained through increasing the doping concentration of the epitaxial layer. However, since the P-type pillar of the super junction structure does not contribute to conduction, the super junction MOSFET device corresponding to the super junction structure is limited to about 50% of the epitaxial layer utilization rate in the practical process, so that a trade-off relationship exists between the reverse voltage carrying capability and the forward current carrying capability for the high voltage power MOSFET device. Therefore, on the premise of ensuring the target bearing capacity, the device has stronger through-current capacity, but the through-current capacity is limited by the smaller transverse occupation of the epitaxial layer, so that the through-current capacity of the super junction MOSFET device is not fully exerted. The super junction MOSFET device of the application ensures stronger voltage withstand capability through the field plate structures, and simultaneously ensures that the distance between two adjacent field plate structures is larger than the width of the field plate structures because the distance between the two adjacent field plate structures is larger than the preset width of the field plate structures, thereby ensuring that the width of the first epitaxial layer between the adjacent field plate structures is larger, ensuring that the through-flow space of the first epitaxial layer is larger, namely ensuring better through-flow capability and stronger voltage withstand capability.
In the implementation process, in the prior art, under the condition that the width of the super junction is the same as that of the adjacent epitaxial layer, the effective utilization rate of the epitaxial layer (i.e. the drift region) is about 50%, and compared with a semiconductor structure without a super junction structure, the resistance of the chip unit area is doubled, so that the current passing capability of the device is severely limited. In the super junction MOSFET device of the present application, the first epitaxial layer is an electron path, so that the larger the ratio of the width of the first epitaxial layer between adjacent field plate structures to the width of the field plate structure, the larger the electron through-flow path, that is, the larger the lateral effective utilization rate of the drift region, and because the distance between two adjacent field plate structures is larger than the width of the field plate structure, the distance between the adjacent field plate structures is larger than the width of the field plate structure, thereby ensuring that the width of the first epitaxial layer between the adjacent field plate structures is larger, and further ensuring that the through-flow space of the first epitaxial layer is larger.
Of course, the doping concentration of the vertical field plates in the field plate structure may also be relatively high, and the specific doping concentration may be determined according to experimental tests.
In order to further ensure the better performance of the super junction MOSFET device, as shown in fig. 1, the super junction MOSFET device further includes a plurality of gate structures 30, where the gate structures 30 are located on a side of the field plate structures 20 away from the substrate 101, and a projection of each of the gate structures 30 in the first epitaxial layer 102 is located between two adjacent field plate structures 20. The super junction MOSFET device further comprises the grid structure, so that the super junction MOSFET device can achieve the performance of a transistor, and the super junction MOSFET device is further guaranteed to be good in performance.
In a specific implementation, as shown in fig. 1, the super junction MOSFET device further includes a second epitaxial layer 40, where the second epitaxial layer 40 is located on a surface of the first epitaxial layer 102 away from the substrate 101, and the gate structure 30 penetrates through the second epitaxial layer 40. The super junction MOSFET device comprises the second epitaxial layer, and the grid structure can be formed in the second epitaxial layer, so that the super junction MOSFET device can realize the performance of a transistor, and the better performance of the super junction MOSFET device is further ensured.
In the implementation process, the second epitaxial layer comprises a body region, the field plate structure is located below the body region, the vertical field plate and the body region are in the same potential when the super junction MOSFET device is conducted, and then a current channel exists on the side wall of the field plate structure, so that the strong current passing capability of the super junction MOSFET device is ensured.
In order to further ensure the better performance of the super junction MOSFET device, as shown in fig. 1, the super junction MOSFET device further includes a plurality of source electrodes 50, where the source electrodes 50 are located in the second epitaxial layer 40, one of the gate structures 30 corresponds to two source electrodes 50, and the two source electrodes 50 are located on two sides of the corresponding gate structure 30, respectively, and the source electrodes 50 are in contact with the gate structure 30. The super junction MOSFET device further comprises a plurality of source electrodes, the source electrodes are located in the second epitaxial layer, and the two source electrodes are located on two sides of the grid structure, so that the function of the transistor of the super junction MOSFET device can be achieved through the source electrodes and the grid structure, and the performance of the super junction MOSFET device is further guaranteed to be good.
In a specific implementation process, the doping types of the substrate and the first epitaxial layer are N type, and the doping type of the second epitaxial layer is P type. Specifically, the doping types of the first epitaxial layer, the substrate and the source electrode are all N-type, and the doping types of the second epitaxial layer and the vertical field plate are P-type.
In the implementation, the first epitaxial layer may also be referred to as a drift region, and the second epitaxial layer may also be referred to as a body region.
In one embodiment, as shown in fig. 1, the gate structure 30 includes a trench gate oxide layer 301 and a trench gate 302, the trench gate oxide layer 301 penetrates the second epitaxial layer 40 into the first epitaxial layer 102, and the trench gate oxide layer 301 contacts the second epitaxial layer 40; the trench gate 302 is located in the corresponding trench gate oxide layer 301, the trench gate 302 penetrates the second epitaxial layer 40 to the first epitaxial layer 102, and the trench gate 302 is in contact with the trench gate oxide layer 301. Because the gate structure comprises the trench gate oxide layer and the trench gate, and because the trench gate is positioned in the trench gate oxide layer, the trench gate can be protected through the trench gate oxide layer, and the function of a transistor gate can be realized through the trench gate, so that the performance of the super junction MOSFET device can be further ensured.
In the specific implementation process, the trench gate and the vertical field plate are made of the same material. Specifically, the materials of the trench gate and the vertical field plate include polysilicon.
In the implementation process, the materials of the substrate, the second epitaxial layer and the first epitaxial layer all include silicon, and the material of the trench gate oxide layer includes silicon oxide. Of course, the materials of the layers in the super junction MOSFET device are not limited to the above materials, and may be specifically determined according to practical situations.
In a specific embodiment, the ratio of the distance between two adjacent field plate structures to the width of the field plate structures is greater than or equal to 5. Because the ratio of the distance between the adjacent field plate structures to the width of the field plate structures is greater than or equal to 5, the width of the first epitaxial layer between the field plate structures is further ensured to be larger, the through-flow space of the first epitaxial layer is further ensured to be larger, the through-flow capacity of the super junction MOSFET device is further ensured to be better, and the performance of the super junction MOSFET device is further ensured to be better.
In the implementation process, the smaller the ratio of the distance between the adjacent field plate structures to the width of the field plate structures, the larger the through-flow space of the first epitaxial layer.
According to the embodiment of the application, a manufacturing method of any one of the super junction MOSFET devices is also provided.
Fig. 2 is a flow chart of a method of fabricating a superjunction MOSFET device according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:
step S201, as shown in fig. 3, providing a base 10 including a stacked substrate 101 and a first epitaxial layer 102;
specifically, the doping type of the substrate and the first epitaxial layer is N-type, and the material of the substrate and the first epitaxial layer includes silicon.
Step S202, as shown in fig. 3 to 4, removing a portion of the first epitaxial layer 102 to form a plurality of first grooves 60 disposed at intervals, wherein a distance between two adjacent first grooves 60 is greater than a width of the first grooves 60, and the width is a width of the first grooves 60 perpendicular to a thickness direction;
specifically, since the distance between two adjacent first grooves is larger than the width of the first groove, the width of the first epitaxial layer between two adjacent first grooves is larger than the width of the first groove.
In step S203, as shown in fig. 4 to 5, a field plate structure 20 is formed in the first recess 60, where the field plate structure 20 includes an oxide layer 201 and a vertical field plate 202, the oxide layer 201 covers the sidewall and the bottom of the first recess 60, and the vertical field plate 202 is located in the remaining first recess 60.
Specifically, since the field plate structure is located in the first groove, and since the width of the first epitaxial layer between two adjacent first grooves is greater than the width of the first groove, the width of the first epitaxial layer between two adjacent first grooves is greater than the width of the field plate structure.
In the method for manufacturing the super junction MOSFET device, firstly, a substrate is provided, and the substrate comprises a laminated substrate and a first epitaxial layer; then, removing part of the first epitaxial layer to form a plurality of first grooves which are arranged at intervals, wherein the distance between two adjacent first grooves is larger than the width of the first grooves, and the width is perpendicular to the thickness direction of the first grooves; finally, a field plate structure is formed in the first groove, the field plate structure comprises an oxide layer and a vertical field plate, the oxide layer covers the side wall and the bottom of the first groove, and the vertical field plate is located in the rest first groove. Compared with the problem of poor performance caused by weak current passing capability of the super junction MOSFET device in the prior art, the manufacturing method of the super junction MOSFET device of the application ensures that the current passing space of the first epitaxial layer is larger by providing the base comprising the substrate and the first epitaxial layer and removing part of the first epitaxial layer, so that a plurality of first grooves which are arranged at intervals can be obtained, the field plate structure is formed in the first grooves, and the width of the first epitaxial layer between two adjacent first grooves is larger than the width of the field plate structure due to the fact that the distance between the two adjacent first grooves is larger than the width of the first grooves, so that the current passing capability of the super junction MOSFET device is better. The problem of poor performance caused by weak current passing capability of the super junction device in the prior art is solved, and the good performance of the super junction MOSFET device is ensured.
In order to further ensure that the performance of the super junction MOSFET device is better, forming a field plate structure in the first recess includes: performing high-temperature oxidation on the side wall and the bottom of the first groove to form the oxide layer; and forming the vertical field plates in the remaining first grooves. By carrying out high-temperature oxidation on the side wall and the bottom of the first groove, the oxide layer can be formed on the exposed surface of the first groove, and the super junction MOSFET device is better in pressure resistance and performance due to the fact that the field plate structure is better in pressure resistance.
In the implementation process, after the vertical field plate is formed in the remaining first groove, firstly, removing the field plate structure and the surface of the first epitaxial layer, which is far away from the substrate, through a chemical mechanical polishing process; forming a second epitaxial layer on the surface of the first epitaxial layer and the surface of the field plate structure, which is far away from the substrate; then forming the body region by ion implantation in the second epitaxial layer; forming a trench by removing a portion of the second epitaxial layer, and forming the gate structure in the trench; and finally, carrying out ion implantation on the body regions at two sides of the grid structure to form the source region, thereby obtaining the super junction MOSFET device.
Of course, the width of the superjunction is limited by the process, and in order to form a superjunction with a smaller width, the superjunction may be formed as follows. Firstly, forming the super junction in a low-temperature epitaxial mode; secondly, forming a thinner seed layer on the substrate, forming seed crystals in the seed layer at intervals, wherein the seed crystals correspond to the widths of the super junctions, forming super junctions on the surfaces of the seed crystals, and forming drift regions on the surfaces of the epitaxial layers between the super junctions, wherein the super junctions with smaller widths and the drift regions with larger widths are formed.
In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) The super junction MOSFET device comprises a substrate and a plurality of field plate structures, wherein the substrate comprises a laminated substrate and a first epitaxial layer; the field plate structures are arranged in the first epitaxial layer at intervals, each field plate structure comprises an oxide layer and a vertical field plate, the oxide layer is in contact with the first epitaxial layer, the surfaces of the vertical field plates, which are far away from the substrate, of the oxide layer are all flush with the surfaces of the first epitaxial layer, which are far away from the substrate, the vertical field plates are arranged in the oxide layer, the extending direction of the vertical field plates is the same as the thickness direction of the first epitaxial layer, the distance between two adjacent field plate structures is larger than the width of the field plate structures, and the width is the width, which is perpendicular to the thickness direction, of the field plate structures. Compared with the problem of poor performance caused by weak current passing capability of the super junction MOSFET device in the prior art, the super junction MOSFET device has the advantages that the distance between two adjacent field plate structures is larger than the preset width of the field plate structures, so that the distance between the adjacent field plate structures is larger than the width of the field plate structures, the width of the first epitaxial layer between the adjacent field plate structures is ensured to be larger, the current passing space of the first epitaxial layer is ensured to be larger, the better current passing capability of the super junction MOSFET device is ensured, and the better voltage withstanding capability of the super junction MOSFET device is ensured due to the existence of the field plate structures, so that the problem of poor performance caused by weak current passing capability of the super junction device in the prior art is solved, and the better performance of the super junction MOSFET device is ensured.
2) In the manufacturing method of the super junction MOSFET device, firstly, a substrate is provided, and the substrate comprises a laminated substrate and a first epitaxial layer; then, removing part of the first epitaxial layer to form a plurality of first grooves which are arranged at intervals, wherein the distance between two adjacent first grooves is larger than the width of the first grooves, and the width is perpendicular to the thickness direction of the first grooves; finally, a field plate structure is formed in the first groove, the field plate structure comprises an oxide layer and a vertical field plate, the oxide layer covers the side wall and the bottom of the first groove, and the vertical field plate is located in the rest first groove. Compared with the problem of poor performance caused by weak current passing capability of the super junction MOSFET device in the prior art, the manufacturing method of the super junction MOSFET device of the application ensures that the current passing capability of the super junction MOSFET device is better by removing part of the first epitaxial layer by providing the base comprising the substrate and the first epitaxial layer, and then forming the field plate structure in the first groove by forming the first groove at intervals, and the width of the first epitaxial layer between two adjacent first grooves is larger than the width of the field plate structure because the distance between the two adjacent first grooves is larger than the width of the first groove, thereby ensuring that the width of the first epitaxial layer between the two adjacent field plate structures is larger, ensuring that the current passing space of the first epitaxial layer is larger, ensuring that the current passing capability of the super junction MOSFET device is better, and ensuring that the super junction MOSFET device has poor voltage withstanding capability caused by weak current passing capability in the prior art because of the field plate structure.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A super junction MOSFET device, the super junction MOSFET device comprising:
a base including a laminated substrate and a first epitaxial layer;
the field plate structures comprise an oxide layer and vertical field plates, the oxide layer is in contact with the first epitaxial layer, the vertical field plates are located in the oxide layer, the extending direction of the vertical field plates is the same as the thickness direction of the first epitaxial layer, the distance between two adjacent field plate structures is larger than the width of the field plate structures, and the width is perpendicular to the thickness direction of the field plate structures.
2. The super junction MOSFET device of claim 1, further comprising:
and the plurality of gate structures are positioned on one side of the field plate structure, which is far away from the substrate, and the projection of each gate structure in the first epitaxial layer is positioned between two adjacent field plate structures.
3. The super junction MOSFET device of claim 2, further comprising:
and the second epitaxial layer is positioned on the surface, away from the substrate, of the first epitaxial layer, and the grid structure penetrates through the second epitaxial layer.
4. The super junction MOSFET device of claim 3, further comprising:
the source electrodes are positioned in the second epitaxial layer, one grid structure corresponds to two source electrodes, the two source electrodes are respectively positioned on two sides of the corresponding grid structure, and the source electrodes are in contact with the grid structure.
5. The super junction MOSFET device of claim 3, wherein a doping type of said substrate and said first epitaxial layer is N-type and a doping type of said second epitaxial layer is P-type.
6. The super junction MOSFET device of claim 3, wherein said gate structure comprises:
the groove gate oxide layer penetrates through the second epitaxial layer to the first epitaxial layer, and the groove gate oxide layer is in contact with the second epitaxial layer;
the trench gate is positioned in the corresponding trench gate oxide layer, penetrates through the second epitaxial layer and is in contact with the first epitaxial layer.
7. The super junction MOSFET device of claim 6, wherein said trench gate is the same material as said vertical field plate.
8. The super junction MOSFET device of claim 1, wherein a ratio of a distance between two adjacent field plate structures to the width of the field plate structures is greater than or equal to 5.
9. A method of fabricating a super junction MOSFET device according to any one of claims 1 to 8, the method comprising:
providing a base comprising a stacked substrate and a first epitaxial layer;
removing part of the first epitaxial layer to form a plurality of first grooves which are arranged at intervals, wherein the distance between two adjacent first grooves is larger than the width of the first grooves, and the width is perpendicular to the thickness direction of the first grooves;
and forming a field plate structure in the first groove, wherein the field plate structure comprises an oxide layer and a vertical field plate, the oxide layer covers the side wall and the bottom of the first groove, and the vertical field plate is positioned in the rest first groove.
10. The method of claim 9, wherein forming a field plate structure in the first recess comprises:
performing high-temperature oxidation on the side wall and the bottom of the first groove to form an oxide layer;
and forming the vertical field plates in the remaining first grooves.
CN202310686122.XA 2023-06-09 2023-06-09 Super junction MOSFET device and manufacturing method thereof Pending CN116705854A (en)

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