CN116702697A - Trigger of FPGA system and operation method thereof - Google Patents

Abstract

The invention discloses a trigger of an FPGA system and an operation method thereof, wherein the trigger comprises a sampling module, a plurality of single-item operation modules, a polynomial operation module and a state machine control module, wherein the sampling module is used for sampling signals under different reference clocks to obtain a plurality of sampling signals; the single-form operation modules are respectively used for screening the sampling signals and carrying out single-form logic operation on the screened signals; the polynomial operation module is used for performing polynomial logic operation on operation results of the plurality of single-item operation modules; the state machine control module is used for outputting corresponding instructions according to the logic operation result of the polynomial module and preset state machine triggering conditions. The trigger has the advantages of high response speed and flexible configuration.

Description

Trigger of FPGA system and operation method thereof

Technical Field

The invention relates to the field of chip verification, in particular to a trigger of an FPGA system and an operation method thereof.

Background

Triggers (trigger) as debug tools can be applied to verification platforms using FPGAs as user design carriers, including emulators (simulation accelerators), prototype verification platforms. By presetting the expected signal value and the related logic expression, the DUT (Device Under Test, tested device) can make triggering action in time when running to the signal trigger point. The tool can accurately position specific signal combinations, and is convenient for users to accurately position problem sending areas. In order to achieve this function, however, different trigger solutions exist in the prior art.

In one solution, the user's RTL code is modified and the trigger is compiled with the user's DUT. Such a trigger sacrifices a certain flexibility in exchange for a faster response speed. In another technical scheme, the function of the trigger is specially realized by selecting an additional custom chip, and the trigger logic expression can be flexibly configured by a recompilation mode although the total signal input by the trigger is limited. The prior art flip-flop has the common defect that the response speed and the configuration flexibility cannot be combined.

Disclosure of Invention

The invention aims to provide a trigger of an FPGA system and an operation method thereof, wherein the trigger has high response speed and flexible configuration.

The embodiment of the invention provides a trigger of an FPGA system, which comprises a sampling module, a plurality of single-item operation modules, a polynomial operation module and a state machine control module,

the sampling module is used for sampling signals under different reference clocks to obtain a plurality of sampling signals;

the single-form operation modules are respectively used for screening the sampling signals and carrying out single-form logic operation on the screened signals;

the polynomial operation module is used for performing polynomial logic operation on operation results of the plurality of single-item operation modules;

the state machine control module is used for outputting corresponding instructions according to the logic operation result of the polynomial module and preset state machine triggering conditions.

In the embodiment of the invention, the single-form operation module screens the sampling signals by performing logical AND operation on the sampling signals and the corresponding masks.

In the embodiment of the invention, the single-form operation module is divided into a plurality of standard bit width operation modules, and sampling signals with different bit widths are processed in a combined mode.

In the embodiment of the invention, the single-term operation module is preset with judging conditions of a plurality of state machines, and different state machines are used as address pointers to point to corresponding judging conditions.

In the embodiment of the invention, a plurality of different sampling clock configurations are preset in a register configured by the sampling module, and different state machines are used as address pointers to point to corresponding sampling clock configurations.

In the embodiment of the invention, the single-term logic operation is one of judging equal, unequal, detecting rising edge and falling edge.

In the embodiment of the invention, the polynomial logical operation comprises logical AND, logical OR and combinations thereof.

In the embodiment of the invention, the polynomial operation module adopts a logic lookup table to realize the polynomial logical operation, namely, the results of the plurality of single-item logical operation are used as addresses, and the storage value inquired in the corresponding address is used as the result of the polynomial logical operation.

The embodiment of the invention also provides an operation method of the trigger of the FPGA system, which comprises the following steps:

sampling signals under different reference clocks;

screening the plurality of sampling signals respectively, and carrying out single-item logic operation on each screened signal respectively;

performing polynomial logical operation on the results of the plurality of single-form logical operations;

and outputting a corresponding instruction according to the polynomial logical operation result and a preset state machine triggering condition.

In the embodiment of the present invention, the single-term logical operation is one of determining equal, unequal, detecting rising edge and falling edge, and the polynomial logical operation includes logical AND, logical OR and combinations thereof.

Compared with the prior art, the trigger of the FPGA system adopts a plurality of single-form operation modules which are respectively used for screening the sampling signals and carrying out single-form logic operation on the screened signals, so that the trigger conditions can be flexibly configured according to all the sampling signals and the reference clock; the single-item operation module screens the sampling signals by carrying out logical AND operation on the sampling signals and the corresponding masks, so that resources can be consumed as little as possible, and the bit width scale of the signals which can participate in triggering is improved; the polynomial operation module carries out polynomial logic operation on the operation results of the plurality of single-item operation modules in a logic lookup table mode, so that the response speed is improved, and triggering can be realized in a single period; in addition, the sharing of the FPGA by the IP and the user design can be realized, and the sampling transmission delay is reduced.

Drawings

Fig. 1 is a schematic diagram of a trigger of an FPGA system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of different configurations directed by different state machines in an embodiment of the present invention.

Fig. 3 is a schematic diagram of a single-term operation module for filtering a sampling signal according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of performing state switching on a single-element operation module according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of the arithmetic logic of the polynomial operation module according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of the logic operation of the state machine control module according to an embodiment of the present invention.

Fig. 7 is a flowchart of a trigger operation method provided in an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and preferred pixels of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

As shown in fig. 1, in the embodiment of the present invention, a trigger of an FPGA system is provided, which includes a sampling module 1, a plurality of single-term operation modules 2, a polynomial operation module 3, and a state machine control module 4. The following description will be given separately.

The sampling module 1 is configured to sample signals under different reference clocks to obtain a plurality of sampling signals.

The trigger is triggered according to the input signal, and when the input signal satisfies the set state logic, the trigger triggers the corresponding instruction. Therefore, the input signal first needs to be sampled by the sampling module 1. Since different input signals may use different reference clocks, the sampling module 1 operates on the principle that a high frequency clock is used to sample the user reference clock, and then a sampling valid signal flag pulse is output for a configured clock edge.

As shown in fig. 2, the registers configured by the sampling module 1 are pre-configured with a plurality of different sampling clock configurations (CLK tables), and different state machine states (0, 1, 2, 3, …) are used as address pointers to point to the corresponding sampling clock configurations, so that a corresponding Reference clock (Reference CLK) can be selected according to different state machines.

The single-form operation modules 1 are respectively used for screening the sampling signals and performing single-form logic operation on the screened signals.

Since the logic decision on the basis of the input signal of the flip-flop is usually a decision whether it is a certain value or not, the latter is a dynamic change process of a certain signal, the decision action is equal, i.e. not equal, to the decision and the detection of the lower edge, lower edge. Therefore, in the present invention, the single-form logical operation is defined as equal to, not equal to, one of judgment and detection of the lower edge and the lower edge.

It should be noted that the sampled signals are binary in composition, and different signals have different bit widths, thereby expressing the values of the signals. Therefore, after sampling the signal, it is necessary to screen out a designated few bits to participate in the subsequent logic operation. If a selector is used for screening, the resources consumed when the signal bit width rises will also rise exponentially. In the embodiment of the invention, the single-item operation module screens the sampling signals by performing logical AND operation on the sampling signals and the corresponding masks (mask 1 and mask2 …), and the basic AND gate function is utilized, so that resources can be consumed as little as possible, and the signal bit width scale which can participate in triggering is improved. As shown in fig. 3, assuming that the total bit width of the sampled signal is 16 bits, which is divided into signal a [7:0] and signal B [15:8], assuming that the current sampling period is bus=0x4589, if signal B is to be screened out, the BUS signal and the corresponding mask 0xff00 are compared to obtain a screened value 0x4500, and then a determination as to whether it is equal to a certain value can be made.

For the operation of edge detection, the signals are screened in a sampling mask mode, and then whether the screened signals meet the condition of edge jump after two times of sampling is judged. For example, the current sampling value is 0x0010, and a rising edge judgment is to be performed on bit2, and at this time, the bit2 value is 0. And performing AND operation on the sampling value and the mask 0x0020 to obtain 0x0000. The precondition for a rising edge is satisfied at this point, i.e. all values are 0. A flag bit will be set and then wait for the next sampling period to become 0x0020, the rising edge condition is met.

Further, in order to enrich the diversity of the conditions, in the implementation of the present invention, the judging conditions of the single-term operation module 2 may be set, as shown in fig. 2, by setting the judging conditions (value 1, value2, …) of a plurality of state machines in the single-term operation module 2 in advance, and pointing different state machine states (0, 1, 2, 3 …) as address pointers to the corresponding judging conditions. Therefore, the single-item operation module 2 can read different corresponding judgment conditions in different state machines. Specifically, as shown in fig. 4, in the state machine 1, the judgment conditions of the two single-term operation modules are a= =0x56 and b= =0x47, respectively, and in the state machine 2, the judgment conditions of the two single-term operation modules are c= =0x88 and d= =0x33, respectively.

Furthermore, the memory of the single-form operation module 2 may be configured with a plurality of different sampling clocks in advance, and different state machines are used as address pointers to point to the corresponding sampling clocks, where the number of selectable reference clocks is determined by the number of state machines.

In the embodiment of the present invention, the single-form operation module 2 may be further divided into a plurality of standard bit width operation modules, so that sampling signals with different bit widths may be processed in a combined manner. For example, by setting the plurality of single-form operation modules to a plurality of small standard bit width modules (for example, 64 bits), the total bit width of the signal to be processed (for example, 2048 bits, i.e., 32 small modules) can be flexibly handled.

The polynomial operation module 3 is configured to perform polynomial logic operation on the operation results of the plurality of single-term operation modules 2. In the present invention, the polynomial logical operation is defined as logical AND, logical OR, and a combination of logical AND and logical OR.

In the embodiment of the present invention, the polynomial operation module 3 adopts a logic lookup table to implement the polynomial logical operation, that is, the results of the multiple single-term logical operations are used as addresses, and the storage value queried in the corresponding address is used as the result of the polynomial logical operation. As shown in fig. 5, assuming that the polynomial logical operation is a & & B, the output is true when the two single-term operation results are 2' B11 (binary 11), the value stored at the address 0x3 is 1, 1 is stored at the address 0x3 in advance, 0 is stored at other address bits, and 1 is output when the condition is satisfied.

The state machine control module 4 is configured to trigger a corresponding instruction according to a logic operation result of the polynomial module and a preset state machine trigger condition.

The instructions triggered by the state machine control module 4 are used for switching different state machines, trigger counters and memories, and these instructions include: triggering, increasing a counter, resetting the counter, setting a flag bit, resetting the flag bit and jumping a state machine. The state machine control module 4 generates instructions by parsing expressions written by a user, and executes each branch when conditions are satisfied. One state machine expression of the standard contains 3 branches, i.e., if, else if, else. The first two inputs can come from a former polynomial logic module, or from a counter, a flag bit and else are executed with the condition that neither of the former two inputs is satisfied, and the instruction analysis is shown in fig. 6.

Further, as shown in fig. 7, the operation process of the trigger of the FPGA system is as follows:

step S1: sampling signals under different reference clocks;

step S2: screening the plurality of sampling signals respectively, and carrying out single-item logic operation on each screened signal respectively;

step S3: performing polynomial logical operation on the results of the plurality of single-form logical operations;

step S4: and outputting a corresponding instruction according to the polynomial logical operation result and a preset state machine triggering condition.

In summary, in the trigger of the FPGA system of the present invention, a plurality of single-form operation modules are adopted, which are respectively used for screening the sampling signals, and the screened signals are subjected to single-form logic operation, so that the trigger conditions can be flexibly configured according to all the sampling signals and the reference clock; the single-item operation module screens the sampling signals by carrying out logical AND operation on the sampling signals and the corresponding masks, so that resources can be consumed as little as possible, and the bit width scale of the signals which can participate in triggering is improved; the polynomial operation module carries out polynomial logic operation on the operation results of the plurality of single-item operation modules in a logic lookup table mode, so that the response speed is improved, and triggering can be realized in a single period; in addition, the sharing of the FPGA by the IP and the user design can be realized, and the sampling transmission delay is reduced.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (10)

1. A trigger of FPGA system is characterized by comprising a sampling module, a plurality of single-item operation modules, a polynomial operation module and a state machine control module,

the sampling module is used for sampling signals under different reference clocks to obtain a plurality of sampling signals;

the single-form operation modules are respectively used for screening the sampling signals and carrying out single-form logic operation on the screened signals;

the polynomial operation module is used for performing polynomial logic operation on operation results of the plurality of single-item operation modules;

the state machine control module is used for outputting corresponding instructions according to the logic operation result of the polynomial module and preset state machine triggering conditions.

2. The trigger of FPGA system of claim 1 wherein said single-term operation module screens said sampled signals by logically ANDed with a corresponding mask.

3. The trigger of FPGA system of claim 1 wherein the single-term operation module is divided into a plurality of standard bit width operation modules and the sampling signals of different bit widths are processed in a combined manner.

4. The trigger of FPGA system as claimed in claim 1, wherein the single-item operation module is preset with a plurality of judging conditions of state machines, and different state machines are used as address pointers to point to corresponding judging conditions.

5. The trigger of FPGA system of claim 1 wherein a plurality of different sampling clock configurations are pre-arranged in registers of the sampling module configuration and different state machines are pointed to corresponding sampling clock configurations as address pointers.

6. The trigger of the FPGA system of claim 1 wherein the single-term logic operates to determine one of equal, unequal, detect rising and falling edges.

7. The flip-flop of an FPGA system of claim 1 wherein said polynomial logical operation comprises a logical and, a logical or a combination of both.

8. The trigger of FPGA system of claim 1, wherein the polynomial operation module implements the polynomial logical operation using a logical lookup table, i.e., taking the results of the plurality of single-term logical operations as addresses and taking the stored values queried in the corresponding addresses as the results of the polynomial logical operation.

9. A method of operating a trigger of an FPGA system, comprising:

sampling signals under different reference clocks;

screening the plurality of sampling signals respectively, and carrying out single-item logic operation on each screened signal respectively;

performing polynomial logical operation on the results of the plurality of single-form logical operations;

and outputting a corresponding instruction according to the polynomial logical operation result and a preset state machine triggering condition.

10. The method of claim 9, wherein the single-term logical operation is one of determining equal to, unequal to, detecting rising edges, and falling edges, and the polynomial logical operation comprises a logical AND, a logical OR, and combinations thereof.