CN116702684A - Voltage drop repairing method, device, equipment and storage medium - Google Patents
Voltage drop repairing method, device, equipment and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuit design and discloses a voltage drop repairing method, a device, equipment and a storage medium. The invention adjusts the Bump arrangement of the integrated circuit based on a preset mode to obtain an arranged integrated circuit; acquiring RC parasitic parameters of the integrated circuit after arrangement, and performing voltage drop analysis based on the RC parasitic parameters to acquire a voltage drop analysis result; performing physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain a repaired integrated circuit; and a power supply point is provided for the repaired integrated circuit, so that the voltage drop is reduced. The voltage drop analysis is carried out according to RC parasitic parameters of the integrated circuit after the arrangement by adjusting the buffer arrangement, physical layout optimization and voltage drop violation repair are carried out according to the voltage drop analysis result, the voltage drop of the integrated circuit is reduced, dynamic voltage drop is further reduced by providing a power supply point, the operation is convenient and rapid, the design efficiency is improved, and the check time is shortened.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a voltage drop repairing method, device, apparatus, and storage medium.
Background
With the high integration of integrated circuits, a new leap is completed, and the standard units in unit area are increased more and more due to the higher chip integration, so that the negative effect is that the current in unit area is increased more and more, and the power consumption is increased gradually. Therefore, power consumption and voltage drop are reduced to current design directions of the current main stream.
In most digital current back-end designs, the analysis and optimization of voltage drop is placed in a earlier stage of the project, such as: a capacitor formed by MOS tubes, namely a decoupling unit/decoupling capacitor, is arranged between a power supply and a wire, and aims to supplement current to a circuit when the instantaneous current increases and the voltage decreases so as to keep the voltage between the power supply and the ground stable and prevent the voltage drop of the power supply wire and the voltage rise of the ground wire; however, the simulation and analysis optimization of each standard unit can be put to a later stage of the whole project, namely the voltage drop violation time of the detection standard unit is shorter, and the detection standard units need to be repaired one by one in a means repairing mode, so that the design efficiency is reduced, and the signing time is influenced.
The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present invention and is not intended to represent an admission that the foregoing is prior art.
Disclosure of Invention
The invention mainly aims to provide a voltage drop repairing method, a device, equipment and a storage medium, and aims to solve the technical problems that the voltage drop violating time of a voltage drop repairing method for detecting a standard unit in the prior art is short, and the voltage drop violating time is required to be repaired one by one in a manual repairing mode, so that the design efficiency is reduced, and the check time is influenced.
To achieve the above object, the present invention provides a voltage drop repairing method for reducing a voltage drop of an integrated circuit, the method comprising the steps of:
adjusting the Bump arrangement of the integrated circuit based on a preset mode to obtain an integrated circuit after arrangement;
acquiring RC parasitic parameters of the integrated circuit after arrangement, and performing voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result;
performing physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain a repaired integrated circuit;
and providing a power supply point for the repaired integrated circuit, and reducing dynamic voltage drop.
Optionally, the step of acquiring the RC parasitic parameter of the integrated circuit after arrangement and performing voltage drop analysis based on the RC parasitic parameter specifically includes:
acquiring a voltage drop analysis import file, wherein the voltage drop analysis import file is used for providing parameter configuration for voltage drop analysis and power consumption calculation;
calculating circuit power consumption of the integrated circuit after arrangement, and acquiring RC parasitic parameters of the integrated circuit after arrangement based on a calculation result of the circuit power consumption;
and carrying out voltage drop dynamic analysis based on the RC parasitic parameters to obtain a voltage drop analysis result, and storing the voltage drop analysis result into a dynamic analysis database.
Optionally, the step of calculating circuit power consumption of the integrated circuit after arrangement and obtaining RC parasitic parameters of the integrated circuit after arrangement based on a calculation result of the circuit power consumption specifically includes:
calculating the circuit power consumption of the integrated circuit after arrangement, and generating a power consumption analysis file according to the circuit power consumption calculation result;
and acquiring RC parasitic parameters of the integrated circuit after arrangement based on the power consumption analysis file.
Optionally, before the step of obtaining the RC parasitic parameter of the integrated circuit after arrangement and performing voltage drop analysis based on the RC parasitic parameter to obtain a voltage drop analysis result, the method further includes:
calling a Voltus tool to identify an existing voltage drop dense region, and analyzing the power consumption distribution condition of the voltage drop dense region through a power density diagram;
layout blocking is provided to limit the standard cell type and number of the voltage drop dense region.
Optionally, the step of adjusting the Bump arrangement of the integrated circuit based on the preset manner to obtain the arranged integrated circuit specifically includes:
and a method of arranging the bus row by row based on dynamic range control is adopted, so that the upper bus and the lower bus are in a staggered distribution state, and the integrated circuit after arrangement is obtained.
Optionally, the method further comprises:
in the posroute phase, voltage drop optimization is performed using the eco method based on the Innovus tool.
Optionally, before the step of calling the Voltus tool to identify the voltage drop dense region that occurs and analyzing the power consumption distribution of the voltage drop dense region by a power density map, the method further includes:
configuring an environment file of the Voltus tool;
and adding a preset file into the environment file, and generating a voltage drop analysis import file based on the environment file.
In addition, in order to achieve the above object, the present invention also proposes a voltage drop repairing device including:
the arrangement module is used for adjusting the Bump arrangement of the integrated circuits based on a preset mode to obtain the arranged integrated circuits;
the voltage drop analysis module is used for acquiring RC parasitic parameters of the integrated circuit after arrangement, and carrying out voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result;
the violation repair module is used for carrying out physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain a repaired integrated circuit;
and the power supply point providing module is used for providing a power supply point for the repaired integrated circuit and reducing dynamic voltage drop.
In addition, to achieve the above object, the present invention also proposes a voltage drop repairing apparatus, the apparatus comprising: a memory, a processor, and a voltage drop repair program stored on the memory and executable on the processor, the voltage drop repair program configured to implement the steps of the voltage drop repair method as described above.
In addition, in order to achieve the above object, the present invention also proposes a storage medium having stored thereon a voltage drop repairing program which, when executed by a processor, implements the steps of the voltage drop repairing method as described above.
The invention adjusts the Bump arrangement of the integrated circuit based on a preset mode to obtain an arranged integrated circuit; acquiring RC parasitic parameters of the integrated circuit after arrangement, and performing voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result; performing physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain a repaired integrated circuit; and provides a power supply point for the repaired integrated circuit to reduce voltage drop. The voltage drop analysis is carried out according to RC parasitic parameters of the integrated circuit after the arrangement, physical layout optimization and voltage drop violation repair are carried out according to the voltage drop analysis result, the voltage drop of the integrated circuit is reduced, dynamic voltage drop is further reduced by providing a power supply point, the operation is convenient and rapid, and the problems that the voltage drop violation time of a standard unit is short in detection of a voltage drop repair method in the prior art, the repair is carried out one by one in a manual repair mode, the design efficiency is reduced, and the check time is influenced are avoided.
Drawings
FIG. 1 is a schematic diagram of a voltage drop repair apparatus for a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flow chart of a first embodiment of a voltage drop repairing method according to the present invention;
FIG. 3 is a schematic diagram of a Bump arrangement according to the voltage drop repair method of the present invention;
FIG. 4 is a flowchart of a second embodiment of the voltage drop repairing method according to the present invention;
fig. 5 is a block diagram of a first embodiment of a voltage drop repairing method apparatus according to the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a voltage drop repair device in a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the voltage drop repair apparatus may include: a processor 1001, such as a central processing unit (Central Processing Unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, a memory 1005. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may further include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a Wireless interface (e.g., a Wireless-Fidelity (Wi-Fi) interface). The Memory 1005 may be a high-speed random access Memory (Random Access Memory, RAM) or a stable nonvolatile Memory (NVM), such as a disk Memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above.
Those skilled in the art will appreciate that the structure shown in fig. 1 does not constitute a limitation of the voltage drop repair apparatus, and may include more or fewer components than shown, or may combine certain components, or may be a different arrangement of components.
As shown in fig. 1, an operating system, a network communication module, a user interface module, and a voltage drop repair program may be included in the memory 1005 as one type of storage medium.
In the voltage drop repair apparatus shown in fig. 1, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the voltage drop repair apparatus of the present invention may be disposed in the voltage drop repair apparatus, and the voltage drop repair apparatus invokes a voltage drop repair program stored in the memory 1005 through the processor 1001 and executes the voltage drop repair method provided by the embodiment of the present invention.
An embodiment of the present invention provides a voltage drop repairing method, referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of the voltage drop repairing method of the present invention.
In this embodiment, the voltage drop repairing method is used for reducing the voltage drop of the integrated circuit, and includes the following steps:
step S10: and adjusting the Bump arrangement of the integrated circuits based on a preset mode to obtain the arranged integrated circuits.
It should be noted that, the execution body of the method of this embodiment may be a terminal device having functions of data processing and program running, such as a computer, a server, etc., or may be an electronic device having the same or similar functions, such as the above-mentioned voltage drop repairing device. Hereinafter, this embodiment and the following embodiments will be described by taking a voltage drop repairing apparatus (hereinafter referred to as repairing apparatus) as an example.
It should be noted that, the voltage drop (IR drop) refers to a phenomenon that the voltage on the power supply and ground networks in the integrated circuit decreases and increases, and as the semiconductor process is continuously evolving, the width of the metal interconnect line is narrower and narrower, the resistance value is continuously increasing (the supply voltage is also smaller) and the effect of the IR drop is more and more obvious. Therefore, the present chip finally uses the analysis of IR drop as a necessary step of chip signing (sign off).
It should be explained that the voltage drop can be divided into dynamic IR drop and static IR drop. The dynamic IR drop is the voltage drop caused by current fluctuations when the power supply switches the circuit switch. The phenomenon is generated at the trigger edge of the clock, the clock edge jump not only brings a large number of transistor switches of the clock, but also brings jump of the combinational logic circuit, so that large current is often generated on the whole chip in a short time, and the IR drop phenomenon is caused by the instantaneous large current. Meanwhile, the larger the number of transistors of the switch is, the easier the dynamic IR drop phenomenon is triggered.
The static IR drop phenomenon is mainly caused by the voltage division of the metal wire of the power network, which is caused by the self-resistance voltage division of the metal wire. The current is passed through the internal power connection to produce a power supply voltage drop. Static IR drop is mainly related to the structure and wiring details of the power supply network. Therefore, the static IR drop mainly considers the resistance effect, and the influence of the resistance is analyzed.
The voltage drop signature standard is provided by a common foundry, for example, the static IR drop is within 5% and the dynamic IR drop is within 10%, and the specific signature standard can be determined according to different casting technologies, which is not limited in this embodiment.
In practical integrated circuit designs, there are many reasons for the voltage drop. Global reasons such as unreasonable floor plan, or insufficient density of power supply network, etc.; there are also local reasons, such as too many clock buffers in a small area, few decaps, etc.
The scheme fuses the Innovus tool and the voltus tool of Cadence company, optimizes IR-drop by using an eco method in the Postroute stage, and can automatically repair voltage drop violations in the PR stage. And before signing, providing power supply points for the cases, increasing the IO number of the power supply and reducing the dynamic IR-drop.
It should be noted that Innovus is a tool developed by Cadence company, and can be used for automatically implementing links such as layout planning, layout and wiring, time sequence analysis, clock tree synthesis, time sequence optimization, etc. in digital integrated circuit design. Voltus is a Sign-off level chip power supply integrity analysis tool, and can provide accurate and efficient analysis means from a module and an IP level for IC power supply in the aspects of debugging, verification, voltage drop, EM, leakage compensation and the like.
Because the windings determine the load of the cell, the specific voltage drop is not only affected by the local power network and the density of the standard cell, but also by the windings of the standard cell, and the voltage drop analysis and optimization can be performed in three stages of place, CTS (Clock Tree Synthesis, clock tree integration) and route.
It is understood that an integrated circuit is a microelectronic device or component. The integrated circuit adopts a certain process to interconnect the needed elements of transistors, resistors, capacitors, inductors and the like and wiring in the circuit, and the elements are manufactured on a small or a few small semiconductor wafers or dielectric substrates and then packaged in a tube shell to form the microstructure with the needed circuit function.
It should be understood that Bump is a Bump that is a ball-shaped or square-shaped solder joint having a certain size that is manufactured by printing solder, electroless plating, vapor plating solder, electroplating solder, nail head solder, or placing solder balls.
The proposal selects to make a Bump plan when the Floorplan is performed, and optimizes the power supply network. The layout of the Power supply bus and the routing layout of the rewiring layer are design emphasis, the size and spacing of the bus are constrained by DRC, and since the Power supply designs inside the modules are different, the Power consumption of the modules themselves are also different, so that it is required to ensure that the Power coming from the Power pins can be uniformly supplied to the top-level Power strip, and that a stable voltage is supplied to each module of the chip through the high-density top-level Power strip.
In a specific implementation, the Bump arrangement of the integrated circuit is adjusted based on a preset mode, and the arranged integrated circuit is obtained.
The step of adjusting the Bump arrangement of the integrated circuit based on the preset mode to obtain the arranged integrated circuit specifically comprises the following steps:
and a method of arranging the bus row by row based on dynamic range control is adopted, so that the upper bus and the lower bus are in a staggered distribution state, and the integrated circuit after arrangement is obtained.
It should be noted that, in this embodiment, the Bump planning is selected during the Floorplan, so as to implement optimization of the power network. The layout of the Power supply bus and the routing layout of the rewiring layer are design keys, the size and the pitch of the bus are constrained by DRC, and since the Power supply designs inside the modules are different, the Power consumption of the modules is also different, so that it is required to ensure that the Power coming from the Power pins can be uniformly supplied to the top layer Power strip, and stable voltages are supplied to each module of the chip through the high-density top layer Power strip.
As shown in FIG. 3, FIG. 3 is a schematic diagram of a Bump arrangement according to the voltage drop repairing method of the present invention.
In one implementation, the embodiment adopts a method of placing the bus row by row under the condition of DRC (Dynamic Range Control ) permission, and simultaneously ensures that the two buses are in a staggered state, and the power supply intensity of each module is weighted through high-density bus programming, so that the IR-drop of the power supply Pad to the wiring layer can be reduced.
The scheme adopts a hierarchical layout design, power strips are added to metal layers M7 and M8, and a top chip adds Power strips to TM 2; it should be noted that M8 and TM2 are defined as horizontal defense lines, and adjacent VDD and VSS form a power bar group, so that the IR-drop phenomenon of the metal line can be significantly optimized by designing the power network with such high density.
Step S20: and acquiring RC parasitic parameters of the integrated circuit after arrangement, and performing voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result.
It should be noted that after the integrated circuit is designed, an aligned integrated circuit may be obtained, and voltage drop analysis may be performed based on RC parasitic parameters of the aligned integrated circuit, thereby obtaining a repaired integrated circuit.
It should be explained that the parasitic parameter is an indicator that can be used to measure the success of a technique. The parasitic parameters may include parasitic capacitance, parasitic resistance, and parasitic inductance. The RC parasitic parameters are parasitic capacitance and parasitic resistance.
In a specific implementation, the repair device acquires RC parasitic parameters of the integrated circuit after arrangement, and performs voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result.
Step S30: and carrying out physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain the integrated circuit after repair.
It should be noted that too dense standard cell (std cell) distribution is prone to voltage drop violations across instance, so std cells in high density regions need to be broken up. In the embodiment, when voltage Drop analysis is performed, a Voltus tool can be called to identify an occurred voltage Drop dense region (IR Drop hostport), the power consumption distribution situation of the voltage Drop dense region is analyzed through a power density diagram (Power Density Map), and layout blocking is further set to limit the standard cell types and the number of the voltage Drop dense region, so that optimization of voltage Drop is achieved, and a repaired integrated circuit is obtained.
It will be appreciated that standard cells may include a variety of basic cells such as inverters, AND gates, registers, selectors, full adders, and the like, each corresponding to a plurality of different sized (W/L), different drive capability cell circuits, and different drive strength circuits being integer multiples of the basic size or minimum size.
In a specific implementation, the repairing device performs physical layout optimization and voltage drop violation repairing on the integrated circuit after arrangement based on a voltage drop analysis result to obtain the integrated circuit after repairing.
Step S40: and providing a power supply point for the repaired integrated circuit, and reducing dynamic voltage drop.
It should be noted that after the physical design and repair of various violations, the voltage drop of the design can be analyzed again, and at this time, the power supply point can be increased to achieve the purpose of reducing the dynamic voltage drop.
In one implementation, two VDD and VSS are selected as power segments, and power is turned on during analysis to increase the voltage drop.
In a specific implementation, the repair device provides a power supply point for the integrated circuit after repair, and reduces dynamic voltage drop.
According to the embodiment, the integrated circuit is obtained after the Bump arrangement of the integrated circuit is adjusted based on a preset mode; acquiring RC parasitic parameters of the integrated circuit after arrangement, and performing voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result; performing physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain a repaired integrated circuit; and provides a power supply point for the repaired integrated circuit to reduce voltage drop. The voltage drop analysis is carried out according to RC parasitic parameters of the integrated circuit after the arrangement, physical layout optimization and voltage drop violation repair are carried out according to the voltage drop analysis result, the voltage drop of the integrated circuit is reduced, dynamic voltage drop is further reduced by providing a power supply point, the operation is convenient and rapid, and the problems that the voltage drop violation time of a standard unit is short in detection of a voltage drop repair method in the prior art, the repair is carried out one by one in a manual repair mode, the design efficiency is reduced, and the check time is influenced are avoided.
Based on the first embodiment of the voltage drop repairing method of the present invention as described above, a second embodiment of the present invention is proposed in order to further reduce the voltage drop.
Referring to fig. 4, fig. 4 is a flowchart illustrating a second embodiment of the voltage drop repairing method according to the present invention.
In this embodiment, the step of obtaining the RC parasitic parameter of the integrated circuit after arrangement and performing voltage drop analysis based on the RC parasitic parameter specifically includes:
step S21: and acquiring a voltage drop analysis import file, wherein the voltage drop analysis import file is used for providing parameter configuration for voltage drop analysis and power consumption calculation.
It should be explained that, in the voltage drop analysis import file, an analysis mode command for setting a voltage drop analysis mode may be included, by which the voltage drop analysis mode may be selectively set to a static mode or a dynamic mode.
It should be noted that the voltage drop analysis mode includes a dynamic mode and a static mode, and the voltage drop analysis is performed by the dynamic mode, so that the dynamic voltage drop of the integrated circuit can be effectively reduced; the static voltage drop of the integrated circuit can be effectively reduced by the voltage drop analysis of the static mode.
It should be explained that, in the voltage drop analysis import file, a power consumption calculation command for calculating the power consumption of the chip may be further included, and the calculation of the power consumption of the chip may be implemented through the power consumption calculation command.
In a specific implementation, the repair device obtains a voltage drop analysis import file.
Step S22: calculating circuit power consumption of the integrated circuit after arrangement, and acquiring RC parasitic parameters of the integrated circuit after arrangement based on a calculation result of the circuit power consumption;
step S23: and carrying out voltage drop dynamic analysis based on the RC parasitic parameters to obtain a voltage drop analysis result, and storing the voltage drop analysis result into a dynamic analysis database.
It should be noted that, after the circuit power consumption of the integrated circuit after the arrangement is calculated, the RC parasitic parameter of the integrated circuit after the arrangement may be extracted based on the calculation result of the circuit power consumption.
In one implementation manner, the step of calculating circuit power consumption of the integrated circuit after arrangement and obtaining RC parasitic parameters of the integrated circuit after arrangement based on a calculation result of the circuit power consumption specifically includes:
calculating the circuit power consumption of the integrated circuit after arrangement, and generating a power consumption analysis file according to the circuit power consumption calculation result;
and acquiring RC parasitic parameters of the integrated circuit after arrangement based on the power consumption analysis file.
After the power consumption calculation is completed, a power consumption analysis file is obtained. The power consumption analysis file may include a power.rpt file, a power.db file, a ptivg file, and the like. Among other things, the ptavg and power db files can be used for voltage drop analysis.
It can be appreciated that when the power consumption analysis result is obtained, RC parasitic parameters may be extracted and power grid inspection may be performed, so as to obtain the RC parasitic parameters of the integrated circuit after arrangement.
It should be appreciated that the power supply point may also be specified when performing the power consumption analysis, thereby further reducing the dynamic voltage drop of the integrated circuit.
It should be appreciated that the dynamic voltage drop analysis of the integrated circuit may be performed when the RC parasitic parameters of the integrated circuit after alignment are obtained.
In the case of performing dynamic analysis of voltage drop, a DEF file, a SPEF file, a STA file, and a LEF file may be used. When performing the Voltus environment file configuration, these files can be added to the Voltus tool for voltage drop dynamic analysis.
It should be noted that the DEF file is a design exchange format file (Design Exchange Format), and the DEF file is usually a configuration file with a suffix of the DEF format. All integrated circuit sub-modules and top-level design data required by voltage drop analysis can be included in the design exchange format file, and physical information and physical connection information of the integrated circuit design can be obtained through the design exchange format file.
It should be noted that, the SPEF file is a standard parasitic exchange format file (Standard Parasitic Exchange Format), and the file suffix of the SPEF file may be. SPEF. The SPEF file may contain RC parasitic parameter information for the integrated circuit connection.
It should be explained that the STA file is a static timing analysis file, and the file suffix of the STA file may be timing. The static time sequence analysis file can generate specific maximum/minimum conversion time, define a timing window and data of a constant network, and can ensure the signing accuracy. In a specific implementation, the STA file may be generated by the RedHwak tool converting the LIB file, SPEF file, SDC file lamp file in a specified format.
It should be noted that the integrated circuit may include at least one analysis database, where the analysis database may be a dynamic analysis database or a static analysis database, and the analysis database may be used to store analysis results of the voltage drop.
Note that, the above-mentioned LEF file is a library exchange format file (Library Exchange Format), and the file suffix of the LEF file may be, typically, LEF. The library swap format file may include tech.lef and design.lef for all standard cells and hard cores.
In specific implementation, the repairing device calculates circuit power consumption of the integrated circuit after arrangement, acquires RC parasitic parameters of the integrated circuit after arrangement based on a calculation result of the circuit power consumption, performs voltage drop dynamic analysis based on the RC parasitic parameters, acquires a voltage drop analysis result, and stores the voltage drop analysis result in a dynamic analysis database.
It should be noted that, in order to make the voltage drop analysis more efficient, the step of calling the Voltus tool to identify the voltage drop dense region that occurs and analyzing the power consumption distribution of the voltage drop dense region by the power density map is preceded by the step of:
configuring an environment file of the Voltus tool;
and adding a preset file into the environment file, and generating a voltage drop analysis import file based on the environment file.
Before the voltage drop analysis, the environment files of the Voltus tool may be configured, and the configuration of the std library, the mem library, the IP library, and other environment files may be performed.
It should be explained that the preset file may be a DEF file, a SPEF file, a STA file, or a LEF file as described above.
It should be noted that the voltage drop analysis and optimization can be performed by the Innovus tool, and the repair device can perform the voltage drop optimization based on the Innovus tool in the posome stage. The repair device adjusts the standard unit of the design by refine based on Innovus tool, and uses eco method to make final analysis and optimization to IR, the code for adjusting can be as follows:
refinePlace
setNanoRouteMode-routewithEco true
-routewithSiDriven false
-routewithTimingDriven false
setNanoRouteMode-drouteFixAntenna true
setNanoRouteMode-drouteUseMulticutviaEffort low
#setNanoRouteMode-routeAntennaCellName"ANTENNA"
#setNanoRouteMode-routeInsertAntennaDiode true
ecoRoute
#ecoRoute-target
#globalDetailRoute
the NanoRoute is a SMART Routing. Its functions may include:
1.Concurrent Signal integrity (SI influence is taken into account at the time of Routing)
2.Concurrent Manufacturing Aware Routing (DFM influence is taken into account in Routing)
3.Concurrent Timing-driven(timing driven routing)
It should be explained that, through the design of each parameter of the nano route, the standard unit adjustment of the design through the refinish is realized, the eco method is used for carrying out final analysis and optimization on the voltage drop, so as to achieve the purpose of reducing the voltage drop, and the power supply point can be provided later, the IO number of the power supply is increased, and the further reduction of the dynamic voltage drop is realized.
According to the embodiment, the voltage drop analysis import file is obtained, the circuit power consumption of the integrated circuit after arrangement is calculated according to the voltage drop analysis import file, and RC parasitic parameters of the integrated circuit after arrangement are obtained based on the calculation result of the circuit power consumption; and carrying out voltage drop dynamic analysis based on the RC parasitic parameters, and storing the obtained voltage drop analysis result into a dynamic analysis database. The power consumption calculation is performed by importing the file through the voltage drop analysis, and the parasitic parameters are extracted, so that the voltage drop dynamic analysis is realized, and the accuracy of the voltage drop analysis and the effect of voltage drop optimization are further enhanced.
In addition, the embodiment of the invention also provides a storage medium, wherein the storage medium stores a voltage drop repairing program, and the voltage drop repairing program realizes the steps of the voltage drop repairing method when being executed by a processor.
Based on the first embodiment of the voltage drop repairing method of the present invention, a first embodiment of the voltage drop repairing device of the present invention is provided, and referring to fig. 5, fig. 5 is a block diagram of the first embodiment of the voltage drop repairing device of the present invention.
As shown in fig. 5, the voltage drop repairing apparatus according to the embodiment of the present invention includes:
the arrangement module 501 is configured to adjust a Bump arrangement of the integrated circuits based on a preset manner, so as to obtain an integrated circuit after arrangement;
the voltage drop analysis module 502 is configured to obtain an RC parasitic parameter of the integrated circuit after arrangement, and perform voltage drop analysis based on the RC parasitic parameter to obtain a voltage drop analysis result;
the violation repair module 503 is configured to perform physical layout optimization and voltage drop violation repair on the arranged integrated circuits based on the voltage drop analysis result, so as to obtain repaired integrated circuits;
and the power supply point providing module 504 is configured to provide a power supply point for the repaired integrated circuit, so as to reduce dynamic voltage drop.
Further, the voltage drop analysis module 502 is further configured to obtain a voltage drop analysis import file, where the voltage drop analysis import file is used to provide parameter configuration for voltage drop analysis and power consumption calculation; calculating circuit power consumption of the integrated circuit after arrangement, and acquiring RC parasitic parameters of the integrated circuit after arrangement based on a calculation result of the circuit power consumption; and carrying out voltage drop dynamic analysis based on the RC parasitic parameters to obtain a voltage drop analysis result, and storing the voltage drop analysis result into a dynamic analysis database.
Further, the voltage drop analysis module 502 is further configured to calculate circuit power consumption of the integrated circuit after arrangement, and generate a power consumption analysis file according to the circuit power consumption calculation result; and acquiring RC parasitic parameters of the integrated circuit after arrangement based on the power consumption analysis file.
Further, the voltage drop repairing device further comprises a physical design module, wherein the physical design module is used for calling a Voltus tool to identify an existing voltage drop dense region and analyzing the power consumption distribution condition of the voltage drop dense region through a power density diagram; layout blocking is provided to limit the standard cell type and number of the voltage drop dense region.
Further, the physical design module is further configured to control a method of adopting a Bump row-by-row emission based on a dynamic range, so that the upper and lower rows of bumps are in a staggered state, so as to obtain an integrated circuit after the arrangement.
Further, the voltage drop analysis module 502 is further configured to perform voltage drop optimization using an eco method based on the Innovus tool in a pos stage.
Further, the apparatus further comprises: the environment configuration module is used for configuring the environment file of the Voltus tool; and adding a preset file into the environment file, and generating a voltage drop analysis import file based on the environment file.
Other embodiments or specific implementations of the voltage drop repairing device of the present invention may refer to the above method embodiments, and will not be described herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. read-only memory/random-access memory, magnetic disk, optical disk), comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. A method for voltage drop repair, the method for reducing a voltage drop of an integrated circuit, the method comprising:
adjusting the Bump arrangement of the integrated circuit based on a preset mode to obtain an integrated circuit after arrangement;
acquiring RC parasitic parameters of the integrated circuit after arrangement, and performing voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result;
performing physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain a repaired integrated circuit;
and providing a power supply point for the repaired integrated circuit, and reducing dynamic voltage drop.
2. The method for repairing voltage drop of claim 1, wherein the steps of obtaining the RC parasitic parameters of the integrated circuit after arrangement and performing voltage drop analysis based on the RC parasitic parameters comprise:
acquiring a voltage drop analysis import file, wherein the voltage drop analysis import file is used for providing parameter configuration for voltage drop analysis and power consumption calculation;
calculating circuit power consumption of the integrated circuit after arrangement, and acquiring RC parasitic parameters of the integrated circuit after arrangement based on a calculation result of the circuit power consumption;
and carrying out voltage drop dynamic analysis based on the RC parasitic parameters to obtain a voltage drop analysis result, and storing the voltage drop analysis result into a dynamic analysis database.
3. The method for repairing voltage drop of claim 2, wherein the step of calculating circuit power consumption of the integrated circuit after arrangement and obtaining RC parasitic parameters of the integrated circuit after arrangement based on the calculation result of the circuit power consumption specifically comprises:
calculating the circuit power consumption of the integrated circuit after arrangement, and generating a power consumption analysis file according to the circuit power consumption calculation result;
and acquiring RC parasitic parameters of the integrated circuit after arrangement based on the power consumption analysis file.
4. The method of voltage drop repair as claimed in claim 2, wherein, before the step of obtaining the RC parasitic parameters of the integrated circuit after arrangement and performing voltage drop analysis based on the RC parasitic parameters to obtain the voltage drop analysis result, the method further comprises:
calling a Voltus tool to identify an existing voltage drop dense region, and analyzing the power consumption distribution condition of the voltage drop dense region through a power density diagram;
layout blocking is provided to limit the standard cell type and number of the voltage drop dense region.
5. The method for repairing voltage drop of claim 1, wherein the step of adjusting the Bump arrangement of the integrated circuit based on a preset manner to obtain the arranged integrated circuit comprises:
and a method of arranging the bus row by row based on dynamic range control is adopted, so that the upper bus and the lower bus are in a staggered distribution state, and the integrated circuit after arrangement is obtained.
6. The voltage drop remediation method of claim 1, further comprising:
in the posroute phase, voltage drop optimization is performed using the eco method based on the Innovus tool.
7. The voltage drop remediation method of claim 4 wherein, prior to the step of invoking the Voltus tool to identify an area of voltage drop concentration that occurs and analyzing the power consumption profile of the area of voltage drop concentration by means of a power density map, the method further comprises:
configuring an environment file of the Voltus tool;
and adding a preset file into the environment file, and generating a voltage drop analysis import file based on the environment file.
8. A voltage drop repair device, the voltage drop repair device comprising:
the arrangement module is used for adjusting the Bump arrangement of the integrated circuits based on a preset mode to obtain the arranged integrated circuits;
the voltage drop analysis module is used for acquiring RC parasitic parameters of the integrated circuit after arrangement, and carrying out voltage drop analysis based on the RC parasitic parameters to obtain a voltage drop analysis result;
the violation repair module is used for carrying out physical layout optimization and voltage drop violation repair on the integrated circuit after arrangement based on the voltage drop analysis result to obtain a repaired integrated circuit;
and the power supply point providing module is used for providing a power supply point for the repaired integrated circuit and reducing dynamic voltage drop.
9. A voltage drop remediation device, the device comprising: a memory, a processor and a voltage drop repair program stored on the memory and executable on the processor, the voltage drop repair program configured to implement the steps of the voltage drop repair method of any one of claims 1 to 7.
10. A storage medium having stored thereon a voltage drop repair program which when executed by a processor implements the steps of the voltage drop repair method of any one of claims 1 to 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117195782A (en) * | 2023-09-08 | 2023-12-08 | 上海合芯数字科技有限公司 | Method for detecting dynamic voltage drop in early stage of physical design and related equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117195782A (en) * | 2023-09-08 | 2023-12-08 | 上海合芯数字科技有限公司 | Method for detecting dynamic voltage drop in early stage of physical design and related equipment |
| CN117195782B (en) * | 2023-09-08 | 2024-05-07 | 上海合芯数字科技有限公司 | Method for detecting dynamic voltage drop in early stage of physical design and related equipment |
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