CN116702667A - Regression testing method, device, equipment and medium for chip - Google Patents
Regression testing method, device, equipment and medium for chip Download PDFInfo
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Abstract
The invention discloses a regression testing method, device, equipment and medium of a chip. Comprising the following steps: acquiring each test case, and dividing the test cases into a plurality of initial test groups; testing each initial test packet in a test process, acquiring initial test information of each test case in the initial test packet, and dividing the test cases into a plurality of test case groups; under the appointed time node, determining a current test packet in a target test case group, and testing the current test packet in a test process to obtain current test information of each test case in the current test packet; and updating each test case group in real time according to the current test information, determining a current test group according to the updated test case group and testing under the next appointed time node until all the test cases meet the test completion condition, and ending the test process. By adopting the technical scheme, the test cases can be grouped reasonably, the test efficiency is improved, and the cost is saved.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a regression testing method, apparatus, device, and medium for a chip.
Background
In the whole flow of chip design, simulation verification is an essential link for ensuring the delivery quality of the chip, and in the simulation verification process, regression testing is a necessary and important means. The regression test needs to execute all test cases in one round of test period, the user needs to analyze the failed test cases after the test, complete debugging and repairing, start a new round of test period, and repeatedly iterate the test for a plurality of times to ensure that no new problem can be found.
However, as the scale and complexity of chip design are continuously increased, the number of test cases is often increased in multiple, the number of test cases is far more than the concurrent quantity of the practical one-time executable cases, and the test cases must be executed in multiple batches, and the simulation time required by different cases is different, which results in that a great amount of maintenance cost is required for fully utilizing computing resources, and the design potential risks of different test cases are different, wherein the design points with larger risks often need to be subjected to multiple rounds of regression test to completely expose the problem, which results in that the regression test needs longer time to reach the convergence goal.
Disclosure of Invention
The invention provides a regression testing method, device, equipment and medium for chips, which can reasonably group test cases, improve the testing efficiency and save the cost.
According to an aspect of the present invention, there is provided a regression testing method of a chip, including:
acquiring each test case, and dividing the test cases into a plurality of initial test groups according to standard computing resources of each test case and total computing resources of a test process;
testing each initial test packet in a test process, obtaining initial test information of each test case in the initial test packet, and dividing the test cases into a plurality of test case groups according to the initial test information;
under the appointed time node, determining a current test packet in a target test case group according to the current residual computing resources of the test process, and testing the current test packet in the test process to obtain the current test information of each test case in the current test packet;
and updating each test case group in real time according to the current test information, determining a current test group according to the updated test case group and testing under the next appointed time node until all the test cases meet the test completion condition, and ending the test process.
According to another aspect of the present invention, there is provided a regression testing apparatus of a chip, including:
the initial test grouping dividing module is used for acquiring each test case and dividing the test cases into a plurality of initial test groupings according to standard computing resources of each test case and total computing resources of a test process;
the test case group selection module is used for testing each initial test packet in the test process, acquiring initial test information of each test case in the initial test packet, and dividing the test cases into a plurality of test case groups according to the initial test information;
the current test information acquisition module is used for determining a current test packet in the target test case group according to the current residual computing resources of the test process under the appointed time node, and testing the current test packet in the test process to acquire the current test information of each test case in the current test packet;
and the circulation test module is used for updating each test case group in real time according to the current test information, determining the current test group according to the updated test case group and testing the current test group under the next appointed time node until all the test cases meet the test completion condition, and ending the test process.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the regression testing method of the chip according to any one of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a regression testing method of the chip according to any one of the embodiments of the present invention.
According to the technical scheme, the test cases are divided into a plurality of initial test groups according to standard computing resources of the test cases and total computing resources of the test processes, the plurality of test case groups are divided according to initial test information of the initial test groups, the current test groups are determined under a designated time node according to current residual computing resources of the test processes, the test case groups are updated in real time according to test information of the current test groups until all the test cases meet test completion conditions, and the test process is ended.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a regression testing method of a chip according to a first embodiment of the present invention;
FIG. 2 is a flowchart of another regression testing method of a chip according to the second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a regression testing apparatus for chips according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device implementing a regression testing method of a chip according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a flowchart of a regression testing method for a chip according to an embodiment of the present invention, where the method may be implemented by a regression testing device for a chip, and the regression testing device for a chip may be implemented in hardware and/or software, and may be configured in a computer or a processor with a data processing function. As shown in fig. 1, the method includes:
s110, acquiring each test case, and dividing the test cases into a plurality of initial test groups according to standard computing resources of each test case and total computing resources of a test process.
It will be appreciated that the computing resources required for the various test cases are different, and that when the test cases are built, there may generally be a standard computing resource that matches the standard computing resource, but in the actual test process, there may be a deviation between the computing resources actually consumed by the test cases and the standard computing resource. The test cases need to be loaded into the test process for testing, the test process has a calculation resource limitation, and the sum of the calculation resources of the test cases loaded into the test process is required to be smaller than the total calculation resources of the test process. In order to save test time and improve test efficiency, test cases can be grouped and tested in groups.
According to the technical scheme, in order to ensure the grouped test case groups, the test efficiency can be improved to the greatest extent, the test time is saved, the initial test groups are divided firstly, the current test groups currently used for testing are divided again according to the test results of the initial test groups, and the current test groups are updated in real time according to the test results of each round, so that each test group loaded into the test process can ensure that the test time is close, and the utilization of the test resources is maximized.
Optionally, when the test cases are obtained, the information such as the test iteration number, the name and the test method of each test case can also be obtained.
Optionally, the initial test packets may be partitioned according to standard computing resources of each test case such that the sum of the standard computing resources of the test cases for each initial test packet is greater than a preset threshold, it being understood that the preset threshold approximates the total computing resources of the test process such that the total computing resources required for each initial test packet approximates the total computing resources of the test process.
S120, testing each initial test packet in a test process, obtaining initial test information of each test case in the initial test packet, and dividing the test cases into a plurality of test case groups according to the initial test information.
It is understood that the initial test information may refer to test information of an initial test packet, where the test information may include an actual test time, an actual computing resource, a test result success or failure of each test case in the initial test packet, and the number of remaining iterations required for the iterative test.
Optionally, after the initial test information of each test case is obtained, the priority of each test case may be updated according to the test result of each test case.
An alternative priority updating method may be to assign an initial priority of 0 to each test case, add 1 to the priority if the test result is failed, subtract 1 to the priority if the test result is successful, and not reduce the priority of the test case with a priority of 0 if the test result is successful.
Optionally, according to the priority information of each test case, the test cases with the same priority are divided into the same test case group.
Optionally, after each round of iterative testing, the priority of the round of testing cases needs to be updated, and the testing case group is updated according to the updated priority.
S130, under a designated time node, determining a current test packet in a target test case group according to the current residual computing resources of the test process, and testing the current test packet in the test process to obtain the current test information of each test case in the current test packet.
It can be appreciated that, in order to ensure that the test process performs the non-intermittent test, a group of current test packets may be supplemented to the test process when the designated time node arrives, so that the current test packets can be tested immediately after the last current test packet is tested. Since the last current test packet may have test cases not yet been tested when the current test packet is supplemented, at this time, the current remaining computing resources of the test process may be obtained, and the current test case set may be determined according to the current remaining computing resources.
Optionally, the designated time node may be preset, and when each round of designated time node arrives, it may be ensured that a certain amount of test cases have been tested in the test process, but there are still incomplete test cases.
Alternatively, the target test case set may refer to a selected test case set of specified priority when determining the current test packet. The target test case group may select the test case group with the highest current priority.
When determining the current test packet, the current test packet may be determined according to the actual test time and the actual computing resources of each test case in the target test case group, and on the basis that the sum of the actual computing resources of each test case in the current test case group needs to be ensured to be similar to the current remaining computing resources of the test process, the actual test time of each test case in the current test case group needs to be made similar as much as possible.
Alternatively, the current test information may refer to the test information of the current test packet.
And S140, updating each test case group in real time according to the current test information, determining a current test group according to the updated test case group and testing under the next appointed time node until all the test cases meet the test completion condition, and ending the test process.
Alternatively, each test case may have an iteration number, and when the number of successive successes of the test case satisfies the iteration number, a test completion condition may be satisfied. When all test cases of the round of test meet the test completion conditions, the test process can be ended, and when part of test cases meet the test completion conditions and part of test cases do not meet the test completion conditions, the test cases meeting the test completion conditions are removed from the test case group, so that the test cases in the current test groups screened in each round are ensured to not meet the test completion conditions.
According to the technical scheme, the test cases are divided into a plurality of initial test groups according to standard computing resources of the test cases and total computing resources of the test processes, the plurality of test case groups are divided according to initial test information of the initial test groups, the current test groups are determined under a designated time node according to current residual computing resources of the test processes, the test case groups are updated in real time according to test information of the current test groups until all the test cases meet test completion conditions, and the test process is ended.
Example two
Fig. 2 is a flowchart of another regression testing method for chips according to the second embodiment of the present invention, and the present embodiment specifically illustrates a grouping process of test cases based on the foregoing embodiment. As shown in fig. 2, the method includes:
s210, acquiring each test case.
S220, according to the standard computing resources of each test case, the test cases are added into the groups one by one, and the total computing resources of the groups are detected in real time.
S230, determining the group as an initial test group when the total computing resource of the group is greater than a preset first computing resource threshold and less than the total computing resource of the test process.
Alternatively, the first computing resource threshold may be a value that approximates the total computing resource of the test process.
S240, testing each initial test packet in the test process to obtain the initial test information of each test case in the initial test packet.
S250, obtaining test results in the initial test information of each test case, and changing the priority of each test case according to the test results in the initial test information.
S260, dividing all the test cases with the same priority into the same test case group according to the priorities of all the test cases.
S270, under the appointed time node, determining a target test case group in a plurality of test case groups according to the priority of each test case group.
S280, acquiring actual execution time of each test case in the target test case group, and determining a plurality of alternative test cases in the target test case group according to the actual execution time of each test case.
Optionally, according to the actual execution time of each test case, the test case with the actual execution time within a certain error range can be screened out as an alternative test case.
S290, adding the alternative test cases into the group one by one according to the current residual computing resources of the test process and the actual computing resources of the alternative test cases, and detecting the total computing resources of the group in real time.
And S2100, determining the grouping as the current test grouping when the total computing resource of the grouping is greater than a preset second computing resource threshold and is less than the current residual computing resource of the test process.
Alternatively, the second computing resource threshold may be a value approximating the current remaining computing resources, and since the current remaining computing resources are typically of varying value, a proportion may be set, for example 99%, i.e. the second computing resource threshold may be 99% of the current remaining computing resources.
S2110, testing the current test packet in the test process, and obtaining the current test information of each test case in the current test packet.
S2120, updating each test case group in real time according to the current test information, determining a current test group according to the updated test case group and testing under the next appointed time node until all test cases meet the test completion condition, and ending the test process.
Alternatively, after all the test cases of each test packet complete the test, a test report matching the test packet may be generated and sent to the user.
It will be appreciated that after all test cases in each test packet have completed testing, a test report matching the test packet may be generated based on information desired by the user.
Optionally, after all the test cases complete the test, the execution times of each test case can be obtained, the test information of the test cases with the same execution times is summarized, and a final test report is generated;
and detecting a test result curve of each test case in the final test report, screening out test cases which do not meet the standard according to the detection result, and sending the final test report and the test cases which do not meet the standard to a user together.
It can be understood that, because a successful or failed result may occur in the test process, the final test frequency of each test case may not be the same as the preset iteration frequency, and further, according to the actual execution frequency of each test case and the data requirement of the user on the final test report, the test information of each test case with the same execution frequency may be summarized, and the final test report may be generated.
In an alternative embodiment, a test result curve may be generated based on the actual number of executions and the results success or failure of each time. According to the test result curve, failure or success trend of each test case in the whole test flow can be observed, and test cases which do not meet the standard can be screened out according to the preset judgment standard.
According to the technical scheme, the test cases are divided into a plurality of initial test groups according to standard computing resources of the test cases and total computing resources of the test processes, the plurality of test case groups are divided according to initial test information of the initial test groups, the current test groups are determined under a designated time node according to current residual computing resources of the test processes, the test case groups are updated in real time according to test information of the current test groups until all the test cases meet test completion conditions, and the test process is ended.
Further, the regression testing method of the chip may further include:
when determining that a failure test case with test failure exists in the target test packet according to the test information, establishing a failure test case test process, and loading each failure test case into the failure test case test process for testing;
and acquiring test information of the failed case matched with the failed case test process, and sending the test information of the failed case to a user.
Optionally, when a failed test case exists in the target test packet, the test case may not be immediately put into the next round of test, and the user may need to correct the information of the test case before dividing the test case group again. In addition, since the user needs more test data to correct the failed test case, and the test process cannot provide enough test data to improve the test efficiency, the test failed case process can be additionally built outside the test process, and the test failed test case is loaded into the test failed case process for testing, so that more abundant test information is obtained.
Further, the regression testing method of the chip may further include:
when the designated test packet sent by the user is detected, the designated test packet is tested in the test process according to the time selected by the user.
Optionally, for the test case specified by the user, the test case can be immediately added into the test process to perform the test, so as to meet the requirements of different users.
Example III
Fig. 3 is a schematic structural diagram of a regression testing device for chips according to a third embodiment of the present invention. As shown in fig. 3, the apparatus includes: an initial test grouping module 310, a test case group selection module 320, a current test information acquisition module 330, and a loop test module 340.
The initial test packet dividing module 310 is configured to obtain each test case, and divide the test case into a plurality of initial test packets according to standard computing resources of each test case and total computing resources of a test process.
The test case group selection module 320 is configured to test each initial test packet in a test process, obtain initial test information of each test case in the initial test packet, and divide the test cases into a plurality of test case groups according to the initial test information.
The current test information obtaining module 330 is configured to determine, under a specified time node, a current test packet in the target test case group according to current remaining computing resources of the test process, and test the current test packet in the test process to obtain current test information of each test case in the current test packet.
And the circulation test module 340 is configured to update each test case group in real time according to the current test information, determine a current test packet according to the updated test case group and perform a test under the next designated time node until all test cases meet the test completion condition, and end the test process.
According to the technical scheme, the test cases are divided into a plurality of initial test groups according to standard computing resources of the test cases and total computing resources of the test processes, the plurality of test case groups are divided according to initial test information of the initial test groups, the current test groups are determined under a designated time node according to current residual computing resources of the test processes, the test case groups are updated in real time according to test information of the current test groups until all the test cases meet test completion conditions, and the test process is ended.
Based on the above embodiments, the initial test packet dividing module 310 may be specifically configured to:
according to the standard computing resources of each test case, adding the test cases into the groups one by one, and detecting the total computing resources of the groups in real time;
when the total computing resource of the packet is greater than a preset first computing resource threshold and less than the total computing resource of the test process, the packet is determined to be an initial test packet.
On the basis of the above embodiments, the test information includes the test result, the actual computing resource, and the actual execution time.
Based on the above embodiments, the test case group selecting module 320 may be specifically configured to:
acquiring test results in initial test information of each test case, and changing the priority of each test case according to the test results in the initial test information;
and dividing the test cases with the same priority into the same test case group according to the priorities of the test cases.
Based on the above embodiments, the current test information obtaining module 330 may be specifically configured to:
under a designated time node, determining a target test case group from a plurality of test case groups according to the priority of each test case group;
acquiring the actual execution time of each test case in the target test case group, and determining a plurality of alternative test cases in the target test case group according to the actual execution time of each test case;
according to the current residual computing resources of the test process and the actual computing resources of each alternative test case, adding the alternative test cases into the group one by one, and detecting the total computing resources of the group in real time;
when the total computing resource of the packet is greater than the preset second computing resource threshold and less than the current remaining computing resources of the test process, the packet is determined to be the current test packet.
Based on the above embodiments, the system may further include a failure test information acquisition module, specifically configured to:
when determining that a failure test case with test failure exists in the target test packet according to the test information, establishing a failure test case test process, and loading each failure test case into the failure test case test process for testing;
and acquiring test information of the failed case matched with the failed case test process, and sending the test information of the failed case to a user.
On the basis of the above embodiments, the device may further include a test specification module, specifically configured to:
when the designated test packet sent by the user is detected, the designated test packet is tested in the test process according to the time selected by the user.
Based on the above embodiments, the system may further include a test report acquisition module, specifically configured to:
after all the test cases of each test group are tested, generating a test report matched with the test group and sending the test report to a user; and
after all test cases are tested, acquiring the execution times of each test case, summarizing the test information of each test case with the same execution times, and generating a final test report;
and detecting a test result curve of each test case in the final test report, screening out test cases which do not meet the standard according to the detection result, and sending the final test report and the test cases which do not meet the standard to a user together.
The regression testing device for the chip provided by the embodiment of the invention can execute the regression testing method for the chip provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example IV
Fig. 4 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the regression testing method of the chip as described in the embodiments of the present invention. Namely:
acquiring each test case, and dividing the test cases into a plurality of initial test groups according to standard computing resources of each test case and total computing resources of a test process;
testing each initial test packet in a test process, obtaining initial test information of each test case in the initial test packet, and dividing the test cases into a plurality of test case groups according to the initial test information;
under the appointed time node, determining a current test packet in a target test case group according to the current residual computing resources of the test process, and testing the current test packet in the test process to obtain the current test information of each test case in the current test packet;
and updating each test case group in real time according to the current test information, determining a current test group according to the updated test case group and testing under the next appointed time node until all the test cases meet the test completion condition, and ending the test process.
In some embodiments, the regression testing method of the chip may be implemented as a computer program, which is tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the regression testing method of the chip described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the regression testing method of the chip in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A regression testing method of a chip, comprising:
acquiring each test case, and dividing the test cases into a plurality of initial test groups according to standard computing resources of each test case and total computing resources of a test process;
testing each initial test packet in a test process, obtaining initial test information of each test case in the initial test packet, and dividing the test cases into a plurality of test case groups according to the initial test information;
under the appointed time node, determining a current test packet in a target test case group according to the current residual computing resources of the test process, and testing the current test packet in the test process to obtain the current test information of each test case in the current test packet;
and updating each test case group in real time according to the current test information, determining a current test group according to the updated test case group and testing under the next appointed time node until all the test cases meet the test completion condition, and ending the test process.
2. The method of claim 1, wherein dividing the test cases into a plurality of initial test packets based on standard computing resources for each test case and total computing resources for the test process, comprises:
according to the standard computing resources of each test case, adding the test cases into the groups one by one, and detecting the total computing resources of the groups in real time;
when the total computing resource of the packet is greater than a preset first computing resource threshold and less than the total computing resource of the test process, the packet is determined to be an initial test packet.
3. The method of claim 1, wherein the test information includes test results, actual computing resources, and actual execution time;
the method comprises the steps of dividing test cases into a plurality of test case groups according to the initial test information, wherein the steps comprise:
acquiring test results in initial test information of each test case, and changing the priority of each test case according to the test results in the initial test information;
and dividing the test cases with the same priority into the same test case group according to the priorities of the test cases.
4. A method according to claim 3, wherein determining the current test packet in the target test case group based on the current remaining computing resources of the test process at the specified time node comprises:
under a designated time node, determining a target test case group from a plurality of test case groups according to the priority of each test case group;
acquiring the actual execution time of each test case in the target test case group, and determining a plurality of alternative test cases in the target test case group according to the actual execution time of each test case;
according to the current residual computing resources of the test process and the actual computing resources of each alternative test case, adding the alternative test cases into the group one by one, and detecting the total computing resources of the group in real time;
when the total computing resource of the packet is greater than the preset second computing resource threshold and less than the current remaining computing resources of the test process, the packet is determined to be the current test packet.
5. The method of any one of claims 1-4, further comprising:
when determining that a failure test case with test failure exists in the target test packet according to the test information, establishing a failure test case test process, and loading each failure test case into the failure test case test process for testing;
and acquiring test information of the failed case matched with the failed case test process, and sending the test information of the failed case to a user.
6. The method as recited in claim 1, further comprising:
when the designated test packet sent by the user is detected, the designated test packet is tested in the test process according to the time selected by the user.
7. The method as recited in claim 1, further comprising:
after all the test cases of each test group are tested, generating a test report matched with the test group and sending the test report to a user; and
after all test cases are tested, acquiring the execution times of each test case, summarizing the test information of each test case with the same execution times, and generating a final test report;
and detecting a test result curve of each test case in the final test report, screening out test cases which do not meet the standard according to the detection result, and sending the final test report and the test cases which do not meet the standard to a user together.
8. A regression testing apparatus of a chip, comprising:
the initial test grouping dividing module is used for acquiring each test case and dividing the test cases into a plurality of initial test groupings according to standard computing resources of each test case and total computing resources of a test process;
the test case group selection module is used for testing each initial test packet in the test process, acquiring initial test information of each test case in the initial test packet, and dividing the test cases into a plurality of test case groups according to the initial test information;
the current test information acquisition module is used for determining a current test packet in the target test case group according to the current residual computing resources of the test process under the appointed time node, and testing the current test packet in the test process to acquire the current test information of each test case in the current test packet;
and the circulation test module is used for updating each test case group in real time according to the current test information, determining the current test group according to the updated test case group and testing the current test group under the next appointed time node until all the test cases meet the test completion condition, and ending the test process.
9. An electronic device, the electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the regression testing method of the chip of any one of claims 1-7.
10. A computer readable storage medium storing computer instructions for causing a processor to perform the regression testing method of the chip of any one of claims 1-7.
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