CN116701256A - Multi-channel arbiter circuit, interface chip and data access method - Google Patents
Multi-channel arbiter circuit, interface chip and data access method Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The application discloses a multi-channel arbiter circuit, an interface chip and a data access method, wherein the scheme is provided with an error correction code decoding unit, a rereading control unit, a data latching unit and a data decryption unit, wherein the error correction code decoding unit corrects firmware data when a codeword error is within a preset error correction range, the rereading control unit enables the access control unit to output an access request signal to a memory when the codeword error exceeds the preset error correction range, the purpose of re-requesting the firmware data when the codeword error cannot be corrected is achieved, the accuracy of the firmware data is ensured, the response to the access request is simultaneously considered, when a target access request is identical with the access address of a last access request, the data latching unit outputs the firmware data of the last access request, the processing of the current target access request can be finished, the response efficiency is improved, the data decryption unit decrypts the firmware data when an access channel has decryption right, and the original firmware data is output when the access channel has no decryption right, and the safety of data access is improved.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a multi-channel arbiter circuit, an interface chip, and a data access method.
Background
SerDes is an abbreviation for Serializer/Deserializer, i.e., serializer and Deserializer, is a "device" that converts parallel data into serial data for transmission, and received serial data into parallel data. The SerDes interface circuit schedules access requests of processors of a plurality of access channels to access the memory through a special arbiter circuit to realize memory resource sharing.
In the prior art, an arbiter circuit generally performs arbitration processing on access requests of a plurality of access channels through an arbitration algorithm to determine a target access request, read firmware data is directly fed back to the access channel corresponding to the target access request, accuracy of the firmware data acquired by the access channel cannot be guaranteed, and reliability is low.
Disclosure of Invention
In order to solve the above problems, the present application provides a multi-channel arbiter circuit, an interface chip and a data access method.
According to an aspect of an embodiment of the present application, a multi-channel arbiter circuit is disclosed, the multi-channel arbiter circuit comprising an arbitration algorithm unit, an access control unit, an error correction code decoding unit, and a reread control unit, wherein the arbitration algorithm unit is configured to receive access requests of a plurality of access channels to access a memory and perform arbitration processing on the access requests to determine a target access request; the access control unit is connected with the arbitration algorithm unit and is configured to output an access request signal to the memory based on the target access request; the error correction code decoding unit is configured to acquire firmware data corresponding to the access request signal, execute error correction code decoding operation on the firmware data, correct the firmware data and output the firmware data when the codeword error of the firmware data is within a preset error correction range, so that the access channel corresponding to the target access request obtains the corrected firmware data, and output an error feedback signal when the codeword error of the firmware data exceeds the preset error correction range; the read-again control unit is connected with the error correction code decoding unit and the access control unit and is configured to output a data read-again signal to the access control unit based on the error feedback signal, and the access control unit is configured to output the access request signal to the memory based on the data read-again signal.
In an exemplary embodiment, the multi-channel arbiter circuit further comprises a data latch unit connecting the error correction code decoding unit and the access control unit, configured to store firmware data output by the error correction code decoding unit based on a last access request and to store an access address of the last access request; the access control unit is configured to acquire the access address of the target access request, and if the access address of the target access request is the same as the access address of the last access request, output a data calling instruction to the data latch unit, and the data latch unit is configured to output the firmware data output by the error correction code decoding unit based on the last access request based on the data calling instruction, so that an access channel corresponding to the target access request obtains the firmware data.
In an exemplary embodiment, the firmware data is encrypted data, the multi-channel arbiter circuit further includes a data decryption unit, where the data decryption unit is connected to the error correction code decoding unit and the arbitration algorithm unit, and is configured to obtain decryption rights of the multiple access channels from the arbitration algorithm unit, decrypt the firmware data output by the error correction code decoding unit and output the decrypted firmware data when the access channel corresponding to the target access request has the decryption rights, so that the access channel corresponding to the target access request obtains the decrypted firmware data, and output the firmware data output by the error correction code decoding unit when the access channel corresponding to the target access request does not have the decryption rights.
In an exemplary embodiment, the multi-channel arbiter circuit further comprises a data latch unit connecting the data decryption unit and the access control unit, configured to store firmware data output by the data decryption unit based on a last access request and to store an access address of the last access request; the access control unit is configured to acquire the access address of the target access request, and if the access address of the target access request is the same as the access address of the last access request, output a data calling instruction to the data latch unit, and the data latch unit is configured to output the firmware data output by the data decryption unit based on the last access request based on the data calling instruction, so that an access channel corresponding to the target access request obtains the firmware data.
In an exemplary embodiment, the error correction code decoding unit, the reread control unit and the data decryption unit each have a control switch for controlling the corresponding unit to start up or close, and the error correction code decoding unit, the reread control unit and the data decryption unit are configured to close when an access address of the target access request is the same as an access address of the last access request.
In one exemplary embodiment, each of the units has a control switch for controlling the corresponding unit to be activated or deactivated.
According to an aspect of an embodiment of the present application, an interface chip is disclosed, which includes the aforementioned multi-channel arbiter circuit.
According to an aspect of an embodiment of the present application, a data access method is disclosed for the foregoing multi-channel arbiter circuit, and the data access method includes:
an arbitration step, namely receiving access requests of a plurality of access channels for accessing a memory through the arbitration algorithm unit and carrying out arbitration processing on the access requests so as to determine a target access request;
a judging step of acquiring an access address of the target access request through the access control unit, judging whether the access address of the target access request is the same as the access address of the last access request, if so, executing a first processing step, otherwise, executing a second processing step;
a first processing step of outputting a data calling instruction to the data latch unit through the access control unit, and outputting firmware data corresponding to a last access request through the data latch unit so as to enable an access channel corresponding to the target access request to obtain the firmware data;
A second processing step of outputting an access request signal to the memory through the access control unit, acquiring firmware data through the error correction code decoding unit, performing an error correction code decoding operation on the firmware data, and correcting the firmware data when a codeword error of the firmware data is within a preset error correction range, and outputting the corrected firmware data to the data decryption unit, so as to decrypt the firmware data output in response to an access request of an access channel having decryption authority through the data decryption unit; and when the code word error of the firmware data exceeds the preset error correction range, the error correction code decoding unit outputs an error feedback signal to the rereading control unit, and the rereading control unit outputs a data rereading signal to the access control unit so as to output the access request signal to the memory.
In an exemplary embodiment, the error correction code decoding unit, the rereading control unit and the data decryption unit are all provided with control switches, and the control switches are used for controlling corresponding units to start working or close, and when the access address of the target access request is judged to be the same as the access address of the last access request, the error correction code decoding unit, the rereading control unit and the data decryption unit are closed.
In an exemplary embodiment, in the second processing step, the arbitration algorithm unit, the error correction code decoding unit, and the reread control unit process a next target access request before the data decryption unit outputs firmware data.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
the application discloses a multi-channel arbiter circuit, which is provided with an error correction code decoding unit and a rereading control unit, wherein the error correction code decoding unit is used for executing error correction code decoding operation on obtained firmware data, and correcting and outputting the firmware data when the code word error of the firmware data is within a preset error correction range, so that the accuracy of the firmware data obtained by an access channel can be ensured; and the error correction code decoding unit outputs an error feedback signal to the rereading control unit when the code word error of the firmware data exceeds the preset error correction range, and the rereading control unit outputs a data rereading signal to the access control unit, so that the access control unit outputs a corresponding access request signal to the memory again, and the firmware data can be re-requested when the code word error of the firmware data can not be corrected, thereby ensuring the accuracy of the firmware data and simultaneously considering the response to the access request, and the reliability of the multi-channel arbiter circuit is high.
In addition, a data latch unit is arranged, firmware data corresponding to the last access request and the access address of the last access request are stored through the data latch unit, when the access control unit judges that the access address of the target access request is the same as the access address of the last access request, the access control unit outputs a data calling instruction to the data latch unit, so that the data latch unit outputs the firmware data corresponding to the last access request, at the moment, the processing of the current target access request can be finished, the response efficiency of the access request can be improved, and meanwhile, the power consumption of the whole multi-channel arbiter circuit is reduced. In addition, a data decryption unit is arranged, when the access channel has decryption authority, the firmware data is decrypted and then output, and when the access channel does not have decryption authority, the original firmware data is output, so that the security of data access is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 shows a block diagram of a prior art multi-channel arbiter circuit.
Fig. 2 shows a schematic diagram of a SerDes interface interconnect system.
Fig. 3 is a block diagram showing the configuration of a multi-channel arbiter circuit according to a first embodiment of the present application.
Fig. 4 shows a block diagram of a multi-channel arbiter circuit according to a second embodiment of the present application.
Fig. 5 shows a block diagram of a multi-channel arbiter circuit according to a third embodiment of the present application.
Fig. 6 shows a block diagram of a multi-channel arbiter circuit according to a fourth embodiment of the present application.
Fig. 7 shows a flow chart of a data access method for the multi-channel arbiter circuit provided in the first embodiment.
Fig. 8 is a timing diagram illustrating the operation of the multi-channel arbiter circuit according to the first embodiment of the present application.
The reference numerals are explained as follows:
100. a multi-channel arbiter circuit; 101. an arbitration algorithm unit; 102. an access control unit; 103. an error correction code decoding unit; 104. a rereading control unit; 105. a data decryption unit; 106. a data latch unit; 200. a memory.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
As shown in fig. 1, in the related art, an arbiter circuit includes a control unit, a multiplexing unit, and a demultiplexing unit. Wherein the multiplexing unit connects a plurality of access channels (channel 1 to channel 8), which receive access requests input by the plurality of access channels and multiplex them. The control unit is connected between the multiplexing unit and the demultiplexing unit, and is used for carrying out arbitration processing on the access request according to a preset arbitration algorithm to determine a target access request and transmitting the target access request to the memory so as to obtain corresponding firmware data. The demultiplexing unit connects the plurality of access channels (channel 1 to channel 8), and outputs the firmware data to the access channel corresponding to the target access request through the demultiplexing unit.
The arbiter circuit shown in fig. 1 does not combine the comprehensive consideration of the characteristics of the processor, data security, data accuracy, access response efficiency and the like, and cannot ensure the accuracy and data security of the firmware data acquired by the access channel, and the access request response efficiency is low. Therefore, the application provides the multi-channel arbiter circuit, which can ensure the accuracy of the firmware data acquired by the access channel, improve the data security and the response efficiency of the access request, and simultaneously consider the low power consumption of the whole multi-channel arbiter circuit.
First, several terms involved in the present application are explained:
and (3) firmware: firmware is computer processor program data written to the non-volatile memory of a hardware device.
An arbiter: the arbiter uses a certain rule to schedule the data buses or communication buses sent by a plurality of devices, so as to realize the sharing of the memory and the control circuit of the shared buses.
ECC (error correction code): ECC, collectively Error Checking and Correction, is an algorithm for memory data error detection and correction.
SerDes: serDes is an abbreviation for Serializer/Deserializer, i.e., serializer and Deserializer, is a "device" that converts parallel data into serial data for transmission, and received serial data into parallel data.
PPA: i.e., performance, power, area, are indicators of chip efficiency.
The multi-channel arbiter circuit of the application can be applied to a SerDes interface controller IP chip using a plurality of channels, is generally integrated into a soc chip system, and can be independently packaged. The SerDes interface controller comprises a plurality of SerDes transceiver channels, and each channel is realized by independent digital and analog circuits and a miniature customized processor. The program data of the processor is called firmware, which is typically stored in a dedicated memory circuit and may be shared in multiple channels for cost optimization.
Typical SerDes interface interconnect systems as shown in fig. 2, large scale integrated circuit chips (ASICs) between two PCB boards are interconnected by a multi-channel SerDes interface for high speed data transmission, where the transmission medium may be coaxial or other forms of transmission cable. The digital circuit in the SerDes interface performs scheduling of the processor access requests of each channel through a special arbiter circuit to realize resource sharing, and the application is described in detail below by taking an arbiter circuit of 8 channels as an example.
Fig. 3 is a block diagram showing the configuration of a multi-channel arbiter circuit according to a first embodiment of the present application.
Referring to fig. 3, the multi-channel arbiter circuit 100 mainly includes an arbitration algorithm unit 101, an access control unit 102, an error correction code decoding unit 103, a rereading control unit 104, a data decryption unit 105, a data latch unit 106, and the like.
Wherein the arbitration algorithm unit 101 is configured to receive access requests of a plurality of access channels (channel 1 to channel 8) to access the memory 200 and perform arbitration processing on the access requests to determine a target access request.
In detail, the arbitration algorithm unit 101 acquires access channels corresponding to all the currently received access requests, and determines a target access request according to a preset arbitration algorithm.
The arbitration algorithm unit 101 may determine the target access request based on the sequence of the access requests, that is, the first access request is used as the current target access request, and the response is preferentially performed; the arbitration algorithm unit 101 may determine the target access request based on the priority of the access request, that is, the access request of the access channel with the highest priority is used as the current target access request, and the response is performed with priority; the arbitration algorithm unit 101 may determine the target access request based on the random number, specifically, generate random numbers for all the access requests, and respond preferentially by using the access request with the largest random number or the smallest random number as the current target access request. Of course, the arbitration algorithm unit 101 may also determine the target access request based on other arbitration algorithms, which are not listed here.
The arbitration algorithm unit 101 may be connected to a plurality of access channels (channels 1 to 8) through a multiplexing unit (not shown in the figure), and receives, through the multiplexing unit, access requests input by the plurality of access channels, multiplexes the access requests, and transmits the multiplexed access requests to the arbitration algorithm unit 101, and the arbitration algorithm unit 101 performs arbitration processing on the received access requests according to a preset arbitration algorithm, so as to determine a target access request.
The access control unit 102 is connected to the arbitration algorithm unit 101 and the data latch unit 106, and the access control unit 102 is configured to acquire an access address of a target access request and determine whether the access address of the target access request is identical to that of the last access request. If the access address of the target access request is the same as the access address of the last access request, a data fetch instruction is output to the data latch unit 106, so that the data latch unit 106 outputs the firmware data corresponding to the last access request. On the contrary, if the access address of the target access request is different from the access address of the previous access request, an access request signal is output to the memory 200 based on the target access request, so that the error correction code decoding unit 103 can acquire the firmware data corresponding to the access request signal.
Wherein the access request signal is a signal corresponding to the target access request generated after the access control unit 102 processes based on the target access request.
The access address refers to a storage address of firmware data in the memory 200, and different firmware data are stored in different storage addresses for the same memory 200, and when a certain storage address of the memory 200 is accessed, the firmware data stored in the storage address can be obtained.
The memory 200 may include a read control unit and a storage unit, wherein the storage unit is used for storing firmware data, and the read control unit is used for reading the firmware data from a corresponding storage address in the storage unit based on an access request signal input by the access control unit 102, and outputting the read firmware data. That is, in this case, the memory 200 may output the corresponding firmware data to the error correction code decoding unit 103 based on the access request signal.
In the embodiment shown in fig. 3, in cooperation with the reread control unit 104, the access control unit 102 is further configured to re-output an access request signal to the memory 200 based on the data reread signal, thereby re-accessing the memory 200.
The error correction code decoding unit 103 is configured to obtain firmware data corresponding to the access request signal, perform error correction code decoding operation on the obtained firmware data, correct the firmware data when a codeword error of the firmware data is within a preset error correction range, and output the corrected firmware data so that an access channel corresponding to the target access request obtains the corrected firmware data, and output an error feedback signal when the codeword error of the firmware data exceeds the preset error correction range.
The preset error correction range may be, for example, one bit number, two bit numbers, or the like. Illustratively, the preset error correction range is one bit number, and when the error correction code decoding unit 103 detects that the codeword error of the firmware data does not exceed one bit number, the error correction code decoding unit 103 corrects the codeword error in the firmware data and outputs the corrected firmware data; when the error correction code decoding unit 103 detects that the codeword errors of the firmware data exceed one bit number, the error correction code decoding unit 103 cannot correct all codeword errors in the firmware data at this time, so that an error feedback signal is output. Still more illustratively, the preset error correction range is two bit numbers, and when the error correction code decoding unit 103 detects that the codeword error of the firmware data does not exceed two bit numbers, the error correction code decoding unit 103 corrects the codeword error in the firmware data and outputs the corrected firmware data; when the error correction code decoding unit 103 detects that the codeword errors of the firmware data exceed two bit numbers, the error correction code decoding unit 103 cannot correct all codeword errors in the firmware data at this time, so an error feedback signal is output.
When error correction code decoding section 103 detects a codeword error that does not exist in the firmware data, the firmware data is directly output.
It should be noted that the error correction code decoding unit 103 may be implemented by any existing error correction code decoding circuit structure, and detailed description of specific components of the error correction code decoding unit 103 is omitted herein.
The re-read control unit 104 is connected to the error correction code decoding unit 103 and the access control unit 102, the re-read control unit 104 being configured to output a data re-read signal to the access control unit 102 based on the error feedback signal.
Wherein the error feedback signal may be a level signal, for example, a high level signal, and the error correction code decoding unit 103 outputs the high level signal when the codeword error of the firmware data exceeds the preset error correction range; similarly, the data rereading signal may be a level signal, for example, a high level signal, and when the rereading control unit 104 receives the high level signal output from the error correction code decoding unit 103, the high level signal is output to the access control unit 102, so that the access control unit 102 re-outputs the access request signal to the memory 200 based on the high level signal, thereby re-accessing the memory 200.
It should be noted that, the rereading control unit 104 may be implemented by any circuit unit capable of generating an output signal based on an input signal, and specific components of the rereading control unit 104 will not be described in detail herein.
The data decryption unit 105 is connected to the error correction code decoding unit 103 and the arbitration algorithm unit 101, the arbitration algorithm unit 101 is configured with decryption rights of a plurality of access channels, the data decryption unit 105 is configured to obtain the decryption rights of the plurality of access channels from the arbitration algorithm unit 101, and when the access channel corresponding to the target access request has the decryption rights, the firmware data output by the error correction code decoding unit 103 is decrypted and output, so that the access channel corresponding to the target access request obtains the decrypted firmware data. In contrast, when the access channel corresponding to the target access request has no decryption authority, the data decryption unit 105 directly outputs the firmware data output by the error correction code decoding unit 103, in which case the access channel corresponding to the target access request obtains the original firmware data output by the error correction code decoding unit 103.
It should be noted that, the original firmware data output by the error correction code decoding unit 103 is encrypted data, if the access channel is from the processor inside the chip, the access channel may be configured to have decryption authority, and if the access channel is from the interface outside the chip, the access channel may be configured to have no decryption authority, so as to protect the core data.
The data decryption unit 105 may be connected to a plurality of access channels (channel 1 to channel 8) through a demultiplexing unit (not shown in the drawing), and outputs the firmware data to the access channel corresponding to the target access request through the demultiplexing unit so that the access channel corresponding to the target access request can obtain the corresponding firmware data.
It should be noted that the data decryption unit 105 may be implemented by any existing data decryption circuit structure, and detailed description of the specific composition of the data decryption unit 105 is omitted herein.
The data latch unit 106 connects the data decryption unit 105 and the access control unit 102, and the data latch unit 106 is configured to store the firmware data output by the data decryption unit 105 based on the last access request and the access address storing the last access request.
The last access request is the last target access request determined by the arbitration algorithm unit 101, and after the data decryption unit 105 outputs firmware data corresponding to the current target access request, the current target access request becomes the last target access request for the next target access request determined by the arbitration algorithm unit 101.
In one embodiment of the present application, the data latch unit 106 stores only the firmware data output by the last access request and the access address of the last access request, and the data latch unit 106 discards more history data directly.
The data latch unit 106 is further configured to output the firmware data output by the data decryption unit 105 based on the last access request based on the data fetch instruction, so that the access channel corresponding to the target access request obtains the firmware data.
The data latch unit 106 may be connected to a plurality of access channels (channel 1 to channel 8) through a demultiplexing unit (not shown in the drawing), and outputs the firmware data to the access channel corresponding to the target access request through the demultiplexing unit so that the access channel corresponding to the target access request can obtain the corresponding firmware data.
It should be noted that the data latch unit 106 may be implemented by any existing data latch circuit structure, and detailed description of the specific composition of the data latch unit 106 is omitted herein.
In the embodiment shown in fig. 3, the error correction code decoding unit 103 performs error correction code decoding operation on the obtained firmware data, corrects the firmware data and outputs the corrected firmware data when the codeword error of the firmware data is within the preset error correction range, so that the accuracy of the firmware data obtained by the access channel can be ensured when the codeword error occurs due to the influence of the immediate electromagnetic interference of the environment and the like on the firmware data; and, the error correction code decoding unit 103 outputs an error feedback signal to the rereading control unit 104 when the codeword error of the firmware data exceeds the preset error correction range, and the rereading control unit 104 outputs a data rereading signal to the access control unit 102, so that the access control unit 102 outputs a corresponding access request signal to the memory 200 again, and the firmware data can be re-requested when the codeword error of the firmware data cannot be corrected, thereby ensuring the accuracy of the firmware data and simultaneously considering the response to the access request, and the reliability of the multi-channel arbiter circuit 100 is high. The data latch unit 106 stores the firmware data corresponding to the last access request and the access address of the last access request, when the access control unit 102 determines that the access address of the target access request is the same as the access address of the last access request, the access control unit 102 outputs a data calling instruction to the data latch unit 106, so that the data latch unit 106 outputs the firmware data corresponding to the last access request, at this time, the processing of the current target access request can be finished, the response efficiency of the access request can be improved, and meanwhile, the power consumption of the whole multi-channel arbiter circuit 100 is reduced. By setting the data decryption unit 105, when the access channel has decryption authority, the firmware data is decrypted and output, and when the access channel does not have decryption authority, the original firmware data is output, so that the security of data access is improved.
That is, in the present embodiment, through the combination of several digital logic circuit units, in the multi-channel communication interface, the response efficiency and reliability of each access channel access request can be improved while the firmware data memory is shared, and the function of encrypting and decrypting the data is realized, so that a certain security is satisfied, and meanwhile, the advantages of good area and power consumption cost are obtained, so that the present embodiment is suitable for market high-speed interface products such as automobile regulations.
Further, in one embodiment of the present application, the arbitration algorithm unit 101, the access control unit 102, the error correction code decoding unit 103, the rereading control unit 104, the data decryption unit 105, and the data latch unit 106 all have control switches for controlling the corresponding units to start up or close. By this design, a unit may be turned off when it is not required to perform a corresponding function, thereby saving power consumption of the entire multi-channel arbiter circuit 100.
Furthermore, in some embodiments of the present application, some constituent elements may be omitted.
Fig. 4 shows a block diagram of a multi-channel arbiter circuit according to a second embodiment of the present application, unlike the first embodiment of fig. 3, in the embodiment of fig. 4, the multi-channel arbiter circuit 100 does not have a data latch unit 106, but includes an arbitration algorithm unit 101, an access control unit 102, an error correction code decoding unit 103, a re-reading control unit 104, and a data decryption unit 105.
The functions performed by the arbitration algorithm unit 101, the error correction code decoding unit 103, the re-reading control unit 104, and the data decryption unit 105 in the second embodiment are the same as those performed in the first embodiment, and are not described herein.
The access control unit 102 is no longer configured to obtain the access address of the target access request, and determines whether the access address of the target access request is the same as the access address of the previous access request, if the access address of the target access request is the same as the access address of the previous access request, the data retrieving instruction is output to the data latch unit 106, and after the target access request determined by the arbitration algorithm unit 101 is obtained, the corresponding access request signal is directly output to the memory 200 based on the target access request, so that the error correction code decoding unit 103 can obtain the firmware data corresponding to the access request signal.
Fig. 5 shows a block diagram of a multi-channel arbiter circuit according to a third embodiment of the present application, unlike the embodiment of fig. 3, in the embodiment of fig. 5, the multi-channel arbiter circuit 100 is not provided with a data decryption unit 105, but includes an arbitration algorithm unit 101, an access control unit 102, an error correction code decoding unit 103, a re-reading control unit 104, and a data latch unit 106.
The functions performed by the access control unit 102, the error correction code decoding unit 103, the rereading control unit 104 and the data latch unit 106 in the third embodiment are the same as those performed in the first embodiment, and will not be described here again.
The arbitration algorithm unit 101 no longer configures the decryption rights for the multiple channels of access.
Accordingly, the data latch unit 106 stores the original firmware data outputted from the error correction code decoding unit 103, and the data outputted to the request channel is also the original firmware data outputted from the error correction code decoding unit 103. The firmware data in the memory 200 may be encrypted data or unencrypted data.
Fig. 6 shows a block diagram of a multi-channel arbiter circuit according to a fourth embodiment of the present application, unlike the embodiment shown in fig. 3, in the embodiment shown in fig. 6, the multi-channel arbiter circuit 100 is not provided with a data latch unit 106 and a data decryption unit 105, but includes an arbitration algorithm unit 101, an access control unit 102, an error correction code decoding unit 103, and a re-reading control unit 104.
The functions performed by the error correction code decoding unit 103 and the rereading control unit 104 in the fourth embodiment are the same as those performed in the first embodiment, and will not be described here again.
The access control unit 102 is no longer configured to obtain the access address of the target access request, and determines whether the access address of the target access request is the same as the access address of the previous access request, if the access address of the target access request is the same as the access address of the previous access request, the data retrieving instruction is output to the data latch unit, and after the target access request determined by the arbitration algorithm unit 101 is obtained, the corresponding access request signal is directly output to the memory 200 based on the target access request, so that the error correction code decoding unit 103 can obtain the firmware data corresponding to the access request signal.
The arbitration algorithm unit 101 no longer configures the decryption rights for the multiple channels of access.
The data output to the request channel is the original firmware data output from the error correction code decoding unit 103. The firmware data in the memory 200 may be encrypted data or unencrypted data.
Referring next to fig. 7, fig. 7 is a flow chart illustrating a data access method for the multi-channel arbiter circuit provided in accordance with the first embodiment.
As shown in fig. 7, the data access method at least includes steps S710 to S790, and is described in detail as follows:
in step S710, an access request of accessing the memory through a plurality of access channels is received by an arbitration algorithm unit and an arbitration process is performed on the access request to determine a target access request.
In step S710, the state of the access processing channel where the pipeline of the present stage is located is also held by the data latch unit.
In step S720, the access control unit obtains the access address of the target access request, and determines whether the access address of the target access request is the same as the access address of the last access request, if yes, the process proceeds to step S730, otherwise, the process proceeds to step S750.
In step S730, a data fetch instruction is output to the data latch unit through the access control unit, and then, the process proceeds to step S740.
In step S740, the firmware data corresponding to the last access request is output through the data latch unit, so that the access channel corresponding to the target access request obtains the firmware data.
In step S750, an access request signal is output to the memory by the access control unit, and then, the process proceeds to step S760.
In step S760, the firmware data is obtained through the error correction code decoding unit, the error correction code decoding operation is performed on the firmware data, and when the codeword error of the firmware data is within the preset error correction range, the firmware data is corrected and then output to the data decryption unit, and step S770 is performed; when the codeword error of the firmware data exceeds the preset error correction range, the error correction code decoding unit outputs an error feedback signal to the rereading control unit, and proceeds to step S780.
In step S770, the firmware data output in response to the access request of the access channel having the decryption right is decrypted by the data decryption unit so that the access channel corresponding to the target access request obtains the decrypted firmware data, and the process proceeds to step S790.
The data decryption unit directly outputs the firmware data outputted in response to the access request of the access channel without the decryption authority, and the access channel obtains the original firmware data outputted by the error correction code decoding unit.
In step S780, a data rereading signal is output to the access control unit through the rereading control unit to output an access request signal to the memory through the access control unit.
In some embodiments, steps S760 through S780 may be performed in a loop to enable multiple initiation of rereading.
In step S790, the data latch unit stores the firmware data output by the data decryption unit and the access address in the target access request, thereby updating the firmware data and the access address stored by the data latch unit.
And finally, the data latch unit releases the state lock of the current pipeline circuit, exits the arbitration, and executes the next arbitration of the pipeline of the stage.
That is, when it is determined that the access address in the target access request is the same as the access address of the previous access request, the firmware data acquired based on the previous access request is directly used to respond to the access request of the access channel corresponding to the target access request, and the arbitration is exited, so that the response efficiency to the access request can be improved; when the access address in the target access request is not consistent with the access address of the last access request, the access control unit is skipped to carry out the next processing.
In one embodiment of the present application, when it is determined in step S720 that the access address of the target access request is the same as the access address of the last access request, the operations of closing the error correction code decoding unit, the reread control unit, and the data decryption unit are performed, so as to save the power consumption of the entire multi-channel arbiter circuit.
In one embodiment of the present application, the arbitration algorithm unit, the error correction code decoding unit, and the rereading control unit process the next target access request before the data decryption unit outputs the firmware data. Thereby, the response efficiency of the whole multi-channel arbiter circuit to the access request can be improved.
Referring specifically to fig. 8, in fig. 8, "closed" means that the corresponding unit is closed, and when the corresponding unit is not operating, "channel 1", "channel 2", "channel 3", "channel 4", "channel 5", "channel 6", "channel 7", "channel 8" means that the corresponding unit is operating.
As shown in fig. 8, the arbitration algorithm unit, the error correction code decoding unit, and the reread control unit equally process the access request of the channel 2 during the idle time in the period T1 in which the entire multi-channel arbiter circuit processes the access request of the channel 1. In the period T2 of the whole multi-channel arbiter circuit processing the access request of the channel 2, the arbitration algorithm unit processes the access requests of the channels 3, 4 and 5 in idle time, the error correction code decoding unit processes the access requests of the channels 3 and 4 in idle time, and the reread control unit processes the access requests of the channels 3 in idle time. In the period T3 of the whole multi-channel arbiter circuit processing the access request of the channel 3, the arbitration algorithm unit processes the access requests of the channels 4, 5 and 6 in idle time, the error correction code decoding unit processes the access requests of the channels 4 and 5 in idle time, and the reread control unit processes the access requests of the channels 4 in idle time. In the period T4 of the whole multi-channel arbiter circuit processing the access request of the channel 4, the arbitration algorithm unit processes the access requests of the channels 5, 6 and 7 in idle time, the error correction code decoding unit processes the access requests of the channels 5 and 6 in idle time, and the reread control unit processes the access requests of the channels 5 in idle time. In the period T5 of the whole multi-channel arbiter circuit processing the access request of the channel 5, the arbitration algorithm unit processes the access requests of the channels 6, 7 and 8 in idle time, the error correction code decoding unit processes the access requests of the channels 6 and 7 in idle time, and the reread control unit processes the access requests of the channels 6 in idle time. In the period T6 of the whole multi-channel arbiter circuit processing the access request of the channel 6, the arbitration algorithm unit processes the access requests of the channels 7, 8 and 1 in idle time, the error correction code decoding unit processes the access requests of the channels 7 and 8 in idle time, and the reread control unit processes the access requests of the channels 7 in idle time. And so on.
When the fetch instruction period of each access channel is larger than the total delay clock beat number of the multi-channel arbiter circuit, the shared firmware data can meet the fetch efficiency requirement of the processor in each access channel, the data security and the system efficiency of the SerDes interface interconnection system are ensured, the firmware execution processor of the main stream communication interface IP in the market at present is generally a non-pipelined multi-period MCU, such as an 8051 singlechip with the instruction period of 12 later clocks (12T) or other MCU smaller than 12T, and the method can be well applied to the application. The processors of each access channel match the response throughput rate of the multi-channel arbiter circuit with the minimum clock, the next access request just arrives after the multi-channel arbiter circuit processes the last access request of the access channel, when the multi-channel arbiter circuit is applied to a SerDes interface chip, a plurality of access channels can safely and efficiently share firmware data, and simultaneously each unit can be precisely subjected to clock gating (closing) according to whether the multi-channel arbiter circuit is enabled or not so as to reduce the power consumption of the whole multi-channel arbiter circuit, and good PPA benefits are obtained.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (10)
1. A multi-channel arbiter circuit comprising:
an arbitration algorithm unit configured to receive access requests of a plurality of access channels to access a memory and perform arbitration processing on the access requests to determine a target access request;
an access control unit, coupled to the arbitration algorithm unit, configured to output an access request signal to the memory based on the target access request;
an error correction code decoding unit configured to obtain firmware data corresponding to the access request signal, perform error correction code decoding operation on the firmware data, correct the firmware data and output the firmware data when a codeword error of the firmware data is within a preset error correction range, so that an access channel corresponding to the target access request obtains the corrected firmware data, and output an error feedback signal when the codeword error of the firmware data exceeds the preset error correction range;
and a rereading control unit connected to the error correction code decoding unit and the access control unit and configured to output a data rereading signal to the access control unit based on the error feedback signal, the access control unit being configured to output the access request signal to the memory based on the data rereading signal.
2. The multi-channel arbiter circuit of claim 1, further comprising:
a data latch unit connecting the error correction code decoding unit and the access control unit, configured to store firmware data output by the error correction code decoding unit based on a last access request and store an access address of the last access request;
the access control unit is configured to acquire the access address of the target access request, and if the access address of the target access request is the same as the access address of the last access request, output a data calling instruction to the data latch unit, and the data latch unit is configured to output the firmware data output by the error correction code decoding unit based on the last access request based on the data calling instruction, so that an access channel corresponding to the target access request obtains the firmware data.
3. The multi-channel arbiter circuit of claim 1, wherein the firmware data is encrypted data, the multi-channel arbiter circuit further comprising:
and the data decryption unit is connected with the error correction code decoding unit and the arbitration algorithm unit and is configured to acquire decryption authorities of the plurality of access channels from the arbitration algorithm unit, decrypt the firmware data output by the error correction code decoding unit and output the decrypted firmware data when the access channel corresponding to the target access request has the decryption authorities, so that the access channel corresponding to the target access request obtains the decrypted firmware data, and output the firmware data output by the error correction code decoding unit when the access channel corresponding to the target access request has no decryption authorities.
4. A multi-channel arbiter circuit according to claim 3, further comprising:
a data latch unit connecting the data decryption unit and the access control unit, configured to store firmware data output by the data decryption unit based on a last access request and store an access address of the last access request;
the access control unit is configured to acquire the access address of the target access request, and if the access address of the target access request is the same as the access address of the last access request, output a data calling instruction to the data latch unit, and the data latch unit is configured to output the firmware data output by the data decryption unit based on the last access request based on the data calling instruction, so that an access channel corresponding to the target access request obtains the firmware data.
5. The multi-channel arbiter circuit of claim 4, wherein,
the error correction code decoding unit, the rereading control unit and the data decryption unit are provided with control switches, the control switches are used for controlling the corresponding units to start working or close, and the error correction code decoding unit, the rereading control unit and the data decryption unit are configured to close when the access address of the target access request is the same as the access address of the last access request.
6. The multi-channel arbiter circuit of any one of claims 1 to 4, wherein each of the cells has a control switch for controlling the corresponding cell to be activated or deactivated.
7. An interface chip, comprising:
a multi-channel arbiter circuit according to any one of claims 1 to 6.
8. A data access method for the multi-channel arbiter circuit of claim 4, comprising:
an arbitration step, namely receiving access requests of a plurality of access channels for accessing a memory through the arbitration algorithm unit and carrying out arbitration processing on the access requests so as to determine a target access request;
a judging step of acquiring an access address of the target access request through the access control unit, judging whether the access address of the target access request is the same as the access address of the last access request, if so, executing a first processing step, otherwise, executing a second processing step;
a first processing step of outputting a data calling instruction to the data latch unit through the access control unit, and outputting firmware data corresponding to a last access request through the data latch unit so as to enable an access channel corresponding to the target access request to obtain the firmware data;
A second processing step of outputting an access request signal to the memory through the access control unit, acquiring firmware data through the error correction code decoding unit, performing an error correction code decoding operation on the firmware data, and correcting the firmware data when a codeword error of the firmware data is within a preset error correction range, and outputting the corrected firmware data to the data decryption unit, so as to decrypt the firmware data output in response to an access request of an access channel having decryption authority through the data decryption unit; and when the code word error of the firmware data exceeds the preset error correction range, the error correction code decoding unit outputs an error feedback signal to the rereading control unit, and the rereading control unit outputs a data rereading signal to the access control unit so as to output the access request signal to the memory.
9. The method according to claim 8, wherein the error correction code decoding unit, the rereading control unit, and the data decryption unit each have a control switch for controlling the corresponding unit to start up or close, and closing the error correction code decoding unit, the rereading control unit, and the data decryption unit when it is determined that the access address of the target access request is the same as the access address of the last access request.
10. The data access method according to claim 8, wherein in the second processing step, the arbitration algorithm unit, the error correction code decoding unit, the reread control unit process a next target access request before the data decryption unit outputs firmware data.
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