CN116700799A - Soft error tolerant design method for realizing instruction level redundancy by utilizing pipeline bubbles - Google Patents

Abstract

The invention discloses a soft error tolerant design method for realizing instruction level redundancy by utilizing pipeline bubbles. Comprising the following steps: adding an instruction scheduling module and an inspection buffer module in a processor kernel; when the processor runs, the instruction scheduling module marks the instruction as first execution or redundant execution, and the instruction is fed into the pipeline twice. The first execution result is stored in the checking buffer and is not written back; and comparing the redundant execution result with the first execution result in the check buffer, and if the redundant execution result is the same with the first execution result in the check buffer, writing the correct result back and moving out of the check buffer. If the three results are different, the instruction scheduling module sends the instruction into the pipeline for error correction execution for the third time, and the correct result is selected through majority voting of the three results and written back; when the check buffer is empty, the processor executes the following instructions for the first time and continuously loops the operation. The invention can greatly improve the soft error tolerance of the processor with extremely small hardware resource expenditure, and effectively reduce the performance expenditure of instruction level redundancy.

Description

Soft error tolerant design method for realizing instruction level redundancy by utilizing pipeline bubbles

Technical Field

The invention relates to the technical field of reliability design of processors, in particular to a soft error tolerant strategy and design method for realizing instruction level redundancy by utilizing pipeline bubbles.

Background

With the continued shrinking of semiconductor device dimensions and the continued development of near threshold calculations, soft errors have become a critical issue to consider in designing and manufacturing processors. Soft errors are typically caused by energetic particles (such as cosmic rays) and alpha particles from the encapsulating material, which are transient in nature, do not permanently damage the circuit, nor recur after disappearance. Soft errors may cause program execution failure within the processor or produce undetectable erroneous results, which is unacceptable for a processor chip with high reliability requirements, and therefore efficient reliability design is an important element of the processor design.

Adding processor system redundancy is a common reliability design strategy, and instruction level redundancy is an efficient system redundancy scheme. The instruction level redundancy performs fine-granularity contrast detection by copying the execution of the instruction, so that near zero-delay soft error detection can be realized. The existing instruction level redundancy implementation scheme is mostly implemented by performing instruction copying and inserting check instructions through a compiler, or by running the same program on a multi-core processor and a synchronous multi-thread processor by using different hardware threads and comparing instruction results through a hardware module. The compiler-assisted approach does not require hardware level modification, reducing design costs, but program performance will be greatly reduced since all instructions are executed in the same pipeline. Redundant thread schemes utilize thread-level parallelism, which results in less program performance overhead, but are only suitable for use in processors supporting multiple threads, which may incur significant unnecessary hardware resources or area overhead.

Disclosure of Invention

Technical problems: the invention aims to provide a soft error tolerant strategy and design method for realizing instruction level redundancy by utilizing pipeline bubbles, which are used for solving the problems of high performance cost, hardware discomfort and large resource area cost of the existing instruction level redundancy scheme. The invention is oriented to a wide processor architecture, is not limited to a single instruction set architecture, and is a software transparent and kernel architecture level soft error tolerant design completely realized by a hardware mechanism. By adding scheduling, detecting and error correcting mechanisms in the kernel, the instruction level redundancy and soft error recovery in a single pipeline are realized. The design scheme is wider in applicability, smaller in hardware resource and performance cost and more balanced for the reliability design of the processor.

The technical scheme is as follows: in order to solve the technical problems, the invention provides the following technical scheme:

a soft error tolerant design method for realizing instruction level redundancy by utilizing pipeline bubbles ensures that each instruction is executed twice in the same pipeline through a scheduling mechanism of hardware, thereby changing the original instruction execution flow. Because the first execution and the redundant execution are complete program instruction streams and no real dependency exists, the switching of the two execution streams eliminates the original pipeline bubbles to a great extent. The results of the two executions are compared in the core to detect if a soft error has occurred. When a soft error is detected, the scheduling mechanism can empty the pipeline and execute the erroneous instruction a third time and select the correct result by majority voting. The method comprises the following steps:

step S1, adding an instruction scheduling module and an inspection buffer module into a processor core framework needing reinforcement.

Step S2, the processor kernel executes the instruction for the first time, and the method specifically comprises the following steps:

in step S201, the instruction scheduling module is initially in a first execution state, and adds a first execution flag for each instruction entering the pipeline.

In step S202, the instruction with the first execution flag is normally executed in the pipeline, but the result is not written back but stored in the check buffer.

Step S203, repeating step S2 until step S3 occurs.

And step S3, decoding the bubble-induced instruction or filling the checking buffer module when the processor executes the instruction for the first time, and starting redundant execution of the instruction by the kernel, wherein the first instruction in the redundant execution is the earliest instruction stored in the checking buffer.

Step S4, the processor kernel performs redundant execution on the instruction, and specifically comprises the following steps:

in step S401, the instruction scheduling module switches to a redundant execution state, and adds a redundant execution flag to each instruction entering the pipeline.

In step S402, the instruction with the redundant execution flag is normally executed in the pipeline, and the result needs to be compared with the first execution result stored in the check buffer before writing back.

Step S403, if there is no difference, the information stored in the checking buffer of the instruction is cleared, and the instruction result is written back. Repeating the step S4, and when the comparison shows a difference, entering the step S5; when the check buffer is empty, go to step S7;

and S5, if the difference exists, namely, when the error is detected, other instruction information stored in the checking buffer is cleared, and only the twice execution results of the error instruction are reserved. The subsequent instructions on the pipeline are also cleared, the instruction scheduling module starts error correction, re-fetches the instruction to the memory address of the error instruction, and performs the third execution.

And S6, performing majority voting on the results of the three execution by the checking and buffering module, and selecting a correct result. The result stored in the check buffer by the erroneous instruction is cleared and the correct result is written back.

And S7, when the redundant execution reaches the condition that the check buffer is empty, the instruction scheduling module switches back to the first execution state and returns to the step S2 until all the instructions complete the steps.

Further, the soft error tolerant strategy may be applied to a wide range of processor core architecture designs, not limited to a specific instruction set architecture or pipeline architecture.

Further, the pipeline bubble is caused by the dependence of instructions in the pipeline on data, structure and control, which can be avoided by increasing the distance between related instructions. Since the first instruction stream and the redundant instruction stream are complete original program instruction streams, the first instruction stream and the redundant instruction stream are independent and uncorrelated. By inserting another instruction stream between two related instructions of the same instruction stream, the distance between related instructions can be effectively increased, thereby eliminating the original bubbles.

Furthermore, the instruction scheduling module is mainly responsible for scheduling control of the execution instruction stream of the kernel, and needs to realize bubble-free execution stream switching, that is, the first execution instruction and the last redundant execution instruction are consecutive in the pipeline, so that a switching mechanism can be ensured not to introduce new bubbles. The instruction dispatch module may be a stand-alone hardware module or control logic combined with other modules.

Furthermore, the checking buffer module is mainly responsible for storing, checking and correcting the information of the first execution instruction. The checking buffer module can store instruction information including instruction type and execution result through FIFO, RAM and other storage structures. The size of the internal storage structure needs to be defined according to various factors such as bubble frequency, bubble size, resource overhead and the like. Likewise, the check buffer module may be a separate hardware module or control logic combined with other modules.

Further, the bubble-inducing instruction refers to an instruction which is easy to form correlation with a subsequent instruction and causes pipeline bubble in the instruction set architecture of the processor. In general, bubble-inducing instructions may include control-class instructions and memory access instructions, but are not limited thereto, as the particular need depends on the actual instruction set architecture or processor architecture.

Further, the instruction stream switching strategy may result in some false dependencies between instructions of different streams, which may be avoided by modifying or adding instruction dependency control logic in the original core pipeline.

Further, the first execution flow saves the instruction result in the check buffer module, which results in that the latest value of the execution flow is not updated to the register, but is saved in the check buffer module. The original core control logic is modified or added so that subsequent instructions can be swapped for the latest value from the check buffer module.

The beneficial effects are that: the invention has the advantages that:

1. the invention is applicable to a wide range of processor architectures, is not limited to a single instruction set architecture, can be realized in a single core, even is expanded to a multi-core architecture, and has high applicability. As described in step S1, the solution can be implemented by adding two modules to a single core, and is not limited to a specific hardware or instruction set architecture.

2. The invention can realize the detection and recovery of soft errors, does not need the support of a software layer, and reduces the development difficulty of the processor software. As can be seen from the technical solution, all the steps do not involve modification of the software level, and the processor cured by the method can directly run the unmodified program and provide soft error tolerance.

3. The invention realizes the resource cost of soft error tolerant design by multi-core or hardware multi-thread mechanism in far lower than the traditional fault tolerant design, and realizes the detection and recovery of soft error. As described in step S1, the scheme can be implemented by adding two modules in a single core, and the resource overhead caused by the multi-core or multi-thread mechanism is far less than that caused by the multi-core or multi-thread mechanism.

4. The invention utilizes inherent pipeline bubbles in the running process of the processor, and greatly reduces the performance cost of instruction level redundancy. After decoding the bubble-inducing instruction, if the pipeline sequentially executes the subsequent instructions, the pipeline bubbles are generated as shown in step S3. By switching to redundant execution in time, the correlation between the subsequent instruction and the bubble-induced instruction is eliminated, and the original bubbles are avoided, so that the performance cost is reduced.

Drawings

FIG. 1 is a flow chart of a soft error tolerant design method for implementing instruction level redundancy using pipeline bubbles.

FIG. 2 is a schematic diagram of a processor execution instruction flow for implementing a soft error tolerant design approach to instruction level redundancy using pipeline bubbles.

FIG. 3 is a schematic diagram of a processor execution flow switching timing of a soft error tolerant design approach to implementing instruction level redundancy using pipeline bubbles.

FIG. 4 is a schematic diagram of a core architecture according to an embodiment of a soft error tolerant design approach for implementing instruction level redundancy using pipeline bubbles.

FIG. 5 is a schematic diagram of an instruction scheduling module according to an embodiment of a soft error tolerant design method for implementing instruction level redundancy using pipeline bubbles.

FIG. 6 is a schematic diagram of a checking buffer module according to an embodiment of a soft error tolerant design method for implementing instruction level redundancy using pipeline bubbles.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

Referring to fig. 1-6, the present embodiment provides a soft error tolerant design method for implementing instruction level redundancy by using pipeline bubbles, which specifically includes the following steps:

and step A, adding an instruction scheduling module and an inspection buffer module into a processor core framework needing reinforcement.

In particular, the soft error tolerant design described in this patent is applicable to a wide range of processor core architecture designs, and is not limited to a particular instruction set architecture or pipeline architecture. In this embodiment, the processor core to be reinforced is selected from an open source RI5CY core based on RISC-V instruction set, which is a sequential single-issue processor core with four stages of pipelines, and the four stages of pipelines are respectively instruction fetch IF, ID decode, EX execute, WB write back, and the structure can be seen in fig. 4.

And B, when the processor runs the application program, the first execution of the instruction by the kernel specifically comprises the following steps:

and B1, the instruction scheduling module is in a first execution state initially, and a first execution mark is added for each instruction entering the pipeline.

Specifically, the execution flag is a 1bit signal, the signal represents first execution in the 0 th time, and the signal represents redundant execution in the 1 st time. The execution flags are passed along the pipeline, and each stage of pipeline can know the execution state of the current instruction.

Step B2, the instruction with the first execution flag is normally executed in the pipeline, but the result is not written back but is saved in the check buffer.

Specifically, when the instruction with the first execution flag enters the WB stage, the WB stage determines that the current instruction is executed for the first time, the result of the instruction is not written back to the register, but is stored in the check buffer.

And step B3, continuously repeating the step B until the step C occurs.

And step C, decoding the bubble-induced instruction or filling the checking buffer module when the processor executes the instruction for the first time, and starting redundant execution of the instruction by the kernel, wherein the first instruction in the redundant execution is the earliest instruction stored in the checking buffer.

Specifically, the fault tolerance policy switches the first execution to redundant execution in both cases. The first is ID stage decoding to bubble inducing instruction; the second is that the FIFO in the check buffer cannot hold new first-time instructions. In both cases, the instruction dispatch module feeds the redundantly executed instructions into the ID phase.

And D, when the processor runs the application program, the redundant execution of the instruction by the kernel specifically comprises the following steps:

and D1, switching the instruction scheduling module into a redundant execution state, and adding a redundant execution mark for each instruction entering the pipeline.

Step D2, the instruction with the redundant execution mark is normally executed in the pipeline, and the result is required to be compared with the first execution result stored in the check buffer before writing back.

And D3, if no difference exists, clearing the result stored in the checking buffer by the instruction, and writing back the instruction result. Repeating the step D, and entering the step E when the comparison shows a difference; when the check buffer is empty, entering a step G;

and E, if the difference exists, namely, when the error is detected, clearing other instruction information stored in the checking buffer, and only reserving the twice execution results of the error instruction. Subsequent instructions on the pipeline are also cleared, the instruction scheduling module starts error correction, re-fetching the instruction to the memory address of the error instruction, and executing for the third time.

And F, checking the majority voting of the buffer module to the results of the three execution, and selecting a correct result. The result stored in the check buffer by the erroneous instruction is cleared and the correct result is written back.

And G, when the redundant execution reaches the condition that the check buffer is empty, the instruction scheduling module switches back to the first execution state and returns to the step B until all instructions complete the steps.

In particular, in this embodiment, pipeline bubbles are caused by the dependency of instructions in the pipeline on data, structure, control, which can be avoided by increasing the distance between dependent instructions. Since the first instruction stream and the redundant instruction stream are complete original program instruction streams, as shown in fig. 2, they are independent. By inserting another instruction stream between two related instructions of the same instruction stream, the distance between related instructions can be effectively increased, thereby eliminating the original bubbles, as shown in fig. 3.

Specifically, in this embodiment, by analyzing trace of the RI5CY kernel running test program, it is known that pipeline bubbles are commonly present after the control instruction and the memory access instruction, so these two types of instructions are defined as bubble-induced instructions.

Specifically, in this embodiment, the instruction scheduling module is mainly responsible for scheduling control of the execution instruction stream of the kernel, and needs to implement bubble-free switching of the execution stream, that is, the first execution instruction and the last redundant execution instruction are consecutive in the pipeline. For this purpose, as shown in fig. 5, an instruction dispatch module internally implements an instruction fetch FIFO that can hold the first executed instruction that is fed into the pipeline. When the state switching is executed, the instruction stored in the instruction fetch FIFO can be directly sent to the ID stage, so that bubbles caused by fetching the instruction again are avoided.

More specifically, in this embodiment, the distance between more than 90% of pipeline bubbles is less than 8 instructions during the running of the test program by the RI5CY core. The consideration of hardware resources and bubble distance is integrated, the instruction fetch FIFO is set to 8 entries, and a maximum of eight instructions can be saved.

Specifically, in this embodiment, the checking buffer module is mainly responsible for storing, checking and correcting the first execution instruction result. The checking buffer module realizes a FIFO structure to store instruction results, and the instruction information includes instruction type and execution result, as shown in fig. 6. This FIFO structure has 8 entries as the instruction fetch FIFOs, and can ensure that the first instruction execution information in all the instruction fetch FIFOs is stored in the check buffer FIFO.

Specifically, in this embodiment, the instruction stream switching strategy may cause some spurious dependencies between the instructions of the primary and redundant streams, as shown in fig. 4, the ID phase of the original core is modified to eliminate such spurious dependencies.

Specifically, in this embodiment, the first execution flow saves the instruction results in the check buffer module, which results in the latest value of the execution flow not being updated to the register. As shown in fig. 4, the addition of the check buffer index table to the core architecture achieves an index to the check buffer FIFO save results.

Specifically, in this embodiment, the step E specifically includes the following steps:

after the error is detected in step E1, an error flag signal is generated in the core, as shown in fig. 6.

And E2, after the error mark is detected by the checking buffer module, clearing the follow-up instruction result stored in the checking buffer module, and storing two different results of the error instruction.

And E3, after the pipeline detects the error mark, clearing instructions in each stage of pipeline, and waiting for error correction execution.

And E4, after the instruction scheduling module detects the error mark, fetching the instruction to the memory address of the error instruction, and preparing for error correction execution.

In summary, the soft error tolerant design method for implementing instruction level redundancy by using pipeline bubbles according to the embodiment has the following benefits compared with the prior art:

1. the scheme is applicable to a wide range of processor architectures, is not limited to a single instruction set architecture, can be realized in a single kernel, even is expanded to a multi-core architecture, and has high applicability.

2. The scheme can realize the detection and recovery of soft errors, does not need the support of a software layer, and reduces the development difficulty of the processor software.

3. The scheme is far lower than the resource overhead of the traditional hardware redundancy design scheme, and realizes the detection and recovery of soft errors.

4. The scheme utilizes inherent pipeline bubbles in the running process of the processor, and greatly reduces the performance overhead of instruction level redundancy.

The present invention is not described in detail in the present application, and is well known to those skilled in the art.

The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention by one of ordinary skill in the art without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims (7)

1. A soft error tolerant design method for implementing instruction level redundancy using pipeline bubbles, the method comprising the steps of:

s1, adding an instruction scheduling module and an inspection buffer module into a processor kernel architecture to be reinforced;

step S2, the processor kernel executes the instruction stream of the program for the first time, and the method specifically comprises the following steps:

step S201, an instruction scheduling module is initially in a first execution state, and a first execution mark is added for each instruction entering a pipeline;

step S202, the instruction with the first execution mark is normally executed in the pipeline, but the result is not written back but stored in the check buffer module;

step S203, repeating step S2 until step S3 occurs;

step S3, when the processor kernel decodes the bubble-induced instruction or the checking buffer module is filled at the moment in the first execution process of the instruction, the instruction scheduling module switches the kernel to the redundant execution of the instruction, and the first instruction of the redundant execution is the earliest instruction stored in the checking buffer;

step S4, redundant execution of instructions by the kernel specifically comprises the following steps:

step S401, switching the instruction scheduling module into a redundant execution state, and adding a redundant execution mark for each instruction entering the pipeline;

step S402, an instruction with a redundant execution mark is normally executed in a pipeline, and the result is required to be compared with a first execution result stored in a check buffer before being written back;

step S403, if there is no difference, clearing the information stored in the checking buffer of the instruction, and writing back the instruction result; repeating the step S4, and when the comparison shows a difference, entering the step S5; when the check buffer is empty, go to step S7;

s5, if the difference exists, namely when an error is detected, other instruction information stored in the checking buffer is cleared, and only the twice execution results of the error instruction are reserved; the subsequent instructions on the pipeline are also cleared, the instruction scheduling module starts error correction, and re-fetching is performed from the memory address of the error instruction for executing the third time;

s6, the checking buffer module performs majority voting on the results of the three execution, and correct results are selected; clearing the result stored in the checking buffer by the error instruction, and writing back the correct result;

and S7, when the redundant execution reaches the condition that the check buffer is empty, the instruction scheduling module switches back to the first execution state and returns to the step S2 until all the instructions complete the steps.

2. The method for soft error tolerant design utilizing pipeline bubbles to realize instruction level redundancy according to claim 1, wherein the pipeline bubbles are caused by the dependence of instructions in a pipeline on data, structure and control, and are avoided by increasing the distance between related instructions; since the first instruction stream and the redundant instruction stream are complete original program instruction streams, the first instruction stream and the redundant instruction stream are independent and uncorrelated; the distance between related instructions is increased by inserting another instruction stream between two related instructions of the same instruction stream, so that the original bubbles are eliminated.

3. The soft error tolerant design method for implementing instruction level redundancy by utilizing pipeline bubbles according to claim 1, wherein the instruction scheduling module is responsible for scheduling control of an instruction stream of kernel execution, and bubble-free execution stream switching is required to be implemented, namely a previous first execution instruction and a subsequent redundant execution instruction are consecutive in the pipeline; the instruction dispatch module is a stand-alone hardware module or control logic combined with other modules.

4. The soft error tolerant design method for implementing instruction level redundancy using pipeline bubbles according to claim 1, wherein the check buffer module is responsible for storing, checking and correcting information of the first execution instruction; the checking buffer module stores instruction information including instruction type and execution result through FIFO and RAM storage structure; the size of the internal storage structure is required to be defined according to various factors of bubble frequency, bubble size and resource overhead; the check buffer module is a separate hardware module or control logic combined with other modules.

5. The method of claim 1, wherein the bubble-induced instruction refers to an instruction that is present in the processor architecture that is subject to forming a dependency with a subsequent instruction and that causes a pipeline bubble; the bubble inducing instructions include control class instructions and memory access instructions.

6. The method of claim 1, wherein the instruction stream switching causes false dependencies between different streams of instructions to be avoided by modifying or adding instruction dependency control logic in the original core pipeline.

7. The method of claim 1, wherein the first execution flow saves instruction results in a check buffer module, which results in the latest value of the execution flow not being updated to the register; the latest value is read from the check buffer module by modifying or adding the original core control logic.