CN116699296B - Load detection circuit and electronic device - Google Patents
Load detection circuit and electronic device Download PDFInfo
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- CN116699296B CN116699296B CN202310989197.5A CN202310989197A CN116699296B CN 116699296 B CN116699296 B CN 116699296B CN 202310989197 A CN202310989197 A CN 202310989197A CN 116699296 B CN116699296 B CN 116699296B
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- 238000001514 detection method Methods 0.000 title claims abstract description 83
- 230000003068 static effect Effects 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 8
- 230000035945 sensitivity Effects 0.000 description 4
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000007306 turnover Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
Abstract
The invention discloses a load detection circuit and an electronic device, wherein the load detection circuit comprises: the load interface is used for connecting a load; the digital controllable current steering circuit is used for outputting a controllable current with a first preset size to the load interface at the initial stage of the load interface being connected with the load so as to provide charging current for the connected load; the load power supply demand identification control circuit is used for detecting the voltage of the load interface so as to determine the power supply demand of an accessed load, and controlling the digital controllable current rudder circuit to output controllable current matched with the load to the load interface according to the power supply demand so as to provide detection current for the accessed load. The present invention aims to improve the accuracy of load detection.
Description
Technical Field
The present invention relates to the field of load detection, and in particular, to a load detection circuit and an electronic device.
Background
The load detection circuit is used for detecting and measuring a load under the condition of micro-power consumption level and outputting an electric signal of the load, and is mainly used in the fields of power management, portable equipment, the Internet of things and the like. The current load detection circuit has low sensitivity to load detection, and some small loads cannot be detected, so that the load detection circuit is difficult to apply in some scenes with high precision requirements.
Disclosure of Invention
The invention mainly aims to provide a load detection circuit and electronic equipment, and aims to improve the sensitivity of load detection.
In order to achieve the above object, the present invention provides a load detection circuit comprising:
the load interface is used for connecting a load;
the digital controllable current steering circuit is used for outputting a first controllable current with a preset size to the load interface at the initial stage of the load interface being connected with the load so as to provide charging current for the connected load;
the load power supply demand identification control circuit is used for detecting the voltage of the load interface so as to determine the power supply demand of an accessed load, and controlling the digital controllable current rudder circuit to output controllable current matched with the load to the load interface according to the power supply demand so as to provide detection current for the accessed load.
Optionally, the output end of the load power supply demand identification control circuit is used for being connected with a control chip, the load power supply demand identification control circuit is used for outputting an access signal to the control chip when detecting that a load is accessed according to the voltage value of the load interface, and the load power supply demand identification control circuit is also used for outputting a sleep signal to the control chip when detecting that the load is not accessed according to the voltage value of the load interface.
Optionally, the load power supply demand identification control circuit includes:
the load power supply demand identification circuit is used for detecting the voltage of the load interface so as to determine the power supply demand of an accessed load and outputting a power supply demand signal;
the load power supply control circuit is used for controlling the digital controllable current rudder circuit to output controllable current matched with the load to the load interface according to the power supply demand signal so as to provide detection current for the accessed load.
Optionally, the load power supply demand identification circuit includes a PMOS tube, a comparator, an and gate, a level shifter and a plurality of inverter circuits, the grid of the PMOS tube is used for accessing the power voltage, the source of the PMOS tube is the input of the load power supply demand identification circuit, the drain of the PMOS tube with the load interface connection, the forward input of the comparator is used for accessing external power supply, the reverse input of the comparator with the load interface connection, the first input of the and gate with the output of the comparator is connected, and be used for connecting the control chip, the second input of the and gate with a plurality of output after the inverter circuit series connection are connected, the output of the and gate with the input of level shifter is connected, the output of level shifter is used for connecting the control chip, a plurality of the controlled end after the inverter circuit series connection with the output of digital controllable current circuit, a plurality of input after the inverter circuit series connection is used for accessing external power supply.
Optionally, each of the inverting circuits includes a first NMOS transistor and a second PMOS transistor, where a gate of the first NMOS transistor is interconnected with a gate of the second PMOS transistor and is a controlled end of the inverting circuit, a source of the second PMOS transistor is an input end of the inverting circuit, a drain of the second PMOS transistor is interconnected with a drain of the first NMOS transistor and is an output end of the inverting circuit, and a source of the first NMOS transistor is grounded.
Optionally, the load power supply control circuit includes a second NMOS transistor, a gate of the second NMOS transistor is a controlled end of the load power supply control circuit, a drain of the second NMOS transistor is an input end of the load power supply control circuit, and a source of the second NMOS transistor is an output end of the load power supply control circuit.
Optionally, the number of the load power supply demand identification control circuit and the number of the digital controllable current steering circuits are multiple, the power input end of each load power supply demand identification control circuit is used for being connected with a first power supply voltage, the power input end of each digital controllable current steering circuit is used for being connected with a second power supply voltage, the output ends of the digital controllable current steering circuits are connected with the input ends of the load power supply demand identification control circuits in a one-to-one correspondence manner, the load power supply demand identification control circuits are connected in parallel, and the digital controllable current steering circuits are connected in parallel.
Optionally, the load detection circuit further includes:
the input end of the bias circuit is used for being connected with an external power supply, the output end of the bias circuit is connected with the power supply input end of the digital controllable current steering circuit and the power supply input end of the load power supply demand identification control circuit, the bias circuit is also used for converting the external power supply and outputting a first power supply voltage and a second power supply voltage to the load power supply demand identification control circuit, and the bias circuit is used for converting the external power supply and outputting a third power supply voltage to the digital controllable current steering circuit.
Optionally, the load detection circuit further includes:
the logic circuit is used for accessing an external control signal and outputting a corresponding logic signal according to the external control signal;
the power supply selection circuit is provided with a plurality of power supply input ends, each power supply input end is used for being connected with an external power supply, the output end of the power supply selection circuit is connected with the input end of the bias circuit, the controlled end of the power supply selection circuit is connected with the output end of the logic circuit, and the power supply selection circuit is used for receiving and selecting the corresponding external power supply to be output to the bias circuit according to the logic signals.
The invention also provides electronic equipment which comprises a control chip and the load detection circuit.
The technical scheme of the invention comprises a load detection circuit formed by a load interface, a digital controllable current rudder circuit and a load power supply demand identification control circuit, wherein the load interface is used for connecting a load; the input end of the digital controllable current steering circuit can be connected with a power supply voltage, and the digital controllable current steering circuit can output controllable current with a first preset size to the load interface at the initial stage of connecting the load interface with a load so as to provide charging current for the connected load; the input end of the load power supply demand identification control circuit is connected with the output end of the digital controllable current steering circuit, the detection end of the load power supply demand identification control circuit is connected with the load interface, the load power supply demand identification control circuit can detect the voltage of the load interface to determine the power supply demand of the accessed load, and the digital controllable current steering circuit is controlled to output controllable current matched with the load to the load interface according to the power supply demand so as to provide detection current for the accessed load. The present invention aims to improve the accuracy of load detection.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a load detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a functional block diagram of another embodiment of a load detection circuit according to the present invention;
FIG. 3 is a schematic circuit diagram illustrating an embodiment of a load power demand identification control circuit in a load detection circuit according to the present invention;
FIG. 4 is a schematic circuit diagram of an embodiment of a digitally controllable current steering circuit in a load detection circuit according to the present invention;
FIG. 5 is a schematic circuit diagram of an embodiment of a bias circuit in a load detection circuit according to the present invention;
FIG. 6 is a schematic diagram of a logic circuit and a power selection circuit in a load detection circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a functional module of a load detection circuit according to another embodiment of the invention.
Reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The invention provides a load detection circuit. The load detection circuit is generally applied to an electronic device having a control chip. The wireless earphone is different in the situation when being put into the charging box and taken out of the charging box, the charging box needs to judge the situation of the wireless earphone, namely, the load is detected, the state of the load is identified, the corresponding function can be selected, the state of the load and the power supply requirement are detected through the load detection circuit, and then a signal is output to a control chip of the electronic device, so that the control chip controls the electronic device to execute the corresponding function. Electronic devices, including but not limited to wireless headphones, may also be used in other scenarios where load detection is desired.
Referring to fig. 1, in an embodiment of the present invention, the load detection circuit includes:
the load interface VO is used for connecting a load;
the digital controllable current steering circuit 10, wherein the input end of the digital controllable current steering circuit 10 is used for being connected with a power supply voltage, and the digital controllable current steering circuit 10 is used for outputting a controllable current with a first preset magnitude to the load interface VO at the initial stage of the load interface VO being connected with a load so as to provide a charging current for the connected load;
The load power supply demand identification control circuit is used for detecting the voltage of the load interface VO so as to determine the power supply demand of an accessed load, and controlling the digital controllable current rudder circuit 10 to output controllable current matched with the load to the load interface VO according to the power supply demand, wherein the input end of the load power supply demand identification control circuit is connected with the output end of the digital controllable current rudder circuit 10, and the detection end of the load power supply demand identification control circuit is connected with the load interface VO.
In this embodiment, the load interface VO is an interface corresponding to the load, and the specific shape of the load interface VO may be set according to the load, for example, when the load interface VO is applied to charging a wireless earphone, the shape of the load interface VO may be set according to a power pin of the wireless earphone. The digital controllable current steering circuit 10 can be composed of a plurality of switching tubes, the digital controllable current steering circuit 10 can generate and output controllable current by receiving an external digital control signal, the digital control signal can be generated by a control chip in electronic equipment, and a user can set the digital control signal output to the digital controllable current steering circuit 10 according to actual requirements, so that the digital controllable current steering circuit 10 can generate current required by the user; for example, the digital control signal is an electrical signal with high and low levels, the switching tube in the digital controllable current steering circuit 10 is controlled to be turned on or off by the electrical signals with different levels, and the time for which the switching tube is turned on or off is controlled, so that the current in the digital controllable current steering circuit 10 is changed, in practical application, a user can preset the digital control signal, so that the digital controllable current steering circuit 10 outputs a controllable current with a first preset magnitude to the load interface VO at the initial stage of the load interface VO accessing the load, and thus, charging current is provided for the accessed load, and the first preset magnitude can be set according to the user requirement and practical situation.
The load power supply demand identification control circuit can judge the demand of the load for the power supply after the load is connected, so as to control the digital controllable current rudder circuit 10 to output corresponding controllable current to the load interface VO to charge the capacitor. For example, the controllable current output by the digital controllable current rudder circuit 10 is divided into two paths or multiple paths, one path provides charging current for the accessed load in the initial stage of accessing the load, if the controllable current of one path cannot meet the static power consumption requirement of the load, the voltage value of the load interface VO is lower than a preset value at the moment, so that the two paths or multiple paths of controllable currents are required to be output to the load interface VO to supply power to the load, and the output of the two paths or multiple paths of controllable currents can be controlled through switching devices such as MOS (metal oxide semiconductor) tubes; if one path of controllable current can meet the static power consumption requirement of the load, the voltage value of the load interface VO is larger than or equal to a preset value, and one path of current is used for supplying power to the load; the magnitude of the preset value is determined by the characteristics of the devices forming the circuit, the magnitude of the controllable current setting, and the load's demand for quiescent current. It can be understood that, in an electronic device applied to the load detection circuit, such as a wireless earphone, a capacitor is generally disposed in a wireless earphone load, and the different loads may have different capacitor sizes, and the larger the capacitor, the slower the charging speed of the capacitor when receiving the current with the same current value; therefore, the load with larger capacitance outputs smaller current, the charging requirement of the load cannot be met, if the load with smaller capacitance outputs larger current, the voltage of the capacitance can be quickly increased or the protection circuit arranged in the circuit can consider the large current as higher jitter, so that the large current is filtered, the voltage change of the capacitance can be influenced, the sensitivity of load access detection is influenced, different load capacitances have different power supply requirements, the digital controllable current rudder circuit 10 charges the load capacitance while the load interface VO is connected with the load, and if the charging current and the load capacitance have larger phase difference, the accuracy of load voltage detection can be influenced, the load capacitance can be normally charged by controlling the output of the digital controllable current rudder circuit 10 and the load capacitance to match the current, and the voltage value of the load interface VO can be kept to be normally increased, so that the influence of the mismatch of the load capacitance and the charging current on the voltage detection of the load interface VO is reduced, and the accuracy of the load detection is improved.
According to the technical scheme, a load detection circuit is formed by a load interface VO, a digital controllable current rudder circuit 10 and a load power supply demand identification control circuit, wherein the load interface VO is used for connecting a load; the input end of the digital controllable current steering circuit 10 can be connected with a power supply voltage, and the digital controllable current steering circuit 10 can output a controllable current with a first preset magnitude to the load interface VO at the initial stage of connecting the load interface VO to a load so as to provide charging current for the connected load; the input end of the load power supply demand identification control circuit is connected with the output end of the digital controllable current rudder circuit 10, the detection end of the load power supply demand identification control circuit is connected with the load interface VO, the load power supply demand identification control circuit can detect the voltage of the load interface VO to determine the power supply demand of an accessed load, and the digital controllable current rudder circuit 10 is controlled to output controllable current matched with the load to the load interface VO according to the power supply demand so as to provide detection current for the accessed load. The present invention aims to improve the accuracy of load detection.
In an embodiment, an output end of the load power supply demand identification control circuit is used for being connected with a control chip, the load power supply demand identification control circuit is used for outputting an access signal to the control chip when detecting that a load is accessed according to a voltage value of the load interface VO, and the load power supply demand identification control circuit is also used for outputting a sleep signal to the control chip when detecting that the load is not accessed according to the voltage value of the load interface VO.
In this embodiment, the load power supply requirement identification control circuit may specifically detect whether the load is connected according to the voltage value of the load interface VO; for example, after the load is connected, since a capacitor is usually disposed in the load, and the voltages at two ends of the capacitor cannot be suddenly changed, the voltage of the capacitor is 0 when the electronic device just begins to work, so that the voltage of the load interface VO is pulled down to the voltage of the capacitor, that is, 0, and then the load is connected according to the low voltage, at this time, the load power supply requirement identification control circuit can output an access signal to the control chip, and the control chip controls the electronic device to start working. Otherwise, when the load is not connected, the controllable current pulls up the voltage of the load interface VO to the voltage of the external power supply, and at the moment, the high voltage is detected, so that the fact that the load is not connected is judged, at the moment, the load power supply demand identification control circuit can output a dormant signal to the control chip, the control chip controls the whole electronic equipment to enter a dormant state, and therefore the whole power consumption of the electronic equipment is reduced.
In one embodiment, the load power supply demand identification control circuit comprises:
the load power supply demand identification circuit 20, a detection end of the load power supply demand identification circuit 20 is connected with the load interface VO, and the load power supply demand identification circuit 20 is used for detecting the voltage of the load interface VO to determine the power supply demand of an accessed load and output a power supply demand signal;
The load power supply control circuit, the controlled end of load power supply control circuit with the output of load power supply demand identification circuit 20 is connected, the input of load power supply control circuit with the output of digital controllable electric current rudder circuit 10 is connected, the output of load power supply control circuit with load interface VO is connected, load power supply control circuit is used for according to the power supply demand signal control digital controllable electric current rudder circuit 10 output with the controllable electric current of load matching is to load interface VO is in order to provide the detection current for the load of switch-on.
In the present embodiment, the load power supply demand recognition control circuit is constituted by the load power supply demand recognition circuit 20 and the load power supply control circuit; when a load is connected to the load interface VO, the load power supply demand identification circuit 20 is configured to detect a voltage of the load interface VO, thereby determining a power supply demand of the connected load, and output a power supply demand signal to the load power supply control circuit, where the load power supply control circuit is configured to control the digital controllable current steering circuit 10 to output a controllable current matched with the load to the load interface VO according to the power supply demand signal, so as to provide a detection current for the connected load. The load power supply demand identification circuit 20 may be formed by electronic elements such as a comparator COMP1 and a MOS transistor, so as to perform a function of comparing the voltage of the load interface VO with the voltage in the circuit, and the load power supply control circuit may be formed by electronic elements such as a MOS transistor, where a source electrode of the MOS transistor is connected to an external power source, and a gate electrode of the MOS transistor is connected to the load interface VO, so that the function of controlling the magnitude of current in the circuit can be performed through on and off of the MOS transistor. Specifically, when a load is inserted, a controllable current with a first preset magnitude output by the digital controllable current rudder circuit 10 starts to charge a capacitor in the load, and if the current can meet the static power consumption requirement of the load, the voltage of the load interface VO is pulled up to a voltage VT which is larger than an opening voltage of an external power supply MOS (metal oxide semiconductor) transistor; namely, the voltage difference between the grid electrode and the drain electrode of the MOS tube meets the following conditions: vgs=vg-Vs < VT, and the MOS transistor is automatically turned off. Where Vg is the gate voltage of mn_sw, vs is the drain voltage of mn_sw, and VT depends on the magnitude of the detected current setting and the load's quiescent current requirement. If the controllable current of the first preset magnitude cannot meet the requirement of the load on the quiescent current, the controllable current matched with the load needs to be output to the load interface VO, and at this time, the voltage at the end of the load interface VO is maintained at a voltage VT smaller than the voltage VT of the external power supply minus the turn-on voltage of the MOS transistor, that is, the MOS transistor meets the following conditions: vgs=vg-Vs > VT, at this time, the MOS transistor is turned on, and the additional current output by the digital controllable current steering circuit 10 and the controllable current with the first preset magnitude are combined into a controllable current matched with the load, and the controllable current is output to the load interface VO to charge the load. Thus, the requirements of different loads on the power supply or the requirements of the loads on the power supply under different conditions can be met.
Referring to fig. 3, in an embodiment, the load power demand identification circuit 20 includes a first PMOS transistor MP1, a comparator COMP1, an AND gate AND, a level shifter LTH, AND a plurality of inverter circuits, where a gate of the first PMOS transistor MP1 is used to access a power supply voltage, a source of the first PMOS transistor MP1 is an input terminal of the load power demand identification circuit 20, a drain of the first PMOS transistor MP1 is connected to the load interface VO, a forward input terminal of the comparator COMP1 is used to access an external power supply, an inverting input terminal of the comparator COMP1 is connected to the load interface VO, a first input terminal of the AND gate AND is connected to an output terminal of the comparator COMP1 AND is used to connect a control chip, a second input terminal of the AND gate AND is connected to a plurality of output terminals after being connected in series to the inverter circuits, an output terminal of the AND gate AND the output terminal of the level shifter LTH is used to connect a control chip, AND a plurality of controlled terminals after being connected to the output terminals of the inverter circuits are connected to the plurality of the inverter circuits in series.
Each inverting circuit comprises a first NMOS tube MN_SW and a second PMOS tube MPdet, wherein the grid electrode of the first NMOS tube MN_SW and the grid electrode of the second PMOS tube MPdet are connected with each other and are the controlled end of the inverting circuit, the source of the second PMOS tube MPdet is the input end of the inverting circuit, the drain electrode of the second PMOS tube MPdet and the drain electrode of the first NMOS tube MN_SW are connected with each other and are the output end of the inverting circuit, and the source electrode of the first NMOS tube MN_SW is grounded.
In this embodiment, three inverter circuits may be connected in series, where when the gate of the first NMOS transistor mn_sw and the gate of the second PMOS transistor MPdet in the inverter circuit receive a high level, the first NMOS transistor mn_sw is turned on, the second PMOS transistor MPdet is turned off, at this time, the output terminal voltage of the inverter circuit is pulled down to ground, when the gate of the first NMOS transistor mn_sw and the gate of the second PMOS transistor MPdet receive a low level, the first NMOS transistor mn_sw is turned off, the second PMOS transistor MPdet is turned on, and at this time, the input terminal voltage of the inverter circuit is pulled high; because the voltage of the VO end of the load interface is not fixed, the standard inverter can be inevitably led to enter an amplifying area to cause very large static power consumption, the inverter is processed by utilizing the thought of amplifying step by step, the overturning voltage of the first-stage inverter is about 1v, the second stage and the third stage mainly form a buffer, the output of the first-stage inverter is enhanced, the final output and loadon signals are AND logic, and the loadon interface can be the output end of a comparator COMP1, so that the influence caused by the voltage jitter of the VO of the load interface can be avoided, and the circuit is guaranteed to have almost no static power consumption. When the load is inserted, it is firstly judged that the load exists, if the capacitance electric quantity is 0, then the voltage at the end of the load interface VO is pulled down to 0, then the load interface VO is triggered to a power supply judging module circuit, an insert signal jumps high, a control circuit can perform operations such as communication and discharging on a chip according to purposes, the insert signal can be output by the output end of a level shifter LTH, the power supply of the load power supply demand identifying circuit 20 is connected with vdd_det except the level shifter LTH, because the power supply of the load detecting circuit is changed, if the power supply of the circuit keeps vdd a, the turnover threshold of an inverter is changed, and then judgment errors are caused, the generated signal is converted into vdd a level, the signal received by a digit is ensured to be a standard level, and the transistor of the digital circuit is prevented from entering a saturation region. If the load is continuously present, when the capacitance electric quantity exceeds the threshold of the power supply judging module, the earphone is required to pull down the interface voltage to 0 to trigger the power supply requirement to execute the operation of the control circuit again. The insert signal is only a pulse signal, and the threshold is related to the magnitude of the capacitor voltage, but only the rising edge is used in the jitter elimination process. If the load is in a balanced state after insertion, the MPdet is in a saturation region, the positive terminal of the comparator COMP1 is connected to the vdd_det, and the negative terminal is connected to the load interface VO, in this embodiment, the input bias voltage vos=200mv set by the comparator COMP 1; the voltage difference Vdiff across the comparator COMP1 is now approximately equal to vdd_det-2Vov. When Vdiff is greater than Vos, the presence of a load can be identified. Vov is the overdrive voltage.
Referring to fig. 3, in an embodiment, the load power supply control circuit includes a second NMOS transistor, a gate of the second NMOS transistor is a controlled end of the load power supply control circuit, a drain of the second NMOS transistor is an input end of the load power supply control circuit, and a source of the second NMOS transistor is an output end of the load power supply control circuit.
In this embodiment, after the load is connected, two or more branch currents output by the digital controllable current rudder circuit 10 start to charge the capacitor, if the controllable current with the first preset magnitude can meet the static power consumption requirement of the load, the voltage of the load interface VO will be pulled up to a voltage value greater than vdd_det minus mn_sw, where the voltage value depends on the magnitude of the detected current setting and the requirement of the load on the static current; namely mn_sw satisfies: vgs=vg-Vs < VT, mn_sw will be turned off automatically. If the controllable current of the first preset magnitude cannot meet the requirement of the load on the quiescent current, outputting the controllable current matched with the load to the load interface VO, wherein the voltage at the end of the load interface VO is maintained to be smaller than the voltage value of vdd_det minus an mn_sw on voltage, that is, mn_sw meets the following conditions: vgs=vg-Vs > VT.
Referring to fig. 2, in one embodiment, the digitally controllable current steering circuit 10 includes:
The detecting current steering circuit 11, wherein the output end of the detecting current steering circuit 11 is connected with the input end of the load power supply demand identification control circuit, and the detecting current steering circuit 11 is used for generating detecting current according to an external digital control signal and outputting the detecting current to the load power supply demand identification control circuit;
the maintaining current rudder circuit 12, wherein the output end of the maintaining current rudder circuit 12 is connected with the input end of the load power supply demand identification control circuit, and the maintaining current rudder circuit 12 is used for generating maintaining current according to an external digital control signal and outputting the maintaining current to the load power supply demand identification control circuit;
the load power supply demand identification control circuit is used for controlling the detection current to be output to the load interface VO when the load is connected and the voltage value of the load interface VO is detected to be larger than or equal to a preset voltage value; the load power supply demand identification control circuit is further configured to control the detection current and the maintenance current to be output to the load interface VO when the load is connected and the voltage value of the load interface VO is detected to be smaller than a preset voltage value.
In this embodiment, the digital controllable current steering circuit 10 may be composed of a detecting current steering circuit 11 and a maintaining current steering circuit 12, and when the load is connected, the load power supply demand identification control circuit may determine the power supply demand of the load according to the controllable current and the voltage value of the load interface VO, output the connection signal to the control chip, and output the detecting current or the maintaining current to the load interface VO, thereby supplying power to the load; after the load is inserted, the currents output by the detection current rudder circuit 11 and the maintenance current rudder circuit 12 start to charge the capacitor in the load, and if the detection currents can meet the static power consumption requirement of the load, the voltage of the load interface VO is pulled up to a voltage VT which is larger than vdd_det minus MN_SW by an opening voltage; namely mn_sw satisfies: vgs=vg-Vs < VT, mn_sw will be turned off automatically. Where Vgs is the gate-drain voltage difference of mn_sw, vg is the gate voltage of mn_sw, vs is the drain voltage of mn_sw, and VT depends on the magnitude of the detected current setting and the load demand for quiescent current. If the detected current cannot meet the load demand for the quiescent current, the holding current will act, and the voltage at the VO terminal of the load interface will be maintained at a voltage VT less than vdd_det minus an mn_sw on-voltage, i.e., mn_sw meets: vgs=vg-Vs > VT. Thus, the requirements of different loads on the power supply or the requirements of the loads on the power supply under different conditions can be met.
In an embodiment, the number of the load power supply demand identification control circuits and the number of the digital controllable current steering circuits 10 are multiple, the power input end of each load power supply demand identification control circuit is used for accessing a first power supply voltage, the power input end of each digital controllable current steering circuit 10 is used for accessing a second power supply voltage, the output ends of the digital controllable current steering circuits 10 are connected with the input ends of the multiple load power supply demand identification control circuits in a one-to-one correspondence manner, the multiple load power supply demand identification control circuits are connected in parallel, and the multiple digital controllable current steering circuits 10 are connected in parallel.
In this embodiment, a plurality of load power supply demand recognition control circuits and a plurality of digital controllable current steering circuits 10 are provided, so that a multi-channel detection function can be realized, and an electronic device with multiple channels can be used, so that control signals can be shared or separately controlled, and as can be known from the above description, only one comparator COMP1 is added for each additional set of load power supply demand recognition control circuits and digital controllable current steering circuits 10 under no-load conditions, and the power consumption of the circuit is also the static power consumption of the comparator COMP1, so that the application scenario of low power consumption can be maintained.
Referring to fig. 5, in an embodiment, the load detection circuit further includes:
the input end of the bias circuit 50 is used for being connected with an external power supply, the output end of the bias circuit 50 is connected with the power supply input end of the digital controllable current steering circuit 10 and the power supply input end of the load power supply demand identification control circuit, the bias circuit 50 is also used for converting the external power supply and outputting a first power supply voltage and a second power supply voltage to the load power supply demand identification control circuit, and the bias circuit 50 is used for converting the external power supply and outputting a third power supply voltage to the digital controllable current steering circuit 10.
In this embodiment, the bias circuit 50 may provide appropriate voltage bias for the comparator COMP1 and the current rudder, so that in order to reduce power consumption, the scheme may use voltage bias, so that the quiescent current of the bias circuit 50 is fixed to be 1uA, a lower quiescent current can be achieved by modifying the size ratio of the internal bias tube, and the lower limit of the value is 0.1uA under the influence of process errors. The circuit adopts a self-bias current mirror structure, and can also adopt other structures, and the circuit respectively generates three voltage biases: vbp, vbn, and det_gate, the first power supply voltage vbp and the second power supply voltage det_gate are provided to the digital controllable current steering circuit 10 and the first PMOS transistor MP1 in the load insertion detection circuit. The third power voltage vbn is mainly provided to the comparator COMP1, so that at least 2 current branches can be saved, and the power consumption of the circuit can be reduced.
Referring to fig. 6, in an embodiment, the load detection circuit further includes:
the logic circuit 30 is used for accessing an external control signal and outputting a corresponding logic signal according to the external control signal;
the power supply selection circuit 40 is provided with a plurality of power supply input ends, each power supply input end is used for being connected with an external power supply, the output end of the power supply selection circuit 40 is connected with the input end of the bias circuit 50, the controlled end of the power supply selection circuit 40 is connected with the output end of the logic circuit 30, and the power supply selection circuit 40 is used for receiving and selecting the corresponding external power supply to be output to the bias circuit 50 according to the logic signal.
In this embodiment, the power supply selection circuit 40 mainly provides power supply under different scenarios to the load detection circuit. The user can output an external control signal to the logic circuit 30 through the external device according to actual needs, and the logic circuit 30 can output a logic signal to the power supply selection circuit 40 according to the external control signal, so that a corresponding power supply is selected to be provided for the load detection circuit; for a multi-power system, the circuit is capable of adaptively powering the power supply. An LDO module and a power supply logic with high automatic switching voltage for multi-power supply are built in. When the control chip of the electronic device starts to operate, if sel_vdd=1, it indicates that the LDO module is powered, i.e. en_load=1. When the work starts, the en_load jumps high firstly, the voltage pmid of the circuit gradually rises, a power supply vbat is selected to supply power at the moment, and pmiok jumps high after pmid rises to the maximum value; since the power consumption is slightly different at different power supplies, the lowest power consumption, i.e., the power vbat of sel_vdd=0, is selected by default. In this way, a diversified power supply scheme is provided, meanwhile, the scheme only has static power consumption in the LDO module power supply mode, when another power supply is selected for power supply, the static power consumption is almost not generated, and multiple power supplies can be one or more and can be flexibly matched according to application scenes. Vdd a in the circuit is the highest power supply for the chip to select itself, only for the power supply of the small module.
For better illustrating the inventive concept of the present invention, the working principle of the present invention will be described with reference to fig. 1 to 6 and the above embodiments:
when the circuit works, the power supply selection circuit 40 can select a power supply before standby, the digital controllable current rudder can also select the output current according to an external digital control signal, and the bias circuit 50 can provide bias voltage, namely power supply voltage, for the digital controllable current rudder and the load detection circuit;
the digital controllable current steering circuit 10 can be divided into a maintaining current branch and a detecting current branch, and two paths of output currents of the digital controllable current steering circuit 10 are connected into a load power supply demand identification control circuit; the maintaining current branch is connected in series with a switch tube MN_SW, and the grid electrode of the maintaining current branch is connected with vdd_det to keep a normally open state. When the load does not exist, the detection current pulls up the voltage of the load interface VO to vdd_det, and the static power consumption of the circuit is 0 because the load interface VO is in an open circuit state; when the load is inserted, the comparator COMP1 first recognizes that the load exists, and since the voltage across the capacitor cannot be suddenly changed, the voltage across the load interface VO is pulled down to 0, and then determines that the load is inserted. At this time, both branch currents start to charge the capacitor, if the detected current can meet the static power consumption requirement of the load, the voltage of the load interface VO is pulled up to be larger than the voltage value of vdd_det minus one starting voltage of MN_SW, and the voltage value depends on the set magnitude of the detected current and the requirement of the load on the static current; namely mn_sw satisfies: vgs=vg-Vs < VT, mn_sw will be turned off automatically. If the detected current cannot meet the load demand for the quiescent current, the holding current will act, and the voltage at the VO terminal of the load interface will be maintained at a voltage value less than vdd_det minus an mn_sw on voltage, i.e., mn_sw meets: vgs=vg-Vs > VT. The load power supply requirement identification circuit 20 can comprise 3 inverter circuits connected in series, because the voltage of the VO end of the load interface is not fixed, a standard inverter is adopted to cause the load interface to enter an amplifying region, and thus very large static power consumption is caused, the inverter circuits are processed by utilizing a gradual amplifying thought, the 3 inverter circuits connected in series are divided into three stages, the overturn voltage of the first-stage inverter circuit is about 1v, the second stage and the third stage mainly form a buffer, the output of the first-stage inverter circuit is enhanced, and finally output and loadon signals are AND-logic, so that the influence caused by the jitter of the VO voltage can be avoided, and meanwhile, the circuit is guaranteed to have almost no static power consumption; since the inverter circuit is constituted by the switching transistor, the threshold voltage of the switching transistor is set lower, and thus the effects of reducing jitter and reducing power consumption can be achieved. When the load is inserted, firstly, the load is judged to exist, the voltage at the end of the load interface VO is pulled down to 0 under the assumption that the capacitance electric quantity is 0, then the load interface VO is triggered to a power supply judging module circuit, an insert signal jumps high, a chip control circuit in the electronic equipment can carry out operations such as communication and discharging on the chip according to purposes, and a power supply of the power supply judging circuit is connected with vdd_det except LTH, because the power supply of the load detecting circuit is changed, if the power supply of the circuit keeps vdd a, the turnover threshold of an inverting circuit is changed, and then, the judgment is wrong, the generated signal is converted into the vdd level, the signal received by the controllable current rudder circuit is ensured to be the standard level, and the transistor of the digital controllable current rudder circuit 10 is prevented from entering a saturation region. If the load is continuously present, when the capacitance electric quantity exceeds the threshold of the power supply judging module, the earphone is required to pull down the interface voltage to 0 to trigger the power supply requirement to execute the operation of the control circuit again. The insert signal is only a pulse signal, and the threshold is related to the magnitude of the capacitor voltage, but only the rising edge is used in the jitter elimination process. If the load is in a balanced state after insertion, the first PMOS tube MP1 is in a saturation region, the positive terminal of the comparator COMP1 is connected to the vdd_det, and the negative terminal is connected to the load interface VO, and at this time, the differential pressure Vdiff across the comparator COMP1 is approximately equal to vdd_det-2Vov. Vdiff is greater than Vos, so the presence of a load can be identified. Vov is the overdrive voltage.
The digital controllable current rudder circuit 10 can comprise a plurality of branches, each branch is provided with a switch, the output of the switches is finally connected together, the output current of the current rudders is digitally controlled, the control ports are a and b respectively, the number of the current rudders is not unique, and the number of the current rudders can be increased or reduced, so that the application scene of the load detection circuit is greatly widened. The output current can have 2 paths, namely a detection current and a maintenance current, the magnitude of the detection current is related to the load capacitance, the relation of the detection current and the load capacitance can be represented by CV=IT, wherein T is the capacitance charging time and is larger than the debounce time T1 of digital pair loadon, and Idet=CV/(T-T1) is assumed, so that a plurality of detection current gears are arranged, and the digital programming is flexible to switch according to different application scenes. The maintaining current can be output to the load to maintain the static power consumption requirement of the load, and when the detecting current can not maintain VO > vdd_det-Vgs (about 1V), the maintaining current can also be output to the load to maintain the power consumption requirement of the load. Assuming that the current idet=1ua in the circuit, the external power supply vdd_det=3.8v, the minimum value cmin= (idet+isustin) T11/(vdd_det-Vgs) of the load capacitance is obtained by calculation, cmin=idet 12/(Vgs), t11+t12=65ms, and cmin=44.3 nF is obtained. This capacitance is already very small in the hardware circuit, and due to the loading effect, idet does not pull the VO point voltage up to the voltage node that causes loadon=0. The problem that the small load is difficult to detect under the condition of low power consumption can be solved through the integral circuit structure, and meanwhile, the sensitivity is high.
The invention further provides electronic equipment.
In an embodiment, the electronic device comprises a load detection circuit as described above. The specific structure of the load detection circuit refers to the above embodiments, and because the electronic device adopts all the technical solutions of all the embodiments, the load detection circuit has at least all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all the equivalent structural changes made by the description of the present invention and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the invention.
Claims (9)
1. A load detection circuit, comprising:
the load interface is used for connecting a load;
the digital controllable current steering circuit is used for outputting a first controllable current with a preset size to the load interface at the initial stage of the load interface being connected with the load so as to provide charging current for the connected load;
The load power supply demand identification control circuit is used for detecting the voltage of the load interface so as to determine the power supply demand of an accessed load, and controlling the digital controllable current rudder circuit to output controllable current matched with the load to the load interface according to the power supply demand so as to provide detection current for the accessed load;
the load power supply demand identification control circuit comprises a load power supply demand identification circuit and a load power supply control circuit, the load power supply demand identification circuit comprises a first PMOS tube, a comparator, an AND gate, a level shifter and a plurality of inverting circuits, the grid electrode of the first PMOS tube is used for being connected with a power supply voltage, the source of the first PMOS tube is the input end of the load power supply demand identification circuit, the drain electrode of the first PMOS tube is connected with a load interface, the forward input end of the comparator is used for being connected with an external power supply, the reverse input end of the comparator is connected with the load interface, the first input end of the AND gate is connected with the output end of the comparator and is used for being connected with a control chip, the output end of the AND gate is connected with the input end of the level shifter, the output end of the level shifter is used for being connected with the control chip, and the controlled end of the inverting circuits after being connected with the output end of the digital controllable current rudder circuit is connected with the output end of the digital controllable current circuit, and the plurality of inverting circuits are connected with the output end of the digital controllable current rudder.
2. The load detection circuit of claim 1, wherein an output terminal of the load power supply demand identification control circuit is configured to be connected to a control chip, the load power supply demand identification control circuit is configured to output an access signal to the control chip when a load access is detected according to a voltage value of the load interface, and the load power supply demand identification control circuit is further configured to output a sleep signal to the control chip when a load non-access is detected according to a voltage value of the load interface.
3. The load detection circuit of claim 1, wherein a detection terminal of the load power supply demand identification circuit is connected to the load interface, the load power supply demand identification circuit is configured to detect a voltage of the load interface to determine a power supply demand of an accessed load, and output a power supply demand signal;
the controlled end of the load power supply control circuit is connected with the output end of the load power supply demand identification circuit, the input end of the load power supply control circuit is connected with the output end of the digital controllable current rudder circuit, the output end of the load power supply control circuit is connected with the load interface, and the load power supply control circuit is used for controlling the digital controllable current rudder circuit to output controllable current matched with the load to the load interface according to the power supply demand signal so as to provide detection current for the accessed load.
4. The load detection circuit of claim 1, wherein each of the inverter circuits comprises a first NMOS transistor and a second PMOS transistor, wherein a gate of the first NMOS transistor and a gate of the second PMOS transistor are interconnected and are controlled ends of the inverter circuit, a source of the second PMOS transistor is an input end of the inverter circuit, a drain of the second PMOS transistor is interconnected with a drain of the first NMOS transistor and is an output end of the inverter circuit, and a source of the first NMOS transistor is grounded.
5. The load detection circuit of claim 1, wherein the load supply control circuit comprises a second NMOS transistor, a gate of the second NMOS transistor being a controlled terminal of the load supply control circuit, a drain of the second NMOS transistor being an input terminal of the load supply control circuit, a source of the second NMOS transistor being an output terminal of the load supply control circuit.
6. The load detection circuit of claim 1, wherein the number of the load power supply demand identification control circuit and the digital controllable current steering circuit is plural, a power input end of each load power supply demand identification control circuit is used for accessing a first power supply voltage, a power input end of each digital controllable current steering circuit is used for accessing a second power supply voltage, output ends of the digital controllable current steering circuits are connected with input ends of the load power supply demand identification control circuits in a one-to-one correspondence manner, the load power supply demand identification control circuits are connected in parallel, and the digital controllable current steering circuits are connected in parallel.
7. The load detection circuit of claim 1, wherein the load detection circuit further comprises:
the input end of the bias circuit is used for being connected with an external power supply, the output end of the bias circuit is connected with the power supply input end of the digital controllable current steering circuit and the power supply input end of the load power supply demand identification control circuit, the bias circuit is also used for converting the external power supply and outputting a first power supply voltage and a second power supply voltage to the load power supply demand identification control circuit, and the bias circuit is used for converting the external power supply and outputting a third power supply voltage to the digital controllable current steering circuit.
8. The load detection circuit of claim 7, wherein the load detection circuit further comprises:
the logic circuit is used for accessing an external control signal and outputting a corresponding logic signal according to the external control signal;
the power supply selection circuit is provided with a plurality of power supply input ends, each power supply input end is used for being connected with an external power supply, the output end of the power supply selection circuit is connected with the input end of the bias circuit, the controlled end of the power supply selection circuit is connected with the output end of the logic circuit, and the power supply selection circuit is used for receiving and selecting the corresponding external power supply to be output to the bias circuit according to the logic signals.
9. An electronic device comprising a control chip and a load detection circuit as claimed in any one of claims 1-8.
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