CN116683905A - Semiconductor device and electronic apparatus - Google Patents

Abstract

The embodiment of the application provides a semiconductor device and electronic equipment comprising the semiconductor device. Relates to the technical field of logic gate circuit processes. Mainly to provide a logic gate circuit that can simplify the interconnection process. The semiconductor device includes a substrate and a first logic gate circuit formed on the substrate, the first logic gate circuit having: an input and a conjugate input, and an output and a conjugate output; the input end, the conjugate input end, the output end and the conjugate output end are formed in the same layer structure, and the input end and the conjugate input end are arranged along a first straight line; the output ends and the conjugate output ends are arranged along a second straight line intersecting the first straight line, for example, the first straight line is perpendicular to the second straight line; and the input end and the conjugate input end are arranged at two sides of the second straight line, and the output end and the conjugate output end are arranged at two sides of the first straight line. The interconnection process is simplified by a unipolar, conjugated, centrally symmetrical arrangement of structures.

Description

Semiconductor devices, electronic equipment

technical field

The present application relates to the technical field of logic gate circuits, and in particular to a semiconductor device and electronic equipment including the semiconductor device.

Background technique

A phase inverter is a circuit that can reverse the phase of an input signal by 180 degrees, and is an important logic unit of an integrated circuit.

FIG. 1 shows a circuit structure diagram of a conventional complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) inverter, and FIG. 2 is a process structure diagram of the CMOS inverter shown in FIG. 1 . Combining Figure 1 and Figure 2 together, in the shown CMOS inverter, a hole-type metal oxide semiconductor field effect transistor (p-type metal oxide semiconductor field effect transistor, pMOSFET) T1 and a hole n-type metal oxide semiconductor field effect transistor (n-type metal oxide semiconductor field effect transistor, nMOSFET) T2.

Wherein, as shown in FIG. 1 and FIG. 2, in the CMOS inverter structure, the gate (Gate) of the pull-up transistor T1 and the gate of the pull-down transistor T2 share a metal wire as the input of the CMOS inverter Terminal IN, the source (Source) of the pull-up transistor T1 and the drain (Drain) of the pull-down transistor T2 share a metal line, which is used as the output terminal OUT of the CMOS inverter, and the drain (Drain) of the pull-up transistor T1 is connected to The power supply voltage (VDD), the source (Source) of the pull-down transistor T2 is connected to the ground terminal voltage (VSS) or the ground (GND). Continuing to see what is shown in Figure 2, the channel of the pull-up transistor T1 (which can also be referred to as the active region) requires n-type doping, and the channel of the pull-down transistor T2 utilizes the substrate (the substrate is not shown in Figure 2) doping.

In the above CMOS inverter, in order to obtain better voltage transmission characteristics, the driving current of nMOSFET and pMOSFET needs to be consistent, and the driving current of nMOSFET and pMOSFET is approximately proportional to the carrier mobility and channel width .

Since the electron mobility (μe) of most semiconductors is different from the hole mobility (μp), in order to achieve current matching, integrated circuit fabrication will use the ratio of the device width of the pMOSFET (Wp) to the device width of the nMOSFET (Wn) (Wp/Wn) is set to μe/μp. However, with the continuous development of integrated circuit manufacturing technology, the miniaturization of traditional Si devices has entered a bottleneck period, and various high-performance channel materials have been proposed, and the μe/μp is relatively large (for example, μe/μp>20, or even larger ), therefore, the ratio of Wp to Wn is relatively large. In the achievable process structure, as shown in FIG. 2 , a large Wp is required to achieve current matching.

In this way, in the structure of the CMOS inverter, the pMOSFET will occupy a larger area. If the CMOS inverter is applied in a more complex circuit structure, the occupied area of the circuit structure will be significantly increased, and the Difficulty in circuit design and increase in manufacturing cost.

Contents of the invention

The present application provides a semiconductor device and electronic equipment with the semiconductor device. The main purpose is to provide a unipolar logic gate circuit with a conjugate input and a conjugate output, and the conjugate input terminal and the conjugate output terminal of the logic gate circuit are arranged symmetrically, so that the logic gate circuit can be applied In complex integrated circuits, it can reduce the occupied area and reduce the difficulty of circuit design.

In order to achieve the above object, the application adopts the following technical solutions:

In one aspect, the present application provides a semiconductor device, and the semiconductor device may be an SRAM memory, a flip-flop, an oscillator, and the like.

The semiconductor device includes a substrate and a first logic gate circuit formed on the substrate, and the first logic gate circuit is a unipolar logic gate circuit. Wherein, the first logic gate circuit has: an input terminal and a conjugate input terminal, and an output terminal and a conjugate output terminal; the input terminal, the conjugate input terminal, the output terminal and the conjugate output terminal are formed in the same layer structure, such as , can be formed in the same layer structure parallel to the substrate; in addition, the input terminal and the conjugated input terminal are arranged along the first straight line; the output terminal and the conjugated output terminal are arranged along the second straight line intersecting the first straight line Arrangement, for example, the first straight line is perpendicular to the second straight line; and the input end and the conjugate input end are arranged on both sides of the second straight line, and the output end and the conjugate output end are arranged on both sides of the first straight line.

Based on the above description of the circuit structure of the first logic gate circuit in the semiconductor device, it can be seen that the logic gate circuit is controlled by a conjugated input signal (that is, includes an input terminal receiving an inverted signal and a conjugated input terminal) and has a conjugated output, that is, includes an output terminal capable of outputting an inverted signal and a conjugated output terminal, thereby forming a conjugated logic gate circuit with a conjugated input and a conjugated output.

In addition, since the first logic gate circuit is a unipolar logic gate circuit, that is to say, in the logic gate circuit, all transistors have the same pole type, for example, all of them may be pMOSFETs, or all of them may be nMOSFETs . In this way, the ratio between the channel width (Wp) of the pMOSFET and the channel width (Wn) of the nMOSFET will not be large due to the need for better voltage transfer characteristics in the traditional CMOS inverter, causing one of the channel The phenomenon that the road occupies a larger area.

In addition, since the logic gate circuit is a conjugate input and a conjugate output, for example, in some more complex logic gate circuits, the above logic gate circuits can be cascaded, that is, the first stage logic gate circuit The conjugated output of can be used as the conjugated input of the second logic gate circuit to form a complex circuit.

In addition, the input terminal and the conjugate input terminal of the logic gate circuit are arranged on both sides of the second straight line, and the output terminal and the conjugate output end are arranged on both sides of the first straight line. That is, the input terminal and the conjugated input terminal, and the output terminal and the conjugated output terminal may be centrosymmetric. If set in this way, when the logic gate circuit is set in multiple stages, for example, when the two logic gate circuits need to be connected to form a logic circuit such as a latch or a ring oscillator, it is only necessary to make the logic gate circuit structure Symmetrical rotation operations and three-dimensional stacking allow simple vertical interconnection. Wherein, the cascade connection of the conjugate input and output of the two logic gate circuits can be realized through the vertical through-hole connection. In this way, the design difficulty of the entire integrated circuit will be significantly reduced, and the occupied area will be reduced, so as to improve the integration degree of the integrated circuit.

In a practicable manner, the semiconductor device further includes: a unipolar second logic gate circuit, the first logic gate circuit is formed in a first layer structure parallel to the substrate, and the second logic gate circuit is formed in In the second layer structure parallel to the first layer structure; the second logic gate circuit has: an input terminal and a conjugate input terminal, and an output terminal and a conjugate output terminal; the input terminal of the second logic gate circuit is connected to the first The output terminals of the logic gate circuit are arranged oppositely and electrically connected through the conductive channel; the conjugate input terminal of the second logic gate circuit is arranged opposite to the conjugate output terminal of the first logic gate circuit and electrically connected through the conductive channel; the second logic gate circuit The output end of the gate circuit is set opposite to the input end of the first logic gate circuit, and is electrically connected through the conductive channel; the conjugate output end of the second logic gate circuit is set opposite to the conjugate input end of the first logic gate circuit, and is connected through the conductive channel. The conductive channels are electrically connected.

That is to say, the above-mentioned first logic gate circuit can be rotated and arranged symmetrically, so that the input terminal of the first logic gate circuit is opposite to the output terminal of the second logic gate circuit, and the conjugate of the second logic gate circuit The input terminal is opposite to the conjugate output terminal of the first logic gate circuit, the output terminal of the second logic gate circuit is set opposite to the input terminal of the first logic gate circuit, and the conjugate output terminal of the second logic gate circuit is connected to the first logic gate circuit. The conjugated input terminals of the circuit are arranged oppositely to realize the vertical interconnection of two logic gate circuits.

In a practicable manner, the first logic gate circuit includes an inverter and a buffer; both the inverter and the buffer have an input terminal, a conjugate input terminal, and an output terminal; in the inverter, the conjugate The input end, output end, and input end are arranged sequentially along the first straight line in the first direction; in the buffer, the input end, output end, and conjugate input end are arranged sequentially along the first straight line in the second direction , the first direction is opposite to the second direction; wherein, one of the output terminal of the inverter and the output terminal of the buffer forms the output terminal of the first logic gate circuit, and the other forms the conjugate output terminal of the first logic gate circuit , so that the output terminal and the conjugate output terminal of the first logic gate circuit are located on the second straight line intersecting the first straight line; the input terminal of the inverter is electrically connected with the input terminal of the buffer to form the first logic gate The input terminal of the circuit; the conjugate input terminal of the inverter is electrically connected with the conjugate input terminal of the buffer to form the conjugate input terminal of the first logic gate circuit, so that the input terminal of the first logic gate circuit and the conjugate The input terminals are arranged on both sides of the second straight line.

In a practicable manner, the inverter includes: a first transistor and a third transistor; a first electrode and a second electrode of the first transistor, and a first electrode and a second electrode of the third transistor along the first The directions are arranged sequentially, and the second electrode of the first transistor and the first electrode of the third transistor share the same first common electrode; the first common electrode forms the output terminal of the first logic gate circuit.

For example, when both the first transistor and the second transistor are N-type transistors, or both are P-type transistors, the inverter formed in this way is a unipolar inverter. In addition, sharing one electrode of the first transistor and the third transistor of the inverter can simplify the process structure of the entire inverter, so that the process structure of each logic gate circuit can be simplified.

In a practicable manner, the buffer includes: a second transistor and a fourth transistor; the first electrode and the second electrode of the second transistor, and the first electrode and the second electrode of the fourth transistor are arranged along the second direction Arranged in sequence, and the second electrode of the second transistor and the first electrode of the fourth transistor share the same second common electrode; the second common electrode forms the conjugate output end of the first logic gate circuit.

Like the transistors in the above-mentioned inverter, all N-type transistors or P-type transistors can be used. Similarly, sharing one electrode with the two transistors of the buffer will correspondingly simplify the process structure of the logic gate circuit.

In a practicable manner, the semiconductor device further includes: a first control gate layer, the first control gate layer is formed between the first transistor and the fourth transistor, and is connected to the gate of the first transistor and the fourth transistor respectively. The gate of the gate is connected to form the conjugate input terminal of the first logic gate circuit; the second control gate layer is formed between the third transistor and the second transistor, and is respectively connected to the gate of the third transistor It is connected with the gate of the second transistor to form the input terminal of the first logic gate circuit.

That is, in the process structure that can be realized, the input terminal and the conjugate input terminal that are arranged symmetrically can be formed by further disposing the first control gate layer and the second control gate layer.

In a possible implementation manner, the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors, or all are P-type transistors.

For example, when both the inverter and the buffer use N-type transistors, the formed logic gate circuit can be called a conjugate N-type logic gate circuit, or, when both the inverter and the buffer use P-type transistors, The formed logic gates may be referred to as conjugate P-type logic gates.

In a practicable manner, the semiconductor device further includes: a first gate transistor and a second gate transistor; the output end of the first logic gate circuit is electrically connected to the first electrode of the first gate transistor, and the first The gating tube and the first logic gate circuit are formed in the first layer structure; the output terminal of the second logic gate circuit is electrically connected to the first electrode of the second gating tube, and the second gating tube and the second logic gate circuit Formed within the second layer structure.

In a manner that can be realized, the semiconductor device is a static random access memory, and the static random access memory also includes: a word line, a conjugated bit line and a bit line, the gate of the first gate and the second gate The gates of the transistors are all electrically connected to the word line; the second electrode of the first gate transistor is electrically connected to the conjugated bit line; the second electrode of the second gate transistor is electrically connected to the bit line.

In this case, the read and write operations of the memory cell are controlled through the word line, the conjugated bit line and the bit line.

In a practicable manner, the conjugated bit line and the bit line are formed in the third layer structure parallel to the substrate, the word line is located in the fourth layer structure parallel to the substrate; the conjugated bit line passes through The conductive channel is electrically connected to the second electrode of the first gating tube; the bit line is electrically connected to the second electrode of the second gating tube through the conductive channel; the grid of the first gating tube and the grid of the second gating tube Electrically connected to the word line through the conductive channel.

That is to say, the signal lines for controlling read and write operations are arranged in other layer structures, so that the space occupied by the layer structure where each logic gate circuit is located can be reduced.

In a practicable manner, the conjugate bit line is formed in the first layer structure; the bit line is formed in the second layer structure; and the word line is formed in the first layer structure or the second layer structure.

In a manner that can be realized, the semiconductor device is a flip-flop, and the flip-flop further includes: a first gate transistor and a second gate transistor, a third gate transistor and a fourth gate transistor; The input end is electrically connected to the first electrode of the first gate transistor, the conjugate input end of the first logic gate circuit is electrically connected to the first electrode of the second gate transistor, and the gate of the first gate transistor and the second selector The gates of the gates are all electrically connected to the clock control signal, and the first gate, the second gate and the first logic gate circuit are formed in the first layer structure; the output end of the second logic gate circuit passes through the third The gating transistor is electrically connected to the input end of the first logic gate circuit, the conjugate output end of the second logic gate circuit is electrically connected to the conjugate input end of the first logic gate circuit through the fourth gating transistor, and the third gating transistor The gate of the gate and the gate of the fourth gate are electrically connected to the anti-clock control signal, and the third gate, the fourth gate and the second logic gate circuit are formed in the second layer structure.

That is, the first gate transistor and the second gate transistor are integrated in the layer structure where the first logic gate circuit is located, and the third gate transistor and the fourth gate transistor are integrated in the layer structure where the second logic gate circuit is located. within the structure.

In a manner that can be realized, the semiconductor device is a ring oscillator, and the ring oscillator further includes: a unipolar third logic gate circuit; the structure of the third logic gate circuit is the same as that of the first logic gate circuit, and The third logic gate circuit is stacked in a third layer structure of the second logic gate circuit away from the first logic gate circuit, and the third layer structure is parallel to the substrate.

In a practicable manner, the first logic gate circuit is manufactured on the substrate by a subsequent process.

By adopting the back-end process, for example, when the first logic gate circuit is applied in the SRAM memory, it can save a lot of area overhead for the front-end processor logic part and improve the integration level of the chip.

In another aspect, the present application also provides an electronic device, including a circuit board and the semiconductor device in any implementation manner of the first aspect above, wherein the semiconductor device is arranged on the circuit board.

In the electronic equipment given in this application, since the semiconductor device in any one of the above-mentioned first aspects is included, and in the semiconductor device, a logic gate circuit with a conjugate input and a conjugate output is included, and the conjugate The conjugated input terminal and the conjugated output terminal of the logic gate circuit are arranged symmetrically, in this way, the integration density of the semiconductor device can be improved.

Description of drawings

Fig. 1 is the circuit diagram of a kind of CMOS inverter in the prior art;

Fig. 2 is a two-dimensional process structure diagram of a CMOS inverter in the prior art;

FIG. 3 is a partial circuit diagram of an electronic device provided in an embodiment of the present application;

FIG. 4 is a circuit diagram of a logic gate circuit provided by an embodiment of the present application;

FIG. 5 is a circuit diagram of a logic gate circuit provided by an embodiment of the present application;

FIG. 6 is a circuit symbol of a logic gate circuit provided by the embodiment of the present application;

FIG. 7 is a circuit diagram of a latch provided in an embodiment of the present application;

FIG. 8 is a two-dimensional process structure diagram of a logic gate circuit provided by an embodiment of the present application;

Fig. 9a is a three-dimensional process structure diagram of a logic gate circuit provided by the embodiment of the present application;

Fig. 9b is a three-dimensional process structure diagram of a logic gate circuit provided by the embodiment of the present application;

FIG. 10 is a process structure diagram of a double-gate transistor provided in an embodiment of the present application;

FIG. 11 is a two-dimensional process structure diagram of a logic gate circuit provided by an embodiment of the present application;

FIG. 12 is a circuit diagram of a storage unit in a SRAM memory provided by an embodiment of the present application;

Fig. 13a is a two-dimensional process structure diagram of a logic gate circuit in the storage unit provided by the embodiment of the present application;

Fig. 13b is a two-dimensional process structure diagram of another logic gate circuit in the memory cell provided by the embodiment of the present application;

Fig. 14 is a three-dimensional process structure diagram of a part of the storage unit provided by the embodiment of the present application;

FIG. 15 is a three-dimensional process structure diagram of a part of the storage unit provided by the embodiment of the present application;

FIG. 16 is a three-dimensional process structure diagram of a part of the storage unit provided by the embodiment of the present application;

Fig. 17a is a two-dimensional process structure diagram of a logic gate circuit and a transistor in the memory cell provided by the embodiment of the present application;

Fig. 17b is a two-dimensional process structure diagram of another logic gate circuit and transistor in the memory cell provided by the embodiment of the present application;

FIG. 18 is a three-dimensional process structure diagram of a storage unit provided in an embodiment of the present application;

FIG. 19 is a two-dimensional process structure diagram of a memory array provided by an embodiment of the present application;

FIG. 20 is a schematic structural diagram of a multi-layer storage array provided by an embodiment of the present application;

FIG. 21 is a schematic structural diagram of a signal line layer in a multilayer memory array provided by an embodiment of the present application;

Fig. 22a is a two-dimensional process structure diagram of a logic gate circuit and a transistor in the memory cell provided by the embodiment of the present application;

Fig. 22b is a two-dimensional process structure diagram of another logic gate circuit and transistor in the memory cell provided by the embodiment of the present application;

FIG. 23 is a three-dimensional process structure diagram of a storage unit provided in an embodiment of the present application;

FIG. 24 is a two-dimensional process structure diagram of a memory array provided by an embodiment of the present application;

FIG. 25 is a three-dimensional structural diagram of an integrated chip provided by an embodiment of the present application;

FIG. 26 is a circuit diagram of a flip-flop provided in an embodiment of the present application;

Fig. 27a is a two-dimensional process structure diagram of a logic gate circuit and a transistor in the flip-flop provided by the embodiment of the present application;

Fig. 27b is a two-dimensional process structure diagram of another logic gate circuit and transistor in the flip-flop provided by the embodiment of the present application;

FIG. 28 is a three-dimensional process structure diagram of the flip-flop provided by the embodiment of the present application;

FIG. 29 is a circuit diagram of a ring oscillator provided by an embodiment of the present application;

Fig. 30a is a two-dimensional process structure diagram of a logic gate circuit in the ring oscillator provided by the embodiment of the present application;

Fig. 30b is a two-dimensional process structure diagram of another logic gate circuit in the ring oscillator provided by the embodiment of the present application;

Fig. 30c is a two-dimensional process structure diagram of another logic gate circuit in the ring oscillator provided by the embodiment of the present application;

Fig. 31 is a three-dimensional process structure diagram of the ring oscillator provided by the embodiment of the present application.

Reference signs:

100 - electronic equipment;

200-CPU;

300 - memory;

400-logic gate circuit;

500 - storage unit;

600 - trigger;

700 - ring oscillator;

800-storage array; 801-first layer storage array; 802-second layer storage array;

900-signal line layer;

1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 1009 - conductive channels;

01-channel;

02 - the first electrode;

03 - the second electrode;

04-the first gate dielectric layer;

05-the second gate dielectric layer;

061-the first grid; 062-the second grid.

Detailed ways

Each of the following embodiments of the present application will be described in detail below with reference to the accompanying drawings in the embodiments of the present application.

The technical solution of the present application can be applied to various electronic devices including integrated circuits. For example, FIG. 3 is a circuit block diagram of an electronic device 100 provided in an embodiment of the present application. Terminal devices, such as mobile phones, tablet computers, and smart bracelets, may also be various types of computing devices such as personal computers (personal computers, PCs), servers, and workstations.

Exemplarily, as shown in FIG. 3 , the electronic device 100 may include a memory 300 , a central processing unit (central processing unit, CPU) 200 and the like. Wherein, the CPU 200 may be electrically connected to the memory 300 through a bus.

In the aforementioned devices such as the CPU 200 and the memory 300, there are integrated circuits including logic gates. Logic gates can include "AND gates", "OR gates", "NOT gates", "NAND gates", "NOR gates", "XOR gates" and so on. These logic gates can also be used in combination to implement more complex logic operations.

The embodiment of the present application provides a logic gate circuit, the logic gate circuit is a unipolar, conjugate logic gate circuit, the conjugate logic gate circuit can be applied to the above-mentioned CPU200, or the memory 300, Or more semiconductor devices.

FIG. 4 is a circuit diagram of a unipolar, conjugate logic gate circuit 400 given in the embodiment of the present application. As shown in FIG. 4, the logic gate circuit 400 not only has an input terminal IN and an output terminal OUT, but also has a conjugate input terminal IN' and a conjugate output terminal OUT'.

It should be explained that: the input terminal IN and the conjugate input terminal IN' involved in this application refer to: the conjugate and anti-phase of the signal transmitted by the input terminal IN and the signal transmitted by the conjugate input terminal IN'. The output terminal OUT and the conjugated output terminal OUT' refer to: the conjugated and inverted phase of the signal transmitted by the output terminal OUT and the signal transmitted by the conjugated output terminal OUT'. For example, the inversion or conjugate signal of a high level "1" is a low level "0".

As shown in FIG. 4 again, all the transistors in the logic gate circuit 400 have the same pole type, and the formed logic gate circuit 400 can be called a unipolar logic gate circuit. For example, in Fig. 4, all transistors are nMOSFET tubes, and the logic gate circuit 400 formed can be called an N-type logic gate circuit; for another example, Fig. 5 provides a circuit diagram of another logic gate circuit 400 of the present application , in this structure, all transistors are pMOSFETs, and the formed logic gate circuit 400 can be called a P-type logic gate circuit.

In combination with the above-mentioned description of the logic gate circuit 400 shown in FIG. 4 and FIG. 5 involved in the present application, it can be seen that, as shown in FIG. 6 , FIG. 6 shows the circuit symbol of the logic gate circuit 400 of the present application, Wherein, the black dotted line represents the signal line conjugated with the black solid line. It can be understood that the logic gate circuit 400 provided in this application is an inverter (Inverter) structure including a conjugate input terminal and a conjugate output terminal as shown in FIG. 6 .

If the logic gate circuit 400 provided by the embodiment of the present application is applied to a more complex circuit, cascade connection can be realized. For example, in some scenarios, the logic gate circuit 400 shown in FIG. 4 can be applied to a latch structure, and FIG. 7 shows a circuit diagram of a latch. In this latch structure, a logic gate circuit 400a and a logic gate circuit 400b formed by the logic gate circuit shown in FIG. The output and conjugate output (OUT and OUT') of logic gate circuit 400b, the input and conjugate input (IN and IN') of logic gate circuit 400b can come from the output and conjugate output (OUT and OUT') of logic gate circuit 400a ), that is, the latch structure is formed by cascading two logic gate circuits.

In addition, the logic gate circuit 400 provided in this application can realize the symmetrical layout of the input terminal IN and the conjugated input terminal IN', the output terminal OUT and the output conjugated terminal OUT' in the process that can be realized, so that If , the connection method of each logic gate circuit can be simplified, and the interconnection method when the logic gate circuit is connected in multiple stages can also be simplified. For example, if the logic gate circuit is applied in a more complex integrated circuit, the area occupied by the integrated circuit can be effectively reduced, the difficulty of designing the integrated circuit can be reduced, and the production cost can also be reduced. The specific process structures that can be realized are as follows.

See Figure 8 and Figure 9a, and Figure 9b, Figure 8 is a two-dimensional process structure diagram of one of the logic gate circuits 400, and Figure 9a and Figure 9b are two of the logic gate circuits 400 that can realize three-dimensional Process structure diagram. Combined with FIG. 8 and FIG. 9a, and FIG. 9b, in the logic gate circuit 400, the input terminal IN and the conjugate input terminal IN' are arranged along the first straight line L1 (for example, parallel to the X direction as shown in the figure) , the output terminal OUT and the output conjugate terminal OUT' are arranged along the second straight line L2 intersecting the first straight line L1 (for example, as shown in the figure parallel to the Y direction), and the input terminal IN and the conjugated input terminal IN' They are arranged on both sides of the second straight line L2, and the output terminal OUT and the output conjugate terminal OUT' are arranged on both sides of the first straight line L1.

In a practicable manner, the first straight line L1 and the second straight line L2 may be perpendicular, or nearly perpendicular.

The input terminal IN and the conjugated input terminal IN' can be arranged symmetrically about the second straight line L2, and the output terminal OUT and the output conjugated terminal OUT' can also be arranged symmetrically about the first straight line L1, so that the input terminal IN and the conjugated input terminal IN', and the output terminal OUT and the output conjugate terminal OUT' are arranged symmetrically about the center.

It can also be understood in this way, the advantages of such design of the input terminal IN and the conjugated input terminal IN', as well as the output terminal OUT and the output conjugated terminal OUT', when the logic gate circuit 400 is set in multiple stages, for example, when two When a logic gate circuit 400 shown in FIG. 8 is electrically connected to form a logic circuit such as a latch or a ring oscillator, only the structure of the logic gate circuit 400 needs to be mirror-symmetrical, rotated, and three-dimensionally stacked, and it can be conducted through conductive Channels enable simple interactive connections. The following will introduce how to perform mirror symmetry and rotation operations in 3D stacking in combination with specific application scenarios.

The logic gate circuit based on this structure can simplify the interconnection of complex circuits including the logic gate circuit, which provides convenience for the process design of the circuit, and also reduces the area occupied by the circuit correspondingly. Further miniaturization as a foreshadowing.

In the process that can be realized, the input terminal IN and the conjugated input terminal IN', as well as the output terminal OUT and the output conjugated terminal OUT' are fabricated in the same layer structure parallel to the substrate 500, so that the The logic gate circuit 400 is three-dimensionally stacked on the substrate 500 in a vertical direction to form a more complex integrated circuit.

As shown in FIG. 8 , the logic gate circuit 400 may include an inverter 401 and a buffer 402 , and the inverter 401 and the buffer 402 are connected in parallel between the first DC voltage terminal and the second DC voltage terminal. For example, the inverter 401 and the buffer 402 are connected in parallel between the power supply voltage VDD and the ground terminal GND.

Wherein, the inverter 401 has an input terminal IN, a conjugate input terminal IN', and an output terminal. Buffer 402 also has an input IN and a conjugate input IN', and an output.

The input terminal of the inverter 401 is coupled to the input terminal of the buffer 402 to form the input terminal IN of the logic gate circuit 400 . The conjugate input terminal of the inverter 401 is coupled to the conjugate input terminal of the buffer 402 to form the conjugate input terminal IN' of the logic gate circuit 400 . One of the output terminal of the inverter 401 and the output terminal of the buffer 402 forms the output terminal OUT of the logic gate circuit 400, and the other forms the output conjugate terminal OUT' of the logic gate circuit.

For example, when the transistors of the inverter 401 and the buffer 402 are all nMOSFETs, the output terminal of the inverter 401 forms the output terminal OUT of the N-type logic gate circuit, and the output terminal of the buffer 402 forms the N-type logic gate circuit OUT. The conjugate output terminal OUT' of the gate circuit. Conversely, when the transistors of the inverter 401 and the buffer 402 are all pMOSFETs, the output terminal of the inverter 401 forms the conjugate output terminal OUT' of the P-type logic gate circuit, and the output terminal of the buffer 402 forms the P-type logic gate circuit. The output terminal OUT of the type logic gate circuit.

Continuing to refer to FIG. 8 and FIG. 9a, and FIG. 9b, in the logic gate circuit 400 provided in the embodiment of the present application, the inverter 401 includes a transistor T1 and a transistor T3, and the buffer 402 includes a transistor T2 and a transistor T4.

In the inverter 401, the transistor T1 and the transistor T3 are connected in series and are electrically connected between the first DC voltage terminal and the second DC voltage terminal; in the buffer 402, the transistor T2 and the transistor T4 are connected in series and are electrically connected to the second DC voltage terminal. between a DC voltage terminal and a second DC voltage terminal.

Realizable circuit structures of the inverter 401 and the buffer 402 include those shown in FIG. 8, FIG. 9a, and FIG. 9b, but are not limited to those shown in FIG. 8, FIG. 9a, and FIG. 9b. For example, transistors can also be added on the basis of FIG. 8, FIG. 9a, and FIG. 9b, and the added transistors can be connected in series with transistor T1 and transistor T3, or in parallel, or a combination of series and parallel. The connection relationship and positional relationship between transistors will be described in detail below by taking the structures of the inverter 401 and the buffer 402 shown in FIG. 8 and FIG. 9a and FIG. 9b as examples.

Referring to FIG. 8 again, in the inverter 401, the first electrode of the transistor T1 is electrically connected to the first DC voltage terminal; the second electrode of the transistor T1 is electrically connected to the first electrode of the transistor T3, that is, the transistor T1 and the transistor T3 are connected in series, And a point at the coupling of the transistor T1 and the transistor T3 forms the output terminal of the inverter 401; the second electrode of the transistor T3 is electrically connected to the second DC voltage terminal.

The gate of the transistor T1 is electrically connected to the conjugate input terminal of the inverter 401 .

The gate of the transistor T3 is electrically connected to the input terminal of the inverter 401 .

That is, in the inverter 401, the first DC voltage terminal, the conjugate input terminal, the output terminal, the input terminal and the second DC voltage terminal are sequentially shown in FIG. 8 along the first straight line L1 in the first direction P1 arranged.

In the buffer 402, the first electrode of the transistor T2 is electrically connected to the first DC voltage terminal; the second electrode of the transistor T2 is electrically connected to the first electrode of the transistor T4, that is, the transistor T2 and the transistor T4 are connected in series, and the transistor T4 and the transistor A point at the coupling of T4 forms the output terminal of the buffer 402; the second electrode of the transistor T4 is electrically connected to the second DC voltage terminal.

The gate of the transistor T4 is electrically connected to the conjugate input terminal of the buffer 402 .

The gate of the transistor T2 is electrically connected to the input terminal of the buffer 402 .

That is, in the buffer 402, the first DC voltage terminal, the conjugate input terminal, the output terminal, the input terminal and the second DC voltage terminal are arranged sequentially in the second direction P2 along the first straight line L1 as shown in FIG. 8 cloth, wherein the second direction P2 is opposite to the first direction P1.

That is to say, the arrangement directions of the plurality of connection terminals of the inverter 401 and the buffer 402 are opposite, so that the corresponding connection terminals of the inverter 401 and the buffer 402 of the logic gate circuit 400 can be The interconnection between them is more simplified, for example, the input end of the inverter 401 is opposite to the input end of the buffer 402, the conjugate input end of the inverter 401 is opposite to the conjugate input end of the buffer 402, Then, when interconnecting, it is easy to realize the electrical connection between the two input terminals, and the interconnection between the two conjugate input terminals, for example, as shown in Figure 8 and Figure 9a, and Figure 9b, The inverter 401 and the buffer 402 are arranged in parallel, and two control gate layers can be formed between the parallel inverter 401 and the buffer 402, and one control gate layer is electrically connected to the input end of the inverter 401 and the The input end of the buffer 402, another control gate layer is electrically connected to the conjugate input end of the inverter 401 and the conjugate input end of the buffer 402, so it is relatively easy to realize the input end of the inverter 401 and the buffer The interconnection of the input terminals of 402 and the interconnection of the conjugate input terminals of the inverter 401 and the conjugate input terminals of the buffer 402 are also easily realized.

In this design, see FIG. 8, the output terminal OUT and the conjugate output terminal OUT' of the logic gate circuit 400 are located on the second straight line L2 intersecting the first straight line L1, and the input terminal IN and the conjugate input terminal of the logic gate circuit 400 The terminal IN' is disposed on both sides of the second straight line L2.

It should be noted that: the first electrode of the transistor referred to in this application refers to one of the source and the drain, and the second electrode of the transistor refers to the other of the source and the drain. For example, in the logic gate circuit 400 formed by nMOSFETs shown in FIG. 8 , the first electrode of the transistor T1 refers to the drain connected to the power supply voltage VDD, and the second electrode is the source. On the contrary, in the logic gate circuit 400 formed by pMOSFET tubes, for pMOSFET tubes, the source electrode is connected to the power supply voltage VDD, and the other electrode is the drain electrode.

In an achievable process, as shown in FIG. 8 and FIG. 9a, and FIG. 9b, the first electrode and the second electrode of the transistor T1, and the first electrode and the second electrode of the transistor T3 are sequentially arranged along the first direction P1. Moreover, the electrode of the transistor T1 coupled and electrically connected with the transistor T3 may share the same electrode layer, that is, in a specific process, a metal wire may be fabricated as an electrode of the transistor T1 and also as an electrode of the transistor T3. In this way, the manufacturing process can be simplified and the area occupied by the entire logic gate circuit can be reduced.

Continuing to refer to FIG. 8 and FIG. 9a, and FIG. 9b, the first electrode and the second electrode of the transistor T2, and the first electrode and the second electrode of the transistor T4 are arranged in sequence along the second direction P2. The electrode of the transistor T2 coupled and electrically connected with the transistor T4 can share the same electrode layer. Similarly, in a specific process, a metal wire can be fabricated as an electrode of the transistor T2 and also as an electrode of the transistor T4. In this way, the manufacturing process can also be simplified and the area occupied by the entire logic gate circuit can be reduced.

Continuing to refer to FIG. 8 and FIG. 9a, and FIG. 9b, the first electrode of the transistor T1 can be used as the conjugate input terminal IN' of the logic gate circuit 400, and the second electrode of the transistor T3 can be used as the input terminal IN of the logic gate circuit 400. or, as shown in FIG. 8, FIG. 9a and FIG. 9b, the gate of the transistor T1 can be connected to the gate of the transistor T4 by using the control gate layer as the conjugate input terminal IN' of the logic gate circuit 400, and then Another control gate layer is used to connect the gate of the transistor T3 to the gate of the transistor T2 to serve as the input terminal IN of the logic gate circuit 400 .

The electrode layer of the transistor T1 shared with the transistor T3 can be used as the output terminal OUT of the logic gate circuit 400, and the electrode layer of the transistor T2 shared with the transistor T4 can be used as the conjugate output terminal OUT' of the logic gate circuit 400. In this way, the center-symmetric arrangement of the input terminal, the conjugate input terminal, the output terminal and the conjugate output terminal of the logic gate circuit 400 is formed.

See Figure 9a and Figure 9b, each transistor shown in Figure 9a and Figure 9b is a single-gate transistor, and the gate of each transistor can be set on the same side as the source and drain as shown in Figure 9a, or , in other realizable structures, as shown in FIG. 9b, the gate is arranged on the other side opposite to the source and drain.

When the gate and the source and drain of the transistor are set on the same side as shown in FIG. The bottom is parallel to the same plane (for example, in the first plane), and the gate of the transistor T1 and the gate of the transistor T3 are also arranged in the first plane, so that, with the gate of the transistor T1 and the gate of the transistor T3 The control gate layer, to which the gates are electrically connected, and the gates of the transistor T1 and the transistor T3 are also in the first plane. In this case, the conjugated output terminal and the conjugated input terminal of the logic gate circuit are both in the first plane, and the logic gate circuit formed in this way can be called the conjugated output terminal, and the conjugated input terminal is in the same position as The substrate is parallel to the same layer structure.

In some other process structures that can be realized, as shown in FIG. 9b, the gate is arranged on the other side opposite to the source and drain, that is to say, in the process structure, the first electrode and the second electrode of the transistor T1 , the first electrode and the second electrode of the transistor T3 are arranged in the same plane parallel to the substrate (for example, in the first plane), and the gates of the transistor T1 and the transistor T3 are arranged in parallel with the substrate In this case, the control gate layer electrically connected to the gate of the transistor T1 and the gate of the transistor T3, and the gate of the transistor T1 and the gate of the transistor T3 are also in the second plane. In this case, the conjugated output terminal of the logic gate circuit is in the first plane, and the conjugated input terminal is in the second plane. The logic gate circuit formed in this way can also be called a conjugated output terminal, a conjugated The input end of the is in the same layer structure parallel to the substrate.

In the logic gate circuit 400 given in this application, the structure of the transistor is not particularly limited. For example, a single-gate transistor or a double-gate transistor can be used. For example, as shown in Figure 8 and Figure 9a, Figure 9b uses a single-gate transistor transistor.

In addition, the gate structure of the transistor can be arranged in different ways, for example, it can be a fin field effect transistor, a ring gate transistor, a vertical structure nanowire field effect transistor, and the like.

FIG. 10 exemplarily shows a process structure diagram of a double-gate transistor. Specifically, as shown in FIG. 10, the double-gate transistor includes a first electrode 02 and a second electrode 03, and a The channel 01 between the second electrodes 03. Moreover, the gate of the double-gate transistor includes a first gate 061 and a second gate 062, the first gate 061 is formed on one side of the channel 01 through the first gate dielectric layer 04, and the second gate 062 is formed through the second The gate dielectric layer 05 is formed on the other side of the channel 01 . The first gate 061 may also be called a top gate (Top Gate), and the second gate 062 is called a bottom gate (Bottom Gate).

When the transistors in the logic gate circuit 400 are double-gate transistors, as shown in FIG. 10 , the first gate 061 and the second gate 062 are connected and connected to the input terminal or the conjugate input terminal. For example, when the transistor T1 adopts a double-gate transistor, then the connected first gate 061 and the second gate 062 form a conjugate input terminal IN'.

In some embodiments, the logic gate circuit 400 of the present application can adjust the threshold voltage (threshold voltage) of the pull-up transistor (transistor T1 and transistor T2) and the pull-down transistor (transistor T3 and transistor T4) to be different, so that the threshold voltage of the pull-up transistor The voltage Vth is less than or equal to 0, and the threshold voltage Vth of the pull-down transistor is greater than 0, so as to realize zero potential loss of the output of the logic gate circuit.

For example, as shown in FIG. 11 , when both the pull-up transistor T1 and the pull-up transistor T2 are double-gate transistors, one gate of the transistor T1 can be coupled and electrically connected to one gate of the transistor T2, and can be connected to the threshold voltage The adjustment port is electrically connected to adjust the threshold voltages of the pull-up transistor T1 and the pull-up transistor T2. FIG. 11 only shows one way to adjust the threshold voltage of the transistor when it is turned on by adjusting the voltage of one of the double gates. Of course, there are other ways to adjust the threshold voltage, for example, by adjusting the transistor channel material, adjusting the gate work function, adjusting the dipole, adjusting the back gate voltage, adjusting the thickness and material of the gate dielectric layer, etc.

Referring to the logic gate circuit 400 shown in FIG. 11 again, when one gate of the transistor T1 is coupled and electrically connected to one gate of the transistor T2, in an achievable process structure, a metal layer can be formed, and the metal layer is respectively connected to the transistor A gate of T1 is electrically connected with a gate of transistor T2, and the metal layer is electrically connected with a threshold voltage adjustment port.

Here, one layer structure of the control gate layer and the metal layer is connected to one gate of the transistor, and the other layer structure is connected to the other gate of the transistor. In specific implementation, the control gate layer and the metal layer can be connected with the substrate The bottom is vertically stacked on both sides of the channel of the transistor to avoid interconnection between the control gate layer and the metal layer. Since FIG. 11 shows a two-dimensional process structure diagram, the metal layer and the control gate layer overlap. In fact, in the three-dimensional structure, the control gate layer and the metal layer are located in different planes.

The above-mentioned logic gate circuit 400 proposed by the embodiment of the present application can be applied in many scenarios, for example, it can be applied in a memory, and it can also be applied in circuit structures such as flip-flops and amplifiers. Some application scenarios including this logic gate circuit are given below, see below for details.

Figure 12 shows a circuit diagram of applying the logic gate circuit involved in the present application in the storage unit of the SRAM memory, in which the storage unit 500 includes a logic gate circuit 400a and a logic gate circuit 400b, and a first gating tube 601 and the second gate tube 602 .

The cascaded logic gate circuit 400a and logic gate circuit 400b form the latch (Latch) structure of the memory cell, and the first electrode of the second gate transistor 602 is electrically connected to the bit line (bit line, BL). The second electrode of the second gate transistor 602 is electrically connected to the output terminal OUT of the logic gate circuit 400b, the first electrode of the first gate transistor 601 is electrically connected to the conjugate bit line BL', and the second electrode of the first gate transistor 601 It is electrically connected with the output terminal OUT of the logic gate circuit 400a, and the bit line BL and the conjugated bit line BL' are used as the input and output terminals of the memory cell. In addition, the gate of the first gate transistor 601 and the second gate transistor 602 The gate of the gate is connected to a word line (word line, WL) to perform switching control of signal reading and writing.

In the process structure of the memory cell in FIG. 12 that can be realized, the cascaded logic gate circuit 400a and the logic gate circuit 400b can be stacked along a direction perpendicular to the substrate. The following describes the stacking method in detail.

The process structure of the logic gate circuit 400a in FIG. 12 can refer to the process structure diagram shown in FIG. 13a. The process structure diagram shown in FIG. 13a is the same as the process structure diagram shown in FIG. repeat. The process structure of the logic gate circuit 400b in FIG. 12 can refer to the process structure diagram shown in FIG. 13b . FIG. 14 shows the process structure diagram of the stacked logic gate circuit 400a and logic gate circuit 400b.

13a and 13b together, in the logic gate circuit 400a, the inverter 401 is arranged along the X direction, and the buffer 402 is also arranged along the X direction, but, in the logic gate circuit 400b, the inverter The buffer 401 is arranged along the Y direction, and the buffer 402 is also arranged along the Y direction. Comparing the logic gate circuit 400b shown in FIG. 13b with the logic gate circuit 400a shown in FIG. 13a, the logic gate circuit 400a shown in FIG. 13a can be rotated 90° clockwise, so that the inverter 401 and the buffer The layout position of 402 is changed to that shown in Fig. 13b.

Further, the logic gate circuit 400b not only needs to be rotated on the basis of the logic gate circuit 400a, but also needs to be mirror-symmetrically reversed. If only the rotation is performed, the first DC voltage terminal (such as the power supply voltage VDD) of the logic gate circuit 400b is vertically opposite to the second DC voltage terminal (such as the ground terminal GND or VSS) of the logic gate circuit 400a. , when cascading two logic gate circuits, the interconnection method is not easy to realize. In order to prevent this phenomenon, combined with Fig. 13a and Fig. 13b, it is also necessary to carry out mirror symmetrical flipping on the basis of the logic gate circuit 400a to obtain Logic gate circuit 400b shown in FIG. 13b.

The specific way of inversion of mirror image symmetry is that the positions of transistor T1 and transistor T3 in the inverter 401 in FIG. The inverter 401 structure shown.

Similarly, the positions of the transistor T2 and the transistor T4 of the buffer 402 shown in FIG. 13a can be swapped, and the positions of the power supply voltage VDD and the ground terminal GND of the buffer 402 can be swapped to obtain the buffer 402 shown in FIG. 13b structure.

When the logic gate circuit 400a and the logic gate circuit 400b are set according to the above-mentioned Figure 13a and Figure 13b, the two logic gate circuits can be stacked in the manner shown in Figure 14, so that the output terminal OUT of the logic gate circuit 400a is The input terminal IN of the AND logic gate circuit 400b is arranged up and down opposite to each other, so that the output terminal OUT of the logic gate circuit 400a and the input terminal of the logic gate circuit 400b can be connected through the conductive channel 1001 penetrating the dielectric layer (not shown in the figure). IN is interconnected. Similarly, the conjugate output terminal OUT' of the logic gate circuit 400a can also be interconnected with the conjugate input terminal IN' of the logic gate circuit 400b through the conductive channel 1002 penetrating the dielectric layer.

Also, in conjunction with FIG. 15 , FIG. 15 shows the interconnection between other partial terminals of the two logic gate circuits. Specifically, the output terminal OUT of the logic gate circuit 400b can be interconnected with the input terminal IN of the logic gate circuit 400a through the conductive channel 1003 penetrating the dielectric layer. Similarly, the conjugate output terminal OUT' of the logic gate circuit 400b can also be connected through The conductive channel 1004 penetrating the dielectric layer is interconnected with the conjugate input terminal IN' of the logic gate circuit 400a.

Fig. 16 shows the interconnection structure of the power supply voltage VDD and the ground terminal GND of the logic gate circuit 400a and the logic gate circuit 400b, that is, the power supply voltage VDD terminal of the logic gate circuit 400a and the power supply voltage VDD terminal of the logic gate circuit 400b are connected through conduction The channel 1005 and the conductive channel 1006 are interconnected, and the ground terminal GND of the logic gate circuit 400 a and the ground terminal GND of the logic gate circuit 400 b are interconnected through the conductive channel 1007 and the conductive channel 1008 .

From the interconnection structures shown in Figure 14, Figure 15 and Figure 16, the three-dimensional stacking of the logic gate circuit 400a and the logic gate circuit 400b can be realized, and when these two logic gate circuits are interconnected, only through the dielectric layer The conductive channel (for example, through silicon via) can be realized, the interconnection method is relatively simple, and it is relatively easy to realize in the process.

The above-mentioned process structure diagram structure of the logic gate circuit 400a and the logic gate circuit 400b shown in FIG. 14, FIG. 15 and FIG. 16, and the stacked interconnection structure between the two logic gate circuits can not only be applied to the above-mentioned SRAM In addition to the storage unit of the memory, it can also be used in other semiconductor devices, such as flip-flops and amplifiers.

Continuing with FIG. 12 , in the memory cell, the first gate transistor 601 is electrically connected to the output terminal OUT of the logic gate circuit 400a, and the second gate transistor 602 is electrically connected to the output terminal OUT of the logic gate circuit 400b. Figure 17a shows one of the process connection structures that can be realized between the first gate transistor 601 and the logic gate circuit 400a, and Figure 17b shows one of the process connection structures that can be realized between the second gate transistor 602 and the logic gate circuit 400b. Process connection structure.

As shown in FIG. 17a and FIG. 17b, the first gate transistor 601 is formed in the same layer structure as the logic gate circuit 400a, and the second gate transistor 602 is formed in the same layer structure as the logic gate circuit 400b. That is, the first gating transistor 601 and the second gating transistor 602, in the same manner as the logic gate circuit 400a and the logic gate circuit 400b, also adopt a stacked layer structure, so that the logic gate circuit 400a and the logic gate circuit 400a can be fully utilized. Each circuit layer of the circuit 400b is located in a layer space so that the first gate transistor 601 and the second gate transistor 602 are respectively interconnected with corresponding logic gate circuits.

Specifically, in the structure shown in FIG. 17a, the first gate transistor 601 is arranged along a direction perpendicular to the transistor T1 or transistor T3, and the second electrode of the first gate transistor 601 is connected to the transistor T1 and transistor T1 through a metal layer. Transistor T3 couples one electrical connection at the junction. In the structure shown in FIG. 17b, the second gate transistor 602 is arranged along a direction parallel to the transistor T1 or the transistor T3, and the second electrode of the first gate transistor 601 is coupled to the transistor T1 and the transistor T3 through a metal layer. A point of electrical connection at a junction.

Figure 18 shows the process structure diagram of the memory cell, as shown in Figure 18, the first gate tube 601 and the second gate tube 602 are set up and down, so that the conductive channel 1009 can be used The gate of the first gate transistor 601 is electrically connected to the gate of the second gate transistor 602 to be electrically connected to the word line WL.

In addition, as shown in FIG. 18, the bit line BL and the conjugated bit line BL' are located in a different layer structure from the logic gate circuit 400a and the logic gate circuit 400b, that is, it can be considered that the logic gate circuit 400a is located in the first layer structure Inside, the logic gate circuit 400b is located in the second layer structure, and the bit line BL and the conjugated bit line BL' are located in the third layer structure parallel to the first layer structure and the second layer structure.

Also, the word line WL can be arranged in another layer structure, for example, the word line WL can be arranged in the fourth layer structure.

That is to say, in the structure shown in FIG. 18, the two logic units are arranged in one layer respectively, and the signal lines (including at least the bit line BL, the conjugated bit line BL' and the word line WL) are arranged in the other two layers. . Such a design can reduce the area occupied by each logic unit layer, ensure the area utilization rate of each logic gate circuit, and improve the integration degree of each logic unit.

In a process that can be realized, the bit line BL located in the third layer structure can be electrically connected to the electrode of the second gate transistor 602 located in the second layer structure through a conductive channel. The conjugated bit line BL' in the third layer structure is electrically connected to the electrode of the first gate transistor 601 in the first layer structure.

FIG. 19 shows a two-dimensional process structure diagram of a one-layer memory array formed after the memory cells shown in FIG. 18 are arrayed. In the memory array 800, as shown in FIG. 19, the extending direction of the bit line BL and the extending direction of the conjugated bit line BL' are parallel, for example, can extend along the X direction parallel to the substrate, however, The extending direction of the word line WL is perpendicular to the extending direction of the bit line BL, for example, it may extend along the Y direction parallel to the substrate.

In combination with FIG. 19 , FIG. 19 also shows a control signal line TG for controlling the threshold voltage of the logic gate circuit, and the extension direction of the control signal line TG is parallel to the extension direction of the word line WL.

The control signal line TG may also be provided in the same layer structure as the word line WL.

In some embodiments, the memory will include at least two layers of memory arrays stacked along the direction perpendicular to the substrate. For example, as shown in FIG. Layer 2 storage array 802 . When each layer of memory arrays is laid out according to the process structure diagram shown in FIG. The signal lines for controlling the reading and writing of the two-layer memory arrays are concentrated in one layer structure, so that the number of metal layers can be reduced, and the integration density of the three-dimensionally integrated memory can be further improved.

FIG. 21 shows one of the structural diagrams of the signal line layer 900, the bit line BL and the conjugated bit line BL' of the first layer memory array 801, and the bit line BL and the conjugated bit line of the second layer memory array 802. BL' is arranged in parallel, for example, can extend along the Y direction parallel to the substrate, and can make the bit line BL and the conjugated bit line BL' spaced apart.

The word lines WL of the first layer memory array 801 and the word lines WL of the second layer memory array 802 are arranged in parallel, for example, may extend along a direction perpendicular to the bit lines.

That is to say, the signal line layer 900 here may include two layers. One of the two layers is arranged with the bit line BL and the conjugate bit line BL' of the first layer memory array 801 and the second layer memory array 802. The word lines WL of the first layer memory array 801 and the second layer memory array 802 are arranged in another layer.

Figure 22a shows another possible process connection structure between the first gate transistor 601 and the logic gate circuit 400a, and Figure 22b shows another possible process connection structure between the second gate transistor 602 and the logic gate circuit 400b. Process connection structure. Compared with the above-mentioned Fig. 17a and Fig. 17b, in Fig. 17a and Fig. 17b, the first gating tube 601 and the second gating tube 602 are arranged up and down oppositely, but in Fig. 22a and Fig. 22b, the first gating tube 601 The first gating tube 601 and the second gating tube 602 are not arranged up and down, but in different orientations. In this way, see Figure 23, which shows the three-dimensional process structure of the memory cell As shown in the figure, the conjugated bit line BL' and the logic gate circuit 400a are located in the first layer, and the bit line BL and the logic gate circuit 400b are located in the second layer. Furthermore, there is no need to set another layer structure for forming signal lines, In this way, the number of layer structures of the entire memory can be reduced.

The word line WL may be provided in the first layer, or, as shown in FIG. 23 , in the first layer.

FIG. 24 shows a structural diagram of a one-layer memory array formed by arranging the memory cells shown in FIG. 23 in an array. In this memory array, as shown in FIG. 24, the extending direction of the bit line BL is perpendicular to the extending direction of the conjugated bit line BL', for example, the conjugated bit line BL' can be parallel to the substrate X direction, and the bit line BL can extend along the Y direction parallel to the substrate, however, the extension direction of the word line WL is parallel to the extension direction of the conjugate bit line BL', for example, can be parallel to the substrate The X-direction extends.

In combination with FIG. 24 , FIG. 24 also shows a control signal line TG for controlling the threshold voltage of the logic gate circuit, and the extension direction of the control signal line TG is parallel to the extension direction of the bit line BL.

For this control signal line TG can be arranged in another layer.

In the memories with two different process structures shown above, the first gate transistor and the first logic gate circuit are arranged in the same layer structure, and the second gate transistor and the second logic gate circuit are arranged in the same layer structure. Of course, in some other achievable process structures, the first gate transistor and the first logic gate circuit can be arranged in different layer structures, and the second gate transistor and the second logic gate circuit can also be arranged in different layer structures. In the layer structure, for example, the first logic gate circuit is arranged in the first layer structure, the second logic gate circuit is arranged in the second layer structure, and the first gate transistor and the second gate transistor are arranged in the third layer structure.

For the above-mentioned storage unit of the SRAM memory, each transistor can be an nMOSFET as shown in FIG. 12 , and in addition, all of them can be a pMOSFET. Then, when the pMOSFET tube is selected, the word line WL can be replaced by the conjugated word line WL', and the bit line BL and the conjugated bit line BL' remain unchanged, but one end of the conjugated word line WL' can be connected to the reverse phase The device is electrically connected, and the other end is electrically connected to the storage unit. With the development of semiconductor technology, the three-dimensional stacking of chips is a trend of process development. In the three-dimensional chip stacking technology, monolithic integration has the advantages of low cost and high interconnection density, and is gradually being widely used. For example, the above-mentioned SRAM memory provided by the present application and the arithmetic logic unit (arithmetic and logic unit, ALU) controlling it can be integrated in one chip. As shown in FIG. 25, the arithmetic logic unit ALU passes through the front end of line (FEOL) process is integrated on the substrate, and the SRAM memory is integrated on the arithmetic logic unit ALU through the back end of line (BEOL) process. The arithmetic logic unit ALU here can generate control signals, and these control signals can be read and write control signals, which are used to control the read and write operations of data in the SRAM memory, thereby realizing the vertical CPU architecture of ALU+SRAM. The CPU of this architecture can shorten the transmission speed of data between the computing unit and the storage unit, improve computing efficiency, and also save more chip area for the front-end process.

Then, since the SRAM memory adopts the back-end BEOL process, the transistors forming the SRAM memory not only need high mobility, but also need to have the characteristics of low-temperature growth. For example, among the available technological means, electronic amorphous oxide semiconductor (amorphous oxide semiconductor, AOS) field effect transistors can be used to fabricate the above logic gate circuit.

FIG. 26 shows another semiconductor device including the above-mentioned logic gate circuit 400a and logic gate circuit 400b. The semiconductor device has a D flip-flop structure. The D flip-flop 600 includes a logic gate circuit 400a, a logic gate circuit 400b, and a gate transistor T1+, a gate transistor T1-, a gate transistor T2+ and a gate transistor T2-.

Wherein, the input terminal IN of the logic gate circuit 400a is connected to the output terminal OUT of the logic gate circuit 400b through the gate transistor T2+, and the conjugate input terminal IN' of the logic gate circuit 400a is connected to the logic gate circuit 400b through the gate transistor T2- The conjugate output terminal OUT' of the gate transistor T2+ is connected, that is, the first electrode of the gate transistor T2+ is connected to the input terminal IN of the logic gate circuit 400a, and the second electrode of the gate transistor T2+ is connected to the output terminal OUT of the logic gate circuit 400b. connection; the first electrode of the gate transistor T2- is connected to the conjugate input terminal IN' in the logic gate circuit 400a, and the second electrode of the gate transistor T2- is connected to the conjugate output terminal OUT' in the logic gate circuit 400b; Moreover, the gates of the gate transistor T2+ and the gate transistor T2− are both electrically connected to the inverse clock signal CLK′.

Also, as shown in Figure 26, the output terminal OUT of the logic gate circuit 400a is connected to the input terminal IN of the logic gate circuit 400b, and the conjugate output terminal OUT' of the logic gate circuit 400a is connected to the conjugate input terminal IN' of the logic gate circuit 400b connect.

Continuing as shown in Figure 26, in the D flip-flop 600, the first electrode of the gate transistor T1+ is connected to the input terminal IN of the logic gate circuit 400a, and the second electrode of the gate transistor T1+ is connected to the input signal D; the gate transistor T1 The first electrode of - is connected to the conjugate input terminal IN' of the logic gate circuit 400a, and the second electrode of the gate transistor T1- is connected to the inverting input signal D'. Both the gate of the gate transistor T1+ and the gate of the gate transistor T1 − are electrically connected to the clock signal CLK.

The output terminal of logic gate circuit 400a is connected with the input terminal of logic gate circuit 400b, and forms the output terminal OUT of this D flip-flop 600, and the conjugate output terminal of logic gate circuit 400a is connected with the conjugate input terminal of logic gate circuit 400b , and forms the conjugate output terminal OUT' of the D flip-flop 600 .

See Figure 27a and Figure 27b, Figure 27a shows one of the process connection structures that can be realized for the logic gate circuit 400a, the gate transistor T1+ and the gate transistor T1-, and Figure 27b shows the logic gate One of the possible process connection structures of the circuit 400b, the gate transistor T2+ and the gate transistor T2-.

Specifically, the logic gate circuit 400b, the gate transistor T2+ and the gate transistor T2- are located in the same layer structure, and the logic gate circuit 400a, the gate transistor T1+ and the gate transistor T1- are located in another same layer structure, for example, as As shown in FIG. 28, FIG. 28 shows a three-dimensional process structure diagram of the above-mentioned D flip-flop 600 in FIG. 26, wherein the logic gate circuit 400a, the gate transistor T1+ and the gate transistor T1- are located in the first layer structure, The logic gate circuit 400b, the gate transistor T2+ and the gate transistor T2- are located in the second layer structure.

In addition, the corresponding connection terminals in the stacked two-layer structure are electrically connected through conductive channels, so as to realize signal intercommunication.

In addition, when the transistors of the above-mentioned D flip-flop 600 all use pMOSFETs, the clock signal CLK and the inverse clock signal CLK' need to be interchanged.

FIG. 29 shows another semiconductor device including the above-mentioned logic gate circuit 400a and logic gate circuit 400b, which is a ring oscillator 700. The ring oscillator 700 includes a logic gate circuit 400c in addition to the logic gate circuit 400a and the logic gate circuit 400b.

Wherein, the output terminal OUT of the logic gate circuit 400a is electrically connected to the input terminal IN of the logic gate circuit 400b, the conjugate output terminal OUT' of the logic gate circuit 400a is electrically connected to the conjugate input terminal IN' of the logic gate circuit 400b, and, The output terminal OUT of the logic gate circuit 400b is electrically connected with the input terminal IN of the logic gate circuit 400c, and the conjugate output terminal OUT' of the logic gate circuit 400b is electrically connected with the conjugate input terminal IN' of the logic gate circuit 400c. In addition, the logic gate circuit The output terminal OUT of the gate circuit 400c is electrically connected to the input terminal IN of the logic gate circuit 400a, and the conjugate output terminal OUT' of the logic gate circuit 400c is electrically connected to the conjugate input terminal IN' of the logic gate circuit 400a to form a ring oscillator .

In the achievable process structure of the above-mentioned ring oscillator 700, as shown in FIG. 30a to FIG. 30c, and as shown in FIG. 31, any logic gate circuit can be set in a layer structure, for example, a logic gate circuit 400a is arranged in the first layer, the logic gate circuit 400b is arranged in the second layer, and the logic gate circuit 400c is arranged in the third layer, that is, three logic gate circuits are arranged in a three-dimensional stack.

Wherein, the process structure of the logic gate circuit 400a at the first layer can be the same as the process structure of the logic gate circuit 400c at the third layer, and the process structure of the logic gate circuit 400b between the first layer and the third layer can be On the basis of the logic gate circuit 400a or the logic gate circuit 400c, it is obtained by performing rotation and symmetrical inversion. The specific structure obtained by the rotation and symmetrical inversion has been explained above and will not be repeated here.

The above-mentioned ring oscillator 700 only shows three logic gate circuits, and in addition, an odd number of logic gate circuits greater than 3 may be included to be cascaded to form a ring oscillator.

Similar to the above-mentioned SRAM memory, similar to the structure of the D flip-flop, it is located between the connection terminals of different layers that need to be electrically connected, and can be electrically connected through a conductive channel perpendicular to the substrate, so that the ring oscillator is three-dimensionally stacked on the substrate. on the bottom.

The above only shows the circuit diagrams of some semiconductor devices including the logic gate circuits involved in the present application, and the corresponding process structure diagrams. In addition, the circuit structure of the logic gate circuit and the corresponding process structure diagram can also be applied in other semiconductor devices, which are not exhaustive here.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (15)

1. A semiconductor device, comprising:

a substrate;

a first logic gate formed on the substrate, the first logic gate being a unipolar logic gate;

wherein the first logic gate circuit has:

an input and a conjugate input, and an output and a conjugate output;

The input end, the conjugate input end, the output end and the conjugate output end are formed in the same layer structure parallel to the substrate;

the input end and the conjugate input end are arranged along a first straight line;

the output end and the conjugate output end are arranged along a second straight line intersecting the first straight line;

and the input end and the conjugate input end are arranged on two sides of the second straight line, and the output end and the conjugate output end are arranged on two sides of the first straight line.

2. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: a second logic gate circuit of a single-pole type, the first logic gate circuit being formed in a first layer structure parallel to the substrate, the second logic gate circuit being formed in a second layer structure parallel to the first layer structure;

the second logic gate circuit has:

an input and a conjugate input, and an output and a conjugate output;

the input end of the second logic gate circuit is opposite to the output end of the first logic gate circuit and is electrically connected with the output end of the first logic gate circuit through a conductive channel;

the conjugate input end of the second logic gate circuit is opposite to the conjugate output end of the first logic gate circuit and is electrically connected with the first logic gate circuit through a conductive channel;

The output end of the second logic gate circuit is opposite to the input end of the first logic gate circuit and is electrically connected with the input end of the first logic gate circuit through a conductive channel;

the conjugate output end of the second logic gate circuit is opposite to the conjugate input end of the first logic gate circuit and is electrically connected with the first logic gate circuit through a conductive channel.

3. The semiconductor device according to claim 1 or 2, wherein the first logic gate circuit includes:

an inverter and a buffer; the inverter and the buffer each have an input and a conjugate input, and an output;

in the inverter, the conjugate input terminal, the output terminal, and the input terminal are sequentially arranged in a first direction along the first straight line;

in the buffer, the input end, the output end and the conjugate input end are sequentially arranged along the first straight line in a second direction, and the first direction is opposite to the second direction;

wherein one of the output terminal of the inverter and the output terminal of the buffer forms an output terminal of the first logic gate circuit, and the other forms a conjugate output terminal of the first logic gate circuit, such that the output terminal and the conjugate output terminal of the first logic gate circuit are located on the second straight line intersecting the first straight line;

The input end of the inverter is electrically connected with the input end of the buffer to form the input end of the first logic gate circuit;

the conjugate input of the inverter is electrically connected with the conjugate input of the buffer to form the conjugate input of the first logic gate, so that the input and the conjugate input of the first logic gate are arranged at two sides of the second straight line.

4. The semiconductor device according to claim 3, wherein,

the inverter includes: a first transistor and a third transistor;

the first electrode and the second electrode of the first transistor and the first electrode and the second electrode of the third transistor are sequentially arranged along the first direction, and the second electrode of the first transistor and the first electrode of the third transistor share the same first common electrode;

the first common electrode forms an output of the first logic gate.

5. The semiconductor device according to claim 4, wherein,

the buffer includes: a second transistor and a fourth transistor;

the first electrode and the second electrode of the second transistor and the first electrode and the second electrode of the fourth transistor are sequentially arranged along the second direction, and the second electrode of the second transistor and the first electrode of the fourth transistor share the same second common electrode;

The second common electrode forms a conjugated output of the first logic gate.

6. The semiconductor device according to claim 5, wherein the semiconductor device further comprises:

a first control gate layer formed between the first transistor and the fourth transistor and connected to the gate of the first transistor and the gate of the fourth transistor, respectively, to form a conjugated input terminal of the first logic gate circuit;

and a second control gate layer formed between the third transistor and the second transistor and connected to the gate of the third transistor and the gate of the second transistor, respectively, to form an input terminal of the first logic gate circuit.

7. A semiconductor device according to claim 5 or 6, wherein,

the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors or all P-type transistors.

8. The semiconductor device according to claim 2, wherein the semiconductor device further comprises:

the first gate tube and the second gate tube;

The output end of the first logic gate circuit is electrically connected with the first electrode of the first gate tube, and the first gate tube and the first logic gate circuit are formed in the first layer structure;

the output end of the second logic gate circuit is electrically connected with the first electrode of the second gate tube, and the second gate tube and the second logic gate circuit are formed in the second layer structure.

9. The semiconductor device according to claim 8, wherein the semiconductor device is a static random access memory, the static random access memory further comprising:

the grid electrode of the first gate tube and the grid electrode of the second gate tube are electrically connected with the word line;

a conjugated bit line, the second electrode of the first gate tube is electrically connected with the conjugated bit line

And the second electrode of the second gate tube is electrically connected with the bit line.

10. The semiconductor device according to claim 9, wherein the conjugated bit line and the bit line are formed in a third layer structure parallel to the substrate, and wherein the word line is formed in a fourth layer structure parallel to the substrate;

the conjugated bit line is electrically connected with the second electrode of the first gate tube through a conductive channel;

The bit line is electrically connected with the second electrode of the second gate tube through a conductive channel;

the word line is electrically connected with the grid electrode of the first gate tube and the grid electrode of the second gate tube through conductive channels.

11. The semiconductor device of claim 9, wherein the semiconductor device comprises a semiconductor substrate,

the conjugate bit line is formed within the first layer structure;

the bit line is formed within the second layer structure;

the word line is formed within the first layer structure or the second layer structure.

12. The semiconductor device according to claim 2, wherein the semiconductor device is a flip-flop, the flip-flop further comprising:

the first gate tube, the second gate tube, the third gate tube and the fourth gate tube;

the input end of the first logic gate circuit is electrically connected with the first electrode of the first gate tube, the conjugated input end of the first logic gate circuit is electrically connected with the first electrode of the second gate tube, the grid electrode of the first gate tube and the grid electrode of the second gate tube are electrically connected with clock control signals, and the first gate tube, the second gate tube and the first logic gate circuit are formed in the first layer structure;

The output end of the second logic gate circuit is electrically connected with the input end of the first logic gate circuit through the third gate tube, the conjugated output end of the second logic gate circuit is electrically connected with the conjugated input end of the first logic gate circuit through the fourth gate tube, the grid electrode of the third gate tube and the grid electrode of the fourth gate tube are electrically connected with inverse clock control signals, and the third gate tube, the fourth gate tube and the second logic gate circuit are formed in the second layer structure.

13. The semiconductor device according to claim 2, wherein the semiconductor device is a ring vibrator, the ring vibrator further comprising: a third logic gate circuit of a single pole type;

the third logic gate circuit has the same structure as the first logic gate circuit, and is stacked in a third layer structure of the second logic gate circuit, which is far away from the first logic gate circuit and is parallel to the substrate.

14. The semiconductor device of any of claims 1-13, wherein the first logic gate circuit is fabricated on the substrate using a subsequent process.

15. An electronic device, comprising:

a circuit board;

a semiconductor device as claimed in any one of claims 1 to 14;

wherein the semiconductor device is disposed on the wiring board.