CN116683905A

CN116683905A - Semiconductor device and electronic apparatus

Info

Publication number: CN116683905A
Application number: CN202210164222.1A
Authority: CN
Inventors: 李骏康; 詹士杰; 吴颖; 许俊豪; 廖恒
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-02-22
Filing date: 2022-02-22
Publication date: 2023-09-01

Abstract

The embodiment of the application provides a semiconductor device and electronic equipment comprising the semiconductor device. Relates to the technical field of logic gate circuit processes. Mainly to provide a logic gate circuit that can simplify the interconnection process. The semiconductor device includes a substrate and a first logic gate circuit formed on the substrate, the first logic gate circuit having: an input and a conjugate input, and an output and a conjugate output; the input end, the conjugate input end, the output end and the conjugate output end are formed in the same layer structure, and the input end and the conjugate input end are arranged along a first straight line; the output ends and the conjugate output ends are arranged along a second straight line intersecting the first straight line, for example, the first straight line is perpendicular to the second straight line; and the input end and the conjugate input end are arranged at two sides of the second straight line, and the output end and the conjugate output end are arranged at two sides of the first straight line. The interconnection process is simplified by a unipolar, conjugated, centrally symmetrical arrangement of structures.

Description

Semiconductor device and electronic apparatus

Technical Field

The present application relates to the field of logic gate technology, and more particularly, to a semiconductor device and an electronic device including the semiconductor device.

Background

An inverter (phase inverter) is a circuit that can invert the phase of an input signal by 180 degrees, and is an important logic unit of an integrated circuit (integrated circuit).

Fig. 1 is a circuit configuration diagram of a conventional complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) inverter, and fig. 2 is a process configuration diagram of the CMOS inverter shown in fig. 1. Referring to fig. 1 and 2 together, a CMOS inverter is shown that includes a hole metal oxide semiconductor field effect transistor (p-type metal oxide semiconductor field effect transistor, pMOSFET) T1 and a hole metal oxide semiconductor field effect transistor (n-type metal oxide semiconductor field effect transistor, nMOSFET) T2.

IN the CMOS inverter structure, as shown IN fig. 1 and 2, the Gate (Gate) of the pull-up transistor T1 and the Gate of the pull-down transistor T2 share one metal line, as the input terminal IN of the CMOS inverter, the Source (Source) of the pull-up transistor T1 and the Drain (Drain) of the pull-down transistor T2 share one metal line, as the output terminal OUT of the CMOS inverter, the Drain (Drain) of the pull-up transistor T1 is connected to the power supply Voltage (VDD), and the Source (Source) of the pull-down transistor T2 is connected to the ground Voltage (VSS) or the Ground (GND). Continuing with the illustration of fig. 2, the channel of pull-up transistor T1 (which may also be referred to as an active region) requires n-type doping, and the channel of pull-down transistor T2 utilizes doping of the substrate (the substrate is not shown in fig. 2).

In the above-described CMOS inverter, in order to obtain better voltage transfer characteristics, the drive currents of the nMOSFET and pMOSFET need to be kept uniform, whereas the drive currents of the nMOSFET and pMOSFET are approximately proportional to carrier mobility and channel width.

Since the electron mobility (μe) and the hole mobility (μp) of most semiconductors are different, in order to achieve current matching, integrated circuit fabrication will set the ratio (Wp/Wn) of the device width (Wp) of pMOSFET to the device width (Wn) of nMOSFET to μe/μp. However, with the continued development of integrated circuit fabrication technology, the miniaturization of conventional Si devices has entered a bottleneck period, and various high performance channel materials have been proposed, where μe/μp is relatively large (e.g., μe/μp >20, or even larger), and therefore, the ratio of Wp to Wn is large, and in a practical process structure, as shown in fig. 2, a large Wp is required to achieve current matching.

In this way, in the CMOS inverter structure, the pMOSFET occupies a larger area, and if the CMOS inverter is applied to a more complex circuit structure, the occupied area of the circuit structure is obviously increased, so that the circuit design difficulty and the manufacturing cost are increased.

Disclosure of Invention

The application provides a semiconductor device and an electronic apparatus having the same. The main object is to provide a unipolar logic gate circuit with conjugate input and conjugate output, and the conjugate input end and the conjugate output end of the logic gate circuit are symmetrically arranged, so that the occupied area of the logic gate circuit can be reduced and the design difficulty of the circuit can be reduced when the logic gate circuit is applied to a complex integrated circuit.

In order to achieve the above purpose, the application adopts the following technical scheme:

in one aspect, the present application provides a semiconductor device that may be an SRAM memory, flip-flop, oscillator, or the like.

The semiconductor device includes a substrate and a first logic gate circuit formed on the substrate, and the first logic gate circuit is a unipolar logic gate circuit. Wherein the first logic gate circuit has: an input and a conjugate input, and an output and a conjugate output; the input terminal, the conjugate input terminal, the output terminal, and the conjugate output terminal are formed in the same layer structure, for example, may be formed in the same layer structure parallel to the substrate; in addition, the input end and the conjugate input end are arranged along a first straight line; the output ends and the conjugate output ends are arranged along a second straight line intersecting the first straight line, for example, the first straight line is perpendicular to the second straight line; and the input end and the conjugate input end are arranged at two sides of the second straight line, and the output end and the conjugate output end are arranged at two sides of the first straight line.

Based on the above description of the circuit configuration of the first logic gate circuit in the semiconductor device, it can be seen that the logic gate circuit is controlled by the conjugated input signal (i.e., includes an input terminal for receiving the inverted signal and a conjugated input terminal), and has a conjugated output, i.e., includes an output terminal capable of outputting the inverted signal and a conjugated output terminal, thereby forming a conjugated input, conjugated output conjugated logic gate circuit.

In addition, since the first logic gate circuit is a unipolar logic gate circuit, that is, in this logic gate circuit, the polar types of all the transistors are the same, for example, all pmosfets may be used, or all nmosfets may be used. In this way, the phenomenon that the channel width (Wp) of the pMOSFET and the channel width (Wn) of the nMOSFET are relatively large because of the better voltage transmission characteristic required in the conventional CMOS inverter, and one of the channels occupies a large area, is not caused.

In addition, since the logic gate circuit is a conjugate input and a conjugate output, for example, in some more complex logic gate circuits, the logic gate circuits can be cascaded, that is, the conjugate output of the first stage logic gate circuit can be used as the conjugate input of the second stage logic gate circuit to form a complex circuit.

The input end and the conjugate input end of the logic gate circuit are arranged on two sides of the second straight line, and the output end and the conjugate output end are arranged on two sides of the first straight line. That is, the input and conjugate inputs, and the output and conjugate outputs may be centrosymmetric. When the logic gate circuit is arranged in multiple stages, for example, when the two logic gate circuits are required to be connected to form a logic circuit such as a latch or a ring oscillator, simple vertical interconnection can be realized by symmetrically rotating and three-dimensionally stacking the logic gate circuit structure. The cascade connection of the conjugate input and output of the two logic gates can be realized through vertical through hole connection. Therefore, the design difficulty of the whole integrated circuit is obviously reduced, the occupied area is reduced, and the integration level of the integrated circuit is improved.

In one implementation, the semiconductor device further includes: a second logic gate circuit of a single-pole type, the first logic gate circuit being formed in a first layer structure parallel to the substrate, the second logic gate circuit being formed in a second layer structure parallel to the first layer structure; the second logic gate circuit has: an input and a conjugate input, and an output and a conjugate output; the input end of the second logic gate circuit is opposite to the output end of the first logic gate circuit and is electrically connected with the first logic gate circuit through a conductive channel; the conjugate input end of the second logic gate circuit is opposite to the conjugate output end of the first logic gate circuit and is electrically connected with the first logic gate circuit through a conductive channel; the output end of the second logic gate circuit is opposite to the input end of the first logic gate circuit and is electrically connected with the input end of the first logic gate circuit through a conductive channel; the conjugate output end of the second logic gate circuit is opposite to the conjugate input end of the first logic gate circuit and is electrically connected through a conductive channel.

That is, the first logic gate circuit may be rotated, and after being symmetrically arranged, the input end of the first logic gate circuit is opposite to the output end of the second logic gate circuit, the conjugated input end of the second logic gate circuit is opposite to the conjugated output end of the first logic gate circuit, the output end of the second logic gate circuit is opposite to the input end of the first logic gate circuit, and the conjugated output end of the second logic gate circuit is opposite to the conjugated input end of the first logic gate circuit, so as to implement vertical interconnection of the two logic gate circuits.

In one implementation, a first logic gate circuit includes an inverter and a buffer; the inverter and the buffer are provided with an input end, a conjugate input end and an output end; in the inverter, a conjugate input end, an output end and an input end are sequentially arranged along a first straight line in a first direction; in the buffer, the input end, the output end and the conjugate input end are sequentially arranged along a first straight line in a second direction, and the first direction is opposite to the second direction; one of the output end of the inverter and the output end of the buffer forms an output end of the first logic gate circuit, and the other forms a conjugate output end of the first logic gate circuit, so that the output end of the first logic gate circuit and the conjugate output end are positioned on a second straight line intersecting the first straight line; the input end of the inverter is electrically connected with the input end of the buffer to form the input end of the first logic gate circuit; the conjugate input of the inverter is electrically connected to the conjugate input of the buffer to form a conjugate input of the first logic gate, such that the input of the first logic gate and the conjugate input are disposed on both sides of the second line.

In one implementation, an inverter includes: a first transistor and a third transistor; the first electrode and the second electrode of the first transistor are sequentially arranged along the first direction, and the second electrode of the first transistor and the first electrode of the third transistor share the same first common electrode; the first common electrode forms an output of the first logic gate.

For example, when the first transistor and the second transistor are both N-type transistors or both P-type transistors, the inverter thus formed is a unipolar inverter. In addition, by sharing one of the electrodes of the first transistor and the third transistor of the inverter, the process structure of the entire inverter can be simplified, so that the process structure of each logic gate circuit is simplified.

In one implementation, a buffer includes: a second transistor and a fourth transistor; the first electrode and the second electrode of the second transistor are sequentially arranged along the second direction, and the second electrode of the second transistor and the first electrode of the fourth transistor share the same second common electrode; the second common electrode forms a conjugated output of the first logic gate.

As with the transistors in the inverter described above, N-type transistors may be used for all, or P-type transistors may be used for all. Similarly, sharing one electrode for both transistors of the buffer correspondingly simplifies the process structure of the logic gate.

In one implementation, the semiconductor device further includes: a first control gate layer formed between the first transistor and the fourth transistor and connected to the gate of the first transistor and the gate of the fourth transistor, respectively, to form a conjugated input terminal of the first logic gate circuit; and a second control gate layer formed between the third transistor and the second transistor and connected to the gate of the third transistor and the gate of the second transistor, respectively, to form an input terminal of the first logic gate circuit.

That is, in the process structure that can be implemented, the first control gate layer and the second control gate layer may be further disposed to form symmetrically disposed input terminals and conjugate input terminals.

In one implementation, the first transistor, the second transistor, the third transistor, and the fourth transistor are all N-type transistors, or are all P-type transistors.

For example, when both the inverter and the buffer use N-type transistors, the formed logic gate may be referred to as a conjugated N-type logic gate, or when both the inverter and the buffer use P-type transistors, the formed logic gate may be referred to as a conjugated P-type logic gate.

In one implementation, the semiconductor device further includes: the first gate tube and the second gate tube; the output end of the first logic gate circuit is electrically connected with the first electrode of the first gate tube, and the first gate tube and the first logic gate circuit are formed in the first layer structure; the output end of the second logic gate circuit is electrically connected with the first electrode of the second gate tube, and the second gate tube and the second logic gate circuit are formed in the second layer structure.

In one implementation, the semiconductor device is a static random access memory, the static random access memory further comprising: the gate of the first gate tube and the gate of the second gate tube are electrically connected with the word line; the second electrode of the first gate tube is electrically connected with the conjugated bit line; the second electrode of the second gate tube is electrically connected with the bit line.

In this way, the read and write operations of the memory cell are controlled by the word line, the conjugated bit line and the bit line.

In one implementation, the conjugated bit lines and bit lines are formed in a third layer structure parallel to the substrate, and the word lines are located in a fourth layer structure parallel to the substrate; the conjugated bit line is electrically connected with the second electrode of the first gate tube through the conductive channel; the bit line is electrically connected with a second electrode of the second gate tube through the conductive channel; the grid electrode of the first gate tube and the grid electrode of the second gate tube are electrically connected with the word line through the conductive channel.

That is, the signal lines for controlling the read/write operations are disposed in other layers, so that the space occupied by the layer structure of each logic gate circuit can be reduced.

In one implementation, the conjugated bit line is formed within the first layer structure; the bit line is formed within the second layer structure; the word line is formed within either the first layer structure or the second layer structure.

In one implementation, the semiconductor device is a flip-flop, the flip-flop further comprising: the first gate tube, the second gate tube, the third gate tube and the fourth gate tube; the input end of the first logic gate circuit is electrically connected with the first electrode of the first gate tube, the conjugated input end of the first logic gate circuit is electrically connected with the first electrode of the second gate tube, the grid electrode of the first gate tube and the grid electrode of the second gate tube are electrically connected with clock control signals, and the first gate tube, the second gate tube and the first logic gate circuit are formed in the first layer structure; the output end of the second logic gate circuit is electrically connected with the input end of the first logic gate circuit through a third gate tube, the conjugated output end of the second logic gate circuit is electrically connected with the conjugated input end of the first logic gate circuit through a fourth gate tube, the grid electrode of the third gate tube and the grid electrode of the fourth gate tube are electrically connected with inverse clock control signals, and the third gate tube, the fourth gate tube and the second logic gate circuit are formed in a second layer structure.

That is, the first gate tube and the second gate tube are integrated in a layer structure where the first logic gate circuit is located, and the third gate tube and the fourth gate tube are integrated in a layer structure where the second logic gate circuit is located.

In one implementation, the semiconductor device is a ring vibrator, the ring vibrator further comprising: a third logic gate circuit of a single pole type; the third logic gate circuit has the same structure as the first logic gate circuit, and is stacked in a third layer structure of the second logic gate circuit, which is far away from the first logic gate circuit, and is parallel to the substrate.

In one implementation, the first logic gate is fabricated on the substrate using a post-process.

By adopting the subsequent process, for example, when the first logic gate circuit is applied in the SRAM memory, a large amount of area overhead can be saved for the logic part of the processor of the previous process, and the integration level of the chip is improved.

In another aspect, the present application further provides an electronic device, including a circuit board and the semiconductor device in any implementation manner of the first aspect, where the semiconductor device is disposed on the circuit board.

In the electronic device provided by the application, the semiconductor device in any one of the embodiments of the first aspect is included, and the logic gate circuit of the conjugate input and the conjugate output is included in the semiconductor device, and the conjugated input end and the conjugated output end of the conjugated logic gate circuit are symmetrically arranged, so that the integration density of the semiconductor device can be improved.

Drawings

FIG. 1 is a circuit diagram of a CMOS inverter according to the prior art;

FIG. 2 is a two-dimensional process block diagram of a CMOS inverter according to the prior art;

fig. 3 is a partial circuit diagram of an electronic device according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a logic gate circuit according to an embodiment of the present application;

FIG. 5 is a circuit diagram of a logic gate circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a logic gate according to an embodiment of the present application;

FIG. 7 is a circuit diagram of a latch according to an embodiment of the present application;

FIG. 8 is a two-dimensional process block diagram of a logic gate circuit according to an embodiment of the present application;

FIG. 9a is a schematic diagram of a three-dimensional process of a logic gate according to an embodiment of the present application;

FIG. 9b is a schematic diagram of a three-dimensional process of a logic gate according to an embodiment of the present application;

fig. 10 is a process structure diagram of a dual gate transistor according to an embodiment of the present application;

FIG. 11 is a two-dimensional process block diagram of a logic gate circuit according to an embodiment of the present application;

FIG. 12 is a circuit diagram of a memory cell in an SRAM memory according to an embodiment of the present application;

FIG. 13a is a two-dimensional process block diagram of a logic gate circuit in a memory cell according to an embodiment of the present application;

FIG. 13b is a two-dimensional process block diagram of another logic gate circuit in a memory cell according to an embodiment of the present application;

FIG. 14 is a three-dimensional process architecture diagram of a portion of a memory cell provided in an embodiment of the present application;

FIG. 15 is a three-dimensional process architecture diagram of a portion of a memory cell provided in an embodiment of the present application;

FIG. 16 is a three-dimensional process architecture diagram of a portion of a memory cell provided in an embodiment of the present application;

FIG. 17a is a schematic diagram of a two-dimensional process of a logic gate and a transistor in a memory cell according to an embodiment of the present application;

FIG. 17b is a schematic diagram illustrating another logic gate and transistor in a memory cell according to an embodiment of the present application;

FIG. 18 is a three-dimensional process architecture diagram of a memory cell provided by an embodiment of the present application;

FIG. 19 is a two-dimensional process architecture diagram of a memory array according to an embodiment of the present application;

FIG. 20 is a schematic diagram of a multi-layer memory array according to an embodiment of the present application;

FIG. 21 is a schematic diagram of a signal line layer in a multi-layer memory array according to an embodiment of the present application;

FIG. 22a is a schematic diagram illustrating a two-dimensional process of a logic gate and a transistor in a memory cell according to an embodiment of the present application;

FIG. 22b is a schematic diagram illustrating another logic gate and transistor in a memory cell according to an embodiment of the present application;

FIG. 23 is a three-dimensional process architecture diagram of a memory cell according to an embodiment of the present application;

FIG. 24 is a two-dimensional process architecture diagram of a memory array provided by an embodiment of the present application;

FIG. 25 is a three-dimensional block diagram of an integrated chip according to an embodiment of the present application;

FIG. 26 is a circuit diagram of a flip-flop according to an embodiment of the present application;

FIG. 27a is a schematic diagram of a two-dimensional process of a logic gate and a transistor in a flip-flop according to an embodiment of the present application;

FIG. 27b is a schematic diagram illustrating another exemplary two-dimensional process of logic gates and transistors in a flip-flop according to an embodiment of the present application;

FIG. 28 is a three-dimensional process architecture diagram of a trigger provided by an embodiment of the present application;

FIG. 29 is a circuit diagram of a ring oscillator according to an embodiment of the present application;

FIG. 30a is a two-dimensional process block diagram of a logic gate circuit in a ring oscillator according to an embodiment of the present application;

FIG. 30b is a two-dimensional process block diagram of yet another logic gate circuit in a ring oscillator provided by an embodiment of the present application;

FIG. 30c is a two-dimensional process block diagram of yet another logic gate circuit in a ring oscillator provided in accordance with an embodiment of the present application;

fig. 31 is a three-dimensional process structure diagram of a ring oscillator according to an embodiment of the present application.

Reference numerals:

100-an electronic device;

200-CPU；

300-memory;

400-logic gates;

500-a memory cell;

600-flip-flops;

700-ring oscillator;

800-a memory array; 801-a first tier storage array; 802-a second tier storage array;

900-signal line layer;

1001. 1002, 1003, 1004, 1005, 1006, 1007, 1008, 1009-conductive path;

01-channel;

02-a first electrode;

03-a second electrode;

04-a first gate dielectric layer;

05-a second gate dielectric layer;

061-a first gate; 062-a second gate.

Detailed Description

The following embodiments of the present application will be described in detail with reference to the accompanying drawings.

The technical solution of the present application may be applied to various electronic devices including an integrated circuit (integrated circuit), for example, fig. 3 is a circuit block diagram of an electronic device 100 provided in an embodiment of the present application, where the electronic device 100 may be a terminal device, for example, a mobile phone, a tablet computer, a smart bracelet, or may be various types of computing devices such as a personal computer (personal computer, PC), a server, a workstation, etc.

By way of example, as also shown in fig. 3, the electronic device 100 may include a memory 300 and a central processing unit (central processing unit, CPU) 200, etc. Wherein the CPU200 may be electrically connected to the memory 300 through a bus.

In the above devices such as CPU200, memory 300, etc., there are integrated circuits that contain logic gates (logic gates). Logic gates may include "and gates," "or gates," "not gates," "nand gates," "nor gates," "exclusive or gates," and the like. These logic gates may also be used in combination to implement more complex logic operations.

The embodiment of the present application provides a logic gate circuit, which is a unipolar conjugated logic gate circuit, and the conjugated logic gate circuit may be applied to the CPU200, the memory 300, or more semiconductor devices.

Fig. 4 is a circuit diagram of a unipolar, conjugated logic gate 400 in accordance with an embodiment of the present application. As shown IN fig. 4, IN the logic gate circuit 400, there are not only an input terminal IN and an output terminal OUT but also a conjugate input terminal IN 'and a conjugate output terminal OUT'.

It should be explained that: the input terminal IN and the conjugate input terminal IN' to which the present application relates refer to: the signal transmitted at input IN is conjugated, inverted, to the signal transmitted at conjugated input IN'. The output terminal OUT and the conjugate output terminal OUT' refer to: the signal transmitted by the output terminal OUT is conjugated, inverted, with respect to the signal transmitted by the conjugated output terminal OUT'. For example, the inverted or conjugated signal of a high level "1" is a low level "0".

As also shown in fig. 4, the polarities of all the transistors in the logic gate 400 are identical, and the logic gate 400 may be referred to as a unipolar logic gate. For example, in fig. 4, all transistors are nMOSFET transistors, and the formed logic gate 400 may be referred to as an N-type logic gate; for another example, fig. 5 shows a circuit diagram of another logic gate 400 of the present application, in which all transistors are pMOSFET transistors, such a logic gate 400 being formed and may be referred to as a P-type logic gate.

In connection with the description of the logic gate circuit 400 shown in fig. 4 and 5 related to the present application described above, it can be seen that, as shown in fig. 6, fig. 6 shows a circuit symbol of the logic gate circuit 400 of the present application, wherein a black dotted line represents a signal line conjugated with a black solid line. It will be appreciated that the logic gate 400 of the present application is shown in fig. 6 as an Inverter (Inverter) structure comprising a conjugated input and a conjugated output.

If the logic gate circuit 400 provided in the embodiment of the present application is applied to a more complex circuit, cascading can be implemented. For example, in some scenarios, the logic gate 400 shown in FIG. 4 may be employed in a latch structure, as shown in FIG. 7, which is a circuit diagram of a latch. IN the latch structure, a logic gate 400a and a logic gate 400b formed of the logic gate shown IN fig. 4 are included, wherein the input and the conjugate input (IN and IN ') of the logic gate 400a may be from the output and the conjugate output (OUT and OUT') of the logic gate 400b, and the input and the conjugate input (IN and IN ') of the logic gate 400b may be from the output and the conjugate output (OUT and OUT') of the logic gate 400a, that is, the latch structure is formed by a cascade of two logic gates.

IN addition, IN the preparation process of the logic gate circuit 400, the input terminal IN and the conjugate input terminal IN ', and the output terminal OUT and the output conjugate terminal OUT' can be symmetrically arranged, so that the connection mode of each logic gate circuit can be simplified, and the interconnection mode of the logic gate circuits IN multi-stage connection can be simplified. For example, if the logic gate circuit is applied to a more complex integrated circuit, the area occupied by the integrated circuit can be effectively reduced, the design difficulty of the integrated circuit can be reduced, and the production cost can be reduced. Specific process structures that may be achieved are described below.

Referring to fig. 8 and 9a, and fig. 9b, fig. 8 is a two-dimensional process structure diagram of one of the logic gates 400, and fig. 9a and 9b are three-dimensional process structure diagrams of two of the logic gates 400. IN this logic gate 400, IN conjunction with fig. 8 and 9a, and fig. 9b, the input terminal IN and the conjugate input terminal IN 'are arranged along a first straight line L1 (e.g., parallel to the X direction as shown IN the drawing), the output terminal OUT and the output conjugate terminal OUT' are arranged along a second straight line L2 intersecting the first straight line L1 (e.g., parallel to the Y direction as shown IN the drawing), and the input terminal IN and the conjugate input terminal IN 'are disposed on both sides of the second straight line L2, and the output terminal OUT and the output conjugate terminal OUT' are disposed on both sides of the first straight line L1.

In an implementation, the first line L1 may be perpendicular, or nearly perpendicular, to the second line L2.

The input terminal IN and the conjugate input terminal IN 'may be symmetrically disposed about the second straight line L2, and the output terminal OUT and the output conjugate terminal OUT' may be symmetrically disposed about the first straight line L1 such that the input terminal IN and the conjugate input terminal IN 'and the output terminal OUT and the output conjugate terminal OUT' are arranged IN a central symmetry.

It will be appreciated that the advantages of such a design of the input terminal IN and the conjugate input terminal IN ', and the output terminal OUT and the output conjugate terminal OUT' are that when the logic gate circuit 400 is arranged IN multiple stages, for example, when two logic gate circuits 400 shown IN fig. 8 need to be electrically connected to form a logic circuit such as a latch or a ring oscillator, only the structure of the logic gate circuit 400 needs to be mirror-symmetrical, rotated, and three-dimensionally stacked, and simple interconnection can be achieved through conductive paths. The following description will be made in connection with a specific application scenario of how mirror symmetry and rotation operations are performed in three-dimensional stacking.

Based on the logic gate circuit with the structure, the interconnection mode of the complex circuit comprising the logic gate circuit can be simplified, the convenience is provided for the process design of the circuit, the occupied area of the circuit can be correspondingly reduced, and the integrated circuit is further miniaturized to be laid.

IN a process that can be implemented, the input terminal IN and the conjugate input terminal IN ', and the output terminal OUT and the output conjugate terminal OUT' are fabricated IN the same layer structure parallel to the substrate 500, so that the logic gate circuit 400 can be three-dimensionally stacked IN a direction perpendicular to the substrate 500 to form a more complex integrated circuit.

Continuing to refer to fig. 8, the logic gate 400 may include an inverter 401 and a buffer 402, and the inverter 401 and the buffer 402 are connected in parallel between the first dc voltage terminal and the second dc voltage terminal. For example, the inverter 401 and the buffer 402 are connected in parallel between the power supply voltage VDD and the ground GND.

The inverter 401 has an input terminal IN and a conjugate input terminal IN', and an output terminal. Buffer 402 also has an input IN and a conjugate input IN', and an output.

An input of the inverter 401 is coupled to an input of the buffer 402, forming an input IN of the logic gate 400. The conjugate input of inverter 401 is coupled to the conjugate input of buffer 402 to form the conjugate input IN' of logic gate 400. One of the output terminals of the inverter 401 and the output terminal of the buffer 402 forms the output terminal OUT of the logic gate 400, and the other forms the output coupling terminal OUT' of the logic gate.

For example, when the transistors of the inverter 401 and the buffer 402 are all nMOSFET transistors, the output terminal of the inverter 401 forms the output terminal OUT of the N-type logic gate circuit, and the output terminal of the buffer 402 forms the conjugated output terminal OUT' of the N-type logic gate circuit. In contrast, when the transistors of the inverter 401 and the buffer 402 are all pMOSFET transistors, the output terminal of the inverter 401 forms the conjugated output terminal OUT' of the P-type logic gate circuit, and the output terminal of the buffer 402 forms the output terminal OUT of the P-type logic gate circuit.

With continued reference to fig. 8 and 9a, and fig. 9b, in the logic gate 400 according to the embodiment of the present application, the inverter 401 includes a transistor T1 and a transistor T3, and the buffer 402 includes a transistor T2 and a transistor T4.

In the inverter 401, the transistor T1 and the transistor T3 are connected in series and electrically connected between the first dc voltage terminal and the second dc voltage terminal; in the buffer 402, the transistor T2 and the transistor T4 are connected in series and electrically connected between the first dc voltage terminal and the second dc voltage terminal.

The circuit configuration that can be implemented by the inverter 401 and the buffer 402 includes those shown in fig. 8 and 9a and fig. 9b, but is not limited to those shown in fig. 8 and 9a and fig. 9 b. For example, it is also possible to add transistors on the basis of fig. 8 and 9a, and 9b, and the added transistors may be connected in series with the transistors T1 and T3, or in parallel, or a combination of series and parallel. The connection relationship and the positional relationship between the transistors will be specifically described below taking the structures of the inverter 401 and the buffer 402 shown in fig. 8 and 9a, and fig. 9b as examples.

Referring again to fig. 8, in inverter 401, a first electrode of transistor T1 is electrically connected to a first dc voltage terminal; the second electrode of the transistor T1 is electrically connected to the first electrode of the transistor T3, i.e. the transistor T1 and the transistor T3 are connected in series, and an output terminal of the inverter 401 is formed at a point at the coupling of the transistor T1 and the transistor T3; a second electrode of the transistor T3 is electrically connected to the second dc voltage terminal.

The gate of transistor T1 is electrically connected to the conjugated input of inverter 401.

The gate of transistor T3 is electrically connected to the input of inverter 401.

That is, in the inverter 401, the first direct-current voltage terminal, the conjugate input terminal, the output terminal, the input terminal, and the second direct-current voltage terminal are sequentially arranged in the first direction P1 along the first straight line L1 as shown in fig. 8.

In the buffer 402, a first electrode of the transistor T2 is electrically connected to a first direct voltage terminal; the second electrode of the transistor T2 is electrically connected to the first electrode of the transistor T4, i.e. the transistor T2 and the transistor T4 are connected in series, and the output of the buffer 402 is formed at a point at the coupling of the transistor T4 and the transistor T4; a second electrode of the transistor T4 is electrically connected to the second dc voltage terminal.

The gate of transistor T4 is electrically connected to the conjugate input of buffer 402.

The gate of transistor T2 is electrically connected to the input of buffer 402.

That is, in the buffer 402, the first direct voltage terminal, the conjugate input terminal, the output terminal, the input terminal, and the second direct voltage terminal are sequentially arranged in the second direction P2 along the first straight line L1 as shown in fig. 8, wherein the second direction P2 is opposite to the first direction P1.

That is, the arrangement directions of the plurality of connection terminals of the inverter 401 and the buffer 402 are opposite, so that the interconnection manner between the corresponding connection terminals of the inverter 401 and the buffer 402 of the logic gate circuit 400 is simplified, for example, the input terminal of the inverter 401 is opposite to the input terminal of the buffer 402, the conjugated input terminal of the inverter 401 is opposite to the conjugated input terminal of the buffer 402, and thus, when interconnection is performed, electrical connection between the two input terminals and interconnection between the two conjugated input terminals are easy to implement, as shown in fig. 8 and 9a, and as shown in fig. 9b, the inverter 401 and the buffer 402 are arranged in parallel, two control gate layers can be formed between the parallel inverter 401 and the buffer 402, one control gate layer is electrically connected to the input terminal of the inverter 401 and the input terminal of the buffer 402, and the other control gate layer is electrically connected to the conjugated input terminal of the inverter 401 and the conjugated input terminal of the buffer 402, so that interconnection between the input terminal of the inverter 401 and the conjugated input terminal of the buffer 402 is easy to implement.

So designed, referring to fig. 8, the output terminal OUT and the conjugate output terminal OUT 'of the logic gate circuit 400 are located on the second straight line L2 intersecting the first straight line L1, and the input terminal IN and the conjugate input terminal IN' of the logic gate circuit 400 are disposed at both sides of the second straight line L2.

It should be noted that: the first electrode of the transistor according to the present application refers to one of a source and a drain, and the second electrode of the transistor refers to the other of the source and the drain. For example, in the logic gate circuit 400 formed of nMOSFET transistors shown in fig. 8, the first electrode of the transistor T1 refers to the drain connected to the power supply voltage VDD, and the second electrode is the source. In contrast, in the logic gate circuit 400 formed of pMOSFET transistors, the source is connected to the power supply voltage VDD, and the other electrode is the drain.

In the process that can be implemented, as shown in fig. 8 and 9a, and fig. 9b, the first and second electrodes of the transistor T1, and the first and second electrodes of the transistor T3 are sequentially arranged along the first direction P1. In addition, the electrode of the transistor T1 electrically coupled to the transistor T3 may share the same electrode layer, that is, in a specific process, one metal trace may be fabricated as one electrode of the transistor T1 and also as one electrode of the transistor T3. In this way, the manufacturing process can be simplified, and the area occupied by the whole logic gate circuit can be reduced.

With continued reference to fig. 8 and 9a, and fig. 9b, the first and second electrodes of the transistor T2, and the first and second electrodes of the transistor T4 are arranged in sequence along the second direction P2. The electrodes of the transistor T2 that are electrically coupled to the transistor T4 may share the same electrode layer, and similarly, in a specific process, a metal trace may be fabricated as one electrode of the transistor T2 and also as one electrode of the transistor T4. In this way, the manufacturing process can be simplified, and the area occupied by the whole logic gate circuit can be reduced.

With continued reference to fig. 8 and 9a, and fig. 9b, the first electrode of transistor T1 may be the conjugated input IN' of the logic gate 400 and the second electrode of transistor T3 may be the input IN of the logic gate 400; alternatively, as shown IN fig. 8, 9a and 9b, the gate of the transistor T1 and the gate of the transistor T4 may be connected by using a control gate layer as the conjugated input terminal IN' of the logic gate circuit 400, and the gate of the transistor T3 and the gate of the transistor T2 may be connected by using another control gate layer as the input terminal IN of the logic gate circuit 400.

The electrode layer of the transistor T1, which is common to the transistor T3, may serve as the output OUT of the logic gate 400, and the electrode layer of the transistor T2, which is common to the transistor T4, may serve as the conjugated output OUT' of the logic gate 400. In this way, a centrally symmetric arrangement of the input, conjugate input, output and conjugate output of the logic gate 400 is formed.

As shown in fig. 9a and 9b, each of the transistors shown in fig. 9a and 9b is a single gate transistor, and the gate of each transistor may be disposed on the same side as the source and drain as shown in fig. 9a, or in other possible structures, the gate may be disposed on the other side opposite the source and drain as shown in fig. 9 b.

When the gate and the source/drain of the transistor are disposed on the same side as shown in fig. 9a, it is also understood that the first electrode and the second electrode of the transistor T1, the first electrode and the second electrode of the transistor T3 are disposed in the same plane parallel to the substrate (for example, in the first plane), and the gate of the transistor T1 and the gate of the transistor T3 are also disposed in the first plane, so that the control gate layer electrically connected to the gate of the transistor T1 and the gate of the transistor T3, and the gate of the transistor T1 and the gate of the transistor T3 are also in the first plane. In this way, the conjugated output and the conjugated input of the logic gate are both in the first plane, and the logic gate thus formed may be referred to as the conjugated output and the conjugated input are in the same layer structure parallel to the substrate.

In some other possible process structures, as shown in fig. 9b, the gate electrode is disposed on the other side opposite to the source and drain electrodes, that is, in the process structure, the first electrode and the second electrode of the transistor T1 are disposed in the same plane parallel to the substrate (for example, in the first plane), and the gate electrode of the transistor T1 and the gate electrode of the transistor T3 are disposed in the second plane parallel to the substrate, so that the control gate layer electrically connected to the gate electrode of the transistor T1 and the gate electrode of the transistor T3, and the gate electrode of the transistor T1 and the gate electrode of the transistor T3 are also disposed in the second plane. In this way, the conjugated output of the logic gate is in a first plane and the conjugated input is in a second plane, and the logic gate thus formed may also be referred to as the conjugated output and the conjugated input are in the same layer structure parallel to the substrate.

In the logic gate circuit 400 according to the present application, the structure of the transistor is not particularly limited, for example, a single gate transistor or a double gate transistor may be used, and as an example, a single gate transistor is used in fig. 8, 9a, and 9 b.

Also, the gate structure of the transistor may be arranged in different manners, for example, fin field effect transistor, ring gate transistor, vertical nanowire field effect transistor, etc.

Fig. 10 exemplarily shows a process structure diagram of a double gate transistor, specifically, as shown in fig. 10, the double gate transistor includes a first electrode 02 and a second electrode 03, and a channel 01 formed between the first electrode 02 and the second electrode 03. The gate of the double-gate transistor includes a first gate 061 and a second gate 062, the first gate 061 is formed on one side of the channel 01 through the first gate dielectric layer 04, and the second gate 062 is formed on the other side of the channel 01 through the second gate dielectric layer 05. The first Gate 061 may also be called Top Gate and the second Gate 062 may be called Bottom Gate.

When the transistors in the logic gate circuit 400 are double gate transistors, as shown in fig. 10, the first gate 061 and the second gate 062 are connected and connected to an input terminal or a conjugated input terminal. For example, when the transistor T1 is a double gate transistor, then the connected first gate 061 and second gate 062 form a conjugated input terminal IN'.

In some embodiments, the logic gate 400 of the present application may adjust the threshold voltages (threshold voltage) of the pull-up transistor (transistor T1 and transistor T2) and the pull-down transistor (transistor T3 and transistor T4) to be different such that the threshold voltage Vth of the pull-up transistor is less than or equal to 0 and the threshold voltage Vth of the pull-down transistor is greater than 0 to achieve zero potential loss of the logic gate output.

For example, as shown in fig. 11, when both the pull-up transistor T1 and the pull-up transistor T2 are dual-gate transistors, one gate of the transistor T1 may be electrically coupled to one gate of the transistor T2 and electrically connected to the threshold voltage adjustment port to adjust the threshold voltages of the pull-up transistor T1 and the pull-up transistor T2. Fig. 11 illustrates only one way to adjust the threshold voltage of a transistor when turned on by adjusting the voltage of one of the double gates. Of course, other manners of adjusting the threshold voltage are also available, for example, by adjusting the channel material of the transistor, adjusting the work function of the gate, adjusting the dipole, adjusting the back gate voltage, adjusting the thickness and the material of the gate dielectric layer, and the like.

Referring again to the logic gate circuit 400 shown in fig. 11, when one gate of the transistor T1 is electrically coupled to one gate of the transistor T2, in a process structure that can be implemented, a metal layer may be formed that is electrically coupled to one gate of the transistor T1 and one gate of the transistor T2, respectively, and that is electrically coupled to the threshold voltage adjustment port.

One of the control gate layer and the metal layer is connected to one gate of the transistor, and the other is connected to the other gate of the transistor, and in practice, the control gate layer and the metal layer may be stacked on both sides of the channel of the transistor in a manner perpendicular to the substrate to avoid interconnection of the control gate layer and the metal layer. Since fig. 11 shows a two-dimensional process structure in which a metal layer and a control gate layer are overlapped, in fact, in a three-dimensional structure, the control gate layer and the metal layer are located in different planes.

The logic gate 400 proposed in the above embodiment of the present application may be applied in many scenarios, for example, may be applied in a memory, and may also be applied in a circuit structure such as a flip-flop, an amplifier, and the like. The following presents a partial application scenario involving this logic gate, see in particular below.

Fig. 12 shows a circuit diagram of applying the logic gate circuit according to the present application to a memory cell of an SRAM memory, and in the memory cell 500, a logic gate circuit 400a and a logic gate circuit 400b, and a first gate pipe 601 and a second gate pipe 602 are included.

The cascaded logic gate circuits 400a and 400b form a Latch (Latch) structure of the memory cell, and a first electrode of the second gate pipe 602 is electrically connected to a Bit Line (BL), a second electrode of the second gate pipe 602 is electrically connected to an output terminal OUT of the logic gate circuit 400b, a first electrode of the first gate pipe 601 is electrically connected to a conjugated bit line BL ', a second electrode of the first gate pipe 601 is electrically connected to an output terminal OUT of the logic gate circuit 400a, the bit line BL and the conjugated bit line BL' serve as input and output terminals of the memory cell, and in addition, a gate of the first gate pipe 601 and a gate of the second gate pipe 602 are connected to Word Lines (WL) for performing switching control of signal reading and writing.

In a process structure that may be implemented for the memory cell of fig. 12, the logic gates 400a and 400b in cascade may be stacked in a direction perpendicular to the substrate. The stacking mode is described in detail below.

The process structure of the logic gate circuit 400a of fig. 12 may refer to the process structure diagram shown in fig. 13a, and the process structure diagram shown in fig. 13a is the same as the process structure diagram shown in fig. 8, which is not repeated here. The process structure of the logic gate 400b of fig. 12 may refer to the process structure diagram shown in fig. 13b, and fig. 14 shows the process structure diagram after the logic gate 400a and the logic gate 400b are stacked.

Referring to fig. 13a and 13b together, in the logic gate 400a, the inverter 401 is arranged along the X direction and the buffer 402 is also arranged along the X direction, but in the logic gate 400b, the inverter 401 is arranged along the Y direction and the buffer 402 is also arranged along the Y direction. Comparing the logic gate 400b shown in fig. 13b with the logic gate 400a shown in fig. 13a, the logic gate 400a shown in fig. 13a can be rotated clockwise by 90 °, so that the layout positions of the inverter 401 and the buffer 402 can be changed to those shown in fig. 13 b.

Further, the logic gate 400b not only rotates on the basis of the logic gate 400a, but also needs to perform mirror-symmetrical inversion. If only the rotation is performed, the first dc voltage terminal (e.g., the power supply voltage VDD) of the logic gate 400b is disposed opposite to the second dc voltage terminal (e.g., the ground terminal GND or VSS) of the logic gate 400a, so that the interconnection manner is not easy to be implemented when the two logic gates are cascaded, and in order to avoid this phenomenon, in conjunction with fig. 13a and fig. 13b, it is also necessary to perform mirror-symmetrical inversion on the basis of the logic gate 400a, so that the logic gate 400b shown in fig. 13b can be obtained.

In a specific mirror-symmetrical inversion method, the positions of the transistor T1 and the transistor T3 in the inverter 401 in fig. 13a can be exchanged, and the power supply voltage VDD and the ground GND of the inverter 401 can be exchanged, so that the inverter 401 structure shown in fig. 13b can be obtained.

Similarly, the positions of the transistor T2 and the transistor T4 of the buffer 402 shown in fig. 13a can be changed, and the power supply voltage VDD and the ground GND of the buffer 402 can be changed, thereby obtaining the buffer 402 structure shown in fig. 13 b.

When the logic gate 400a and the logic gate 400b are arranged according to fig. 13a and 13b, the two logic gates are stacked IN the manner shown IN fig. 14, and thus, the output terminal OUT of the logic gate 400a and the input terminal IN of the logic gate 400b are disposed opposite to each other, so that the output terminal OUT of the logic gate 400a and the input terminal IN of the logic gate 400b can be interconnected through the conductive path 1001 penetrating the dielectric layer (not shown), and similarly, the conjugated output terminal OUT 'of the logic gate 400a can be also interconnected with the conjugated input terminal IN' of the logic gate 400b through the conductive path 1002 penetrating the dielectric layer.

Also, in conjunction with fig. 15, fig. 15 shows the interconnections between the other partial ends of the two logic gates. Specifically, the output terminal OUT of the logic gate 400b may be interconnected with the input terminal IN of the logic gate 400a through the conductive path 1003 extending through the dielectric layer, and similarly, the conjugated output terminal OUT 'of the logic gate 400b may be interconnected with the conjugated input terminal IN' of the logic gate 400a through the conductive path 1004 extending through the dielectric layer.

Fig. 16 shows an interconnection structure of the power supply voltage VDD of the logic gate 400a and the ground terminal GND of the logic gate 400b, that is, the power supply voltage VDD terminal of the logic gate 400a and the power supply voltage VDD terminal of the logic gate 400b are interconnected by the conductive path 1005 and the conductive path 1006, and the ground terminal GND terminal of the logic gate 400a and the ground terminal GND terminal of the logic gate 400b are interconnected by the conductive path 1007 and the conductive path 1008.

The interconnection structure shown in fig. 14, 15 and 16 can implement three-dimensional stacking of the logic gate 400a and the logic gate 400b, and when the two logic gate circuits are interconnected, the two logic gate circuits can be implemented only through a conductive channel (such as a through silicon via) penetrating through a dielectric layer, so that the interconnection mode is relatively simple, and the implementation is relatively easy in the process.

The process structure of the logic gate 400a and the logic gate 400b shown in fig. 14, 15 and 16 and the stacked interconnection structure between the two logic gates can be applied not only to the memory cells of the SRAM memory but also to other semiconductor devices, such as flip-flops and amplifiers.

With continued reference to fig. 12, in the memory cell, a first gate 601 is electrically connected to an output OUT of the logic gate 400a, and a second gate 602 is electrically connected to an output OUT of the logic gate 400 b. Fig. 17a shows a process connection structure that can be implemented by one of the first gate pipe 601 and the logic gate circuit 400a, and fig. 17b shows a process connection structure that can be implemented by one of the second gate pipe 602 and the logic gate circuit 400 b.

As shown in fig. 17a and 17b, the first gate 601 and the logic gate 400a are formed in the same layer structure, and the second gate 602 and the logic gate 400b are formed in the same layer structure. Namely, the first gate 601 and the second gate 602 are in stacked layers similar to the arrangement of the logic gate 400a and the logic gate 400b, so that the space of each circuit layer of the logic gate 400a and the logic gate 400b can be fully utilized, so that the first gate 601 and the second gate 602 are respectively interconnected with the corresponding logic gates.

Specifically, in the structure shown in fig. 17a, the first gate 601 is disposed along a direction perpendicular to the transistor T1 or the transistor T3, and the second electrode of the first gate 601 is electrically connected to a point at the coupling connection position of the transistor T1 and the transistor T3 through the metal layer. In the structure shown in fig. 17b, the second gate 602 is disposed in a direction parallel to the transistor T1 or the transistor T3, and the second electrode of the first gate 601 is electrically connected to a point at which the transistor T1 and the transistor T3 are coupled through a metal layer.

Fig. 18 shows a process structure of the memory cell, and as shown in fig. 18, the first gate tube 601 and the second gate tube 602 are disposed opposite to each other vertically, so that the gate of the first gate tube 601 and the gate of the second gate tube 602 can be electrically connected to the word line WL by using the conductive channel 1009.

In addition, as further shown in fig. 18, the bit line BL and the conjugated bit line BL 'are located in different layer structures from the logic gate 400a and the logic gate 400b, that is, it can be said that the logic gate 400a is located in the first layer structure, the logic gate 400b is located in the second layer structure, and the bit line BL and the conjugated bit line BL' are located in the third layer structure parallel to the first layer structure and the second layer structure.

Also, the word line WL may be provided in another layer structure, for example, the word line WL may be provided in a fourth layer structure.

That is, the structure shown in fig. 18 is such that two logic cells are each provided in one layer, and signal lines (including at least bit lines BL, conjugated bit lines BL', and word lines WL) are provided in the other two layers. By the design, the occupied area of each logic unit layer can be reduced, the area utilization rate of each layer of logic gate circuit is guaranteed, and the integration level of each logic unit is improved.

In one possible process, the bit line BL in the third layer structure may be electrically connected to the electrode of the second gate tube 602 in the second layer structure through a conductive channel, and similarly, the conjugated bit line BL' in the third layer structure may be electrically connected to the electrode of the first gate tube 601 in the first layer structure.

FIG. 19 is a two-dimensional process architecture diagram of a memory array of FIG. 18 after array layout of the memory cells. In the memory array 800, as shown in fig. 19, the extending direction of the bit line BL and the extending direction of the conjugated bit line BL' are parallel, for example, may extend in the X direction parallel to the substrate, whereas the extending direction of the word line WL is perpendicular to the extending direction of the bit line BL, for example, may extend in the Y direction parallel to the substrate.

Referring again to fig. 19, fig. 19 also shows a control signal line TG for controlling the threshold voltage of the logic gate circuit, and the extending direction of the control signal line TG is parallel to the extending direction of the word line WL.

The control signal line TG may be provided in the same layer structure as the word line WL.

In some embodiments, the memory may include at least two layers of memory arrays stacked in a direction perpendicular to the substrate, for example, as shown in fig. 20, where fig. 20 illustrates a first layer of memory array 801 and a second layer of memory array 802 included in the memory. When each memory array is arranged according to the process structure diagram shown in fig. 19, the signal line layer 900 can be stacked between the first memory array 801 and the second memory array 802, that is, the signal lines for controlling the reading and writing of the two memory arrays are collectively arranged in a single layer structure, so that the number of metal layers can be reduced, and the integration density of the three-dimensional integrated memory can be further improved.

Fig. 21 shows one of the block diagrams of the signal line layer 900, the bit lines BL and the conjugated bit lines BL ' of the first-layer memory array 801, and the bit lines BL and the conjugated bit lines BL ' of the second-layer memory array 802 are arranged in parallel, for example, may extend in the Y direction parallel to the substrate, and the bit lines BL and the conjugated bit lines BL ' may be arranged at intervals.

The word lines WL of the first-layer memory array 801 and the word lines WL of the second-layer memory array 802 are arranged in parallel, for example, may extend in a direction perpendicular to the bit lines.

That is, the signal line layer 900 herein may include two layers, one of which lays out the bit lines BL and the conjugate bit lines BL' of the first and second layer memory arrays 801 and 802, and the other of which lays out the word lines WL of the first and second layer memory arrays 801 and 802.

Fig. 22a shows another possible process connection structure of the first gate pipe 601 and the logic gate circuit 400a, and fig. 22b shows another possible process connection structure of the second gate pipe 602 and the logic gate circuit 400 b. In fig. 17a and 17b, the first gate 601 and the second gate 602 are arranged vertically opposite to each other, but in fig. 22a and 22b, the first gate 601 and the second gate 602 are not arranged vertically opposite to each other but are positioned in different orientations, so that fig. 23 shows a three-dimensional process structure of the memory cell, the conjugated bit line BL' and the logic gate 400a are positioned in the first layer, the bit line BL and the logic gate 400b are positioned in the second layer, and further, a further layer structure for forming a signal line is not required, and thus, the number of layer structures of the entire memory can be reduced.

The word line WL may be provided in the first layer, or, as shown in fig. 23, in the first layer.

Fig. 24 is a diagram showing a structure of a memory array of one layer formed after array layout of the memory cells shown in fig. 23. In the memory array, as shown in fig. 24, the extension direction of the bit line BL is perpendicular to the extension direction of the conjugated bit line BL ', for example, the conjugated bit line BL ' may extend in an X direction parallel to the substrate, and the bit line BL may extend in a Y direction parallel to the substrate, however, the extension direction of the word line WL is parallel to the extension direction of the conjugated bit line BL ', for example, may extend in an X direction parallel to the substrate.

Referring again to fig. 24, fig. 24 also shows a control signal line TG for controlling the threshold voltage of the logic gate circuit, and the extending direction of the control signal line TG is parallel to the extending direction of the bit line BL.

The control signal line TG may be provided in another layer.

In the memories with two different process structures shown above, the first gate tube and the first logic gate circuit are arranged in the same layer structure, and the second gate tube and the second logic gate circuit are arranged in the same layer structure. Of course, in some other realizable process structures, the first gate tube and the first logic gate circuit may be disposed in different layer structures, or the second gate tube and the second logic gate circuit may be disposed in different layer structures, for example, the first logic gate circuit is disposed in the first layer structure, the second logic gate circuit is disposed in the second layer structure, and the first gate tube and the second gate tube are disposed in the third layer structure.

For the memory cell of the SRAM memory described above, the nMOSFET transistors shown in fig. 12 may be used for each transistor, and pMOSFET transistors may be used for each transistor. Then, when the pMOSFET transistor is selected, the word line WL may be replaced with a conjugated word line WL ', and the bit line BL and the conjugated bit line BL ' remain unchanged, but one end of the conjugated word line WL ' may be electrically connected to the inverter, and the other end may be electrically connected to the memory cell. With the development of semiconductor technology, three-dimensional stacking of chips is a trend of process development, and in the three-dimensional stacking technology of chips, monolithic integration (monolithic Integration) has advantages of low cost and high interconnection density, and is increasingly widely adopted. For example, the SRAM memory provided by the present application and an arithmetic logic unit (arithmetic and logic unit, ALU) for controlling the same may be integrated in one chip, and as shown in fig. 25, the arithmetic logic unit ALU is integrated on a substrate through a front end of line (FEOL) process, and the SRAM memory is integrated on the arithmetic logic unit ALU through a back end of line (BEOL) process. The arithmetic logic unit ALU can generate control signals, and the control signals can be read-write control signals, and are used for controlling the read-write operation of data in the SRAM memory, so that the vertical CPU architecture of alu+sram is realized. The CPU with the architecture can shorten the transmission speed of data between the computing unit and the storage unit, improve the computing efficiency, and save more chip area for the previous process.

Then, since the SRAM memory adopts the subsequent BEOL process, the transistor forming the SRAM memory needs not only high mobility but also low temperature growth. For example, the logic gate circuit can be fabricated using an amorphous oxide semiconductor (amorphous oxide semiconductor, AOS) field effect transistor of an electron type, among other process means that can be implemented.

Fig. 26 shows another semiconductor device including the above-described logic gate 400a and logic gate 400b, which is a D flip-flop structure. The D flip-flop 600 includes a logic gate 400a, a logic gate 400b, and gate T1-, gate T2-, and gate T2-respectively.

The input end IN of the logic gate circuit 400a is connected with the output end OUT of the logic gate circuit 400b through a gate tube T2+, the conjugated input end IN 'of the logic gate circuit 400a is connected with the conjugated output end OUT' of the logic gate circuit 400b through a gate tube T2-, that is, the first electrode of the gate tube T2+ is connected with the input end IN of the logic gate circuit 400a, and the second electrode of the gate tube T2+ is connected with the output end OUT of the logic gate circuit 400 b; the first electrode of the gate T2-is connected with the conjugated input end IN 'IN the logic gate circuit 400a, and the second electrode of the gate T2-is connected with the conjugated output end OUT' IN the logic gate circuit 400 b; and, the gate of gate T2+ and the gate of gate T2-are electrically connected to the inverse clock signal CLK'.

Further, as shown IN fig. 26, the output terminal OUT of the logic gate 400a is connected to the input terminal IN of the logic gate 400b, and the conjugated output terminal OUT 'of the logic gate 400a is connected to the conjugated input terminal IN' of the logic gate 400 b.

As shown IN fig. 26, IN the D flip-flop 600, a first electrode of the gate tube t1+ is connected to the input terminal IN of the logic gate circuit 400a, and a second electrode of the gate tube t1+ is connected to the input signal D; the first electrode of the gate T1-is connected to the conjugated input IN 'of the logic gate 400a and the second electrode of the gate T1-is connected to the inverted input signal D'. The gate of the gate T1+ and the gate of the gate T1-are electrically connected to the clock signal CLK.

An output terminal of the logic gate 400a is connected to an input terminal of the logic gate 400b and forms an output terminal OUT of the D flip-flop 600, and a conjugate output terminal of the logic gate 400a is connected to a conjugate input terminal of the logic gate 400b and forms a conjugate output terminal OUT' of the D flip-flop 600.

Referring to fig. 27a and 27b, fig. 27a shows a process connection structure that one of the logic gate circuit 400a, the gate tube t1+ and the gate tube T1-can implement, and fig. 27b shows a process connection structure that one of the logic gate circuit 400b, the gate tube t2+ and the gate tube T2-can implement.

Specifically, the logic gate circuit 400b, the gate tube t2+ and the gate tube T2-are located in the same layer structure, and the logic gate circuit 400a, the gate tube t1+ and the gate tube T1-are located in another same layer structure, for example, as shown in fig. 28, fig. 28 shows a three-dimensional process structure diagram of the D flip-flop 600 in fig. 26, where the logic gate circuit 400a, the gate tube t1+ and the gate tube T1-are located in a first layer structure, and the logic gate circuit 400b, the gate tube t2+ and the gate tube T2-are located in a second layer structure.

And the corresponding connecting ends in the stacked two-layer structure are electrically connected through conductive channels so as to realize signal intercommunication.

In addition, when all the transistors of the D flip-flop 600 described above employ pMOSFET transistors, the clock signal CLK and the inverted clock signal CLK' need to be interchanged.

Fig. 29 shows another semiconductor device including the above-described logic gate 400a and logic gate 400b, which is a ring oscillator 700. The ring oscillator 700 includes a logic gate 400c in addition to the logic gates 400a and 400 b.

The output terminal OUT of the logic gate 400a is electrically connected to the input terminal IN of the logic gate 400b, the conjugated output terminal OUT 'of the logic gate 400a is electrically connected to the conjugated input terminal IN' of the logic gate 400b, the output terminal OUT of the logic gate 400b is electrically connected to the input terminal IN of the logic gate 400c, the conjugated output terminal OUT 'of the logic gate 400b is electrically connected to the conjugated input terminal IN' of the logic gate 400c, the output terminal OUT of the logic gate 400c is electrically connected to the input terminal IN of the logic gate 400a, and the conjugated output terminal OUT 'of the logic gate 400c is electrically connected to the conjugated input terminal IN' of the logic gate 400a to form a ring oscillator.

In the process structure that can be implemented in the ring oscillator 700 described above, as shown in fig. 30a to 30c, and as shown in fig. 31, any logic gate circuit may be disposed in a layer structure, for example, the logic gate circuit 400a is disposed in a first layer, the logic gate circuit 400b is disposed in a second layer, and the logic gate circuit 400c is disposed in a third layer, that is, three logic gate circuits are disposed in a three-dimensional stack.

The process structure of the logic gate 400a in the first layer may be the same as the process structure of the logic gate 400c in the third layer, and the process structure of the logic gate 400b between the first layer and the third layer may be obtained by performing rotation and symmetrical inversion on the basis of the logic gate 400a or the logic gate 400c, and the specific structure obtained by performing rotation and symmetrical inversion is explained above and will not be repeated here.

Only three logic gates are shown in the ring oscillator 700 described above, and in addition, an odd number of logic gates greater than 3 may be included to cascade together to form the ring oscillator.

Similar to the structure of the SRAM and the D trigger, the connection ends which are positioned in different layers and need to be electrically connected can be electrically connected through the conductive channels which are perpendicular to the substrate, so that the ring oscillator is three-dimensionally stacked on the substrate.

The above only gives a circuit diagram of a part of the semiconductor device including the logic gate circuit according to the present application, and a corresponding structural construction diagram of the process. In addition, the circuit structure of the logic gate circuit and the corresponding structure diagram of the process structure can be applied to other semiconductor devices, and are not exhaustive.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, comprising:

a substrate;

a first logic gate formed on the substrate, the first logic gate being a unipolar logic gate;

wherein the first logic gate circuit has:

an input and a conjugate input, and an output and a conjugate output;

The input end, the conjugate input end, the output end and the conjugate output end are formed in the same layer structure parallel to the substrate;

the input end and the conjugate input end are arranged along a first straight line;

the output end and the conjugate output end are arranged along a second straight line intersecting the first straight line;

and the input end and the conjugate input end are arranged on two sides of the second straight line, and the output end and the conjugate output end are arranged on two sides of the first straight line.

2. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: a second logic gate circuit of a single-pole type, the first logic gate circuit being formed in a first layer structure parallel to the substrate, the second logic gate circuit being formed in a second layer structure parallel to the first layer structure;

the second logic gate circuit has:

an input and a conjugate input, and an output and a conjugate output;

the input end of the second logic gate circuit is opposite to the output end of the first logic gate circuit and is electrically connected with the output end of the first logic gate circuit through a conductive channel;

the conjugate input end of the second logic gate circuit is opposite to the conjugate output end of the first logic gate circuit and is electrically connected with the first logic gate circuit through a conductive channel;

The output end of the second logic gate circuit is opposite to the input end of the first logic gate circuit and is electrically connected with the input end of the first logic gate circuit through a conductive channel;

the conjugate output end of the second logic gate circuit is opposite to the conjugate input end of the first logic gate circuit and is electrically connected with the first logic gate circuit through a conductive channel.

3. The semiconductor device according to claim 1 or 2, wherein the first logic gate circuit includes:

an inverter and a buffer; the inverter and the buffer each have an input and a conjugate input, and an output;

in the inverter, the conjugate input terminal, the output terminal, and the input terminal are sequentially arranged in a first direction along the first straight line;

in the buffer, the input end, the output end and the conjugate input end are sequentially arranged along the first straight line in a second direction, and the first direction is opposite to the second direction;

wherein one of the output terminal of the inverter and the output terminal of the buffer forms an output terminal of the first logic gate circuit, and the other forms a conjugate output terminal of the first logic gate circuit, such that the output terminal and the conjugate output terminal of the first logic gate circuit are located on the second straight line intersecting the first straight line;

The input end of the inverter is electrically connected with the input end of the buffer to form the input end of the first logic gate circuit;

the conjugate input of the inverter is electrically connected with the conjugate input of the buffer to form the conjugate input of the first logic gate, so that the input and the conjugate input of the first logic gate are arranged at two sides of the second straight line.

4. The semiconductor device according to claim 3, wherein,

the inverter includes: a first transistor and a third transistor;

the first electrode and the second electrode of the first transistor and the first electrode and the second electrode of the third transistor are sequentially arranged along the first direction, and the second electrode of the first transistor and the first electrode of the third transistor share the same first common electrode;

the first common electrode forms an output of the first logic gate.

5. The semiconductor device according to claim 4, wherein,

the buffer includes: a second transistor and a fourth transistor;

the first electrode and the second electrode of the second transistor and the first electrode and the second electrode of the fourth transistor are sequentially arranged along the second direction, and the second electrode of the second transistor and the first electrode of the fourth transistor share the same second common electrode;

The second common electrode forms a conjugated output of the first logic gate.

6. The semiconductor device according to claim 5, wherein the semiconductor device further comprises:

a first control gate layer formed between the first transistor and the fourth transistor and connected to the gate of the first transistor and the gate of the fourth transistor, respectively, to form a conjugated input terminal of the first logic gate circuit;

and a second control gate layer formed between the third transistor and the second transistor and connected to the gate of the third transistor and the gate of the second transistor, respectively, to form an input terminal of the first logic gate circuit.

7. A semiconductor device according to claim 5 or 6, wherein,

the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors or all P-type transistors.

8. The semiconductor device according to claim 2, wherein the semiconductor device further comprises:

the first gate tube and the second gate tube;

The output end of the first logic gate circuit is electrically connected with the first electrode of the first gate tube, and the first gate tube and the first logic gate circuit are formed in the first layer structure;

the output end of the second logic gate circuit is electrically connected with the first electrode of the second gate tube, and the second gate tube and the second logic gate circuit are formed in the second layer structure.

9. The semiconductor device according to claim 8, wherein the semiconductor device is a static random access memory, the static random access memory further comprising:

the grid electrode of the first gate tube and the grid electrode of the second gate tube are electrically connected with the word line;

a conjugated bit line, the second electrode of the first gate tube is electrically connected with the conjugated bit line

And the second electrode of the second gate tube is electrically connected with the bit line.

10. The semiconductor device according to claim 9, wherein the conjugated bit line and the bit line are formed in a third layer structure parallel to the substrate, and wherein the word line is formed in a fourth layer structure parallel to the substrate;

the conjugated bit line is electrically connected with the second electrode of the first gate tube through a conductive channel;

The bit line is electrically connected with the second electrode of the second gate tube through a conductive channel;

the word line is electrically connected with the grid electrode of the first gate tube and the grid electrode of the second gate tube through conductive channels.

11. The semiconductor device of claim 9, wherein the semiconductor device comprises a semiconductor substrate,

the conjugate bit line is formed within the first layer structure;

the bit line is formed within the second layer structure;

the word line is formed within the first layer structure or the second layer structure.

12. The semiconductor device according to claim 2, wherein the semiconductor device is a flip-flop, the flip-flop further comprising:

the first gate tube, the second gate tube, the third gate tube and the fourth gate tube;

the input end of the first logic gate circuit is electrically connected with the first electrode of the first gate tube, the conjugated input end of the first logic gate circuit is electrically connected with the first electrode of the second gate tube, the grid electrode of the first gate tube and the grid electrode of the second gate tube are electrically connected with clock control signals, and the first gate tube, the second gate tube and the first logic gate circuit are formed in the first layer structure;

The output end of the second logic gate circuit is electrically connected with the input end of the first logic gate circuit through the third gate tube, the conjugated output end of the second logic gate circuit is electrically connected with the conjugated input end of the first logic gate circuit through the fourth gate tube, the grid electrode of the third gate tube and the grid electrode of the fourth gate tube are electrically connected with inverse clock control signals, and the third gate tube, the fourth gate tube and the second logic gate circuit are formed in the second layer structure.

13. The semiconductor device according to claim 2, wherein the semiconductor device is a ring vibrator, the ring vibrator further comprising: a third logic gate circuit of a single pole type;

the third logic gate circuit has the same structure as the first logic gate circuit, and is stacked in a third layer structure of the second logic gate circuit, which is far away from the first logic gate circuit and is parallel to the substrate.

14. The semiconductor device of any of claims 1-13, wherein the first logic gate circuit is fabricated on the substrate using a subsequent process.

15. An electronic device, comprising:

a circuit board;

a semiconductor device as claimed in any one of claims 1 to 14;

wherein the semiconductor device is disposed on the wiring board.