CN116683895B - Clock signal transmission circuit - Google Patents

Clock signal transmission circuit Download PDF

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Publication number
CN116683895B
CN116683895B CN202310969503.9A CN202310969503A CN116683895B CN 116683895 B CN116683895 B CN 116683895B CN 202310969503 A CN202310969503 A CN 202310969503A CN 116683895 B CN116683895 B CN 116683895B
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clock signal
transistor
signal
unit
calibration
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CN116683895A (en
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付玉山
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Niuxin Semiconductor Shenzhen Co ltd
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Niuxin Semiconductor Shenzhen Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The application belongs to the technical field of digital circuits, and particularly relates to a clock signal transmission circuit. Comprising the following steps: at least one clock signal driving module; the clock signal driving module includes: the input end of the driving unit receives a clock signal, the output end of the driving unit outputs the clock signal, and the driving unit is used for transmitting the clock signal; the input end of the current adjusting unit receives an adjusting signal, and the current adjusting unit is used for switching on and switching off according to the adjusting signal and providing current gain for transmitting the clock signal for the driving unit so as to ensure the signal quality of the clock signal.

Description

Clock signal transmission circuit
Technical Field
The application belongs to the technical field of digital circuits, and particularly relates to a clock signal transmission circuit.
Background
The high speed transmission interface circuit generally includes a phase locked loop, a transmitter, and a receiver. The transmitter transmits the low-speed data transmitted by the coding layer in combination with a clock signal generated by the phase-locked loop. Different configurations of the high-speed transmission interface circuits generally include a plurality of transmitter circuits and a phase-locked loop circuit, when the distance between the transmitter circuits and the phase-locked loop circuit is long, the clock signal needs to be transmitted in a long distance, and long-distance transmission is realized through connection of a plurality of driving stages, but the structure of the driving stages limits the driving capability, so that the clock signal is easily distorted, and the data transmission effect of the transmitter is affected.
Disclosure of Invention
The application aims to provide a clock signal transmission circuit so as to improve the effect of transmitting clock signals.
The embodiment of the application provides a clock signal transmission circuit, which comprises at least one clock signal driving module; the clock signal driving module includes:
The input end of the driving unit receives a clock signal, the output end of the driving unit outputs the clock signal, and the driving unit is used for transmitting the clock signal;
the input end of the current adjusting unit receives an adjusting signal, and the current adjusting unit is used for switching on and switching off according to the adjusting signal and providing current gain for transmitting the clock signal for the driving unit so as to ensure the signal quality of the clock signal.
Further, the driving unit includes:
A differential pair unit receiving the clock signal for providing a driving capability for transmitting the clock signal;
The frequency band adjusting unit is connected with the differential pair unit and used for widening the working bandwidth of the differential pair unit so as to match the frequency of the clock signal.
Further, the frequency band adjusting unit includes:
And the inductance unit is connected with the differential pair unit and is used for widening the working bandwidth of the differential pair unit.
Further, the current adjusting unit includes:
The input end of the first adjusting unit receives a first adjusting signal, and the first adjusting unit is used for switching on and switching off according to the first adjusting signal;
The input end of the second adjusting unit receives a second adjusting signal, and the second adjusting unit is used for switching on and switching off according to the second adjusting signal;
The first adjusting unit is connected with one end of the second adjusting unit, the other end of the second adjusting unit is connected with the driving unit, and the magnitude of the current gain flowing through the driving unit is adjusted by controlling the on-off of the first adjusting unit and the second adjusting unit so as to ensure the signal quality of the clock signal.
Further, the clock signal transmission circuit further includes:
The signal calibration module comprises a first input end and a second input end, the first input end receives the clock signal, the second input end is connected with the output end of the clock signal driving module, and the output end of the signal calibration module is connected with the input end of the clock signal driving module;
The signal calibration module is used for generating a calibration signal according to the clock signal output by the clock signal driving module and transmitting the clock signal subjected to gain adjustment to the clock signal driving module according to the clock signal and the calibration signal.
Further, the signal calibration module includes:
The input end of the judging unit receives the output end of the clock signal driving module and is used for generating a calibration signal according to the clock signal output by the clock signal driving module;
And the first input end of the calibration unit is used for receiving the clock signal, and the second input end of the calibration unit is connected with the output end of the judging unit and is used for adjusting the clock signal according to the clock signal and the calibration signal so as to output the clock signal subjected to gain adjustment to the clock signal driving module.
Further, the decision unit includes:
The input end of the judging stage is connected with the output end of the clock signal driving module, and the output end of the judging stage is connected with the second input end of the calibration unit;
The judging stage is used for generating the calibration signal according to the clock signal output by the clock signal driving module.
Further, the calibration unit includes:
The input end of the signal driving stage is used for receiving the clock signal and providing driving capability for transmitting the clock signal;
The input end of the current calibration stage is connected with the output end of the judging unit, and the output end of the current calibration stage is connected with the signal driving stage and is used for generating gain current according to the calibration signal;
The signal driving stage adjusts the clock signal based on the gain current to output the gain-adjusted clock signal to the clock signal driving module to enhance driving capability of transmitting the clock signal.
Further, the current calibration stage further includes a signal end, and the signal end receives a current adjustment signal, where the current adjustment signal is used to adjust the magnitude of the gain current generated by the current calibration stage.
Further, the clock signal transmission circuit further includes:
the input end of the reference voltage module is used for accessing reference current, the first output end of the reference voltage module is connected with the clock signal driving module, and the second output end of the reference voltage module is connected with the signal calibration module;
the reference voltage module is used for converting the reference current into reference voltage, and the clock signal driving module and the signal calibration module are enabled through the reference voltage.
In the embodiment of the application, the clock signal driving module comprises at least one clock signal driving module, the clock signal driving module comprises a driving unit and a current adjusting unit, the driving unit is used for transmitting clock signals, the current adjusting unit is connected with the driving unit, wherein the input end of the current adjusting unit receives the adjusting signals, the current adjusting unit is switched on and switched off according to the adjusting signals to adjust the current gain flowing to the driving unit so as to improve the driving capability of the driving unit for transmitting the clock signals, ensure the signal quality of the clock signals and ensure that the duty ratio of the clock signals is not distorted.
Other features and advantages of the application will be apparent from the following detailed description, or may be learned by the practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 shows a schematic diagram of a clock signal transmission circuit according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a clock signal transmission circuit according to an embodiment of the application.
Fig. 3 is a schematic circuit diagram of a clock signal transmission module according to another embodiment of the application.
Fig. 4 shows a schematic circuit configuration of the current adjustment unit 120.
Fig. 5 is a schematic diagram of a clock signal transmission circuit according to another embodiment of the application.
Fig. 6 shows a schematic diagram of the structure of the signal calibration module 200.
Fig. 7 shows a circuit configuration diagram of the decision unit 210.
Fig. 8 shows a circuit configuration diagram of the calibration unit 220.
Fig. 9 shows a schematic circuit configuration of the reference voltage module 300.
Reference numerals illustrate:
The clock signal driving module 100, the driving unit 110, the current adjusting unit 120, the first adjusting unit 121, the second adjusting unit 122, the signal calibration module 200, the decision unit 210, the calibration unit 220, the signal driving stage 221, the current calibration stage 222, and the reference voltage module 300.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
The high-speed transmission interface generally comprises a phase-locked loop, a transmitter and a receiver, wherein the transmitter can transmit data without separating a clock signal no matter adopting a half-speed clock architecture or a full-speed clock architecture. While the transmitter itself does not generate the clock signal, the required clock signal is provided by the phase locked loop. In the circuit layout, when the distance between the transmitter interface and the phase-locked loop is longer, the driving capability of the transmission clock signal is weakened, so that the clock signal is distorted.
In order to improve the driving capability of the clock signal transmission, the embodiment of the application provides a clock signal transmission circuit.
Fig. 1 shows a schematic diagram of a clock signal transmission circuit according to an embodiment of the present application.
The embodiment of the application provides a clock signal transmission circuit, which comprises at least one clock signal driving module; the clock signal driving module 100 includes:
The driving unit 110, the input end of the driving unit 110 receives the clock signal, the output end of the driving unit 110 outputs the clock signal, and the driving unit 110 is used for transmitting the clock signal;
The current adjusting unit 120, the input end of the current adjusting unit 120 receives the adjusting signal, the current adjusting unit 120 is configured to switch on and off according to the adjusting signal, and provide the current gain of the transmission clock signal for the driving unit 110, so as to ensure the signal quality of the clock signal.
As an alternative embodiment, when long-distance clock signal transmission is required, a plurality of clock signal driving modules are cascaded according to the requirement.
Fig. 2 shows a schematic diagram of the structure of the clock signal transmission circuit provided in the present embodiment.
Each clock signal module 100 includes a driving unit 110 and a current adjusting unit 120, wherein the driving unit 110 is configured to provide driving capability for transmitting a clock signal. The input end of the driving unit 110 is used as the input end of the clock signal transmission module, the output end of the driving unit 110 is used as the output end of the clock signal transmission module, the input end is used for receiving the clock signal, and the output end is used for outputting the clock signal.
When the next module of the clock signal module is connected with the transmitter, the clock signal output by the output end is transmitted to the transmitter. When a plurality of clock signal transmission modules exist, the current clock signal transmission module transmits a clock signal to the next clock signal transmission module through an output end.
The current adjusting unit 120 is connected to the driving unit 110, the input end of the current adjusting unit 120 receives an adjusting signal SEL, the adjusting signal SEL is used for controlling on-off of the current adjusting unit 120, when the current adjusting unit 120 is turned on, a current is output to the driving unit 110, and the driving unit 110 enhances the capability of transmitting a clock signal based on the current, so as to realize providing a current gain of transmitting the clock signal to the driving unit 110.
In the embodiment of the application, a clock signal transmission module comprising a driving unit 110 and a current adjusting unit 120 is provided, a clock signal is transmitted through the driving unit 110, the current adjusting unit 120 is connected with the driving unit 110, wherein the input end of the current adjusting unit 120 receives an adjusting signal, the adjusting signal is used for controlling the on-off of the current adjusting unit 120, thereby controlling the current gain output to the driving unit 110 so as to pull the driving capability of the driving unit 110 for transmitting the clock signal, thereby enabling the clock signal not to be distorted and ensuring the signal quality of the clock signal to a certain extent; on the other hand, the embodiment includes at least one clock signal transmission module, when the clock signal needs to be transmitted for a long distance, the clock signal transmission modules are cascaded, the clock signal is transmitted for a long distance through the driving capability of each clock signal transmission module, and the signal quality of the clock signal can be ensured.
Optionally, in the clock signal transmission circuit provided in this embodiment, the clock signal is a differential signal, the clock signal includes a first clock signal clk_inn and a second clock signal clk_inp, and the amplitudes of the first clock signal clk_inn and the second clock signal clk_inp are the same and the phases are opposite.
Fig. 3 shows a schematic circuit structure of the clock signal transmission module according to the present embodiment.
Further, the driving unit 110 includes:
a differential pair unit, which receives the clock signal and is used for providing driving capability of the transmission clock signal;
The frequency band adjusting unit is connected with the differential pair unit and used for widening the working bandwidth of the differential pair unit so as to match the frequency of the clock signal.
Specifically, the differential pair unit is constituted by a pair of transistors including a first transistor MOS1 and a second transistor MOS2.
On the basis of the above embodiment, the first clock signal clk_inn is input through the gate of the first transistor MOS1, the second clock signal clk_inp is input through the gate of the second transistor MOS2, and the output terminals of the differential pair units are respectively led out from the sources of the respective transistors.
The frequency band adjusting unit comprises an inductance unit, and the inductance unit is connected with the differential pair unit and used for widening the working bandwidth of the differential pair unit.
The inductance unit includes a first inductance L1 and a second inductance L2.
The frequency band adjusting unit is connected with the differential pair unit and used for widening the working bandwidth of the differential pair unit so as to match the frequency of the clock signal.
When the input frequency of the clock signal is too high and the structure of the differential pair unit is difficult to transmit the clock signal, the working bandwidth is adjusted by the frequency band adjusting unit.
Further, the differential pair unit further includes a first resistor R1 and a second resistor R2. A first end of the first resistor R1 is connected with the first inductor L1, and a second end of the first resistor R1 is connected with a source electrode of the first transistor MOS 1; the first end of the second resistor R2 is connected to the second inductor L2, and the second end of the second resistor R2 is connected to the source of the second transistor MOS 2.
The first resistor R1 and the second resistor R2 are used for adjusting the current on the branch where the first resistor R1 and the second resistor R2 are located, and the normal operation of the differential pair unit is ensured.
Fig. 4 shows a schematic circuit configuration of the current adjustment unit 120.
Further, the current adjustment unit 120 includes:
The first adjusting unit 121, the input end of the first adjusting unit 121 receives a first adjusting signal sel_1, and the first adjusting unit 121 is configured to switch on and off according to the first adjusting signal sel_1;
the second adjusting unit 122, the input end of the second adjusting unit 122 receives a second adjusting signal sel_2, and the second adjusting unit 122 is configured to switch according to the second adjusting signal sel_2;
the first adjusting unit 121 is connected to one end of the second adjusting unit 122, the other end of the second adjusting unit 122 is connected to the driving unit 110, and the magnitude of the current gain flowing through the driving unit 110 is adjusted by controlling the on-off state of the first adjusting unit 121 and the second adjusting unit 122, so as to ensure the signal quality of the clock signal.
The level of seln_1 is opposite to the level of the first adjustment signal sel_1, and the level of seln_2 is opposite to the level of the second adjustment signal sel_2.
Specifically, the first adjusting unit 121 is connected to one end of the second adjusting unit 122, and the other end of the second adjusting unit 122 is connected to the driving unit 110.
The circuit configuration of the first adjusting unit 121 is the same as that of the second adjusting unit 122.
The first adjusting unit 121 includes a third transistor MOS3, a fourth transistor MOS4, and a fifth transistor MOS5. The second adjustment unit 122 includes a sixth transistor MOS6, a seventh transistor MOS7, and an eighth transistor MOS8.
The gates of the third transistor MOS3 and the fifth transistor MOS5 are both connected to the first adjustment signal sel_1, the source of the third transistor MOS3 is connected to the gate of the fourth transistor MOS4, and the source of the fifth transistor MOS5 is connected to a connection point between the source of the third transistor MOS3 and the gate of the fourth transistor MOS 4.
Further, the current adjusting unit 120 further includes a ninth transistor MOS9 and a tenth transistor MOS10.
The gate of the ninth transistor MOS9 is connected with the enabling end, and the source electrode and the drain electrode of the ninth transistor MOS9 are grounded, so that the filtering effect of the ninth transistor MOS9 is realized by the connection method.
The gate of the tenth transistor MOS10 is commonly connected to the gate of the ninth transistor MOS9 at the enable terminal SET, and the source of the tenth transistor MOS10 is connected to the drain of the third transistor MOS3, the source of the fourth transistor MOS4, and the source of the seventh transistor MOS 7. The drain of the sixth transistor MOS6 is connected to the enable terminal SET.
In the second adjustment unit 122, the gates of the sixth transistor MOS6 and the eighth transistor MOS8 are connected to the second adjustment signal sel_2, and the connection path between the drain of the sixth transistor MOS6 and the enable terminal SET is connected to the driving unit 110.
In this embodiment, the current adjusting unit 120 is provided with a first adjusting unit 121 and a second adjusting unit 122, and the first adjusting unit 121 and the second adjusting unit 122 are cascaded and respectively controlled to be on-off by corresponding adjusting signals, so as to control the current connected to the driving unit 110, thereby improving the pulling capability of the differential pair unit on the transmission clock signal and ensuring the signal quality of the clock signal.
Fig. 5 shows a schematic diagram of the structure of the clock signal transmission circuit.
Further, the clock signal transmission circuit further includes:
The signal calibration module 200, the signal calibration module 200 includes the first input end and second input end, the first input end receives the clock signal, the second input end connects the output end of the clock signal driving module, the output end of the signal calibration module 200 connects with input end of the clock signal driving module;
The signal calibration module 200 is configured to generate a calibration signal according to the clock signal output by the clock signal driving module, and transmit the clock signal after gain adjustment to the clock signal driving module according to the clock signal and the calibration signal.
Fig. 6 shows a schematic diagram of the structure of the signal calibration module 200.
Further, the signal calibration module 200 includes:
The input end of the judging unit 210 is connected with the output end of the clock signal driving module, and is used for generating a calibration signal according to the clock signal output by the clock signal driving module;
The first input end of the calibration unit 220 receives the clock signal, and the second input end of the calibration unit 220 is connected to the output end of the decision unit 210, so as to adjust the clock signal according to the clock signal and the calibration signal, and output the clock signal after gain adjustment to the clock signal driving module.
Further, the decision unit 210 includes:
At least one decision stage, the input end of which is connected with the output end of the clock signal driving module, and the output end of which is connected with the second input end of the calibration unit 220;
the decision stage is used for generating a calibration signal according to the clock signal output by the clock signal driving module.
Specifically, a decision stage is used for deciding the clock signal, that is, determining whether the clock signal has distortion according to the level of the last output current.
Fig. 7 shows a circuit configuration diagram of the decision unit 210. The number of decision stages can be increased according to the actual requirement, and two decision stages are cascaded to adjust the current level of the calibration signal output by the decision unit 210.
Fig. 8 shows a circuit configuration diagram of the calibration unit 220. Further, the calibration unit 220 includes:
A signal driving stage 221, an input terminal of the signal driving stage 221 receives a clock signal for providing driving capability for transmitting the clock signal;
The input end of the current calibration stage 222 is connected with the output end of the decision unit 210, and the output end of the current calibration stage 222 is connected with the signal driving stage 221 unit for generating gain current according to the calibration signal;
The signal driving stage 221 adjusts the clock signal based on the gain current to output the gain-adjusted clock signal to the clock signal driving module to enhance the driving capability of the transmission clock signal.
As shown in fig. 8, the signal driving stage 221 includes a second inductance unit, a third resistance R3, and a fourth resistance R4, wherein the second inductance unit includes a third inductance L3 and a fourth inductance L4, an eleventh transistor MOS11, a twelfth transistor MOS12, a thirteenth transistor MOS13, a fourteenth transistor MOS14, a fifteenth transistor MOS15, a sixteenth transistor MOS16, a seventeenth transistor MOS17, an eighteenth transistor MOS18, a nineteenth transistor MOS19, and a twentieth transistor MOS20.
The thirteenth transistor MOS13, the fourteenth transistor MOS14, and the fifteenth transistor MOS15 are connected in the same manner as the third transistor MOS3, the fourth transistor MOS4, and the fifth transistor MOS 5; the sixteenth transistor MOS16, the seventeenth transistor MOS17, and the eighteenth transistor MOS18 are connected in the same manner as the sixth transistor MOS6, the seventh transistor MOS7, and the eighth transistor MOS 8;
The source of the thirteenth transistor MOS13, the source of the fourteenth transistor MOS14, and the source of the seventeenth transistor MOS17 are connected to the drains of the eleventh transistor MOS11 and the twelfth transistor MOS 12.
The nineteenth transistor MOS19 and the twentieth transistor MOS20 have their gates connected to the enable terminal SET, and the twentieth transistor MOS20 has its source connected to the drain of the thirteenth transistor MOS 13. The gates of the eleventh transistor MOS11 and the twelfth transistor MOS12 receive the clock signal as inputs.
Specifically, the output end of the current calibration stage 222 is connected to the output branch of the signal driving stage 221, so as to provide a current gain for the signal driving stage 221, so as to improve the driving capability of the transmission clock signal.
An input of the decision unit 210 receives as a second input of the signal calibration module 200 a clock signal output by an output of the clock signal transmission module, based on which a calibration signal is generated.
In this embodiment, the first input end of the signal calibration module 200 receives the clock signal, and the second input end is connected to the output end of the clock signal transmission module.
The signal calibration module 200 is a mechanism that feeds back the signal quality of the transmit clock signal. The second part of the signal calibration module 200 receives the clock signal output by the clock signal transmission module through the second input end, and judges whether the signal quality of the clock signal meets the transmission requirement, if not, the calibration signal is transmitted to the first part.
The first part receives the calibration signal transmitted by the second part, and further adjusts the gain to increase the driving capability of the transmission clock signal. Further, the current calibration stage 222 further includes a signal terminal, and the signal terminal receives a current adjustment signal, where the current adjustment signal is used to adjust the magnitude of the gain current generated by the current calibration stage 222.
As shown in fig. 8, the current calibration stage 222 includes a second differential pair unit composed of a twenty-first transistor MOS21 and a twenty-second transistor MOS22, and the gates of the twenty-first transistor MOS21 and the twenty-second transistor MOS22 are connected to the output terminal of the decision unit 210.
Further, the current calibration stage 222 further includes a twenty-third transistor MOS23, a twenty-fourth transistor MOS24, a twenty-fifth transistor MOS25, a twenty-sixth transistor MOS26, a twenty-seventh transistor MOS27, a twenty-eighth transistor MOS28, and a twenty-ninth transistor MOS29.
The gate of the thirteenth transistor MOS23 receives the current adjustment signal trim_1, and the twenty-fifth transistor MOS25 receives the current adjustment signal TRIMN _1. The gate of the twenty-sixth transistor MOS26 receives the current adjustment signal trim_2 and the gate of the twenty-eighth transistor MOS28 receives the current adjustment signal TRIMN _2.
The levels of the current adjustment signals TRIM_1 and TRIMN _1 are opposite, and the levels of the current adjustment signals TRIM_2 and TRIMN _2 are opposite. For example, TRIM_1 is denoted as 1 and TRIM_1 is denoted as 0.
The gate of the twenty-ninth transistor MOS29 is connected to the enable terminal SET, and the source of the twenty-ninth transistor MOS29 is connected to the drain of the twenty-third transistor MOS23 and the drain of the twenty-sixth transistor MOS 26.
The drain of the twenty-sixth transistor MOS26 is connected to the enable terminal SET and the second differential pair unit.
Fig. 9 shows a schematic circuit configuration of the reference voltage module 300.
As shown in fig. 9, further, the clock signal transmission circuit further includes:
the input end of the reference voltage module 300 is used for accessing a reference current I_STAND, the first output end of the reference voltage module 300 is connected with the clock signal driving module 100, and the second output end of the reference voltage module 300 is connected with the signal calibration module 200;
The reference voltage module 300 is configured to convert a reference current into a reference voltage, and enable the clock signal driving module 100 and the signal calibration module 200 through the reference voltage SET.
The reference voltage module 300 is used for enabling the clock signal driving module 100 and the signal calibration module 200 together, so that consistency of circuit layout is facilitated.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the application. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a server, a touch terminal, or a network device, etc.) to perform the method according to the embodiments of the present application.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (9)

1. A clock signal transmission circuit, comprising at least one clock signal driving module; the clock signal driving module includes:
The input end of the driving unit receives a clock signal, and the driving unit is used for receiving the current gain provided by the current adjusting unit so as to transmit the clock signal driven by the current gain;
the input end of the current adjusting unit receives an adjusting signal, and the current adjusting unit is used for switching on and switching off according to the adjusting signal and providing current gain for the driving unit for transmitting the clock signal so as to ensure the signal quality of the clock signal;
The signal calibration module comprises a first input end and a second input end, the first input end receives the clock signal, the second input end is connected with the output end of the clock signal driving module, and the output end of the signal calibration module is connected with the input end of the clock signal driving module;
The signal calibration module is used for generating a calibration signal according to the clock signal output by the clock signal driving module and transmitting the clock signal subjected to gain adjustment to the clock signal driving module according to the clock signal and the calibration signal.
2. The clock signal transmission circuit according to claim 1, wherein the driving unit includes:
A differential pair unit receiving the clock signal for providing a driving capability for transmitting the clock signal;
The frequency band adjusting unit is connected with the differential pair unit and used for widening the working bandwidth of the differential pair unit so as to match the frequency of the clock signal.
3. The clock signal transmission circuit according to claim 2, wherein the band adjustment unit includes:
And the inductance unit is connected with the differential pair unit and is used for widening the working bandwidth of the differential pair unit.
4. The clock signal transmission circuit according to claim 1, wherein the current adjusting unit includes:
The input end of the first adjusting unit receives a first adjusting signal, and the first adjusting unit is used for switching on and switching off according to the first adjusting signal;
The input end of the second adjusting unit receives a second adjusting signal, and the second adjusting unit is used for switching on and switching off according to the second adjusting signal;
The current adjusting unit further includes a ninth transistor and a tenth transistor; the grid electrode of the tenth transistor is commonly connected with the grid electrode of the ninth transistor to form an enabling end, the drain electrode of the ninth transistor and the source electrode of the ninth transistor are connected with the source electrode of the tenth transistor, and the drain electrode of the tenth transistor is connected with the connection point of the first adjusting unit and the second adjusting unit and the driving unit;
the first adjusting unit comprises a third transistor, a fourth transistor and a fifth transistor; the second adjusting unit comprises a sixth transistor, a seventh transistor and an eighth transistor;
The source electrode of the third transistor and the source electrode of the sixth transistor are commonly connected with an enabling end;
The grid electrode of the third transistor and the grid electrode of the fifth transistor are connected with a first adjusting signal;
the drain electrode of the third transistor is connected with the grid electrode of the fourth transistor, and the drain electrode of the fifth transistor is connected with the drain electrode of the third transistor and the connection point of the grid electrode of the fourth transistor;
The grid electrode of the sixth transistor and the grid electrode of the eighth transistor are both connected with the second adjusting signal;
The drain electrode of the sixth transistor is connected with the gate electrode of the seventh transistor, and the drain electrode of the eighth transistor is connected with a connection point of the drain electrode of the sixth transistor and the gate electrode of the seventh transistor; the connection point of the drain electrode of the fourth transistor and the drain electrode of the seventh transistor is the connection point of the first adjusting unit, the second adjusting unit and the driving unit; the source of the tenth transistor is connected to the source of the fifth transistor, the source of the fourth transistor, the source of the seventh transistor, and the source of the eighth transistor.
5. The clock signal transmission circuit of claim 1, wherein the signal calibration module comprises:
The input end of the judging unit receives the output end of the clock signal driving module and is used for generating a calibration signal according to the clock signal output by the clock signal driving module;
And the first input end of the calibration unit is used for receiving the clock signal, and the second input end of the calibration unit is connected with the output end of the judging unit and is used for adjusting the clock signal according to the clock signal and the calibration signal so as to output the clock signal subjected to gain adjustment to the clock signal driving module.
6. The clock signal transmission circuit of claim 5, wherein the decision unit comprises:
The input end of the judging stage is connected with the output end of the clock signal driving module, and the output end of the judging stage is connected with the second input end of the calibration unit;
The judging stage is used for generating the calibration signal according to the clock signal output by the clock signal driving module.
7. The clock signal transmission circuit of claim 5, wherein the calibration unit comprises:
The input end of the signal driving stage is used for receiving the clock signal and providing driving capability for transmitting the clock signal;
The input end of the current calibration stage is connected with the output end of the judging unit, and the output end of the current calibration stage is connected with the signal driving stage and is used for generating gain current according to the calibration signal;
The signal driving stage adjusts the clock signal based on the gain current to output the gain-adjusted clock signal to the clock signal driving module to enhance driving capability of transmitting the clock signal.
8. The clock signal transmission circuit of claim 7, wherein the current calibration stage further comprises a signal terminal that receives a current adjustment signal for adjusting the magnitude of the gain current generated by the current calibration stage.
9. The clock signal transmission circuit of claim 1, wherein the clock signal transmission circuit further comprises:
the input end of the reference voltage module is used for accessing reference current, the first output end of the reference voltage module is connected with the clock signal driving module, and the second output end of the reference voltage module is connected with the signal calibration module;
the reference voltage module is used for converting the reference current into reference voltage, and the clock signal driving module and the signal calibration module are enabled through the reference voltage.
CN202310969503.9A 2023-08-03 2023-08-03 Clock signal transmission circuit Active CN116683895B (en)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
CN1992521A (en) * 2005-12-30 2007-07-04 英特尔公司 Forwarded clock filtering
CN107612529A (en) * 2017-10-17 2018-01-19 中电科技集团重庆声光电有限公司 A kind of clock duty cycle auto-adjusting circuit
CN108604895A (en) * 2016-01-28 2018-09-28 赛灵思公司 The method of phase interpolator and implementing phase interpolater
CN110995215A (en) * 2019-12-16 2020-04-10 北京时代民芯科技有限公司 Gain-adjustable high-speed high-precision comparator circuit
CN115225065A (en) * 2022-08-31 2022-10-21 上海韬润半导体有限公司 Clock adjusting circuit

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Publication number Priority date Publication date Assignee Title
US7863958B2 (en) * 2008-12-31 2011-01-04 International Business Machines Corporation High speed clock signal duty cycle adjustment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1992521A (en) * 2005-12-30 2007-07-04 英特尔公司 Forwarded clock filtering
CN108604895A (en) * 2016-01-28 2018-09-28 赛灵思公司 The method of phase interpolator and implementing phase interpolater
CN107612529A (en) * 2017-10-17 2018-01-19 中电科技集团重庆声光电有限公司 A kind of clock duty cycle auto-adjusting circuit
CN110995215A (en) * 2019-12-16 2020-04-10 北京时代民芯科技有限公司 Gain-adjustable high-speed high-precision comparator circuit
CN115225065A (en) * 2022-08-31 2022-10-21 上海韬润半导体有限公司 Clock adjusting circuit

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