CN116682872A

CN116682872A - Solar cell and photovoltaic module

Info

Publication number: CN116682872A
Application number: CN202310792934.2A
Authority: CN
Inventors: 金井升; 张彼克; 廖光明
Original assignee: Zhejiang Jinko Solar Co Ltd; Jinko Solar Haining Co Ltd
Current assignee: Zhejiang Jinko Solar Co Ltd; Jinko Solar Haining Co Ltd
Priority date: 2023-06-29
Filing date: 2023-06-29
Publication date: 2023-09-01

Abstract

The embodiment of the disclosure relates to the field of photovoltaics, and provides a solar cell and a photovoltaic module, wherein the solar cell comprises: the substrate is provided with a plurality of first grooves which are arranged at intervals along a first direction and a plurality of second grooves which are arranged at intervals along a second direction, part of the inner wall of each first groove is provided with at least one first texture part, the first texture parts are recessed towards the inside of the substrate along the inner wall surface of each first groove or protrude towards the direction away from the substrate along the surface of each first groove, part of the inner wall of each second groove is provided with at least one second texture part at intervals, and the second texture parts are recessed towards the inside of the substrate along the inner wall surface of each second groove or protrude towards the direction away from the substrate along the surface of each second groove; the solar cell further includes a tunneling layer; doping the conductive layer; a passivation layer; the auxiliary grids penetrate through the passivation layer opposite to the first groove and are in contact connection with the doped conductive layer; and the main grids are connected with the auxiliary grids in a contact way. The performance of the solar cell can be improved.

Description

Solar cell and photovoltaic module

Technical Field

The embodiment of the disclosure relates to the field of photovoltaics, in particular to a solar cell and a photovoltaic module.

Background

The fossil energy has the advantages of air pollution and limited reserves, and solar energy has the advantages of cleanness, no pollution, abundant resources and the like, so the solar energy is gradually becoming a core clean energy for replacing the fossil energy, and the solar cell becomes the development center of gravity for the utilization of the clean energy due to the good photoelectric conversion efficiency of the solar cell.

The photovoltaic module comprises a battery string, a packaging film and a cover plate, wherein the battery string is composed of a plurality of battery pieces which are connected in sequence. The battery pieces are provided with a plurality of bonding pads, and the selected connecting parts are electrically contacted with the bonding pads in the process of preparing the battery string, so that the adjacent battery pieces are interconnected, and the battery string with specific output power is formed.

The performance of solar cells is currently being improved.

Disclosure of Invention

The embodiment of the disclosure provides a solar cell and a photovoltaic module, which can at least improve the performance of the solar cell.

According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a solar cell, including: the substrate comprises a front surface and a back surface which are opposite, wherein the back surface of the substrate is provided with a plurality of first grooves which are arranged at intervals along a first direction and a plurality of second grooves which are arranged at intervals along a second direction, part of inner walls of the first grooves are provided with at least one first texture part, the first texture part is recessed towards the inside of the substrate along the inner wall surfaces of the first grooves or protrudes towards the direction away from the substrate along the surfaces of the first grooves, part of inner walls of the second grooves are provided with at least one second texture part at intervals, and the second texture part is recessed towards the inside of the substrate along the inner wall surfaces of the second grooves or protrudes towards the direction away from the substrate along the surfaces of the second grooves; a tunneling layer covering the back surface of the substrate and covering inner walls of the first and second grooves; a doped conductive layer covering a surface of the tunneling layer remote from the back surface; a passivation layer covering a surface of the doped conductive layer remote from the back surface; the auxiliary grids are arranged at intervals along the first direction, correspond to the first grooves one by one, penetrate through the passivation layer opposite to the first grooves and are in contact connection with the doped conductive layer; the main grids are arranged at intervals along the second direction, correspond to the second grooves one by one, and are in contact connection with the auxiliary grids.

In some embodiments, the ratio of the orthographic projection area of any one of the first texture portions on the inner wall of the first groove to the surface area of the inner wall of the first groove is a first ratio, the ratio of the orthographic projection area of any one of the second texture portions on the inner wall of the second groove to the surface area of the inner wall of the second groove is a second ratio, and the first ratio is different from the second ratio.

In some embodiments, the first ratio is 20% to 80% and the second ratio is 50% to 95%.

In some embodiments, the first textured portion is recessed toward the substrate, and an orthographic projection of the first textured portion at the first groove surface is circular.

In some embodiments, the first textured portion is recessed toward the substrate, and an orthographic projection of the first textured portion at the first groove surface is a mixture of circular and square shapes.

In some embodiments, the first textured portion projects away from the substrate, and an orthographic projection of the first textured portion on the first groove surface is square.

In some embodiments, a portion of the back surface of the substrate other than the first recess and the second recess includes a plurality of third texture portions, each of the third texture portions protruding away from the substrate, and an orthographic projection of the third texture portions at the substrate surface is square.

In some embodiments, the area of orthographic projection of any one of the second texture portions on the surface of the substrate is larger than the area of orthographic projection of any one of the first texture portions on the surface of the first groove.

In some embodiments, the first grooves between adjacent second grooves include a middle portion and end portions on opposite sides of the middle portion, and the roughness of the middle portion surface is less than the roughness of the end portion surfaces.

In some embodiments, the roughness of the inner wall surface of the first groove increases gradually from a direction away from the second groove toward a direction closer to the second groove.

In some embodiments, the substrate includes edge regions at both ends and a middle region between the two edge regions; the depth of the first groove corresponding to the edge area is larger than that of the first groove corresponding to the middle area.

In some embodiments, the depth of the first groove is the same as the depth of the second groove.

In some embodiments, the depth of the first groove is greater than the depth of the second groove.

According to some embodiments of the present disclosure, there is also provided, in another aspect, a photovoltaic module including: a cell string comprising a solar cell as described above; an encapsulation layer for covering the surface of the battery string; and the cover plate is used for covering the surface, far away from the battery strings, of the packaging layer.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the back of the substrate is provided with a plurality of first grooves and a plurality of second grooves, the first grooves and the second grooves are respectively in one-to-one correspondence with the auxiliary grid and the main grid, the auxiliary grid is corresponding to the first grooves, so that the auxiliary grid can be recessed towards the inside of the substrate, the contact area between the auxiliary grid and the doped conductive layer can be increased, the carrier collecting capacity of the auxiliary grid can be increased, the auxiliary grid is recessed towards the inside of the substrate, the light incident from the front of the substrate can be reflected back to the substrate by the auxiliary grid, the light utilization rate can be further increased, the first texture part is arranged on the inner wall of the first groove, the inner wall of the second groove is provided with a second texture part, so that the surface areas of the inner walls of the first groove and the second groove can be increased, the contact area between the auxiliary grid and the doped conductive layer can be correspondingly increased, the contact resistance between the auxiliary grid and the doped conductive layer can be correspondingly reduced, the contact resistance between the main grid and the auxiliary grid can be reduced, the interface composite deterioration on the inner wall surface of the first groove can be reduced by arranging a first texture part on part of the inner wall of the first groove, and the resistance of the solar cell and the interface composite deterioration of the solar cell can be balanced and reduced.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a structural cross-sectional view of a first solar cell according to an embodiment of the present disclosure;

fig. 2 is a structural cross-sectional view of a second solar cell according to an embodiment of the present disclosure;

fig. 3 is a structural cross-sectional view of a third solar cell according to an embodiment of the present disclosure;

FIG. 4 is a top view of a first solar cell according to an embodiment of the present disclosure;

FIG. 5 is a top view of a second solar cell according to one embodiment of the present disclosure;

FIG. 6 is a top view of a third solar cell according to an embodiment of the present disclosure;

FIG. 7 is a top view of a first texture feature according to one embodiment of the present disclosure;

FIG. 8 is a schematic structural view of a first groove according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a second groove according to an embodiment of the disclosure;

FIG. 10 is a microscopic top view of a first texture feature according to one embodiment of the present disclosure;

FIG. 11 is a microscopic top view of a second first texture provided in an embodiment of the present disclosure;

FIG. 12 is a microscopic top view of a third first texture feature provided in an embodiment of the present disclosure;

FIG. 13 is a microscopic cross-sectional view of a first texture feature provided in an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a photovoltaic module according to another embodiment of the present disclosure.

Detailed Description

As known from the background art, the performance of the solar cell needs to be improved.

The implementation of the present disclosure provides a solar cell, a plurality of first grooves and a plurality of second grooves are arranged on the back of a substrate along a first direction at intervals, the first grooves and the second grooves are respectively in one-to-one correspondence with a sub-grid and a main grid, the sub-grid is arranged to correspond to the first grooves, so that the sub-grid can be recessed towards the inside of the substrate, the contact area between the sub-grid and a doped conductive layer can be increased, the capability of collecting carriers by the sub-grid can be increased, the sub-grid can be recessed towards the inside of the substrate, light incident from the front of the substrate can be reflected back to the substrate by the sub-grid, the utilization rate of light can be further increased, a first texture part is arranged on the inner wall of the first groove, a second texture part is arranged on the inner wall of the second groove, the inner wall of the first groove can be increased, the contact area between the sub-grid and the doped conductive layer can be correspondingly increased, the contact area between the main grid and the sub-grid can be correspondingly reduced, the contact resistance between the sub-grid and the doped conductive layer can be correspondingly reduced, the contact resistance between the sub-grid and the inner wall of the solar cell and the solar cell can be reduced, and the contact interface between the solar cell and the inner wall of the solar cell can be reduced, and the contact surface of the solar cell can be deteriorated, and the composite interface can be reduced, and the contact resistance between the solar cell and the solar cell can be reduced, and the contact surface can be made, and the composite interface surface has a deterioration resistance between the solar cell can be formed by the contact surface and the contact surface.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Referring to fig. 1 to 13, fig. 1 is a structural cross-sectional view of a first solar cell according to an embodiment of the present disclosure; fig. 2 is a structural cross-sectional view of a second solar cell according to an embodiment of the present disclosure; fig. 3 is a structural cross-sectional view of a third solar cell according to an embodiment of the present disclosure; FIG. 4 is a top view of a solar cell according to an embodiment of the present disclosure; FIG. 5 is a top view of a second solar cell according to one embodiment of the present disclosure; FIG. 6 is a top view of a third solar cell according to an embodiment of the present disclosure; FIG. 7 is a top view of a first texture feature according to one embodiment of the present disclosure; FIG. 8 is a schematic structural view of a first groove according to an embodiment of the present disclosure; FIG. 9 is a schematic diagram of a first second groove according to an embodiment of the disclosure; FIG. 10 is a microscopic top view of a first texture feature according to one embodiment of the present disclosure; FIG. 11 is a microscopic top view of a second first texture provided in an embodiment of the present disclosure; FIG. 12 is a microscopic top view of a third first texture feature provided in an embodiment of the present disclosure; fig. 13 is a microscopic cross-sectional view of a first texture provided in an embodiment of the present disclosure.

In some embodiments, a solar cell may include: the substrate 100, the substrate 100 includes a front surface 101 and a back surface 102 opposite to each other, a plurality of first grooves 110 arranged at intervals along a first direction X and a plurality of second grooves 120 arranged at intervals along a second direction Y are provided on the back surface 102 of the substrate 100, at least one first texture portion 111 is provided on a part of an inner wall of the first grooves 110, the first texture portion 111 is recessed toward the inside of the substrate 100 along an inner wall surface of the first grooves 110 or protrudes toward a direction away from the substrate 100 along a surface of the first grooves 110, at least one second texture portion 121 is provided on a part of an inner wall of the second grooves 120 at intervals, and the second texture portion 121 is recessed toward the inside of the substrate 100 along an inner wall surface of the second grooves 120 or protrudes toward a direction away from the substrate 100 along a surface of the second grooves 120.

The solar cell may further include: the tunneling layer 130, the tunneling layer 130 covers the back surface 102 of the substrate 100, and covers the inner walls of the first recess 110 and the second recess 120.

The solar cell may further include: doped conductive layer 140, doped conductive layer 140 covers the surface of tunneling layer 130 remote from back surface 102.

The solar cell may further include: a passivation layer 150, the passivation layer 150 covering the surface of the doped conductive layer 140 remote from the back surface 102.

The solar cell may further include: the plurality of sub-gates 160 are arranged at intervals along the first direction X, the sub-gates 160 are in one-to-one correspondence with the first grooves 110, and the sub-gates 160 penetrate through the passivation layer 150 opposite to the first grooves 110 to be in contact connection with the doped conductive layer 140.

The solar cell may further include: and a plurality of main grids 170 arranged at intervals along the second direction Y, wherein the main grids 170 are in one-to-one correspondence with the second grooves 120, and the main grids 170 are in contact connection with the auxiliary grids 160.

By arranging the back surface 102 of the substrate 100 with a plurality of first grooves 110 arranged at intervals along the first direction X and a plurality of second grooves 120 arranged at intervals along the second direction Y, the first grooves 110 and the second grooves 120 respectively correspond to the auxiliary grids 160 and the main grids 170 one by one, the auxiliary grids 160 are arranged to correspond to the first grooves 110, so that the auxiliary grids 160 can be recessed towards the inside of the substrate 100, the contact area between the auxiliary grids 160 and the doped conductive layer 140 can be increased, the capability of collecting carriers of the auxiliary grids 160 can be increased, the auxiliary grids 160 are arranged towards the inside of the substrate 100, light incident from the front surface 101 of the substrate 100 can be reflected back to the substrate 100 by the auxiliary grids 160, the utilization rate of the light can be further increased, and through setting up partial inner wall of first recess 110 and being equipped with at least one first texture portion 111, partial inner wall of second recess 120 is equipped with at least one second texture portion 121, can increase the inner wall surface area of first recess 110 and second recess 120, thereby can increase the area of contact of auxiliary grid 160 and doped conducting layer 140 correspondingly, and can also increase the area of contact between main grid 170 and auxiliary grid 160, can reduce the contact resistance of auxiliary grid 160 and doped conducting layer 140 correspondingly, and can reduce the contact resistance between main grid 170 and auxiliary grid 160, through setting up partial inner wall of first recess 110 and being equipped with first texture portion 111 can reduce the interface complex degradation that appears at the inner wall surface of first recess 110, through setting up tunneling layer 130, doped conducting layer 140 and passivation layer 150 and substrate 100 and constitute solar cell jointly.

In some embodiments, the substrate 100 may be a semiconductor substrate, such as silicon, germanium, silicon germanium, or silicon on insulator. The material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, which may be silicon or germanium, for example. The elemental semiconductor material may be in a single crystal state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a single crystal state and an amorphous state, referred to as a microcrystalline state), and for example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The material of the substrate is silicon, and the material of the substrate 100 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The material of the substrate 100 may also be a compound semiconductor material. For example, the material of the substrate 100 may be silicon carbide, an organic material, or a multi-element compound.

In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any of a group v element such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element. The P-type semiconductor substrate is doped with a P-type element, and the P-type doped element may be any one of group iii elements such as boron (B) element, aluminum (Al) element, gallium (Ga) element, and gallium (In) element.

Referring to fig. 1 and 2, in some embodiments, the depth of the first groove 110 is greater than the depth of the second groove 120. The depth of the first groove 110 is set to be greater than the depth of the second groove 120, that is, the depth of the sub-gate 160 toward the substrate 100 is greater than the depth of the main gate 170 toward the substrate 100, the sub-gate 160 has the capability of collecting carriers, and the main gate 170 functions to collect the carriers of the sub-gate 160 onto the main gate 170, which does not have a strong capability of collecting carriers, so that the shallower depth of the second groove 120 can also avoid the main gate 170 from affecting the lateral transmission of the carriers in the solar cell.

With continued reference to fig. 1, in some embodiments, in the direction of the back side 102 toward the front side 101, any one of the first grooves 110 has a depth of 1-10 μm, such as 2 μm, 3 μm, 4 μm, 5 μm, or 9 μm, etc. By providing the first grooves 110 to be recessed toward the substrate 100 so that light emitted from the back surface 102 can be reflected back to the substrate 100 through the sub-grids 160, the depth of the first grooves 110 is set to be 1-10 μm, so that the sub-grids 160 can be recessed toward the substrate 100 to a certain depth while avoiding the depth of the first grooves 110 from being too deep, and the lateral transmission capability in the solar cell is prevented from being affected.

It can be appreciated that if the depth of the first groove 110 is less than 1 μm, the depth of the first groove 110 is too shallow, the ability to improve the contact area between the sub-gate 160 and the doped conductive layer 140 is not strong, and the ability to reflect the light emitted from the back surface 102 back to the substrate 100, and to improve the light utilization in the solar cell is not strong; if the depth of the first groove 110 is greater than 10 μm, the depth of the first groove 110 is too deep, which reduces the thickness of the substrate 100 corresponding to the first groove 110, and the first groove 110 affects the lateral transport of carriers in the substrate 100.

In some embodiments, the depth of the first groove 110 may be 2-3 μm, and by setting the depth of the first groove 110 to 2-3 μm, the contact area between the sub-gate 160 and the doped conductive layer 140 may be increased, and at the same time, a certain light emitted from the back surface 102 may be reflected back to the substrate 100, and the capability of the first groove 110 to affect the lateral transmission of carriers in the substrate 100 may be reduced.

Referring to fig. 2, in some embodiments, in the direction of the back surface 102 toward the front surface 101, the depth of any second groove 120 is 1 to 5 μm, for example, 1 μm, 2 μm, 3 μm, or 4 μm, etc., it is understood that by providing the second groove 120 to be recessed toward the substrate 100, so that the light emitted from the back surface 102 can be reflected back to the substrate 100 through the main grid 170, the light utilization efficiency of the solar cell can be improved, and by providing the depth of the second groove 120 to be 1 to 5 μm, the main grid 170 can be recessed toward the substrate 100 to have a certain depth while avoiding the depth of the first groove 110 from being too deep, thereby avoiding affecting the lateral transmission capability in the solar cell.

It will be appreciated that if the depth of the second recess 120 is less than 1 μm, the depth of the second recess 120 is too shallow, the ability to reflect light emitted from the back surface 102 back to the substrate 100 through the main gate 170 is not strong, and if the depth of the second recess 120 is greater than 5 μm, the depth of the second recess 120 is too deep, such that the main gate 170 impedes the lateral transport of carriers within the substrate 100, which in turn reduces the reliability of the solar cell.

In some embodiments, the depth of the second groove 120 may be 1-2 μm, and by providing the depth of the second groove 120 to be 1-2 μm, the ability to reflect light emitted from the back surface 102 back to the substrate 100 through the main grid 170 may be increased, while also avoiding the depth of the second groove 120 from being too deep, thereby avoiding affecting the lateral transmission capability of the solar cell.

In some embodiments, the depth of the first groove 110 and the depth of the second groove 120 may be the same. The first and second grooves 110 and 120 may be formed using the same process by setting the depth of the first groove 110 to be the same as the depth of the second groove 120, so that the entire solar cell manufacturing process may be facilitated.

In some embodiments, the depth of the first groove 110 and the depth of the second groove 120 may be the same, and the shape and size of the first texture portion 111 on the inner wall of the first groove 110 and the shape and size of the second texture portion 121 on the inner wall of the second groove 120 may be the same, so that the first groove 110 and the second groove 120 may be formed simultaneously, and the first texture portion 111 and the second texture portion 121 may be formed in the same process step, so that the process difficulty of the whole solar cell may be reduced, and the process steps of solar cell preparation may be reduced.

In some embodiments, the provision of at least one first texture 111 on a portion of the inner wall of the first groove 110 may mean that: a first textured portion 111 is provided on any one or any two of the inner walls of the first groove 110, or a first textured portion 111 is provided on all the inner walls of the first groove 110; the provision of at least one second texture portion 121 on a portion of the inner wall of the second groove 120 may mean that: the second textured portion 121 is provided on any one of the inner walls of the second groove 120, or the second textured portion 121 is provided on all the inner walls of the second groove 120.

It will be appreciated that the first textured portion 111 is recessed toward the substrate 100 along the surface of the first groove 110, or protrudes toward the direction away from the substrate 100 along the surface of the first groove 110, so that the surface of the doped conductive layer 140 facing the first groove 110 formed later also has a textured pattern corresponding to the first textured portion 111, and the surface of the sub-gate 160 facing the first groove 110 also has a textured pattern, so that the contact area between the sub-gate 160 and the doped conductive layer 140 is increased, and therefore, the greater the number of the first textured portions 111, the greater the contact area between the sub-gate 160 and the doped conductive layer 140 is increased, the greater the capability of reducing the contact resistance between the sub-gate 160 and the doped conductive layer 140 is increased, however, the greater the number of the first textured portions 111 may cause the interface composite to be deteriorated, and thus, by providing a portion of the inner wall of the first groove 110 with the first textured portion 111, the contact resistance between the sub-gate 160 and the doped conductive layer 140 is reduced.

In some embodiments, the ratio of the orthographic projection area of any first texture portion 111 on the inner wall of the first groove 110 to the surface area of the inner wall of the first groove 110 is a first ratio, the ratio of the orthographic projection area of any second texture portion 121 on the inner wall of the second groove 120 to the surface area of the inner wall of the second groove 120 is a second ratio, and the first ratio is different from the second ratio. It is understood that the first recess 110 corresponds to the sub-gate 160, the sub-gate 160 is used for collecting carriers in the substrate 100, the second recess 120 corresponds to the main gate 170, and the main gate 170 is used for collecting carriers collected on the sub-gate 160, which are not the same, so that the first ratio and the second ratio are different. In some embodiments, the first ratio and the second ratio may also be the same.

It should be noted that, there are three inner walls on the inner wall of the first groove 110, and similarly, there may be corresponding first texture portions 111 on all three inner walls, where the first ratio refers to: the ratio of the sum of the orthographic projection areas of the first texture parts 111 on the three inner walls to the sum of the surface areas of the three inner walls; corresponding second texture portions 121 may be present on all three inner walls of the second groove 120, where the second ratio refers to: the ratio of the sum of the orthographic projection areas of the second texture parts 121 on the three inner walls to the sum of the surface areas of the three inner walls.

In some embodiments, the first ratio is 20% to 80%, e.g., 30%, 40%, 50%, 60%, or 70%, etc., and the second ratio is 50% to 95%, e.g., 55%, 65%, 75%, or 85%, etc.

It is understood that the sub-gate 160 corresponding to the first groove 110 needs to be in contact with the substrate 100, and by setting the first ratio to 20% -80%, the contact area between the sub-gate 160 and the substrate 100 can be increased, and at the same time, the series resistance of the solar cell can be reduced, and the interface passivation deterioration between the sub-gate 160 and the substrate 100 can be avoided.

If the first ratio is less than 20%, the effect of increasing the contact area between the sub-gate 160 and the substrate 100 may be poor, and if the first ratio is greater than 80%, the contact area between the sub-gate 160 and the substrate 100 may be excessively large, resulting in deterioration of interface passivation, which is rather disadvantageous for improving the performance of the solar cell.

The main gate 170 corresponding to the second groove 120 may not need to take charge of collecting carriers, so that there may be no fear of deterioration of interface passivation, and thus the contact area between the main gate 170 and the sub-gate 160 may be further increased and the contact resistance between the main gate 170 and the sub-gate 160 may be reduced by correspondingly increasing the second ratio, that is, the second ratio may be set to 50% to 95%.

In some embodiments, the maximum dimension of the first texture portion 111 in the direction of the back surface 102 towards the front surface 101 is 200nm to 2 μm, for example 300nm, 500nm, 700nm or 1 μm, etc. It will be appreciated that, here, in the direction of the back surface 102 toward the front surface 101, the maximum dimension of the first textured portion 111, that is, the maximum depth of the first textured portion 111, the greater the contact area between the sub-gate 160 and the doped conductive layer 140, and the greater the contact resistance between the reduced sub-gate 160 and the doped conductive layer 140, however, the larger the dimension of the first textured portion 111 may affect the substrate 100 and affect the lateral transmission within the substrate 100. By setting the maximum size of the first textured portion 111 to be 200nm to 2 μm, the contact area of the sub-gate 160 and the doped conductive layer 140 can be increased while avoiding affecting lateral transmission within the substrate 100.

If the maximum size of the first texture portion 111 is less than 200nm, the contact area between the sub-gate 160 and the doped conductive layer 140 is increased too little, and the capability of improving the contact resistance between the sub-gate 160 and the doped conductive layer 140 is also smaller; if the maximum size of the first texture portion 111 is greater than 2 μm, the first texture portion 111 may affect the lateral transport of carriers within the substrate 100, which may in turn affect the performance of the solar cell.

Referring to fig. 7, 8, 12 and 13, in some embodiments, the first texture portion 111 is recessed toward the inside of the substrate 100 along the surface of the first groove 110, and the orthographic projection of the surface of the first groove 110 of the first texture portion 111 is circular. In other words, the first texture portion 111 is a hemispherical recess. By providing the first texture portion 111 to be recessed toward the substrate 100 along the surface of the first groove 110, and the orthographic projection of the surface of the first groove 110 of the first texture portion 111 is circular, the first texture portion 111 can be formed conveniently, and the contact area between the sub-gate 160 and the doped conductive layer 140 can be increased as much as possible through the first texture portion 111.

In some embodiments, the orthographic projection of the first texture portion 111 on the surface of the first groove 110 is circular, and the orthographic projection of the first texture portion 111 on the surface of the substrate 100 has a diameter of 300nm to 2.5 μm. That is, by providing the opening diameter of the first texture portion 111 on the surface of the first groove 110 in the substrate 100 within a range of 300nm to 2.5 μm, on one hand, the first texture portion 111 on the inner wall of the first groove 110 has a larger specific surface area, so that the contact area between the sub-gate 160 and the doped conductive layer 140 is larger, and further, the contact resistance is reduced, and on the other hand, in this range, the concave-convex surface of the back surface 102 of the substrate 100 corresponding to the first groove 110 has a lower reflectivity for incident light, so that the substrate 100 can absorb the incident light better.

Referring to fig. 6 and 11, in some embodiments, the first texture portion 111 is recessed along the surface of the first groove 110 toward the inside of the substrate 100, and the orthographic projection of the first texture portion 111 on the surface of the first groove 110 is a mixture of a circle and a square. In other words, the first texture 111 is a mixture of hemispherical grooves and square pits. The mixing of the first texture portion 111 with grooves and pits may increase the ability to reduce contact resistance more than the mixing of the first texture portion 111 with grooves and pits.

Referring to fig. 10, in some embodiments, the first texture part 111 protrudes along the surface of the first groove 110 toward away from the substrate 100, and the front projection of the first texture part 111 on the surface of the first groove 110 is square. In other words, the first texture 111 is a tower base topography. The contact area of the sub-gate 160 and the doped conductive layer 140 can also be increased by providing the first textured portion 111 with a tower-like topography.

It should be noted that, the tower foundation shape is the part of the pyramid shape which is remained after the tower tip is removed, and the hemispherical shape, the round shape and the square shape can refer to standard hemispherical shape, round shape and square shape, and can be quasi-hemispherical shape, 1/3 spherical shape, quasi-round shape, quasi-elliptic shape, quasi-square shape and the like.

In some embodiments, the front projection of the first texture portion 111 on the surface of the first groove 110 is square, the side length of the front projection of the first texture portion 111 on the surface of the substrate 100 is 200 nm-2 μm, for example 300nm, 500nm, 700nm or 1 μm, and the like, and by setting the side length of the front projection of the first texture portion 111 on the surface of the substrate 100 to be 200 nm-2 μm, on one hand, the first texture portion 111 on the inner wall of the first groove 110 has a larger specific surface area, so that the contact area between the sub-gate 160 and the doped conductive layer 140 is larger, and the contact resistance is further reduced, on the other hand, in this range, the reflectivity of the incident light on the concave-convex surface of the back surface 102 of the substrate 100 corresponding to the first groove 110 can be lower, so that the incident light can be better absorbed by the substrate 100.

In some embodiments, the orthographic projection of the second texture portion 121 on the surface of the second groove 120 may be a circle, a square, or a mixture of a circle and a square, which may be the same as the first texture portion 111, and the description of the second texture portion 121 is referred to in the above description and will not be repeated here.

In some embodiments, the second textured portion 121 may have the same size as the first textured portion 111, in other words, the second textured portion 121 and the first textured portion 111 may be formed using the same process, so that the process difficulty of the entire solar cell may be reduced.

In some embodiments, the size of the second textured portion 121 may also be different from the size of the first textured portion 111. The size of the second texture part 121 may be different from the size of the first texture part 111 by providing the second texture part 121, so that the size of the second texture part 121 may be selected correspondingly according to the actual situation.

Referring to fig. 3, in some embodiments, a portion of the surface of the back surface 102 of the substrate 100 other than the first recess 110 and the second recess 120 includes a plurality of third texture portions 112, each third texture portion 112 protrudes away from the substrate 100, and the orthographic projection of the third texture portion 112 on the surface of the substrate 100 is square. By providing the rear surface 102 of the substrate 100 including a plurality of third texture parts 112 not being part of the surfaces of the first and second grooves 110 and 120, the light absorption capability of the solar cell can be improved, and the photoelectric conversion efficiency of the solar cell can be improved.

In some embodiments, the area of orthographic projection of any one of the third texture portions 112 on the surface of the substrate 100 is larger than the area of orthographic projection of any one of the first texture portions 111 on the surface of the first groove 110. In other words, the size of the tower base morphology of the first texture portion 111 is smaller than that of the third texture portion 112, the smaller the tower base morphology of the first texture portion 111, the larger the number of first texture portions 111 that can be formed, and the larger the contact area between the sub-gate 160 and the doped conductive layer 140 is, so that the contact resistance between the sub-gate 160 and the doped conductive layer 140 can be further reduced.

It should be noted that, the orthographic projection shapes of the first texture portion 111, the second texture portion 112, and the third texture portion 112 on the surface of the substrate 100 are determined by the spot shape formed by the laser beam in the laser process after focusing, and the laser beam having the different shape of the spot can be formed by adjusting the parameters of the laser process.

Referring to fig. 5, the first grooves 110 between the adjacent second grooves 120 include a middle portion 113 and end portions 114 at opposite sides of the middle portion 113, and the roughness of the surface of the middle portion 113 is smaller than that of the end portions 114.

It will be appreciated that, since the first grooves 110 intersect the second grooves 120, there must be a portion of the first grooves 110 between two adjacent second grooves 120, the portion of the first grooves 110, that is, the first grooves 110 located between two adjacent second grooves 120, dividing the portion of the first grooves 110 into two side end portions 114 and a middle portion 113 between the two side end portions 114, the second grooves 120 corresponding to the main gate 170, the first grooves 110 corresponding to the sub-gate 160, the closer to the main gate 170, the higher the concentration of the collected carriers, the farther from the main gate 170, the lower the concentration of the collected carriers, and therefore, by providing a small roughness on the surface of the middle portion 113, the lower the composite current density can be ensured while the contact benefit can be further improved by providing a large roughness on the end portions 114.

In some embodiments, the middle portion 113 may be a portion that occupies 3/5 of the volume of the first groove 110 between adjacent second grooves 120, and the two side end portions 114 may each occupy 1/5 of the volume of the first groove 110 between adjacent second grooves 120.

It should be noted that, the shape of the sub-gate 160 is shown in fig. 5, the sub-gate 160 is formed in the first groove 110, the shape of the sub-gate 160 is affected by the first groove 110, the shape of the inner wall of the first groove 110 can be reflected by the shape of the sub-gate 160, and the middle portion 113 and the end portion 114 in the drawings actually belong to the first groove 110, but here, for the sake of more clear schematic structure, reference numerals of the middle portion 113 and the end portion 114 are labeled on the sub-gate 160.

In some embodiments, the roughness of the inner wall surface of the first groove 110 increases gradually from the direction away from the second groove 120 toward the direction toward the second groove 120.

It will be appreciated that the second recess 120 corresponds to the main gate 170, and the first recess 110 corresponds to the sub-gate 160, and the closer to the main gate 170, the higher the concentration of the collected carriers, so that the roughness of the side of the first recess 110 close to the second recess 120 is set to be large, so that the contact area of the portion of the sub-gate 160 close to the main gate 170 can be further increased, and although the area composite current density can be increased, the contact benefit can be greater than the negative benefit of the increase of the composite current density on the premise of enriching a large amount of carriers; the carrier density is lower in the position of keeping away from the main grid 170, so can set up that first recess 110 keeps away from second recess 120 one side roughness is little to can guarantee to keep away from the partial compound current density low of main grid 170 when improving certain area of contact, moreover, through setting up the roughness of first recess 110 inner wall surface from keeping away from second recess 120 towards being close to the direction of second recess 120 in the gradual increase can make first recess 110 inner wall change mild, avoid the transmission of carrier to appear unusual in auxiliary grid 160, improve solar cell's reliability.

The roughness of the inner wall of the first groove 110 is smaller as the first texture portion 111 is flatter, and the roughness of the inner wall of the first groove 110 is larger as the surface of the first texture portion 111 is rougher.

Referring to fig. 6, in some embodiments, the shapes of the first texture portions 111 on the inner walls of the portions of the first grooves 110 are the same, the shapes of the first texture portions 111 on the inner walls of the portions of the first grooves 110 are different, in other words, the shapes of the portions of the sub-grids 160 are the same, the shapes of the portions of the sub-grids 160 are different, the projection of the portions of the sub-grids 160 corresponding to the first texture portions 111 on the substrate 100 may be circular, the projection of the portions of the sub-grids 160 corresponding to the first texture portions 111 on the substrate 100 may be square, and the projection of the portions of the sub-grids 160 corresponding to the first texture portions 111 on the substrate 100 may be a mixture of circular and square; in some embodiments, the first texture 111 on the inner wall of the first groove 110 is of varying topography.

In some embodiments, the shapes of the first texture portions 111 on the inner wall of the portion of the first groove 110 are the same, the shapes of the first texture portions 111 on the inner wall of the portion of the first groove 110 are different, the ratio of the orthographic projection area of any one first texture portion 111 on the inner wall of the first groove 110 to the surface area of the inner wall of the first groove 110 is a first ratio, the first texture portions 111 with the same shape are the same as the first ratio of the first groove 110, and the first ratio of the first texture portions 111 with different shapes to the first groove 110 is different.

Referring to fig. 4, in some embodiments, the substrate 100 includes edge regions 103 at both ends and a middle region 104 between the two edge regions 103; wherein the depth of the first groove 110 in the edge region 103 is greater than the depth of the first groove 110 in the middle region 104, and the depth of the second groove 120 in the edge region 103 is greater than the depth of the second groove 120 in the middle region 104.

It can be understood that the edge region 103 of the solar cell is a portion of the solar cell that is easily damaged, and by providing the first groove 110 and the second groove 120 in the edge region 103 to be deeper, the reliability of the main gate 170 and the sub-gate 160 in the edge region 103 can be improved, and since the depths of the sub-gate 160 and the main gate 170 in the edge region 103 are deeper, the probability of affecting the sub-gate 160 and the main gate 170 is smaller, and the reliability of the solar cell can be further improved.

It should be noted that, the edge region 103 may refer to an edge of the substrate 100, and the surface area accounts for 1/5 of the surface area of the back surface 102 of the substrate 100, and the middle region 104 may refer to a center of the substrate 100, and the surface area accounts for 3/5 of the surface area of the back surface 102 of the substrate 100.

In some embodiments, the tunneling layer 130 and the doped conductive layer 140 may form a passivation contact structure on the surface of the substrate 100, and the tunneling layer 130 and the doped conductive layer 140 may reduce the recombination of carriers on the surface of the cell, and increase the open-circuit voltage of the cell, so as to improve the efficiency of the solar cell.

In some embodiments, the tunneling layer 130 may be located only on the back surface 102 of the substrate 100, and the tunneling layer 130 may also be located on both the back surface 102 and the front surface 101 of the substrate 100.

The front surface 101 herein may refer to a light receiving surface of a solar cell, and the back surface 102 herein may refer to a backlight surface of a solar cell.

In some embodiments, the tunneling layer 130 may also be used to mitigate or prevent diffusion of dopant ions of the doped conductive layer 140 into the substrate 100.

In some embodiments, the material of the tunneling layer 130 may include, but is not limited to, dielectric materials having tunneling effect such as aluminum oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polycrystalline silicon. Specifically, the tunneling layer 130 may be formed of a silicon oxide layer including silicon oxide (SiOx), which has good passivation characteristics, and carriers may easily tunnel through the silicon oxide layer.

In some embodiments, the thickness of the tunneling layer 130 may be 0.5nm to 2.5nm, alternatively, the thickness of the tunneling layer 130 is 0.5nm to 2nm, and further, the thickness of the tunneling layer 130 is 0.5nm to 1.2nm. When the thickness of the tunneling layer 130 is less than 0.5mm, the process difficulty of forming the tunneling layer 130 is high; when the thickness of the tunneling layer 130 is greater than 2.5mm, the tunneling effect is weak.

In some embodiments, the material of doped conductive layer 140 may be one of doped amorphous silicon, doped polysilicon, or doped microcrystalline silicon material. In other embodiments, the doped conductive layer 140 may be made of other materials, and may be selected according to practical situations, for example, silicon carbide.

In some embodiments, the doped conductive layer 140 may be formed by first forming a conductive layer on the surface of the tunneling layer 130 and then doping the conductive layer to form the doped conductive layer 140.

In some embodiments, the thickness of the doped conductive layer 140 ranges from 40nm to 150nm, alternatively, the thickness of the doped conductive layer 140 ranges from 60nm to 90nm, and the thickness of the doped conductive layer 140 can ensure that the optical loss of the doped conductive layer 140 is small and the interface passivation effect of the tunneling layer 130 is good, thereby improving the cell efficiency. The material of doped conductive layer 140 in embodiments of the present application may be polysilicon.

In some embodiments, the doping type of the doped conductive layer 140 is the same as the doping type of the substrate 100, and it is understood that when the doping type of the substrate 100 is N-type and the doping type of the doped conductive layer 140 is P-type, the electrons of the substrate 100 and the holes of the doped conductive layer 140 are holes, and the holes are directly ablated in a recombination manner therebetween, so that the carriers collected by the sub-gate 160 are reduced, and therefore, the doping type of the doped conductive layer 140 is the same as the doping type of the substrate 100, so that the carriers collected by the sub-gate 160 can be prevented from being reduced.

In some embodiments, the substrate 100 is an N-type base and the doped conductive layer 140 is an N-type polysilicon layer; in other embodiments, the substrate may be a P-type substrate, and the doped conductive layer is a P-type polysilicon layer. The N-type substrate and the N-type polysilicon layer have high photoelectric conversion efficiency, the P-type substrate and the P-type polysilicon layer are formed by simple processes, and can be selected according to practical situations, and the embodiment of the application does not limit the substrate 100 and the doped conductive layer 140.

In some embodiments, the bottom surfaces of the sub-gate 160 and the main gate 170 away from the front surface 101 are lower than the bottom surface of the passivation layer 150, in other words, the sub-gate 160 and the main gate 170 protrude from the passivation layer 150. In some embodiments, the thickness of the sub-gate 160 and the main gate 170 may be 5 to 15 μm, and the thickness of the passivation layer 150 may be 70 to 90nm.

In some embodiments, the passivation layer 150 may be an anti-reflective film layer, so that the emitted light of the solar cell surface may be reduced, thereby increasing the light transmission of the solar cell, the passivation layer 150 may be a single-layer structure or a stacked-layer structure, and the material of the passivation layer 150 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide. In some embodiments, passivation layer 150 is a hydrogen-containing passivation layer, such as silicon hydroxide, silicon nitride, silicon oxynitride, or the like.

In some embodiments, the sub-grid 160 is used to collect and summarize carriers of the solar cell, and the material of the sub-grid 160 may be one or more of aluminum, silver, gold, nickel, molybdenum, or copper. In some cases, the sub-gate 160 refers to a thin gate line or a finger-shaped gate line to distinguish from a main gate electrode line or a bus bar.

In some embodiments, the primary gate 170 is used to collect carriers collected on the secondary gate 160 and to lead out of the solar cell.

In some embodiments, the material of the auxiliary gate 160 is different from the material of the main gate 170, for example, the material of the auxiliary gate 160 may be a burn-through paste, the material of the main gate 170 may be a non-burn-through paste, and the material of the auxiliary gate 160 may be a burn-through paste, so that the first groove 110 with a deeper depth may be matched, thereby not only taking into account the capability of the auxiliary gate 160 to collect carriers, but also increasing the contact area between the auxiliary gate 160 and the doped conductive layer 140, and the material of the main gate 170 may be a non-burn-through paste, so as to avoid the influence of the main gate 170 on the lateral transmission of carriers by the second groove 120 with a shallower depth.

In some embodiments, an emitter 180 and a front passivation layer 190 are also sequentially provided on the front side 101 of the substrate 100.

In some embodiments, the dopant ion type in emitter 180 is different from the dopant ion type in substrate 100, e.g., the dopant ion type in emitter 180 is N-type, then the dopant ion type in substrate 100 is P-type; the dopant ion type in the emitter 180 is P-type and then the dopant ion type in the substrate 100 is N-type to form a PN junction in the emitter 180 and the substrate 100.

In some embodiments, the front passivation layer 190 may be a single layer structure or a stacked structure. The material of the front passivation layer 190 may be the same as that of the passivation layer 150, and may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide. In some embodiments, the front side passivation layer 190 may also be a hydrogen-containing passivation layer, such as silicon hydroxide, silicon nitride, silicon oxynitride, or the like. The open circuit voltage, the short circuit current, and the fill factor of the solar cell can be increased by providing the front side passivation layer 190.

A front electrode 200 is further disposed on the front surface of the substrate 100, and the front electrode 200 penetrates through the front passivation layer 190 to be in contact connection with the emitter 180.

In some embodiments, the front side 101 of the substrate 100 is a pyramidal textured surface, and thus the front passivation layer 190 and the emitter 180 on the front side 101 are both pyramidal textured surfaces. The front surface of the substrate 100 is provided with the pyramid suede, so that the reflectivity of the substrate 100 to incident light is smaller, the absorption and utilization rate of the incident light is larger, and the photoelectric conversion efficiency of the solar cell is higher.

Another embodiment of the present disclosure further provides a photovoltaic module, where the photovoltaic module includes a solar cell in some or all of the foregoing embodiments, and the description of the photovoltaic module provided in another embodiment of the present disclosure will be given below with reference to the accompanying drawings, where the description of the same or corresponding portions of the foregoing embodiments may refer to the corresponding descriptions of the foregoing embodiments, and the description will not be repeated below.

In some embodiments, referring to fig. 14, another aspect of an embodiment of the present application also provides a photovoltaic module for converting received light energy into electrical energy and transmitting to an external load. The photovoltaic module includes: at least one cell string formed by connecting a plurality of solar cells 10 in some or all of the above embodiments; a packaging adhesive film 21 for covering the surface of the battery string; and a cover plate 22 for covering the surface of the packaging adhesive film 21 facing away from the battery strings.

The packaging adhesive film 21 may be an organic packaging adhesive film such as EVA or POE, and the packaging adhesive film 21 covers the surface of the battery string to seal and protect the battery string.

In some embodiments, the encapsulation film 21 includes an upper encapsulation film and a lower encapsulation film respectively covering both sides of the surface of the battery string.

The cover plate 22 may be a glass cover plate or a plastic cover plate, etc. for protecting the battery strings, and the cover plate 22 covers the surface of the packaging adhesive film 21 facing away from the battery strings. In some embodiments, light trapping structures are provided on the cover plate 22 to increase the utilization of the incident light. The photovoltaic module has higher current collection capability and lower carrier recombination rate, and can realize higher photoelectric conversion efficiency. In some embodiments, the cover 22 includes an upper cover and a lower cover on either side of the battery string.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A solar cell, comprising:

the substrate comprises a front surface and a back surface which are opposite, wherein the back surface of the substrate is provided with a plurality of first grooves which are arranged at intervals along a first direction and a plurality of second grooves which are arranged at intervals along a second direction, part of inner walls of the first grooves are provided with at least one first texture part, the first texture part is recessed towards the inside of the substrate along the inner wall surfaces of the first grooves or protrudes towards the direction away from the substrate along the surfaces of the first grooves, part of inner walls of the second grooves are provided with at least one second texture part at intervals, and the second texture part is recessed towards the inside of the substrate along the inner wall surfaces of the second grooves or protrudes towards the direction away from the substrate along the surfaces of the second grooves;

A tunneling layer covering the back surface of the substrate and covering inner walls of the first and second grooves;

a doped conductive layer covering a surface of the tunneling layer remote from the back surface;

a passivation layer covering a surface of the doped conductive layer remote from the back surface;

the auxiliary grids are arranged at intervals along the first direction, correspond to the first grooves one by one, penetrate through the passivation layer opposite to the first grooves and are in contact connection with the doped conductive layer;

the main grids are arranged at intervals along the second direction, correspond to the second grooves one by one, and are in contact connection with the auxiliary grids.

2. The solar cell according to claim 1, wherein a ratio of an orthographic projection area of any one of the first texture portions on the first groove inner wall to a surface area of the first groove inner wall is a first ratio, and a ratio of an orthographic projection area of any one of the second texture portions on the second groove inner wall to a surface area of the second groove inner wall is a second ratio, the first ratio being different from the second ratio.

3. The solar cell according to claim 2, wherein the first ratio is 20% to 80% and the second ratio is 50% to 95%.

4. The solar cell of claim 1, wherein the first textured portion is recessed toward the substrate and an orthographic projection of the first textured portion on the first groove surface is circular.

5. The solar cell of claim 1, wherein the first textured portion is recessed toward the substrate and an orthographic projection of the first textured portion on the first groove surface is a mixture of circular and square shapes.

6. The solar cell according to claim 1, wherein the first textured portion protrudes in a direction away from the substrate, and an orthographic projection of the first textured portion on the first groove surface is square.

7. The solar cell of claim 6, wherein a portion of the back surface of the substrate other than the first and second grooves includes a plurality of third textured portions, each of the third textured portions protruding away from the substrate, and wherein the orthographic projection of the third textured portions on the substrate surface is square.

8. The solar cell according to claim 7, wherein an area of orthographic projection of any one of the third texture portions on the surface of the substrate is larger than an area of orthographic projection of any one of the first texture portions on the surface of the first groove.

9. The solar cell of claim 1, wherein the first grooves between adjacent second grooves include a middle portion and end portions on opposite sides of the middle portion, and wherein the roughness of the middle portion surface is less than the roughness of the end portions surfaces.

10. The solar cell according to claim 1, wherein the roughness of the inner wall surface of the first groove gradually increases from a direction away from the second groove toward a direction closer to the second groove.

11. The solar cell of claim 1, wherein the substrate comprises edge regions at both ends and an intermediate region between the two edge regions; the depth of the first groove corresponding to the edge area is larger than that of the first groove corresponding to the middle area.

12. The solar cell of claim 1, wherein the depth of the first groove is the same as the depth of the second groove.

13. The solar cell of claim 1, wherein the depth of the first groove is greater than the depth of the second groove.

14. A photovoltaic module, comprising:

a cell string comprising the solar cell of any one of claims 1 to 13;

an encapsulation layer for covering the surface of the battery string;

and the cover plate is used for covering the surface, far away from the battery strings, of the packaging layer.