CN116682822A

CN116682822A - Semiconductor device and forming method

Info

Publication number: CN116682822A
Application number: CN202310511663.9A
Authority: CN
Inventors: 张正伟; 沙哈吉·B·摩尔; 谭伦光; 周其雨; 白岳青
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-10
Filing date: 2023-05-08
Publication date: 2023-09-01

Abstract

The nanostructure transistor may be formed in a manner that may reduce the likelihood of source/drain regions merging in the nanostructure transistor. In a top view of the nanostructured transistors described herein, the source/drain regions on opposite sides of the nanostructured channel of the nanostructured transistor are staggered such that the distance between the source/drain regions increases. This reduces the likelihood of source/drain region merging, which reduces the likelihood of failure and/or other defects forming in the nanostructured transistor. Accordingly, staggering the source/drain regions, as described herein, may facilitate miniaturization of semiconductor devices including nanostructured transistors while maintaining and/or increasing semiconductor device yield of the semiconductor devices. Embodiments of the present application provide a semiconductor device and a method of forming.

Description

Semiconductor device and forming method

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming.

Background

As semiconductor device fabrication advances and technology process node sizes decrease, transistors may be affected by Short Channel Effects (SCE) such as hot carrier degradation, barrier lowering, and quantum confinement, among other examples. In addition, as the gate length of the transistor for smaller technology nodes decreases, source/drain (S/D) electron tunneling increases, which increases the off-current of the transistor (the current flowing through the channel of the transistor when the transistor is in the off configuration). Silicon (Si)/silicon germanium (SiGe) nanostructure transistors, such as nanowires, nanoplates, and full-gate-all-around (GAA) devices, are potential candidates for overcoming short channel effects on smaller technology nodes. Nanostructured transistors are efficient structures that can withstand reduced SCE and increased carrier mobility relative to other types of transistors.

Disclosure of Invention

Some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of channel layers arranged along a first direction over a semiconductor substrate. The semiconductor device includes a gate structure surrounding each of the plurality of channel layers. The semiconductor device includes a first source/drain region adjacent a first side of the plurality of channel layers. The semiconductor device includes a second source/drain region adjacent a second side of the plurality of channel layers, the second side opposite the first side along a second direction that is substantially perpendicular to the first direction, wherein the first side and the second side are offset a distance along a third direction in the semiconductor device that is substantially perpendicular to the first direction and the second direction in a top view of the semiconductor.

Some embodiments described herein provide a semiconductor device. The semiconductor device includes an NMOS active region including a first plurality of nanoplatelets positioned over a semiconductor substrate. The semiconductor device includes a PMOS active region 208b, the PMOS active region 208b including a second plurality of nanoplatelets located over the semiconductor substrate. The semiconductor device includes an isolation region between the NMOS active region and the PMOS active region, the isolation region including a third plurality of nanoplatelets located over the semiconductor substrate. The semiconductor device includes a respective gate structure surrounding each of the first, second, and third pluralities of nanoplatelets, wherein the third plurality of nanoplatelets flex between the NMOS region and the PMOS region in a top view of the semiconductor device.

Some embodiments described herein provide a method of forming a semiconductor device. The method includes forming a nanoplatelet stack including a first plurality of nanoplatelets and a second plurality of nanoplatelets alternating with the first plurality of nanoplatelets. The method includes forming a first semiconductor device region, a second semiconductor device region, and a transition region extending between the first semiconductor device region and the second semiconductor device region along a first direction in a top view of the semiconductor device, wherein the first semiconductor device region and the second semiconductor device region are staggered along a second direction that is substantially perpendicular to the first direction in the top view of the semiconductor device. The method includes forming a dummy gate structure over the transition region. The method includes forming NMOS source/drain regions in a first semiconductor device region in the nanoplatelet stack. The method includes forming PMOS source/drain regions in a second semiconductor device region in the nanoplatelet stack.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of an exemplary environment in which the systems and/or methods described herein may be implemented;

FIG. 2 is a schematic diagram of an exemplary semiconductor device described herein;

fig. 3A and 3B are schematic diagrams of exemplary embodiments of portions of a semiconductor device described herein;

4A-4C are schematic diagrams of exemplary embodiments of various dimensions of the semiconductor devices described herein;

fig. 5A and 5B are schematic diagrams of exemplary embodiments of portions of a semiconductor device described herein;

6A-6F are schematic diagrams of exemplary embodiments described herein;

fig. 7 is a schematic diagram of an exemplary embodiment of a semiconductor device described herein;

FIGS. 8A and 8B are schematic diagrams of exemplary embodiments described herein;

fig. 9 is a schematic diagram of an exemplary embodiment of a semiconductor device described herein;

FIG. 10 is a schematic diagram of exemplary components of a device described herein;

fig. 11 is a flow chart of an exemplary process associated with forming a semiconductor device.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "under …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In some cases, reducing the geometry and dimensional characteristics of fin field effect transistors (finfets) may reduce the performance of the finfets. As an example, as finFET technology processing nodes decrease, the likelihood of short channel effects such as drain induced barrier lowering in finfets may increase. Additionally or alternatively, as the gate length of the finFET decreases, the likelihood of electron tunneling and leakage in the finFET may increase.

Nanostructured transistors (e.g., nanowire transistors, nanoplatelet transistors, full-gate-all (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and/or other types of nanostructured transistors) may overcome one or more of the shortcomings of finfets described above. However, nanostructured transistors face manufacturing challenges that can lead to performance problems and/or device failure.

For example, semiconductor device yield is a challenge in the fabrication of nanostructured transistors. Miniaturization of semiconductor devices, such as Complementary Metal Oxide Semiconductor (CMOS) devices and other types of semiconductor devices including nanostructured transistors, can enable greater semiconductor device yields on a single wafer. However, as the size of nanostructure transistors used to support miniaturization of semiconductor devices decreases, increased defect rates may occur due to the merging of two or more structures in the nanostructure transistors and/or adjacent nanostructure transistors. For example, source/drain regions in a nanostructured transistor and/or an adjacent nanostructured transistor may merge, wherein the source/drain regions become physically connected. This may result in electrical shorts in the nanostructure transistor and/or in neighboring nanostructure transistors, which may lead to semiconductor device failure and reduced semiconductor device yield.

Some embodiments described herein provide semiconductor devices and methods of formation that may reduce the likelihood of source/drain region incorporation in nanostructured transistors. The source/drain regions may refer to the source or drain individually or collectively, depending on the context. In a top view of the nanostructured transistors described herein, the source/drain regions on opposite sides of the nanostructured channel of the nanostructured transistor are staggered such that the distance between the source/drain regions increases. This reduces the likelihood of source/drain region merging, which reduces the likelihood of failure and/or other defects forming in the nanostructured transistor. Accordingly, staggering the source/drain regions, as described herein, may facilitate miniaturization of semiconductor devices including nanostructured transistors while maintaining and/or increasing semiconductor device yield of the semiconductor devices.

FIG. 1 is a schematic diagram of an exemplary environment 100 in which the systems and/or methods described herein may be implemented in the exemplary environment 100. As shown in fig. 1, the exemplary environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer/die transfer tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etch tool 108, a planarization tool 110, a plating tool 112, and/or other types of semiconductor processing tools. Tools included in the exemplary environment 100 may be included in semiconductor clean rooms, semiconductor processing facilities, and/or manufacturing facilities, as well as other examples.

The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 comprises a spin-on tool capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, the deposition tool 102 comprises a Chemical Vapor Deposition (CVD) tool, such as a Plasma Enhanced CVD (PECVD) tool, a high density plasma CVD (HDP-CVD) tool, a sub-atmospheric pressure CVD (SACVD) tool, a Low Pressure CVD (LPCVD) tool, an Atomic Layer Deposition (ALD) tool, a Plasma Enhanced Atomic Layer Deposition (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 comprises a Physical Vapor Deposition (PVD) tool, such as a sputtering tool or other type of PVD tool. In some embodiments, the deposition tool 102 comprises an epitaxial tool configured to form layers and/or regions of the device by epitaxial growth. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an Ultraviolet (UV) source (e.g., deep UV light source, extreme UV light (EUV) source, and/or the like), an X-ray source, an electron beam (e-beam) source, and/or the like. The exposure tool 104 may expose the photoresist layer to a radiation source to transfer a pattern from the photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming structures of one or more semiconductor devices, may include patterns for etching portions of semiconductor devices, and/or the like. In some embodiments, the exposure tool 104 includes a scanner, stepper, or similar type of exposure tool.

The development tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the development tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

The etch tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and/or the like. In some embodiments, the etching tool 108 includes a chamber that may be filled with an etchant, and the substrate is placed in the chamber for a specified period of time to remove one or more portions of a specified amount of the substrate. In some embodiments, the etching tool 108 uses plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gas to isotropically or directionally etch the one or more portions. In some embodiments, the etching tool 108 includes a plasma-based asher to remove photoresist material and/or other materials.

The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a Chemical Mechanical Planarization (CMP) tool, and/or other types of planarization tools capable of polishing or planarizing a layer or surface of deposited or plated material. The planarization tool 110 may polish or planarize the surface of the semiconductor device by a combination of chemical and mechanical forces (e.g., chemical etching and free-abrasive polishing). The planarization tool 110 may use abrasive and corrosive chemical slurries in conjunction with polishing pads and retaining rings (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may be rotated about different axes of rotation to remove material and planarize any irregular topography of the semiconductor device so that the semiconductor device is planarized or planarized.

Plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., wafer, semiconductor device, and/or the like) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a composite or alloy (e.g., tin-silver, tin-lead, and/or the like) plating device, and/or a plating device for one or more other types of conductive materials, metals, and/or similar types of materials.

Wafer/die transfer tool 114 includes a mobile robot, robotic arm, tram or rail car, overhead Hoist Transport (OHT) system, automated Material Handling System (AMHS), and/or other type of equipment configured to transfer substrates and/or semiconductor devices between semiconductor processing tools 102-112, to transfer substrates and/or semiconductor devices between processing chambers of the same semiconductor processing tool, and/or to and from other locations such as wafer racks, storage chambers, and/or the like. In some implementations, the wafer/die transfer tool 114 may be a programming device configured to travel a particular path and/or may operate semi-autonomously or autonomously. In some implementations, the exemplary environment 100 includes a plurality of wafer/die transfer tools 114.

For example, in a cluster tool, or in other types of tools that include multiple process chambers, a wafer/die transfer tool 114 may be included, and the wafer/die transfer tool 114 may be configured to transfer substrates and/or semiconductor devices between multiple process chambers, between a process chamber and a buffer, between a process chamber and an interface tool such as an Equipment Front End Module (EFEM), and/or between a process chamber and a transfer carrier (e.g., a Front Opening Unified Pod (FOUP)), among other examples. In some embodiments, a wafer/die transfer tool 114 may be included in the multi-chamber (or cluster) deposition tool 102, and the multi-chamber (or cluster) deposition tool 102 may include a pre-clean process chamber (e.g., for cleaning or removing oxides, oxidizers, and/or other types of contaminants or byproducts from substrates and/or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer/die transfer tool 114 is configured to transfer substrates and/or semiconductor devices between the process chambers of the deposition tool 102 without breaking or removing vacuum (or at least partial vacuum) between the process chambers and/or between processing operations in the deposition tool 102, as described herein.

As described herein, the semiconductor processing tools 102-112 may implement a combination of operations to form one or more portions of a nanostructured transistor. In some implementations, the semiconductor processing tools 102-112 may form a plurality of channel layers arranged along a first direction over a semiconductor substrate of a semiconductor device; a first source/drain region may be formed adjacent a first side of the plurality of channel layers; a second source/drain region may be formed adjacent to a second side of the plurality of channel layers opposite the first side along a second direction substantially perpendicular to the first direction, wherein the first side and the second side are offset in the semiconductor device by a distance along a third direction substantially perpendicular to the first direction and the second direction in a top view of the semiconductor device; and/or a gate structure may be formed around each of the plurality of channel layers.

In some implementations, the semiconductor processing tools 102-112 may form an n-type metal oxide semiconductor (NMOS) active region over a semiconductor substrate of a semiconductor device that includes a first plurality of nanoplatelets; a p-type metal oxide semiconductor (PMOS) active region may be formed over the semiconductor substrate, including a second plurality of nanoplatelets; an isolation region may be formed between the NMOS active region and the PMOS active region that includes a third plurality of nanoplatelets located over the semiconductor substrate; and a respective gate structure surrounding each of the first, second, and third plurality of nanoplatelets may be formed, wherein the third plurality of nanoplatelets is curved between the NMOS region and the PMOS region in a top view of the semiconductor device.

In some embodiments, the semiconductor processing tools 102-112 may form a nano-sheet stack comprising a first plurality of nano-sheets, and a second plurality of nano-sheets alternating with the first plurality of nano-sheets; a first semiconductor device region, a second semiconductor device region, and a transition region may be formed in the nanoplatelet stack, the transition region extending along a first direction between the first semiconductor device region and the second semiconductor device region in a top view of the semiconductor device, wherein the first semiconductor device region and the second semiconductor device region are staggered along a second direction substantially perpendicular to the first direction in a top view of the semiconductor device; a dummy gate structure may be formed over the transition region; NMOS source/drain regions may be formed in the first semiconductor device region in the nanoplatelet stack; and/or PMOS source/drain regions may be formed in the second semiconductor device region in the nanoplatelet stack.

The number and arrangement of devices shown in fig. 1 are provided as one or more examples. Indeed, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown in fig. 1. In addition, two or more devices shown in fig. 1 may be implemented within a single device, or a single device shown in fig. 1 may be implemented as a plurality of distributed devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of the exemplary environment 100 may implement one or more functions described as being implemented by other devices of the exemplary environment 100.

Fig. 2 is a schematic diagram of an exemplary semiconductor device 200 described herein. The semiconductor devices may include logic devices (e.g., processors, central Processing Unit (CPU) cores, graphics Processing Unit (GPU) cores), memory devices (e.g., static Random Access Memory (SRAM) devices), input/output (I/O) devices, and/or other types of semiconductor devices 200.

The semiconductor device 200 includes one or more transistors. The one or more transistors may include nanostructure transistor(s), such as nanowire transistor(s), nanoplatelet transistor(s), full-gate-all-around (GAA) transistor(s), multi-bridge channel transistor(s), nanoribbon transistor(s), and/or other types of nanostructure transistor(s). Semiconductor device 200 may include one or more additional devices, structures, and/or layers not shown in fig. 2. For example, semiconductor device 200 may include additional layers and/or dies formed on layers above and/or below the portion of semiconductor device 200 shown in fig. 2. Additionally or alternatively, one or more additional semiconductor structures and/or semiconductor devices may be formed in the same layer of an electronic device or Integrated Circuit (IC) including the semiconductor device of semiconductor device 200 as shown in fig. 2.

As shown in fig. 2, layers and/or structures of semiconductor device 200 may be described with reference to one or more directions or axes. For example, the X direction may correspond to a substantially horizontal direction in the semiconductor device 200. The Y-direction may correspond to a substantially horizontal direction that is substantially perpendicular to the X-direction. The Z-direction may correspond to a substantially vertical direction in the semiconductor device 200. The Z direction may be substantially perpendicular to the X direction and the Y direction. Fig. 5A, 5B, 6A-6F, 7, 8A and 8B, and 9 may include schematic cross-sectional views of various portions of semiconductor device 200 along one or more of the cross-sections shown in fig. 2. For example, one or more cross-sectional views of semiconductor device 200 may be shown along section A-A shown in fig. 2. The cross section A-A may be in and/or along the X-direction. As another example, one or more cross-sectional views of semiconductor device 200 may be shown along section B-B shown in fig. 2. Section B-B may be in and/or along the X-direction. The sections A-A and B-B may be located at positions along different Y directions in the semiconductor device 200.

Fig. 2 illustrates portions of layers and/or structures of a semiconductor device as seen along section B-B. As shown in fig. 2, the semiconductor device 200 includes a semiconductor substrate 202. The semiconductor substrate 202 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates. The semiconductor substrate 202 may include various layers including a conductive layer or an insulating layer formed on the semiconductor substrate. The semiconductor substrate 202 may include a compound semiconductor and/or an alloy semiconductor. The semiconductor substrate 202 may include various doping configurations to meet one or more design parameters. For example, different doping profiles (e.g., n-well, p-well) may be formed in regions on the semiconductor substrate 202 designed for different device types (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors, n-type metal oxide semiconductor (NMOS) nanostructure transistors). Suitable doping may include ion implantation and/or diffusion processes of dopants. In addition, the semiconductor substrate 202 may include an epitaxial layer (epi-layer), may be strained to enhance performance, and/or may have other suitable enhancement features. The semiconductor substrate 202 may include portions of a semiconductor wafer on which other semiconductor devices are formed.

A mesa region 204 is included above (and/or extends above) the semiconductor substrate 202. Mesa region 204 may also be referred to as a nanostructure pillar and may provide a structure on which the nanostructures of semiconductor device 200 are formed, such as nanostructure channels, nanostructure gate portions surrounding each nanostructure channel, and/or sacrificial nanostructures, among other examples. In some implementations, one or more mesa regions 204 are formed in and/or from fin structures (e.g., silicon fin structures) formed in the semiconductor substrate 202. Mesa region 204 may comprise the same material as semiconductor substrate 202 and is formed from semiconductor substrate 202. In some embodiments, mesa region 204 is doped to form different types of nanostructure transistors, such as p-type nanostructure transistors and/or n-type nanostructure transistors. In some embodiments, mesa region 204 comprises a silicon (Si) material or other base semiconductor material such as germanium (Ge). In some embodiments, mesa region 204 comprises an alloy semiconductor material, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

Mesa region 204 may be fabricated by suitable semiconductor process techniques such as masking, photolithography, and/or etching processes, as well as other examples. As an example, the fin structure may be formed by etching away a portion of the semiconductor substrate 202 to form a recess in the semiconductor substrate 202. The recess may then be filled with a recessed or etched back isolation material to form Shallow Trench Isolation (STI) regions 206 over the semiconductor substrate 202 and between the fin structures. Source/drain recesses may be formed in the fin structure such that mesa regions 204 are formed between the source/drain recesses. However, other fabrication techniques may be used for STI region 206 and/or mesa region 204.

STI regions 206 may electrically isolate adjacent mesa regions 204 and may provide layers on which other layers and/or structures of semiconductor device 200 are formed. STI region 206 may include a dielectric material, such as silicon oxide (SiO _x ) Silicon nitride (Si) _x N _y ) Silicon oxynitride (SiON), fluorosilicate glass (FSG), low-k dielectric materials, and/or other suitable insulating materials. STI region 206 may include a multi-layer structure, for example with one or more liner layers.

Semiconductor device 200 may include a CMOS-based device that includes NMOS active region 208a and PMOS active region 208b. NMOS active region 208a and PMOS active region 208b may be used for logic, memory, and/or other types of semiconductor technology in semiconductor device 200. In some embodiments, NMOS active region 208a may be included in semiconductor device 200 adjacent (or in close proximity to) PMOS active region 208b, and/or PMOS active region 208b may be included in semiconductor device 200 adjacent (or in close proximity to) NMOS active region 208 a. The NMOS active region 208a and the PMOS active region 208b may be electrically isolated by an isolation region 210 between the NMOS active region 208a and the PMOS active region 208b.

An "active region" (also referred to as an Operating Domain (OD)) refers to a portion of the semiconductor device 200 that is electrically activated when the semiconductor device 200 is in operation. For example, the NMOS active region 208a may include a plurality of nanostructure channels (or channel regions) extending between the one or more NMOS source/drain regions 212a and electrically connected to the one or more NMOS source/drain regions 212 a. The nanostructure channel of NMOS active region 208a provides a channel between NMOS source/drain regions 212a through which current can selectively flow. The nanostructure channels or nanoplatelets of the NMOS active region 208a are arranged along a direction (e.g., Z-direction) that is substantially perpendicular to the semiconductor substrate 202. In other words, the nanostructure channels or nanoplatelets of the NMOS active region 208a are arranged or stacked vertically above the semiconductor substrate 202 and above the mesa region 204.

As another example, PMOS active region 208b may include a plurality of nanostructure channels (or channel regions) extending between and electrically connected to one or more PMOS source/drain regions 212 b. The nanostructure channel of PMOS active region 208b provides a channel between PMOS source/drain regions 212b through which current can selectively flow. The nanostructure channels or nanoplatelets of the PMOS active region 208b are arranged along a direction (e.g., Z-direction) that is substantially perpendicular to the semiconductor substrate 202. In other words, the nanostructure channels or nanoplatelets of PMOS active region 208b are arranged or stacked vertically above semiconductor substrate 202 and above mesa region 204.

Isolation region 210 may also be referred to as an OD junction region or an OD-to-OD junction. Isolation region 210 may include a similar composition of layers and/or structures as NMOS active region 208a and/or PMOS active region 208 b. For example, isolation region 210 may include a plurality of nanoplatelets or channel layers arranged along a direction (e.g., Z-direction) substantially perpendicular to semiconductor substrate 202. Multiple nanoplatelets or channel layers may extend between the NMOS source/drain regions 212a and the PMOS source/drain regions 212 b.

Although isolation region 210 includes similar layer and/or structure compositions as NMOS active region 208a and/or PMOS active region 208b (which reduces the manufacturing complexity of forming semiconductor device 200), isolation region 210 includes regions in semiconductor device 200 that are not electrically active. In other words, the isolation region 210 is not electrically connected to a signal line or other metallization layer in the semiconductor device 200. Instead, isolation region 210 is configured to provide electrical isolation between NMOS active region 208a and PMOS active region 208 b. The electrical isolation may reduce noise between the NMOS active region 208a and the PMOS active region 208b, may reduce current leakage between the NMOS active region 208a and the PMOS active region 208b, may reduce parasitic capacitance between the NMOS active region 208a and the PMOS active region 208b, and/or may reduce other types of undesirable electrical effects in the semiconductor device 200.

The nanostructure channels of NMOS active region 208a and the nanostructure channels of PMOS active region 208b include silicon-based nanostructures (e.g., nanoplates or nanowires, among other examples) that serve as semiconductor channels for the nanostructure transistor(s) of semiconductor device 200. In some embodiments, the NMOS active region 208a and/or the PMOS active region 208b (or the nanostructure channel included therein) may comprise silicon (Si) or other silicon-based material. Similarly, isolation regions 210 may comprise silicon (Si) or other silicon-based material and may be formed by the same or similar process as NMOS active region 208a and/or PMOS active region 208 b.

The NMOS source/drain regions 212a and PMOS source/drain regions 212B may include silicon (Si) with one or more dopants, such As P-type materials (e.g., boron (B) or germanium (Ge), among other examples), n-type materials (e.g., phosphorus (P) or arsenic (As), among other examples), and/or other types of dopants. NMOS source/drain regions 212a may refer to source and/or drain regions of NMOS nanostructure transistors of semiconductor device 200.

In some implementations, an epitaxial region 214 may be included below the NMOS source/drain regions 212a, between the NMOS source/drain regions 212a and the fin structure above the semiconductor substrate 202. Epitaxial region 214 may sometimes be referred to as the L0 region of NMOS source/drain region 212 a. Epitaxial region 214 may provide isolation between NMOS source/drain regions 212a and adjacent mesa regions 204. Epitaxial region 214 may be included to reduce, minimize, and/or prevent electrons from traversing mesa region 204 (e.g., rather than through the nanostructure channel of NMOS active region 208a, thereby reducing current leakage), and/or epitaxial region 214 may be included to reduce, minimize, and/or prevent dopants from NMOS source/drain region 212a from entering mesa region 204 (which reduces short channel effects). Similarly, an epitaxial region 214 may be included below the PMOS source/drain region 212b, between the PMOS source/drain region 212b and the fin structure above the semiconductor substrate 202. The epitaxial region 214 of the semiconductor device 200 may include an epitaxially grown material, such as silicon (Si), silicon doped with one or more types of dopants, and/or other epitaxially grown materials.

The NMOS source/drain regions 212a may include a buffer layer 216 (sometimes referred to as a seed layer), an epitaxial layer 218 (sometimes referred to as an Ll epitaxial layer), and an epitaxial layer 220 (sometimes referred to as an L2 epitaxial layer). A buffer layer 216 may be included over and/or on the epitaxial region 214 and over and/or on the ends of the nanostructure channel of the NMOS active region 208a adjacent to the NMOS source/drain region 212 a. In some embodiments, if NMOS source/drain region 212a is adjacent or immediately adjacent to isolation region 210, a portion of buffer layer 216 may be included over and/or on the end of the nanostructure layer of isolation region 210. Since silicon germanium (SiGe) of epitaxial layer 218 may not grow on portions of the nanoplatelets in NMOS active region 208a, the buffer layer may serve as a seed layer for epitaxial layer 218.

An epitaxial layer 218 may be included over and/or on the buffer layer 216. An epitaxial layer 220 may be included over and/or on epitaxial layer 218. The one or more PMOS source/drain regions 212b of the semiconductor device 200 may include a similar configuration of buffer layer 216, epitaxial layer 218, and/or epitaxial layer 220.

Buffer layer 216 may include silicon nitride (Si _x N _y ) Silicon (Si), epitaxially grown silicon, silicon doped with one or more types of dopants, and/or other suitable materials. By way of example, epitaxial layer 218 may include a silicon-germanium material (e.g., siGe: B) doped with boron. In this case, the boron doping concentration may be included in about 1×10 ²⁰ From about 8x10 atoms per cubic centimeter ²⁰ In the range of atoms per cubic centimeter. Additionally or alternatively, the germanium content in epitaxial layer 218 may be included in a range of about 15% to about 35%. However, other combinations of materials, dopants, doping concentrations, and compositions (e.g., germanium content, and other examples) in epitaxial layer 218 are within the scope of the invention.

By way of example, epitaxial layer 220 may include a silicon-germanium material (e.g., siGe: B) doped with boron. In this case, the boron doping concentration may be included in the range of about 8×10 ²⁰ From about 3 x10 atoms per cubic centimeter ²¹ In the range of atoms per cubic centimeter. However, other combinations of values/ranges of dopant and dopant concentration in epitaxial layer 220 are within the scope of the present invention. Additionally or alternatively, the germanium content in epitaxial layer 220 may be included inIn the range of about 35% to about 55%. However, other combinations of materials, dopants, doping concentrations, and compositions (e.g., germanium content, and other examples) in epitaxial layer 220 are within the scope of the invention.

Epitaxial layer 218 may be shaped such that a portion of buffer layer 216 is included between epitaxial layer 218 and one or more adjacent nanostructure channels. Additionally, epitaxial layer 218 may be shaped such that epitaxial layer 220 is included in a recess in epitaxial layer 218. In some embodiments, epitaxial layer 218 is shaped such that an end of epitaxial layer 218 extends outwardly in the Y-direction beyond an end of buffer layer 216 in semiconductor device 200. Epitaxial layer 218 may include a curved end portion that curves at least partially around an end portion of buffer layer 216. In some embodiments, epitaxial layer 220 is shaped such that an end of epitaxial layer 220 extends outwardly in the Y-direction beyond an end of epitaxial layer 218 in semiconductor device 200.

At least a subset of the nanostructure channels of the one or more NMOS active regions 208a extend through the one or more gate structures 222. Similarly, at least a subset of the nanostructure channels of the one or more PMOS active regions 208b extend through the one or more gate structures 222. In some implementations, at least a subset of the nanostructure channels of the isolation region 210 extend through one or more gate structures 222. However, the one or more gate structures 222 through which the nanostructure channels of the isolation regions 210 extend may be inactive gate structures.

As further shown in fig. 2, portions of gate structure 222 are formed between pairs of nanostructure channels in semiconductor device 200 with alternating active regions arranged vertically along the Z-direction. In other words, the semiconductor device 200 includes one or more vertical stacks of alternating portions of the nanostructure channel and gate structure 222, as shown in fig. 2. In this manner, gate structure 222 surrounds the active region's associated nanostructure channel on all sides of the active region's nanostructure channel, which improves control of the active region's nanostructure channel, increases the drive current of the nanostructure transistor(s) of semiconductor device 200, and reduces the Short Channel Effect (SCE) of the nanostructure transistor(s) of semiconductor device 200. Other portions of gate structure 222 may be included above and/or over the vertical stack of alternating portions of nanostructure channels and gate structure 222.

As an example, between the nanostructure channels of the NMOS active region 208a between two or more NMOS source/drain regions 212a, a portion of the gate structure 222 may be included, and the portion of the gate structure 222 may surround the nanostructure channels of the NMOS active region 208 a. Over the NMOS active region 208a, other portions of the gate structure 222 may be included, and other portions of the gate structure 222 may surround two or more sides of the NMOS active region 208 a. As another example, portions of gate structure 222 may be included between nanostructure channels of PMOS active region 208b between two or more PMOS source/drain regions 212b, and portions of gate structure 222 may surround nanostructure channels of the PMOS active region 208 b. Over PMOS active region 208b, other portions of gate structure 222 may be included, and other portions of gate structure 222 may surround two or more sides of PMOS active region 208 b. As another example, a portion of the gate structure 222 may be included between the nanoplatelets or channel layers of the isolation region 210 between the NMOS source/drain region 212a and the PMOS source/drain region 212b, and a portion of the gate structure 222 may surround the nanoplatelets or channel layers of the isolation region 210. Over the isolation region 210, other portions of the gate structure 222 may be included, and other portions of the gate structure 222 may surround two or more sides of the isolation region 210. An internal spacer (InSP) 224 may be included between the NMOS source/drain region 212a and the adjacent gate structure 222, and/or between the PMOS source/drain region 212b and the adjacent gate structure 222. An internal spacer 224 may be included on the end of the portion of the gate structure 222 between the gate structure 222 and the epitaxial layer 218 of an adjacent source/drain region. An internal spacer 224 may be included in the cavity formed between the ends of vertically adjacent nanostructure channels. An internal spacer 224 may be included to reduce parasitic capacitance and to protect the source/drain of the semiconductor device 200 The regions are protected from etching away during a nanoplatelet release operation to remove sacrificial nanoplatelets between nanostructure channels of the active region of semiconductor device 200. The internal spacers 224 comprise silicon nitride (Si _x N _y ) Silicon oxide (SiO) _x ) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and/or other dielectric materials.

The gate structure 222 may be formed by one or more layers and/or one or more materials. The gate structure 222 may include one or more metallic materials, one or more high dielectric constant (high-k) materials, and/or one or more other types of materials. For example, the gate structure 222 may include a work function tuning layer 226, an interface layer 228, a metal electrode layer 230, and/or a gate dielectric layer 232, among other examples. In some embodiments, a dummy gate structure (e.g., a Polysilicon (PO) gate structure or other type of gate structure) is formed at the location of gate structure 222 (e.g., prior to formation) such that one or more other layers and/or structures of semiconductor device 200 may be formed prior to forming gate structure 222. This reduces and/or prevents damage to the gate structure 222 that would otherwise be caused by the formation of one or more layers and/or structures. A Replacement Gate Process (RGP) is then performed to remove the dummy gate structure and replace the dummy gate structure with gate structure 222 (e.g., a replacement gate structure).

One or more spacer layers 234 may be included over and/or on sidewalls of the gate structure 222. The one or more spacer layers 234 may include one or more low dielectric constant (low-k) materials having a dielectric constant less than that of silicon oxide (e.g., less than about 3.9), less than that of silicon oxide (SiO _x ) Silicon oxynitride (SiON), silicon nitride (Si _x N _y ) Silicon oxycarbonitride (SiOCN), and/or other suitable dielectric materials.

The one or more spacer layers 234 may include a spacer layer 234a and another spacer layer 234b, including the spacer layer 234a on the sidewalls of the gate structure 222, and the spacer layer 234b on the spacer layer 234 a. The end of the spacer layer 234a may surround the end of the spacer layer 234b, as shown in fig. 2. In addition, the ends of spacer layer 234a may be adjacent to or proximate to the sides of the active region of semiconductor device 200 (e.g., proximate to the sides of NMOS active region 208a, proximate to the sides of PMOS active region 208 b), and/or may be adjacent to or proximate to the sides of isolation region 210. The ends of the spacer layer 234a may also be located proximate to the ends of the buffer layer 216 and/or proximate to the ends of the epitaxial layer 218 of the one or more source/drain regions (e.g., the one or more NMOS source/drain regions 212a, the one or more PMOS source/drain regions 212 b) of the semiconductor device 200.

The semiconductor device 200 may also include an inter-layer dielectric (ILD) layer 236 over the STI region 206. ILD layer 236 may be referred to as an ILD0 layer. ILD layer 236 may be included between gate structures 222 of semiconductor device 200 to provide electrical isolation and/or insulation between source/drain regions and/or gate structures 222 of semiconductor device 200, as well as other examples. ILD layer 236 may comprise silicon nitride (SiN) _x ) Oxide (e.g. silicon oxide (SiO) _x ) And/or other oxide materials), and/or other types of dielectric materials. ILD layer 236 may be surrounded by a Contact Etch Stop Layer (CESL) 238, and Contact Etch Stop Layer (CESL) 238 may comprise aluminum oxide (Al ₂ O ₃ ) Aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiO) _x N _y ) Aluminum oxynitride (AlON), and/or silicon oxide (SiO) _x ) And other examples.

As shown in fig. 2, a portion of ILD layer 236 may extend below the bottom of gate structure 222. A portion of ILD layer 236 below the bottom of gate structure 222 may be included in oxide region 240 included within STI region 206. Oxide region 240 may include silicon oxide (SiO _x ) And/or other oxide materials.

As shown in fig. 2, and as described in more detail herein (e.g., in connection with fig. 3A, 3B, 4A, and 4B, and other examples), in a top view of semiconductor device 200, one or more sides of NMOS source/drain regions 212a are offset or offset from one or more sides of PMOS source/drain regions 212B along the Y-direction of semiconductor device 200. In other words, in a top view of the semiconductor device 200, although the sides (or edges) of the NMOS source/drain regions 212a and the sides (or edges) of the PMOS source/drain regions 212b may be substantially parallel, the sides (or edges) of the NMOS source/drain regions 212a and the sides (or edges) of the PMOS source/drain regions 212b are not aligned along the X-direction (e.g., not in the same plane). This causes the nanoplatelets of the isolation region 210 to bend between the NMOS source/drain region 212a and the PMOS source/drain region 212b immediately opposite the isolation region 210. The curved shape of the isolation region 210 increases the distance between the NMOS source/drain region 212a and the PMOS source/drain region 212b immediately opposite the isolation region 210, compared to the case where the isolation region 210 is rectangular (and the case where the sides of the isolation region 210 are straight between the NMOS source/drain region 212a and the PMOS source/drain region 212 b). The increased distance between NMOS source/drain regions 212a and PMOS source/drain regions 212b provided by the curved shape of isolation regions 210 provides increased isolation between NMOS source/drain regions 212a and PMOS source/drain regions 212b and reduces the likelihood of NMOS source/drain regions 212a and PMOS source/drain regions 212b merging during fabrication of semiconductor device 200.

As noted above, fig. 2 is provided as an example. Other examples may differ from those described with respect to fig. 2.

Fig. 3A and 3B are schematic diagrams of exemplary embodiments 300 of portions of the semiconductor device 200 described herein. In particular, fig. 3A and 3B are top views of portions of semiconductor device 200 and illustrate components, structures, and/or layers visible in the top view of semiconductor device 200.

As shown in fig. 3A, isolation region 210 may include a first edge 302 and a second edge 304. The first edge 302 may extend between the buffer layer 216 of the NMOS source/drain region 212a adjacent or proximate to a first side of the isolation region 210 and the buffer layer 216 of the PMOS source/drain region 212b adjacent to a second side of the isolation region 210 opposite the first side. The second edge 304 may extend between the buffer layer 216 of the NMOS source/drain region 212a and the buffer layer 216 of the PMOS source/drain region 212 b.

The first edge 302 and the second edge 304 are located on opposite sides of the isolation region 210 and adjacent to the gate structure 222. It should be noted that the gate structure 222 adjacent to the first edge 302 and the second edge 304 may also surround the top of the isolation region 210. However, for clarity, the portion of gate structure 222 surrounding the top of isolation region 210 is omitted from fig. 3A.

As further shown in fig. 3A, in a top view of the semiconductor device 200, the first edge 302 and the second edge 304 are curved. The first edge 302 and the second edge 304 may bend between the buffer layer 216 of the NMOS source/drain region 212a and the buffer layer 216 of the PMOS source/drain region 212 b. The curvature of the first edge 302 and the second edge 304 may result from an offset of one or more sides of the NMOS source/drain region 212a from one or more sides of the PMOS source/drain region 212b along the Y-direction of the semiconductor device 200. Additionally and/or alternatively, the curvature of the first edge 302 and the second edge 304 may result from the length dimension of the NMOS source/drain regions 212a along the Y-direction being greater relative to the length dimension of the PMOS source/drain regions 212b along the Y-direction.

As further shown in fig. 3A, one or more of the NMOS active region 208a or the PMOS active region 208b may include recesses 306 on opposite sides along the Y-direction. The recess 306 may be the result of one or more processing operations performed in the fabrication of the semiconductor device 200. For example, a spacer may be formed on the sidewalls of the nanoplatelets of the semiconductor device 200, and one or more dummy gate structures may be formed over the spacer. The nanoplatelets may then be etched to form NMOS active regions 208a, PMOS active regions 208b, and isolation regions 210. In a replacement gate process, the removal of one or more dummy gate structures may be performed along with the isolation liner. Removal of the isolation liner may result in etching into the sidewalls of NMOS active region 208a, and/or into the sidewalls of PMOS active region 208b (and in some cases into the sidewalls of isolation region 210), which results in the formation of recess 306. The recess 306 may prevent or reduce the likelihood of the gate structure 222 pinching into adjacent source/drain regions (e.g., adjacent NMOS source/drain regions 212a, adjacent PMOS source/drain regions 212 b) that would otherwise result in an electrical short between the gate structure 222 and the adjacent source/drain regions.

Fig. 3B shows a close-up top view of isolation region 210. As shown in fig. 3B, isolation region 210 may include a connection region 308 and a connection region 310. Connection region 308 and connection region 310 may be located on opposite sides of isolation region 210. The connection region 308 includes a portion of the isolation region 210 that contacts an adjacent NMOS source/drain region 212 a. The connection region 308 of the isolation region may span substantially the entire length of the buffer layer 216 of the NMOS source/drain region 212a along the Y-direction. This prevents or reduces the possibility of the epitaxial layer 218 of the NMOS source/drain region 212a from pinching into the gate structure 222 associated with the isolation region 210.

The connection region 310 includes a portion of the isolation region 210 that contacts an adjacent PMOS source/drain region 212 b. The connection region 310 of the isolation region may span substantially the entire length of the buffer layer 216 of the PMOS source/drain region 212b along the Y-direction. This prevents or reduces the possibility of the epitaxial layer 218 of the PMOS source/drain region 212b from pinching into the gate structure 222 associated with the isolation region 210. The width of the buffer layer 216 along the X-direction of the NMOS source/drain regions 212a and the PMOS source/drain regions 212b may be less than the width of the spacer layer 234 to further prevent or reduce the possibility of the epitaxial layer 218 of the NMOS source/drain regions 212a and the epitaxial layer 218 of the PMOS source/drain regions 212b from squeezing into the gate structure 222 associated with the isolation region 210.

As further shown in fig. 3B, the first edge 302 may include a plurality of curve segments having different slopes, different lengths, and/or one or more other different dimensions. The first edge 302 may include a curved section 312 adjacent to the connection region 308, a curved section 314 adjacent to the connection region 310, and a curved section 316 between the curved section 312 and the curved section 314. The curve segment 316 may have a greater length relative to the lengths of the curve segments 312 and 314. The curve segments 312 and 314 may have flatter or shallower slopes relative to the slope of the curve segment 316.

Second edge 304 may include a curved section 318 adjacent to connecting region 308, a curved section 320 adjacent to connecting region 310, and a curved section 322 between curved section 318 and curved section 320. Curve segment 318 may have a greater length relative to the lengths of curve segment 320 and curve segment 322. Curve segment 318 may have a maximum slope followed by a slope of curve segment 322 and again a slope of curve segment 320. The curvature of the second edge 304 results in a portion of the isolation region 210 (and thus, a portion of the nanoplatelets of the isolation region 210) being located between the gate structure 222 and the buffer layer 216 of the NMOS source/drain region 212 a.

The total length of the second edge 304 along the curved segments 318-320 may be greater relative to the length of the first edge 302 along the curved segments 312-322. This may be caused, for example, by the relative positions of the NMOS source/drain regions 212a and the PMOS source/drain regions 212b along the Y-direction, and/or by the dimensional differences of the NMOS source/drain regions 212a and the PMOS source/drain regions 212b along the Y-direction, among other examples.

The total radius of curvature of the second edge 304 along the curved sections 318-322 may be greater relative to the total radius of curvature of the first edge 302 along the curved sections 312-316. For example, the radius of curvature of the second edge 304 may be included in the range of about 0.8 nanometers to about 1.2 nanometers, while the radius of curvature of the first edge 302 may be included in the range of about 0.5 nanometers to about 0.9 nanometers. Forming the isolation region 210 such that the radius of curvature of the second edge 304 is included in the range of about 0.8 nanometers to about 1.2 nanometers and such that the radius of curvature of the first edge 302 is included in the range of about 0.5 nanometers to about 0.9 nanometers may reduce the likelihood of pinching between the NMOS source/drain regions 212a and the gate structure 222, and between the PMOS source/drain regions 212b and the gate structure 222. However, other values of these ranges are also within the scope of the present invention.

As noted above, fig. 3A and 3B are provided as examples. Other examples may differ from those described with respect to fig. 3A and 3B.

Fig. 4A-4C are schematic diagrams of exemplary embodiments 400 of various dimensions of the semiconductor device 200 described herein. In particular, fig. 4A-4C illustrate various top view dimensions of semiconductor device 200.

As shown in fig. 4A, exemplary dimensions of semiconductor device 200 may include offset O1, offset O1 being an offset along the X-direction between a first edge of NMOS active region 208a and a corresponding first edge of PMOS active region 208b on opposite sides of isolation region 210. The offset O1 may be along the Y direction. In other words, along the X-direction, the respective first edges of the NMOS active region 208a and the PMOS active region 208b lie in different planes. In some embodiments, offset O1 may be included in a range of about 15 nanometers to about 30 nanometers. However, other values of this range are also within the scope of the invention.

As further shown in fig. 4A, exemplary dimensions of semiconductor device 200 may include an offset O2, where offset O2 is an offset between a second edge of NMOS active region 208a opposite a first edge of NMOS active region 208a and a corresponding second edge of PMOS active region 208b opposite a first edge of PMOS active region 208 b. The offset O2 may be along the Y direction. In other words, along the X-direction, the respective second edges of the NMOS active region 208a and the PMOS active region 208b lie in different planes. In some embodiments, offset O2 may be included in a range of about 15 nanometers to about 150 nanometers. However, other values of this range are also within the scope of the invention.

As further shown in fig. 4A, exemplary dimensions of semiconductor device 200 may include a width Wl of isolation region 210, which is the width between NMOS source/drain region 212a and PMOS source/drain region 212b, and between connection region 308 and connection region 310 on opposite sides of isolation region 210. Offset O1 and offset O2 result in width W1 being the diagonal of isolation region 210 between connection region 308 and connection region 310, rather than being entirely along the X-direction, which increases the size of width W1 as compared to width W1 being entirely along the X-direction. For example, the offset O1 and the offset O2 may be such that the width W1 (e.g., diagonal width) is included in a range of about 18 nanometers to about 60 nanometers, while the width W2 between the contact etch stop layers 238 adjacent opposite sides of the isolation region 210 may be included in a range of about 10 nanometers to about 50 nanometers. Having the width W1 included in the range of about 18 nanometers to about 60 nanometers may enable the isolation region 210 to provide increased electrical isolation between the NMOS source/drain region 212a and the PMOS source/drain region 212b, and may reduce the likelihood of merging between the NMOS source/drain region 212a and the PMOS source/drain region 212b as compared to having the width W1 entirely along the X-direction. The offset O1 and the offset O2 may be included in the respective offset ranges described above to achieve the width W1 included in the ranges. However, other values of the range of the width W1 are also within the scope of the present invention.

As shown in fig. 4B, exemplary dimensions of semiconductor device 200 may include a width W3 of a portion of isolation region 210, width W3 being the width between gate structure 222 associated with isolation region 210 and buffer layer 216 adjacent NMOS source/drain region 212a of isolation region 210. In some embodiments, the width W3 is included in a range of about 5 nanometers to about 20 nanometers to reduce the likelihood of the NMOS source/drain regions 212a pinching into the gate structure 222 and to provide sufficient area in the nanoplatelets of the isolation region 210 to form the internal spacers 224 in the isolation region 210. However, other values of this range are within the scope of the invention.

As further shown in fig. 4B, exemplary dimensions of the semiconductor device 200 may include a length Ll, which is the length of the one or more NMOS active regions 208a along the Y-direction of the semiconductor device 200. In some embodiments, the length L1 is included in a range of about 30 nanometers to about 150 nanometers to achieve sufficient epitaxial growth of the NMOS source/drain regions 212a and to reduce the likelihood of pinching of the NMOS source/drain regions 212 a. However, other values of this range are also within the scope of the invention.

As further shown in fig. 4B, exemplary dimensions of semiconductor device 200 may include a length L2, length L2 being the length of one or more PMOS active regions 208B along the Y-direction of semiconductor device 200. The length Ll of the one or more NMOS active regions 208a may be greater relative to the length L2 of the one or more PMOS active regions 208B, alone or in combination with the offset O1 and the offset O2, which may form the isolation region 210 to have an asymmetric and curved shape as shown in fig. 4B. However, in other embodiments, length L1 and length L2 are substantially the same length. In some embodiments, length L2 is included in a range of about 25 nanometers to about 60 nanometers to achieve sufficient epitaxial growth of PMOS source/drain regions 212b and to reduce the likelihood of pinching of PMOS source/drain regions 212 b. However, other values of this range are also within the scope of the invention.

As further shown in fig. 4B, exemplary dimensions of semiconductor device 200 may include a length L3, length L3 being the length of the nanoplatelets of isolation region 210 between the bottom of the curve of second edge 304 and the top of the curve of second edge 304 of isolation region 210. In some embodiments, the length L3 is included in a range of about 15 nanometers to about 150 nanometers to reduce the likelihood of the NMOS source/drain regions 212a adjacent the isolation region 210 pinching into the gate structure 222 associated with the isolation region 210. However, other values of this range are also within the scope of the invention.

As further shown in fig. 4B, exemplary dimensions of the semiconductor device 200 may include a length L4, the length L4 being the length between the bottom of the curve of the first edge 302 and the top of the curve of the first edge 302 of the isolation region 210. The length L4 may correspond to the length of the portion of the isolation region 210 (including the portion of the first edge 302) of the buffer layer 216 of the NMOS source/drain region 212a that extends outward in the Y-direction. In some embodiments, the length L4 is included in a range of about 15 nanometers to about 30 nanometers to reduce the likelihood of the PMOS source/drain regions 212b adjacent the isolation region 210 pinching into the gate structure 222 associated with the isolation region 210. However, other values of this range are also within the scope of the invention.

As shown in fig. 4C, exemplary dimensions of the semiconductor device 200 may include a length L5 of the connection region 308 of the isolation region 210, the length L5 being the length of the connection region 308 adjacent to or immediately adjacent to the buffer layer 216 adjacent to the NMOS source/drain region 212a of the isolation region 210. In some embodiments, length L3 may be smaller than length L5. The length L5 may be greater relative to the length L3 to provide sufficient area in the connection region for connection between the isolation region 210 and the NMOS source/drain region 212 a. In some embodiments, length L5 and length L1 are substantially the same. In some embodiments, the length of the buffer layer 216 of the NMOS source/drain region 212a is less than or substantially equal to the length L5 of the isolation region 210 in the connection region 308 to reduce the likelihood of the NMOS source/drain region 212a pinching into the gate structure 222, which may reduce the likelihood of merging between the NMOS source/drain region 212a and the PMOS source/drain region 212b along the first edge 302 and/or along the second edge 304. In some embodiments, length L5 is included in the range of about 30 nanometers to about 150 nanometers to provide sufficient area in the connection region for connection between isolation region 210 and NMOS source/drain region 212 a. However, other values of this range are also within the scope of the invention.

As further shown in fig. 4C, exemplary dimensions of the semiconductor device 200 may include a length L6 of the connection region 310 of the isolation region 210, the length L6 being the length of the connection region 310 adjacent to or immediately adjacent to the buffer layer 216 adjacent to the PMOS source/drain region 212b of the isolation region 210. In some embodiments, length L4 may be smaller than length L6. Length L6 may be greater relative to length L4 to provide sufficient area in the connection region for connection between isolation region 210 and PMOS source/drain region 212 b. In some embodiments, length L6 and length L2 may be approximately equal lengths. In some embodiments, the length of the buffer layer 216 of the PMOS source/drain region 212b is less than or substantially equal to the length of the isolation region 210 in the connection region 310 to reduce the likelihood of the PMOS source/drain region 212b pinching into the gate structure 222, which may reduce the likelihood of merging between the NMOS source/drain region 212a and the PMOS source/drain region 212b along the first edge 302 and/or along the second edge 304. In some embodiments, length L6 is included in the range of about 15 nanometers to about 30 nanometers to provide sufficient area in the connection region for connection between isolation region 210 and PMOS source/drain region 212b and to reduce the likelihood of PMOS source/drain region 212b pinching into gate structure 222 associated with isolation region 210. However, other values of this range are also within the scope of the invention.

As further shown in fig. 4C, exemplary dimensions of semiconductor device 200 include a thickness Tl of connection region 310. The thickness Tl may be included in a range of about 5 nm to about 20 nm to reduce the likelihood of the PMOS source/drain regions 212b pinching into the gate structure 222 and to achieve sufficient growth of the internal spacers 224 in the connection regions 310 of the isolation regions 210. However, other values of this range are also within the scope of the invention.

As noted above, fig. 4A-4C are provided as examples. Other examples may differ from those described with respect to fig. 4A-4C.

Fig. 5A and 5B are schematic diagrams of exemplary embodiments 500 of portions of semiconductor device 200 described herein. The top of fig. 5A shows a top view of a portion of the semiconductor device, and the bottom of fig. 5A shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). The cross-section A-A in the top view is along the X-direction in the semiconductor device 200 and includes portions of the NMOS active region 208a, portions of the NMOS source/drain region 212a, portions of the isolation region 210, portions of the PMOS active region 208b, and portions of the PMOS source/drain region 212 b.

In the cross-sectional view along section A-A in fig. 5A, isolation region 210 is side-by-side with NMOS source/drain regions 212a and PMOS source/drain regions 212b on opposite sides of isolation region 210 along the X-direction. In the cross-sectional view along section A-A in fig. 5A, NMOS source/drain regions 212a are located between isolation region 210 and NMOS active region 208 a. In the cross-sectional view along section A-A in fig. 5A, PMOS source/drain region 212b is located between isolation region 210 and PMOS active region 208 b.

As shown in the cross-sectional view of fig. 5A, the nanoplatelets of NMOS active region 208a alternate with the nanoplatelets of the associated gate structure 222. The gate structure 222 completely surrounds the nano-platelet of the NMOS active region 208 a. Between the NMOS source/drain regions 212a, a nano-platelet of the NMOS active region 208a and a nano-platelet of the gate structure 222 associated with the NMOS active region 208a may be included. Above the epitaxial regions 214, NMOS source/drain regions 212a may be included, and each NMOS source/drain region 212a may include a buffer layer 216, an epitaxial layer 218, and an epitaxial layer 220. An internal spacer 224 may be included in the cavity on the end of the nanoplatelets of the gate structure 222 and between the gate structure 222 and the epitaxial layer 218 of the NMOS source/drain region 212 a. Buffer layer 216 of NMOS source/drain region 212a is included between inner spacers 224 and between the nano-sheets of NMOS active region 208a and epitaxial layer 218 so that buffer layer 216 does not extend over spacer layer 234 and into gate structure 222. A buffer layer 216 is included between the epitaxial region 214 and the epitaxial layer 218 of the NMOS source/drain region 212a to reduce the likelihood of dopant diffusion into the mesa region 204 below the NMOS active region 208 a.

Epitaxial layer 220 may be included within a recess in epitaxial layer 218 having a height that is approximately the same as or higher than the uppermost internal spacers 224 to limit the growth area of epitaxial layer 220 because the germanium concentration in epitaxial layer 220 is relatively high (e.g., germanium in the range of about 25% to about 55%). This may reduce the likelihood of defects forming in epitaxial layer 220.

As further shown in the cross-sectional view of fig. 5A, the nanoplatelets of PMOS active region 208b alternate with the nanoplatelets of the associated gate structure 222. Gate structure 222 completely surrounds the nanoplatelets of PMOS active region 208 b. Between PMOS source/drain regions 212b, a nano-platelet of PMOS active region 208b and a nano-platelet of gate structure 222 associated with PMOS active region 208b may be included. Above epitaxial region 214, PMOS source/drain regions 212b may be included, and each PMOS source/drain region 212b may include buffer layer 216, epitaxial layer 218, and epitaxial layer 220. An internal spacer 224 may be included in the cavity on the end of the nanoplatelets of the gate structure 222 and between the gate structure 222 and the epitaxial layer 218 of the PMOS source/drain region 212 b. Buffer layer 216 of PMOS source/drain region 212b is included between inner spacers 224 and between the nanoplatelets of PMOS active region 208b and epitaxial layer 218 such that buffer layer 216 does not extend over spacer layer 234 and into gate structure 222. A buffer layer 216 is included between the epitaxial region 214 and the epitaxial layer 218 of the PMOS source/drain region 212b to reduce the likelihood of dopant diffusion into the mesa region 204 below the PMOS active region 208 b.

As further shown in the cross-sectional view of fig. 5A, the nanoplatelets of isolation regions 210 alternate with nanoplatelets of the associated gate structure 222. Gate structure 222 completely surrounds the nanoplatelets of isolation region 210. Between the NMOS source/drain regions 212a and the PMOS source/drain regions 212b, a nanoplatelet of the isolation region 210 and a nanoplatelet of the gate structure 222 associated with the isolation region 210 may be included.

The top of fig. 5B shows a top view of a portion of the semiconductor device, and the bottom of fig. 5B shows a cross-sectional view of a portion of the semiconductor device 200 along section B-B in the top view (which corresponds to section B-B in fig. 2). Section B-B in the top view is along the X-direction in semiconductor device 200 and includes portions of NMOS active region 208a, NMOS source/drain regions 212a, isolation region 210, gate structure 222 associated with isolation region 210, ILD layer 236, and gate structure 222 associated with PMOS active region 208B.

In a cross-sectional view along section B-B in fig. 5B, isolation region 210 is side-by-side with NMOS source/drain regions 212a and gate structure 222, wherein gate structure 222 surrounds the nanoplatelets of isolation region 210. In a cross-sectional view along section B-B in fig. 5B, NMOS source/drain regions 212a are located between isolation region 210 and NMOS active region 208 a. In a cross-sectional view along section B-B in fig. 5B, gate structure 222 is located between isolation region 210 and ILD layer 236. ILD layer 236 is adjacent PMOS source/drain regions 212b along the Y-direction.

In section A-A in fig. 5A, isolation region 210 is adjacent PMOS source/drain region 212B, and in section B-B in fig. 5B, is adjacent gate structure 222, due to the curvature of the nanoplatelets of isolation region 210. The width of the nanoplatelets of the isolation region 210 along the X-direction in section A-A in fig. 5A is also greater relative to the width W3 of the nanoplatelets of the isolation region 210 along the X-direction in section B-B in fig. 5B, due to the curvature of the nanoplatelets of the isolation region 210. As further shown in the cross-sectional view along section B-B in fig. 5B, ILD layer 236 may include a curved bottom 502 that is located in oxide region 240 within STI region 206.

As noted above, fig. 5A and 5B are provided as examples. Other examples may differ from those described with respect to fig. 5A and 5B.

Fig. 6A-6F are schematic diagrams of exemplary embodiments 600 described herein. The exemplary embodiment 600 includes an example of forming the isolation region 210 for the semiconductor device 200, wherein the isolation region 210 includes an asymmetric and/or curved shape. One or more of the semiconductor processing tools 102-112 may perform one or more of the operations described in connection with fig. 6A-6F.

The top of fig. 6A shows a top view of a portion of the semiconductor device, and the bottom of fig. 6A shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). As shown in fig. 6A, the processing of the semiconductor device 200 is performed in conjunction with the semiconductor substrate 202. The deposition tool 102 may form or deposit a stack of nanoplatelets over and/or onto the semiconductor substrate 202. The stack of nanoplatelets may be referred to as a superlattice. In some embodiments, one or more operations are performed in conjunction with semiconductor substrate 202 prior to forming the nanoplatelet stack. For example, an anti-punch-through (APT) implant operation may be performed. The APT implant operation may be performed in one or more regions of the semiconductor substrate 202 on which the active regions of the semiconductor device 200 are to be formed. For example, APT implantation operations are implemented to reduce and/or prevent punch-through or unwanted diffusion into the semiconductor substrate 202.

The nanoplatelet stack comprises a plurality of alternating layers arranged along a direction (Z-direction) substantially perpendicular to the semiconductor substrate 202. For example, the nanoplatelet stack includes vertically alternating layers of a first layer 602 and a second layer 604 over the semiconductor substrate 202. The number of first layers 602 and the number of second layers 604 shown in fig. 6A are examples, and other numbers of first layers 602 and second layers 604 are within the scope of the invention. In some embodiments, the first layer 602 and the second layer 604 are formed to different thicknesses. For example, the second layer 604 may be formed to have a greater thickness relative to the thickness of the first layer 602. In some embodiments, the first layer 602 (or a subset thereof) is formed to a thickness in a range of about 4 nanometers to about 7 nanometers. In some embodiments, the second layer 604 (or a subset thereof) is formed to a thickness in a range of about 8 nanometers to about 12 nanometers. However, other values for the thickness of the first layer 602 and the thickness of the second layer 604 are within the scope of the invention.

The first layer 602 includes a first material composition and the second layer 604 includes a second material composition. In some embodiments, the first material composition and the second material composition are the same material composition. In some embodiments, the first material composition and the second material composition are different material compositions. As an example, the first layer 602 may include silicon germanium (SiGe) and the second layer 604 may include silicon (Si). In some embodiments, the first material composition and the second material composition have different oxidation rates and/or etch selectivities.

As described herein, the second layer 604 may be processed to form a nanostructure channel or nanoplatelet layer of the active region (e.g., NMOS active region 208a, PMOS active region 208 b) of the nanostructure transistor of the semiconductor device 200. In addition, the second layer 604 may be processed to form a nanostructure channel or nanoplatelet layer of the isolation region 210 between two or more nanostructure transistors of the semiconductor device 200. The first layer 602 is a sacrificial nanostructure or sacrificial nanoplatelet layer that is eventually removed and serves to define a vertical distance between adjacent nanostructure channels or nanoplatelets for the gate structure 222 of the subsequently formed semiconductor device 200. Accordingly, the first layer 602 may be referred to as a sacrificial layer, and the second layer 604 may be referred to as a channel layer.

The deposition tool 102 deposits and/or grows alternating layers of the stack of nanoplatelets to include nanostructures (e.g., nanoplatelets) on the semiconductor substrate 202. For example, the deposition tool 102 grows alternating layers by epitaxial growth. However, other processes may be used to form alternating layers of the nanoplatelet stack. Epitaxial growth of alternating layers of the nanoplatelet stack may be performed by Molecular Beam Epitaxy (MBE) processes, metal Organic Chemical Vapor Deposition (MOCVD) processes, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer, such as the second layer 604, comprises the same material as the semiconductor substrate 202. In some embodiments, the first layer 602 and/or the second layer 604 comprise a material different from the material of the semiconductor substrate 202. As described above, in some embodiments, the first layer 602 comprises an epitaxially grown silicon germanium (SiGe) layer, and the second layer 604 comprises an epitaxially grown silicon (Si) layer. Alternatively, the first layer 602 and/or the second layer 604 may include other materials, such as: germanium (Ge); compound semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium Arsenide (IAs), indium antimonide (InSb); alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP); and/or combinations thereof. The material(s) of the first layer 602 and/or the material(s) of the second layer 604 may be selected based on providing different oxidation characteristics, different etch selectivity characteristics, and/or other different characteristics.

In some embodiments, the deposition tool 102 may form one or more additional layers over and/or on the nanoplatelet stack. For example, a Hard Mask (HM) layer may be formed over and/or on the nano-sheet stack (e.g., over the topmost second layer 604 of the nano-sheet stack). As another example, a capping layer may be formed over and/or on the hard mask layer. As another example, other hard mask layers including oxide layers and nitride layers may be formed over and/or on the capping layer. One or more Hard Mask (HM) layers may be used to form one or more structures of the semiconductor device 200. The oxide layer may serve as an adhesion layer between the nanoplatelet stack and the nitride layer, and may serve as an etch stop layer for etching the nitride layer. The one or more hard mask layers may include silicon germanium (SiGe), silicon nitride (Si) _x N _y ) Silicon oxide (SiO) _x ) And/or other materials. The capping layer may include silicon (Si) and/or other materials. In some embodiments, the capping layer is formed of the same material as the semiconductor substrate 202.In some embodiments, one or more additional layers may be thermally grown, deposited by CVD, PVD, ALD, and/or formed using other deposition techniques.

The top of fig. 6B shows a top view of a portion of the semiconductor device, and the bottom of fig. 6B shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). As shown in fig. 6B, alternating first and second layers 602, 604 of the nano-sheet stack and the semiconductor substrate 202 are etched to remove portions of the alternating first and second layers 602, 604 of the nano-sheet stack and to remove portions of the semiconductor substrate 202. After the etching operation, the remaining portions of the alternating first and second layers 602, 604 of the nanoplatelet stack include the first semiconductor device region 606, the second semiconductor device region 608, and a transition region 610 extending between the first and second semiconductor device regions 606, 608 along the X-direction in a top view of the semiconductor device 200.

The first semiconductor device region 606 may include a region in which an NMOS nanostructure transistor of the semiconductor device 200 is to be formed. The second semiconductor device region 608 may include a region in which a PMOS nanostructure transistor of the semiconductor device 200 is to be formed. The transition region 610 may include a region in which the isolation region 210 of the semiconductor device 200 is to be formed.

The first semiconductor device region 606, the second semiconductor device region 608, and the transition region 610 may be formed by any suitable semiconductor processing technique. For example, the deposition tool 102, the exposure tool 104, the development tool 106, and/or the etch tool 108 may form the first semiconductor device region 606, the second semiconductor device region 608, and the transition region 610 using one or more photolithographic processes including double patterning or multiple patterning processes. Typically, a double patterning or multiple patterning process combines a lithographic and a self-aligned process, allowing for the creation of patterns with smaller pitches than those obtainable using a single direct lithographic process, for example. For example, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed using a self-aligned process alongside the patterned sacrificial layer. The sacrificial layer is then removed, after which the fin structure may be patterned using the remaining spacers.

In some embodiments, the deposition tool 102 forming a photoresist layer over and/or on the hard mask layer includes: the exposure tool 104 exposes the photoresist layer to radiation (e.g., deep Ultraviolet (UV) radiation, extreme Ultraviolet (EUV) radiation), performs a post-exposure bake process (e.g., removes residual solvent from the photoresist layer), and the development tool 106 develops the photoresist layer to form a pattern in the photoresist layer, which is then used to pattern the hard mask layer. In some embodiments, patterning the photoresist layer is performed using an electron beam (e-beam) lithography process to form a pattern, and etching is used to transfer the pattern to the hard mask layer. Then, based on the pattern in the hard mask layer, the etch tool 108 may etch into the alternating first and second layers 602, 604 and into the semiconductor substrate 202 to form the first semiconductor device region 606, the second semiconductor device region 608, and the transition region 610.

As further shown in fig. 6B, the first semiconductor device region 606 and the second semiconductor device region 608 are staggered in the Y direction along the X direction. In other words, the edge of the first semiconductor device region 606 and the edge of the second semiconductor device region 608 lie in different planes along the X-direction. The misalignment of the first semiconductor device region 606 and the second semiconductor device region 608 results in the asymmetric and/or curved shape of the transition region 610 shown in fig. 6B. The transition region 610 includes the first edge 302 and the second edge 304 that are curved between the first semiconductor device region 606 and the second semiconductor device region 608.

The top of fig. 6C shows a top view of a portion of the semiconductor device, and the bottom of fig. 6C shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). As shown in fig. 6C, a spacer pad 612 may be formed on the sidewalls and on the top surface of the uppermost second layer 604. A Polysilicon (PO) layer may be formed over and/or on the spacer 612. In some embodiments, the isolation pad 612 corresponds to a portion of the STI region 206 deposited around the first semiconductor device region 606, the second semiconductor device region 608, and the transition region 610. The deposition tool 102 may deposit the spacer pad 612 and the polysilicon layer using CVD techniques, PVD techniques, ALD techniques, epitaxial techniques, and/or other suitable deposition techniques.

The spacer 612 may comprise a dielectric material, such as silicon oxide (SiO) _x ) Silicon nitride (Si) _x N _y ) Silicon oxynitride (SiON), fluorine doped silicate glass (FSG), low-k dielectric materials, and/or other suitable insulating materials. The polysilicon layer may include polysilicon and/or other suitable materials.

Portions of the polysilicon layer and corresponding portions of the spacer 612 may be removed. The remaining portion of the polysilicon layer may correspond to dummy gate structure 614, wherein a remaining portion of the spacer pad 612 is included between the dummy gate structure 614 and the nano-sheet stack of semiconductor device 200. Over the sidewalls of the nano-sheet stack in the first semiconductor device region 606, a dummy gate structure may be included, and the dummy gate structure may surround the sidewalls of the nano-sheet stack in the first semiconductor device region 606. Over the sidewalls of the nano-sheet stack in the second semiconductor device region 608, a dummy gate structure may be included, and the dummy gate structure may surround the sidewalls of the nano-sheet stack in the second semiconductor device region 608. Over the sidewalls of the nano-sheet stack in transition region 610, a dummy gate structure may be included, and the dummy gate structure may surround the sidewalls of the nano-sheet stack in transition region 610. In the semiconductor device 200, further dummy gate structures 614 may be included.

In some embodiments, the spacer pad 612 and the polysilicon layer may be etched using a pattern in the photoresist layer to form the dummy gate structure 614. In these embodiments, the deposition tool 102 forms a photoresist layer over the polysilicon layer. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developing tool 106 develops portions of the photoresist layer and removes portions of the photoresist layer to expose the pattern. Based on the pattern, the etch tool 108 etches the polysilicon layer and the isolation pad 612 to form a dummy gate structure 614. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or other types of etching operations. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or other techniques). In some embodiments, the hard mask layer is used as an alternative technique for etching the polysilicon layer based on the pattern. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or other techniques).

The top of fig. 6D shows a top view of a portion of the semiconductor device, and the bottom of fig. 6D shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). As shown in fig. 6D, a spacer layer 234 may be formed over and/or over sidewalls of the dummy gate structure 614. The deposition tool 102 may conformally deposit the spacer layer 234 and the etch tool 108 may etch back the conformally deposited material such that the spacer layer 234 remains on the sidewalls of the dummy gate structure 614. In some embodiments, the spacer layer 234 includes multiple types of spacer layers. For example, the spacer layer 234 may include a spacer layer 234a (sometimes referred to as a sealing spacer layer) formed on sidewalls of the dummy gate structure 614, and a spacer layer 234b (sometimes referred to as a bulk spacer layer) formed on the spacer layer 234 a. Spacer layer 234a and spacer layer 234b may be formed from similar materials or different materials. In some embodiments, spacer layer 234b is formed without a plasma surface treatment for spacer layer 234 a.

As further shown in fig. 6D, spacer layer 234 is formed on a subset of the sidewalls of dummy gate structure 614 in transition region 610. A spacer layer 234 may be included on sidewalls of the dummy gate structure 614 on both sides of the connection region 310. However, the spacer layer 234 includes a case on the sidewalls of the dummy gate structure 614 on only one side of the connection region 308, as shown in the top view in fig. 6D. This occurs due to the curvature of the second edge 304. The curvature of the second edge 304 provides a transition between the semiconductor device region 606 and the semiconductor device region 608 and results in a portion of the nanoplatelet stack (including a portion of the first layer 602 and a portion of the second layer 604) being located between the dummy gate structure 614 and the connection region 308 in the transition region 610.

The top of fig. 6E shows a top view of a portion of the semiconductor device, and the bottom of fig. 6E shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). As shown in fig. 6E, NMOS source/drain regions 212a may be formed in the first semiconductor device region 606 and PMOS source/drain regions 212b may be formed in the second semiconductor device region 608. The formation of NMOS source/drain regions 212a and PMOS source/drain regions 212b results in the formation of NMOS active region 208a in first semiconductor device region 606, PMOS active region 208b in second semiconductor device region 608, and isolation region 210 in transition region 610.

An NMOS active region 208a may be included between two or more NMOS source/drain regions 212a along the X-direction. PMOS active region 208b may be included between two or more PMOS source/drain regions 212b along the X-direction. Isolation regions 210 may be included along the X-direction between NMOS source/drain regions 212a and PMOS source/drain regions 212b. As further shown in fig. 6E, the edges of NMOS source/drain regions 212a and PMOS source/drain regions 212b may be offset or staggered in the Y-direction along the X-direction in a top view of semiconductor device 200. The offset or shift may be caused by an asymmetric and/or curved shape of the isolation region 210.

As further shown in fig. 6E, the spacer pad 612 is completely covered or contained by the spacer layer 234 and the dummy gate structure 614. The dummy gate structure 614 and the isolation pad 612 are completely isolated or separated from the NMOS source/drain region 212a and the PMOS source/drain region 212b, which reduces the likelihood of merging between two or more source/drain regions of the semiconductor device 200.

Source/drain recesses may be formed in the nanoplatelet stack of the first layer 602 and the second layer 604 in an etching operation to form NMOS active regions 208a, PMOS active regions 208b, and isolation regions 210. Source/drain recesses are formed to provide space in which NMOS source/drain regions 212a and PMOS source/drain regions 212b are to be formed. The etching operation may be performed by the etching tool 108 and may be referred to as a strained source/drain (SSD) etching operation. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and/or other types of etching techniques.

The etching operation may also result in the formation of mesa region 204 below NMOS active region 208a, PMOS active region 208b, and isolation region 210. In an embodiment, the semiconductor substrate 202 includes a silicon (Si) material having a (100) orientation. A face having a (111) orientation may be formed at the bottom of the source/drain recess such that a V-shaped or triangular cross-section is formed at the bottom of the source/drain recess. In some embodiments, a V-shaped profile is formed using wet etching using tetramethylammonium hydroxide (TMAH) and/or chemical dry etching using hydrochloric acid (HCl). However, the cross-section at the bottom of the source/drain recess may include other shapes, such as circular or semi-circular, as well as other examples.

The internal spacers 224 may be formed on the ends of the first layer 602 before the NMOS source/drain regions 212a and PMOS source/drain regions 212b are formed in the source/drain recesses. The etch tool 108 may laterally etch the ends of the first layer 602 (e.g., along a direction substantially parallel to the length of the first layer 602) through the source/drain recesses to form cavities between the NMOS active region 208a, the PMOS active region 208b, and the ends of the nanoplatelets of the isolation region 210.

In embodiments where the first layer 602 is silicon germanium (SiGe) and the second layer 604 is silicon (Si), the first layer is formed using a material such as a material including hydrogen peroxide (H) ₂ O ₂ ) Acetic acid (CH) ₃ COOH), and/or Hydrogen Fluoride (HF), followed by water (H) ₂ O) cleaning, the etching tool 108 may selectively etch the first layer 602. The mixed solution and water may be provided into the source/drain recesses to etch the first layer 602 from the source/drain recesses. In some embodiments, the etching with the mixed solution and the rinsing with water may be repeated from about 10 times to about 20 times. In some embodiments, the etching with the mixed solution is performed for a time in the range of about 1 minute to about 2 minutes. Can be at about 60 degrees Celsius to about 90 degrees Celsius The mixed solution is used at a temperature in the range of degrees. However, other values of the parameters of the etching operation are within the scope of the invention.

The cavity in the end of the first layer 602 may be formed in a generally curved shape, a generally concave shape, a generally triangular shape, a generally square shape, or other shapes. In some embodiments, the depth of the one or more cavities (e.g., the size of the cavities extending from the source/drain recesses into the first layer 602) is in the range of about 0.5 nanometers to about 5 nanometers. In some embodiments, the depth of the one or more cavities is in the range of about 1 nanometer to about 3 nanometers. However, other values of cavity depth are within the scope of the invention.

After the cavity formation in the end of the first layer 602, an insulating layer may be conformally deposited along the bottom and sidewalls of the source/drain recesses. The deposition tool 102 may deposit an insulating layer using CVD techniques, PVD techniques, and ALD techniques, and/or other deposition techniques. The deposition tool 102 forms the insulating layer to be thick enough to fill the cavity in the end of the first layer 602. For example, the insulating layer may be formed to have a thickness in the range of about 1 nm to about 10 nm. As another example, the insulating layer may be formed to have a thickness in a range of about 2 nanometers to about 5 nanometers. However, other values of the thickness of the insulating layer are within the scope of the invention. The insulating layer is partially removed such that the remaining portion of the insulating layer corresponds to the inner spacers 224 in the cavity. The etching tool 108 may perform an etching operation to partially remove the insulating layer.

In some embodiments, the etching operation may cause the surfaces of the inner spacers 224 facing the source/drain recesses to bend or recess. The depth of the recess in the inner spacer 224 may be in the range of about 0.2 nanometers to about 3 nanometers. As another example, the depth of the recess in the inner spacer 224 may be in the range of about 0.5 nanometers to about 2 nanometers. As another example, the depth of the recess in the inner spacer 224 may be in the range of less than about 0.5 nanometers. In some embodiments, the surface of the inner spacer 224 facing the source/drain recess is substantially planar.

The source/drain recesses are then filled with one or more layers to form NMOS source/drain regions 212a and PMOS source/drain regions 212b in the source/drain recesses. In some embodiments, the second semiconductor device region 608 is masked, a source/drain recess is formed in the first semiconductor device region 606, and a PMOS source/drain region 212b is formed in the source/drain recess while the second semiconductor device region 608 is masked. Then, the first semiconductor device region 606 is masked, a source/drain recess is formed in the second semiconductor device region 608, and an NMOS source/drain region 212a is formed in the source/drain recess while the first semiconductor device region 606 is masked. Alternatively, the PMOS source/drain regions 212b may be formed before the NMOS source/drain regions 212a are formed.

To deposit the source/drain regions (e.g., NMOS source/drain regions 212a, PMOS source/drain regions 212 b), the deposition tool 102 may deposit the epitaxial region 214 at the bottom of the source/drain recess, and the deposition tool 102 may deposit the buffer layer 216 on the epitaxial region 214 and on the ends of the nanoplatelets in the source/drain recess (e.g., on the ends of the nanoplatelets of the NMOS active region 208a, on the ends of the nanoplatelets of the PMOS active region 208b, on the ends of the nanoplatelets of the isolation region 210). The deposition tool 102 may then partially fill the source/drain recesses with the epitaxial layer 218 over the inner spacers 224 and over the buffer layer 216, and may fill the remaining portions of the source/drain recesses with the epitaxial layer 220 over the epitaxial layer 218.

The asymmetric and/or curved shape of the isolation region 210 increases the length of the first edge 302 of the isolation region and increases the length of the second edge 304 of the isolation region 210. The increased length of the first edge 302 between the connection region 308 and the connection region 310, and the increased length of the second edge 304 between the connection region 308 and the connection region 310, reduces the likelihood that one or more layers (e.g., buffer layer 216, epitaxial layer 218) of the NMOS source/drain region 212a adjacent to the connection region 308 merge with one or more layers (e.g., buffer layer 216, epitaxial layer 218) of the PMOS source/drain region 212b adjacent to the connection region 310. In particular, the increased length of the first edge 302 reduces the likelihood that one or more layers (e.g., buffer layer 216, epitaxial layer 218) of the NMOS source/drain region 212a and one or more layers (e.g., buffer layer 216, epitaxial layer 218) of the PMOS source/drain region 212b adjacent to the connection region 308 will grow along the first edge 302 and merge together along the first edge 302. Similarly, the increased length of the second edge 304 reduces the likelihood that one or more layers (e.g., buffer layer 216, epitaxial layer 218) of the NMOS source/drain region 212a and one or more layers (e.g., buffer layer 216, epitaxial layer 218) of the PMOS source/drain region 212b adjacent to the connection region 308 will grow along the second edge 304 and merge together along the second edge 304.

The top of fig. 6F shows a top view of a portion of the semiconductor device, and the bottom of fig. 6F shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). As shown in fig. 6F, ILD layer 236 and contact etch stop layer 238 are formed over and around the source/drain regions, including over and around NMOS source/drain regions 212a and over and around PMOS source/drain regions 212 b. ILD layer 236 and contact etch stop layer 238 fill in the areas between dummy gate structures 614. ILD layer 236 is formed to reduce the likelihood of damaging the source/drain regions and/or to prevent damaging the source/drain regions during the replacement gate process.

Over and around the source/drain regions, the contact etch stop layer 238 may be conformally deposited (e.g., by deposition tool 102). ILD layer 236 is then deposited (e.g., by deposition tool 102) over contact etch stop layer 238. In some embodiments, a contact etch stop layer 238 and ILD layer 236 are also formed over dummy gate structure 614, and planarization tool 110 performs a CMP operation and/or other type of planarization operation to remove portions of dummy gate structure 614 that contact etch stop layer 238 and portions of ILD layer 236. Contact etch stop layer 238 may provide a mechanism to stop the etching process when contacts or vias for source/drain regions are formed. The contact etch stop layer 238 may be formed of a dielectric material having a different etch selectivity than an adjacent layer or component. Contact etch stop The stop layer 238 may include or may be a nitrogen-containing material, a silicon-containing material, and/or a carbon-containing material. In addition, the contact etch stop layer 238 may include or may be silicon nitride (Si _x N _y ) Silicon carbonitride (SiCN), carbon Nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or combinations thereof, among other examples. The contact etch stop layer 238 may be deposited using a deposition process such as ALD, CVD, or other deposition techniques.

As noted above, fig. 6A-6F are provided as examples. Other examples may differ from those described with respect to fig. 6A-6F.

Fig. 7 is a schematic diagram of an exemplary embodiment 700 of a semiconductor device 200 described herein. The top of fig. 7 shows a top view of a portion of the semiconductor device, and the bottom of fig. 7 shows a cross-sectional view of a portion of the semiconductor device 200 along section C-C in the top view. Section C-C is along the X-direction and passes through the portion of isolation region 210 adjacent to the associated dummy gate structure 614.

As shown in the cross-sectional view of fig. 7, isolation region 210 is adjacent to NMOS source/drain regions 212a and dummy gate structure 614 on opposite sides of isolation region 210. A spacer pad 612 is included between the dummy gate structure 614 and the isolation region 210. The width W4 of the spacer pad 612 between the dummy gate structure 614 and the isolation region 210 may be included in a range of about 2 nanometers to about 10 nanometers to reduce the likelihood of the first layer 602 squeezing into the dummy gate structure 614 and to provide sufficient area for forming the internal spacers 224. However, other values of this range are also within the scope of the invention.

Dummy gate structure 614 is adjacent to the portion of epitaxial layer 220 of PMOS source/drain region 212b that is located over STI region 206. In a top view of semiconductor device 200, portions of epitaxial layer 220 extend laterally outward along the Y-direction from buffer layer 216 and epitaxial layer 218 of PMOS source/drain regions 212 b. Spacer layer 234 is located between dummy gate structure 614 and epitaxial layer 220.

In addition, in the cross-sectional view of semiconductor device 200, spacer layer 234 surrounds the bottom of epitaxial layer 220. Thus, a spacer layer 234 is included in the cross-sectional view between the STI region 206 and the epitaxial layer 220. The top surface of spacer layer 234 located below epitaxial layer 220 may be at a greater height along the Z-direction in semiconductor device 200 relative to the height of the top surface of epitaxial region 214. The thickness T2 of spacer 234 between STI region 206 and epitaxial layer 220 may be included in the range of about 5 nanometers to about 35 nanometers to reduce the likelihood of epitaxial layer 220 squeezing into dummy gate structure 614 and to achieve sufficient growth of epitaxial layer 220. However, other values of this range are also within the scope of the invention.

As noted above, fig. 7 is provided as an example. Other examples may differ from those described with respect to fig. 7.

Fig. 8A and 8B are schematic diagrams of an exemplary embodiment 800 described herein. The exemplary embodiment 800 includes an example of a replacement gate process for replacing the dummy gate structure 614 with the gate structure 222 (e.g., a replacement gate structure) of the semiconductor device 200. In some embodiments, following the operations described in connection with fig. 6A-6F, the operations described in connection with exemplary embodiment 800 are implemented.

The top of fig. 8A shows a top view of a portion of the semiconductor device, and the bottom of fig. 8A shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (which corresponds to section A-A in fig. 2). As shown in fig. 8A, the replacement gate operation is implemented (e.g., by one or more semiconductor processing tools 102-112) to remove the dummy gate structure 614 and the isolation pad 612 from the semiconductor device 200. The removal of dummy gate structure 614 leaves an opening (or recess) between ILD layers 236 over the source/drain regions. Removal of the spacer 612 leaves a recess 306 in the sidewall of the nanoplatelet of the NMOS active region 208a, in the sidewall of the nanoplatelet of the PMOS active region 208b, and/or in the sidewall of the nanoplatelet of the spacer region 210. The dummy gate structures 614 and the isolation pads 612 may be removed in one or more etching operations performed by the etching tool 108. Such etching operations may include plasma etching techniques, wet chemical etching techniques, and/or other types of etching techniques.

As further shown in fig. 8A, a nanostructure release operation (e.g., siGe release operation) is performed to remove the first layer 602 (e.g., silicon germanium layer). This results in openings between the nano-sheets (e.g., the area around the nano-sheets) of the NMOS active region 208a, the PMOS active region 208b, and the isolation region 210. The nanostructure release operation may include: the etch tool 108 performs an etch operation that removes the first layer 602 based on the difference in etch selectivity between the material of the first layer 602 and the material of the nano-sheets of the NMOS active region 208a, the PMOS active region 208b, and the isolation region 210, and based on the difference in etch selectivity between the material of the first layer 602 and the material of the internal spacers 224. The inner spacers 224 may be used as an etch stop layer in an etching operation to protect the source/drain regions from etching.

The top of fig. 8B shows a top view of a portion of the semiconductor device, and the bottom of fig. 8B shows a cross-sectional view of a portion of the semiconductor device 200 along section A-A in the top view (corresponding to section A-A in fig. 2). As shown in fig. 8B, the replacement gate operation continues, wherein the deposition tool 102 and/or the plating tool 112 form gate structures 222 (e.g., replacement gate structures) in the openings between the source/drain regions and between the ILD layer 236. In particular, the gate structure 222 fills the area between and around the nanoplatelets (or nanostructure channels) previously occupied by the first layer 602 such that the gate structure 222 completely surrounds the nanoplatelets (or nanostructure channels) and surrounds the nanoplatelets (or nanostructure channels). The gate structure 222 may include a metal gate structure. A conformal high-k dielectric liner may be deposited prior to forming gate structure 222. The gate structure 222 may include additional layers such as interface layers, work function tuning layers, metal electrode structures, other layers described in connection with fig. 2, and/or other layers, as well as other examples.

As noted above, fig. 8A and 8B are provided as examples. Other examples may differ from those described with respect to fig. 8A and 8B.

Fig. 9 is a schematic diagram of an exemplary embodiment 900 of the semiconductor device 200 described herein. The semiconductor device 200 in the exemplary embodiment 900 may include a configuration and/or arrangement similar to the structure shown in fig. 2. However, in the exemplary embodiment 900, the isolation region 210 of the semiconductor device 200 is connected with the plurality of PMOS source/drain regions 212b.

As shown in fig. 9, the semiconductor device 200 may include NMOS source/drain regions 212a adjacent to the connection region 902 of the isolation region 210. The NMOS source/drain region 212a may be located between the connection region 902 and the NMOS active region 208 a.

As further shown in fig. 9, the semiconductor device 200 may include a first PMOS source/drain region 212b adjacent to the connection region 904 of the isolation region 210 opposite the connection region 902. The first PMOS active region 208b may be located adjacent to the first PMOS source/drain region 212b such that the first PMOS source/drain region 212b is located between the connection region 904 and the first PMOS active region 208 b.

The second PMOS source/drain region 212b may be located adjacent to the connection region 906 of the isolation region 210 that is also opposite the connection region 902. The second PMOS active region 208b may be located adjacent to the second PMOS source/drain region 212b such that the second PMOS source/drain region 212b is located between the connection region 906 and the second PMOS active region 208 b.

In some embodiments, the connection regions 904 and 906 are substantially parallel and aligned along the Y-direction of the semiconductor device 200. In some embodiments, connection region 904 and connection region 906 are not aligned along the Y-direction of semiconductor device 200.

As further shown in fig. 9, outer edges 908a and 908b of isolation region 210 are curved between connection region 902 and connection region 904, and between connection region 902 and connection region 906, respectively. Additionally, the inner edge 910 of the isolation region 210 may be continuous between the connection regions 904 and 906. The inner edge 910 may be curved in a generally U-shaped manner.

The curvature of the isolation region 210 described above may reduce the likelihood of merging between the NMOS source/drain region 212a adjacent to the isolation region 210 and the plurality of PMOS source/drain regions 212b adjacent to the isolation region 210. In particular, the curvature of outer edges 908a and 908b and the curvature of inner edge 910 may increase the distance between connection region 902 and connection regions 904 and 906. The increased distance between the connection region 902 and the connection regions 904 and 906 may reduce the likelihood that one or more layers of the NMOS source/drain regions 212a will merge with one or more of the plurality of PMOS source/drain regions 212b along the outer edges 908a and 908b and/or along the inner edge 910.

As noted above, fig. 9 is provided as an example. Other examples may differ from those described with respect to fig. 9.

Fig. 10 is a schematic diagram of exemplary components of a device 1000 described herein. In some embodiments, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transfer tool 114 may include one or more devices 1000 and/or components of one or more devices 1000. As shown in fig. 10, device 1000 may include a bus 1010, a processor 1020, a memory 1030, an input component 1040, an output component 1050, and a communication component 1060.

Bus 1010 includes one or more components that enable wired and/or wireless communication among the components of device 1000. Bus 1010 may connect two or more of the components of fig. 10 together, for example, by an operational connection, a communication connection, an electrical connection, and/or an electrical connection. Processor 1020 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and/or other types of processing components. The processor 1020 is implemented in hardware, a fixed component, or a combination of hardware and software. In some implementations, the processor 1020 includes one or more processors that are capable of being programmed to carry out one or more operations or processes described elsewhere herein.

Memory 1030 includes volatile and/or nonvolatile memory. For example, memory 1030 may include Random Access Memory (RAM), read Only Memory (ROM), a hard disk drive, and/or other types of memory (e.g., flash memory, magnetic memory, and/or optical memory). Memory 1030 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable over the universal serial bus connection). Memory 1030 may be a non-transitory computer-readable medium. Memory 1030 stores information, instructions, and/or software (e.g., one or more software applications) related to operation of device 1000. In some implementations, memory 1030 includes one or more memories coupled to one or more processors (e.g., processor 1020) via, for example, bus 1010.

Input component 1040 enables device 1000 to receive inputs, such as user inputs and/or sense inputs. For example, input components 1040 may include a touch screen, keyboard, keypad, mouse, buttons, microphone, switches, sensors, global positioning system sensors, accelerometers, gyroscopes, and/or actuators. Output component 1050 enables device 1000 to provide output, such as through a display, speakers, and/or light emitting diodes. The communication component 1060 enables the device 1000 to communicate with other devices via wired and/or wireless connections. For example, the communication component 1060 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

Device 1000 may implement one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1030) may store a set of instructions (e.g., one or more instructions or code) for execution by processor 1020. The processor 1020 may execute the set of instructions to implement one or more of the operations or processes described herein. In some implementations, execution of the set of instructions by the one or more processors 1020 causes the one or more processors 1020 and/or the device 1000 to perform one or more of the operations or processes described herein. In some implementations, one or more operations or processes described herein are implemented using hardwired circuitry in place of or in combination with instructions. Additionally or alternatively, the processor 1020 may be configured to implement one or more operations or processes described herein. Thus, embodiments described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown in fig. 10 are provided as examples. Device 1000 may include additional components, fewer components, different components, or components in a different arrangement than those shown in fig. 10. Additionally or alternatively, one set of components (e.g., one or more components) of device 1000 may implement one or more functions described as being implemented by another set of components of device 1000.

Fig. 11 is a flow chart of an exemplary process 1100 associated with forming a semiconductor device. In some implementations, one or more of the process blocks of FIG. 11 are implemented by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102-112). Additionally or alternatively, one or more process blocks of fig. 11 may be implemented by one or more components of device 1000, such as processor 1020, memory 1030, input component 1040, output component 1050, and/or communication component 1060.

As shown in fig. 11, process 1100 may include forming a nanoplatelet stack including a first plurality of nanoplatelets and a second plurality of nanoplatelets alternating with the first plurality of nanoplatelets (block 1110). For example, one or more of the semiconductor processing tools 102-112 may form a nano-sheet stack that includes a first plurality of nano-sheets (e.g., the first layer 602) and a second plurality of nano-sheets (e.g., the second layer 604) alternating with the first plurality of nano-sheets, as described above.

As further shown in fig. 11, process 1100 may include forming a first semiconductor device region, a second semiconductor device region, and a transition region extending between the first semiconductor device region and the second semiconductor device region along a first direction in a top view of the semiconductor device in the nanoplatelet stack (block 1120). For example, one or more of the semiconductor processing tools 102-112 may form a first semiconductor device region 606, a second semiconductor device region 608, and a transition region 610 extending between the first semiconductor device region 606 and the second semiconductor device region 608 along a first direction (e.g., along an X-direction) in a top view of the semiconductor device 200 in the nanoplatelet stack, as described above. In some embodiments, in a top view of semiconductor device 200, first semiconductor device region 606 and second semiconductor device region 608 are staggered along a second direction (e.g., Y-direction) that is substantially perpendicular to the first direction (e.g., X-direction).

As further shown in fig. 11, process 1100 may include forming a dummy gate structure over the transition region (block 1130). For example, one or more of the semiconductor processing tools 102-112 may form a dummy gate structure 614 over the transition region 610, as described above.

As further shown in fig. 11, process 1100 may include forming NMOS source/drain regions in a first semiconductor device region in the nanoplatelet stack (block 1140). For example, one or more of the semiconductor processing tools 102-112 may form NMOS source/drain regions 212a in the first semiconductor device region 606 in the nanoflake stack, as described above.

As further shown in fig. 11, process 1100 may include forming PMOS source/drain regions in a second semiconductor device region in the nanoplatelet stack (block 1150). For example, one or more of the semiconductor processing tools 102-112 may form PMOS source/drain regions 212b in the second semiconductor device region 608 in the nanoflake stack, as described above.

Process 1100 may include additional embodiments, such as any single embodiment or any combination of embodiments, of one or more other processes described below and/or elsewhere herein.

In the first embodiment, forming the NMOS source/drain region 212a includes forming the NMOS source/drain region 212a adjacent to the first connection region 308 of the transition region 610, and forming the PMOS source/drain region 212b includes forming the PMOS source/drain region 212b adjacent to the second connection region 310 of the transition region 610 opposite to the first connection region 308. In a second embodiment, alone or in combination with the first embodiment, the process 1100 includes forming a dummy gate structure 614 on a sidewall of the transition region 610 between the first connection region 308 and the second connection region 310, and forming the dummy gate structure 614 includes forming the dummy gate structure 614 on the spacer 612 over the sidewall of the transition region.

In a third embodiment, alone or in combination with one or more of the first and second embodiments, the process 1100 includes forming a first spacer layer 234 on a first side of the dummy gate structure 614 and forming a second spacer layer 234 on a second side of the dummy gate structure 614 opposite the first side, the first spacer layer 234 being adjacent to the first connection region 308 and the second spacer layer 234 being adjacent to the second connection region 310. In the fourth embodiment, alone or in combination with one or more of the first through third embodiments, the first spacer layer 234 is completely covered by the dummy gate structure 614 and the spacer liner 612 immediately adjacent to the first connection region 308, and the second spacer layer 234 is completely covered by the dummy gate structure 614 and the spacer liner 612 immediately adjacent to the second connection region 310.

In a fifth embodiment, either alone or in combination with one or more of the first through fourth embodiments, the NMOS source/drain region 212a includes a buffer layer 216 adjacent to the first connection region 308, a first epitaxial layer 220, and a second epitaxial layer 218 between the buffer layer 216 and the first epitaxial layer 220, wherein the length of the buffer layer 216 and the length of the first connection region 308 are substantially the same length.

While fig. 11 shows exemplary blocks of process 1100, in some embodiments process 1100 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in fig. 11. Additionally or alternatively, two or more blocks of process 1100 may be implemented in parallel.

The nanostructure transistor may be formed in a manner that may reduce the likelihood of source/drain regions merging in the nanostructure transistor. In a top view of the nanostructured transistors described herein, the source/drain regions on opposite sides of the nanostructured channel of the nanostructured transistor are staggered such that the distance between the source/drain regions increases. This reduces the likelihood of source/drain region merging, which reduces the likelihood of failure and/or other defects forming in the nanostructured transistor. Accordingly, staggering the source/drain regions, as described herein, may facilitate miniaturization of semiconductor devices including nanostructured transistors while maintaining and/or increasing semiconductor device yield of the semiconductor devices.

As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of channel layers arranged along a first direction over a semiconductor substrate. The semiconductor device includes a gate structure surrounding each of the plurality of channel layers. The semiconductor device includes a first source/drain region adjacent a first side of the plurality of channel layers. The semiconductor device includes a second source/drain region adjacent a second side of the plurality of channel layers, the second side opposite the first side along a second direction that is substantially perpendicular to the first direction, wherein the first side and the second side are offset a distance along a third direction in the semiconductor device that is substantially perpendicular to the first direction and the second direction in a top view of the semiconductor.

In some embodiments, in the top view of the semiconductor device, a length of the first source/drain region along the third direction is greater relative to a length of the second source/drain region along the third direction; wherein the first source/drain region comprises an n-type metal oxide semiconductor (NMOS) source/drain region; and wherein the second source/drain region comprises a p-type metal oxide semiconductor (PMOS) source/drain region. In some embodiments, in the top view of the semiconductor device, a first edge of the first source/drain region and a second edge of the second source/drain region are substantially parallel and not aligned along the second direction. In some embodiments, in the top view of the semiconductor device, a first edge of the plurality of channel layers is curved between the first side and the second side; and wherein, in the top view of the semiconductor device, second edges of the plurality of channel layers opposite the first side are curved between the first side and the second side. In some embodiments, the first amount of curvature of the second edge is greater relative to the second amount of curvature of the second edge. In some embodiments, in the top view of the semiconductor device, a length of the plurality of channel layers between a curved top of the second edge and the curved bottom of the second edge is smaller relative to a length of the first side. In some embodiments, in the top view of the semiconductor device, a length of the plurality of channel layers between a curved top of the first edge and the curved bottom of the first edge is greater relative to a length of the second side.

As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes an NMOS active region including a first plurality of nanoplatelets positioned over a semiconductor substrate. The semiconductor device includes a PMOS active region 208b, the PMOS active region 208b including a second plurality of nanoplatelets located over the semiconductor substrate. The semiconductor device includes an isolation region between the NMOS active region and the PMOS active region, the isolation region including a third plurality of nanoplatelets located over the semiconductor substrate. The semiconductor device includes a respective gate structure surrounding each of the first, second, and third pluralities of nanoplatelets, wherein the third plurality of nanoplatelets flex between the NMOS region and the PMOS region in a top view of the semiconductor device.

In some embodiments, in the top view of the semiconductor device, the length of the NMOS active region is greater relative to the length of the PMOS active region. In some embodiments, the isolation region is juxtaposed to an NMOS source/drain region of the semiconductor device and a PMOS source/drain region of the semiconductor device in a first cross-sectional view along a first direction that is substantially perpendicular to a second direction along which the respective gate structures extend; and wherein, in a second cross-sectional view along the first direction, the isolation region is juxtaposed with the NMOS source/drain regions of the respective gate structures of the semiconductor device and the gate structures surrounding the third plurality of nanoplatelets. In some embodiments, in the first cross-sectional view along the first direction, the NMOS source/drain region is located between the isolation region and the NMOS active region; and wherein, in the first cross-sectional view along the first direction, the PMOS source/drain region is located between the isolation region and the PMOS active region. In some embodiments, in the second cross-sectional view along the first direction, the NMOS source/drain region is located between the isolation region and the NMOS active region; and wherein, in the second cross-sectional view along the first direction, the gate structure is located between the isolation region and an interlayer dielectric (ILD) layer adjacent to the PMOS source/drain region along the second direction. In some embodiments, at least one of the NMOS active region or the PMOS active region includes recesses on opposite sides of the at least one of the NMOS active region or the PMOS active region in the top view of the semiconductor device. In some embodiments, the semiconductor device further comprises: an NMOS source/drain region adjacent to the first connection region of the isolation region; wherein the NMOS source/drain region is located between the first connection region and the NMOS active region; a first PMOS source/drain region adjacent a second connection region of the isolation region opposite the first connection region, wherein the PMOS active region comprises a first PMOS active region adjacent the first PMOS source/drain region, and wherein the first PMOS source/drain region is located between the second connection region and the first PMOS active region; a second PMOS source/drain region adjacent a third connection region of said isolation region opposite said first connection region; and a second PMOS active region, wherein the second PMOS source/drain region is located between the third connection region and the second PMOS active region.

As described in more detail above, some embodiments described herein provide a method. The method includes forming a nanoplatelet stack including a first plurality of nanoplatelets and a second plurality of nanoplatelets alternating with the first plurality of nanoplatelets. The method includes forming a first semiconductor device region, a second semiconductor device region, and a transition region extending between the first semiconductor device region and the second semiconductor device region along a first direction in a top view of the semiconductor device, wherein the first semiconductor device region and the second semiconductor device region are staggered along a second direction that is substantially perpendicular to the first direction in the top view of the semiconductor device. The method includes forming a dummy gate structure over the transition region. The method includes forming NMOS source/drain regions in a first semiconductor device region in the nanoplatelet stack. The method includes forming PMOS source/drain regions in a second semiconductor device region in the nanoplatelet stack.

In some embodiments, forming the NMOS source/drain regions comprises: forming the NMOS source/drain region adjacent to a first connection region (308) of the transition region; and wherein forming the PMOS source/drain regions comprises: the PMOS source/drain region is formed adjacent to a second connection region of the transition region opposite the first connection region. In some embodiments, the method further comprises: forming a spacer on sidewalls of the transition region between the first connection region and the second connection region, wherein forming the dummy gate structure comprises: the dummy gate structure is formed on the isolation liner over the sidewalls of the transition region. In some embodiments, the method further comprises: forming a first spacer layer on a first side of the dummy gate structure; and forming a second spacer layer on a second side of the dummy gate structure opposite the first side, wherein the first spacer layer is adjacent to the first connection region, and wherein the second spacer layer is adjacent to the second connection region. In some embodiments, the first spacer layer is entirely covered by the dummy gate structure and the isolation liner immediately adjacent the first connection region; and wherein the second spacer layer is entirely covered by the dummy gate structure and the isolation liner immediately adjacent the second connection region. In some embodiments, the PMOS source/drain regions include: a buffer layer adjacent to the first connection region; a first epitaxial layer; and a second epitaxial layer between the buffer layer and the first epitaxial layer, wherein a length of the buffer layer and a length of the first connection region are substantially the same length.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device, comprising:

a plurality of channel layers arranged along a first direction over the semiconductor substrate;

a gate structure surrounding each of the plurality of channel layers;

a first source/drain region adjacent a first side of the plurality of channel layers; and

a second source/drain region adjacent a second side of the plurality of channel layers, the second side opposite the first side along a second direction substantially perpendicular to the first direction,

wherein in a top view of the semiconductor, the first side and the second side are offset a distance along a third direction in the semiconductor device that is substantially perpendicular to the first direction and the second direction.

2. The semiconductor device of claim 1, wherein a length of the first source/drain region along the third direction is greater relative to a length of the second source/drain region along the third direction in the top view of the semiconductor device;

wherein the first source/drain region comprises an n-type metal oxide semiconductor (NMOS) source/drain region; and is also provided with

Wherein the second source/drain region comprises a p-type metal oxide semiconductor (PMOS) source/drain region.

3. The semiconductor device of claim 1, wherein, in the top view of the semiconductor device, a first edge of the first source/drain region and a second edge of the second source/drain region are substantially parallel and not aligned along the second direction.

4. The semiconductor device of claim 1, wherein, in the top view of the semiconductor device, first edges of the plurality of channel layers are curved between the first side and the second side; and is also provided with

Wherein, in the top view of the semiconductor device, second edges of the plurality of channel layers opposite the first edges are curved between the first side and the second side.

5. The semiconductor device of claim 4, wherein the first amount of curvature of the first edge is greater relative to the second amount of curvature of the second edge.

6. The semiconductor device of claim 4, wherein in the top view of the semiconductor device, a length of the plurality of channel layers between a curved top of the second edge and the curved bottom of the second edge is smaller relative to a length of the first side.

7. The semiconductor device of claim 4, wherein in the top view of the semiconductor device, a length of the plurality of channel layers between a curved top of the first edge and the curved bottom of the first edge is greater relative to a length of the second side.

8. A semiconductor device, comprising:

an n-type metal oxide semiconductor (NMOS) active region comprising a first plurality of nanoplatelets positioned over a semiconductor substrate;

a p-type metal oxide semiconductor (PMOS) active region comprising a second plurality of nanoplatelets located over the semiconductor substrate;

an isolation region between the NMOS active region and the PMOS active region comprising a third plurality of nanoplatelets over the semiconductor substrate; and

A respective gate structure surrounding each of the first plurality of nanoplatelets, the second plurality of nanoplatelets, and the third plurality of nanoplatelets,

wherein, in a top view of the semiconductor device, the third plurality of nanoplatelets are curved between the NMOS region and the PMOS region.

9. The semiconductor device of claim 8, wherein the NMOS active region has a greater length relative to the length of the PMOS active region in the top view of the semiconductor device.

10. A method of forming a semiconductor device, comprising:

forming a nanoplatelet stack comprising a first plurality of nanoplatelets and a second plurality of nanoplatelets alternating with the first plurality of nanoplatelets;

forming in the nanoplatelet stack:

a first semiconductor device region is provided which has a first semiconductor device region,

a second semiconductor device region, and

a transition region extending between the first semiconductor device region and the second semiconductor device region along a first direction in a top view of the semiconductor device,

wherein, in the top view of the semiconductor device, the first semiconductor device region and the second semiconductor device region are staggered along a second direction substantially perpendicular to the first direction;

Forming a dummy gate structure over the transition region;

forming n-type metal oxide semiconductor (NMOS) source/drain regions in the first semiconductor device region in the nanoplatelet stack; and

p-type metal oxide semiconductor (PMOS) source/drain regions are formed in the second semiconductor device region in the nanoplatelet stack.