CN116682783A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

Info

Publication number
CN116682783A
CN116682783A CN202310651326.XA CN202310651326A CN116682783A CN 116682783 A CN116682783 A CN 116682783A CN 202310651326 A CN202310651326 A CN 202310651326A CN 116682783 A CN116682783 A CN 116682783A
Authority
CN
China
Prior art keywords
layer
hard mask
etching
metal layer
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310651326.XA
Other languages
Chinese (zh)
Inventor
王嘉南
黄永彬
李乐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GTA Semiconductor Co Ltd
Original Assignee
GTA Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GTA Semiconductor Co Ltd filed Critical GTA Semiconductor Co Ltd
Priority to CN202310651326.XA priority Critical patent/CN116682783A/en
Publication of CN116682783A publication Critical patent/CN116682783A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein an isolation device is formed in the substrate, and the isolation device is provided with a metal layer protruding from the substrate; forming a barrier layer coating the metal layer, and sequentially stacking a dielectric layer and a hard mask layer on the barrier layer; etching the hard mask layer and the dielectric layer to form an initial through hole by taking the barrier layer as an etching stop layer; cleaning the initial through hole; etching the barrier layer to expose part of the surface of the metal layer by taking the etched hard mask layer as a mask so as to form a target through hole; cleaning the target through hole; and forming a connection structure in contact with the metal layer in the target through hole to obtain the semiconductor structure. According to the technical scheme, through twice etching and twice cleaning, etching byproducts are thoroughly cleaned, gaps between the connecting structure and the metal layer are reduced, and device performance is improved.

Description

Semiconductor structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
In the semiconductor process, in order to make the isolation device reach high voltage resistance, a thicker Inter-Metal Dielectric (IMD) layer is required to be disposed on the Metal layer of the isolation device. Please refer to fig. 1, which is a schematic diagram illustrating a semiconductor structure according to an embodiment of the prior art. As shown in fig. 1, the semiconductor structure includes: a metal layer 11, an inter-metal dielectric layer 12, and a connection structure 13. The inter-metal dielectric layer 12 wraps the metal layer 11, and the bottom of the connection structure 13 is located above the metal layer 11, and the top of the connection structure is substantially flush with the surface of the inter-metal dielectric layer 12. The inter-metal dielectric layer 12 has a relatively large thickness, and thus a relatively deep Via (Via) needs to be etched for forming the connection structure 13, and a large amount of by-products (polymers) are generated during the etching. Since the byproducts generated by etching are difficult to be thoroughly removed by one-time cleaning, the byproducts remaining in the through holes volatilize during the subsequent processes such as annealing, and a gap 14 is generated between the metal layer 11 and the connection structure 13, so that the resistance value of the isolation device is too high, and the electromigration test (EM) fails.
Therefore, how to improve the semiconductor process and reduce the generation of the gap between the metal layer of the isolation device and the connection structure is a problem to be solved at present.
Disclosure of Invention
The invention aims to solve the technical problems of improving a semiconductor process, reducing the generation of gaps between a metal layer of an isolation device and a connecting structure, and providing a semiconductor structure and a preparation method thereof.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a substrate, wherein an isolation device is formed in the substrate, and the isolation device is provided with a metal layer protruding out of the substrate; forming a barrier layer coating the metal layer, and sequentially stacking a dielectric layer and a hard mask layer on the barrier layer; etching the hard mask layer and the dielectric layer to form an initial through hole by taking the blocking layer as an etching stop layer; cleaning the initial through hole; etching the barrier layer until part of the surface of the metal layer is exposed by taking the etched hard mask layer as a mask, so as to form a target through hole; cleaning the target through hole; and forming a connection structure in contact with the metal layer in the target through hole to obtain the semiconductor structure.
In some embodiments, the step of forming a barrier layer covering the metal layer and a dielectric layer and a hard mask layer sequentially stacked on the barrier layer further comprises: depositing a blocking material on the surface of the substrate to form a blocking layer, wherein the blocking layer wraps the surface and two side surfaces of the metal layer, and the etching selectivity of the blocking layer is smaller than that of the dielectric layer; depositing a dielectric material on the surface of the barrier layer to form a dielectric layer, wherein the thickness of the dielectric layer is larger than a preset threshold value; and depositing a hard mask material on the surface of the dielectric layer to form the hard mask layer.
In some embodiments, the barrier layer and the hard mask layer are the same material.
In some embodiments, the step of forming the initial via hole by using the barrier layer as an etching stop layer and etching the hard mask layer and the dielectric layer further comprises: spin-coating a photoresist layer on the surface of the hard mask layer and patterning; and etching the hard mask layer and the dielectric layer by taking the patterned photoresist layer as a mask and the barrier layer as an etching stop layer until part of the surface of the barrier layer is exposed, so as to form the initial through hole.
In some embodiments, the step of cleaning the initial via further comprises: and cleaning byproducts generated in the etching process by adopting an alkaline solution.
In some embodiments, the step of etching the barrier layer to expose a portion of the surface of the metal layer with the etched hard mask layer as a mask, to form a target via further includes: etching the barrier layer until part of the surface of the metal layer is exposed by taking the etched hard mask layer as a mask, so as to form the target through hole; and removing the residual hard mask layer.
In some embodiments, the step of cleaning the target via further comprises: and cleaning byproducts generated in the etching process by adopting an alkaline solution.
In some embodiments, the step of forming a connection structure in contact with the metal layer in the target via further includes: depositing a conductive material within the target via and planarizing to form the connection structure, a bottom of the connection structure in contact with the metal layer, and a top of the connection structure substantially flush with a surface of the dielectric layer.
In order to solve the above problems, the present invention provides a semiconductor structure, which is manufactured by the method of the present invention, comprising: a substrate in which an isolation device having a metal layer protruding from the substrate is formed; the barrier layer is positioned on the surface of the metal layer and wraps two side surfaces of the metal layer; the dielectric layer is positioned on the surface of the barrier layer; and the connecting structure is formed in the blocking layer and the dielectric layer, the bottom of the connecting structure is in contact with the metal layer, and the top of the connecting structure is basically flush with the surface of the dielectric layer.
In some embodiments, the thickness of the dielectric layer is greater than a predetermined threshold.
According to the technical scheme, the barrier layer is formed on the surface of the metal layer of the isolation device, the hard mask layer is formed on the surface of the dielectric layer on the barrier layer, and etching byproducts are thoroughly cleaned through twice etching and twice cleaning, so that gaps between the connection structure and the metal layer are reduced, and the performance of the device is improved; meanwhile, the blocking layer formed on the surface of the metal layer can further increase the withstand voltage of the device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described. It is apparent that the drawings in the following description are only some specific embodiments of the present invention, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structure diagram of an embodiment of a semiconductor structure in the prior art.
Fig. 2 is a flowchart illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention.
Fig. 3A-3G are process flow diagrams illustrating an embodiment of a method for fabricating a semiconductor structure according to the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Referring to fig. 2-3G, fig. 2 is a flowchart illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the invention; fig. 3A-3G are process flow diagrams illustrating an embodiment of a method for fabricating a semiconductor structure according to the present invention.
As shown in fig. 2, the method for preparing the semiconductor structure according to the embodiment includes the following steps: step S21, providing a substrate, wherein an isolation device is formed in the substrate, and the isolation device is provided with a metal layer protruding out of the substrate; step S22, forming a barrier layer coating the metal layer, and a dielectric layer and a hard mask layer which are sequentially stacked on the barrier layer; step S23, etching the hard mask layer and the dielectric layer to form an initial through hole by taking the barrier layer as an etching stop layer; step S24, cleaning the initial through hole; step S25, etching the barrier layer until part of the surface of the metal layer is exposed by taking the etched hard mask layer as a mask, so as to form a target through hole; step S26, cleaning the target through hole; and step S27, forming a connection structure in contact with the metal layer in the target through hole to obtain the semiconductor structure.
Referring to fig. 3A and step S21, a substrate 30 is provided, in which an isolation device is formed, and the isolation device has a metal layer 31 protruding from the substrate. In some embodiments, the material of the metal layer 31 may be metallic titanium (Ti). In other embodiments, the material of the metal layer 31 may also be titanium nitride (TiN).
Referring to fig. 3B and step S22, a barrier layer 32 covering the metal layer 31, and a dielectric layer 33 and a hard mask layer 34 sequentially stacked on the barrier layer 32 are formed. In some embodiments, the step of forming the barrier layer 32 covering the metal layer 31 and the dielectric layer 33 and the hard mask layer 34 sequentially stacked on the barrier layer 32 further includes: depositing a barrier material on the surface of the substrate 30 to form the barrier layer 32, wherein the barrier layer 32 wraps the surface and two side surfaces of the metal layer 31, and the etching selectivity of the barrier layer 32 is smaller than that of the dielectric layer 33; depositing a dielectric material on the surface of the barrier layer 32 to form a dielectric layer 33; a hard mask material is deposited on the surface of the dielectric layer 33 to form the hard mask layer 34. The etching selectivity ratio refers to the relative etching rate of one material to another material under the same etching conditions, and is defined as the ratio of the etching rate of the etched material to the etching rate of the other material. The etching process with high etching selectivity can only etch the material with high etching selectivity, and the material with small etching selectivity can not be etched.
In some embodiments, the thickness of the dielectric layer 33 is greater than a predetermined threshold, and the isolation device achieves high withstand voltage by using a thicker dielectric layer.
In some embodiments, the methods of forming the barrier layer 32, the dielectric layer 33, and the hard mask layer 34 include, but are not limited to, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, the barrier layer 32 and the hard mask layer 34 are the same material. In this embodiment, the material of the blocking layer 32 and the hard mask layer 34 may be silicon nitride (SiN), and the material of the dielectric layer 33 may be silicon dioxide (SiO 2).
Referring to step S23 of fig. 3C, the hard mask layer 34 and the dielectric layer 33 are etched to form an initial via 39 by using the barrier layer 32 as an etching stop layer. In some embodiments, the step of forming the initial via 39 by using the barrier layer 32 as an etching stop layer and etching the hard mask layer 34 and the dielectric layer 33 further includes: spin-coating a photoresist layer on the surface of the hard mask layer 34 and patterning; the hard mask layer 34 and the dielectric layer 33 are etched to expose a portion of the surface of the barrier layer 32 with the patterned photoresist layer as a mask and the barrier layer 32 as an etch stop layer, thereby forming the initial via 39. Since the depth of the initial through hole 39 formed by etching is deeper and the thickness of the photoresist layer of the mask is thicker, a large amount of byproducts 38 generated in the etching process are difficult to volatilize to the outside and remain in the initial through hole 39.
In some embodiments, the hard mask layer 34 and the dielectric layer 33 are etched to form an initial via 39, and the hard mask layer 34 and the dielectric layer 33 may be etched using either a dry etch or a wet etch.
In this embodiment, wet etching is used to etch the hard mask layer 34 and the dielectric layer 33. Taking photoresist as a mask, firstly adopting a hot phosphoric acid wet etching process to etch the hard mask layer 34 until the etching is stopped at the dielectric layer 33; and then, taking the hard mask layer 34 as a mask, and adopting buffer oxide etching liquid to etch the dielectric layer 33 until the etching is stopped at the position of the barrier layer 32. Due to phosphoric acid (H) 3 PO 4 ) The etch rate for silicon nitride is much greater than the etch rate for silicon oxide, so the hard mask layer 34 is etched using heated phosphoric acid. The buffer oxide etching liquid is formed by mixing ammonium fluoride and water.
In other embodiments, the hard mask layer 34 and the dielectric layer 33 may also be etched by dry etching. The etching apparatus ionizes inert gas (such as argon) into plasma by glow discharge, contains positively charged ions and free electrons, accelerates the charged ions under the action of an externally applied electric field, and bombards the hard mask layer 34 and the dielectric layer 33, so as to knock out atoms of the hard mask layer 34 and the dielectric layer 33, thereby completing etching.
Referring to step S24 of fig. 3D, the initial via 39 is cleaned. In some embodiments, the step of cleaning the initial via 39 further comprises: the by-product 38 generated during etching is cleaned with an alkaline solution. In this example, the alkaline solution was an alkaline solution composed of an Amine-based Stripper (Amine-based Stripper), an organic solvent, an anticorrosive agent (Corrosion Inhibitor), and water. The amines here are mainly hydroxylamines (HDA for short). The initial through holes 39 are soaked in an alkaline solution for 2min at a temperature of 25-40 ℃, then washed with deionized water to remove residual alkaline solution, and then dried in a nitrogen atmosphere. After the initial via 39 is cleaned, a portion of the by-product 38 is removed, and a small amount of by-product 38 remains.
Referring to step S25 of fig. 3E, the barrier layer 32 is etched until a portion of the surface of the metal layer 31 is exposed, with the etched hard mask layer 34 as a mask, so as to form a target via 37. In some embodiments, the step of etching the barrier layer 32 to expose a portion of the surface of the metal layer 31 with the etched hard mask layer 34 as a mask to form the target via hole 37 further includes: etching the barrier layer 32 until part of the surface of the metal layer 31 is exposed by using the etched hard mask layer 34 as a mask, so as to form the target through hole 37; the remaining hard mask layer 34 is removed. In the process of etching to form the target via hole 37, since only the barrier layer 32 is etched, fewer byproducts 38 are generated. In addition, since the photoresist layer in step S23 has been removed, the distance from the bottom of the target via hole 37 to the surface of the structure is reduced, and the byproducts 38 in the etching process are more easily volatilized, and the byproducts 38 remain less and are more easily removed.
In some embodiments, the barrier layer 32 may be etched using either a dry etch or a wet etch to etch the barrier layer 32.
In this embodiment, the barrier layer 32 is etched by wet etching. And taking the hard mask layer 34 as a mask, and simultaneously etching the barrier layer 32 and the hard mask layer 34 by adopting a hot phosphoric acid wet etching process until the etching is stopped at the metal layer 31. The barrier layer 32 and the hard mask layer 34 are etched using heated phosphoric acid. Since the barrier layer 32 is the same material as the hard mask layer 34, the hard mask layer 34 is removed when the barrier layer 32 is etched. In some embodiments, the hard mask layer 34 is completely removed, exposing the surface of the dielectric layer 33. In other embodiments, a portion of the hard mask layer 34 remains, and the remaining hard mask layer 34 may further improve the voltage endurance and reliability of the device.
In other embodiments, the barrier layer 32 and the hard mask layer 34 may also be etched by dry etching. The etching apparatus ionizes inert gas (such as argon) into plasma by glow discharge, contains positively charged ions and free electrons, accelerates the charged ions under the action of an externally applied electric field, and bombards the barrier layer 32 and the hard mask layer 34, so as to strike atoms of the barrier layer 32 and the hard mask layer 34, thereby completing etching.
Referring to step S26 of fig. 3F, the target through hole 37 is cleaned. In some embodiments, the step of cleaning the target via 37 further comprises: a small amount of by-product 38 generated during etching is cleaned with an alkaline solution. In this example, the alkaline solution was an alkaline solution composed of an Amine-based Stripper (Amine-based Stripper), an organic solvent, an anticorrosive agent (Corrosion Inhibitor), and water. The amines here are mainly hydroxylamines (HDA for short). The initial through holes 39 are soaked in an alkaline solution for 2min at a temperature of 25-40 ℃, then washed with deionized water to remove residual alkaline solution, and then dried in a nitrogen atmosphere. After cleaning the target via hole 37, the by-product 38 is completely removed.
Referring to step S27 of fig. 3G, a connection structure 35 contacting the metal layer 31 is formed in the target via 37, so as to obtain the semiconductor structure. In some embodiments, the step of forming the connection structure 35 in contact with the metal layer 31 in the target via 37 further includes: a conductive material is deposited and planarized within the target via 37 to form the connection structure 35, the bottom of the connection structure 35 being in contact with the metal layer 31, the top of the connection structure 35 being substantially flush with the surface of the dielectric layer 33.
In some embodiments, the connection structure 35 may be formed by filling the target via 37 with a conductive material using a chemical vapor deposition, an atomic layer deposition, or the like. The connection structure 35 is used to connect the metal layer 31 of the isolation device with an external circuit. In this embodiment, the material of the connection structure 35 is tungsten metal. In other embodiments, the material of the connection structure 35 may be titanium nitride, metal silicide, copper, or copper tungsten alloy.
According to the technical scheme, the barrier layer is formed on the surface of the metal layer of the isolation device, the hard mask layer is formed on the surface of the dielectric layer on the barrier layer, and etching byproducts are thoroughly cleaned through twice etching and twice cleaning, so that gaps between the connection structure and the metal layer are reduced, and the performance of the device is improved; meanwhile, the blocking layer formed on the surface of the metal layer can further increase the withstand voltage of the device.
Based on the same thought, the invention also provides a semiconductor structure.
The semiconductor structure is manufactured by adopting the manufacturing method of the semiconductor structure shown in the figures 2-3G. Referring to fig. 3G, the semiconductor structure includes: a substrate 30, a metal layer 31, a barrier layer 32, a dielectric layer 33, a connection structure 35. An isolation device having a metal layer 31 protruding from the substrate is formed in the substrate 30. The barrier layer 32 is located on the surface of the metal layer 31, and the barrier layer 32 wraps both sides of the metal layer 31. The dielectric layer 33 is located on the surface of the barrier layer 32. The connection structure 35 is formed in the barrier layer 32 and the dielectric layer 33, and the bottom of the connection structure 35 is in contact with the metal layer 31, and the top of the connection structure 35 is substantially flush with the surface of the dielectric layer 33.
According to the technical scheme, the barrier layer is formed on the surface of the metal layer of the isolation device, the hard mask layer is formed on the surface of the dielectric layer on the barrier layer, and etching byproducts are thoroughly cleaned through twice etching and twice cleaning, so that gaps between the connection structure and the metal layer are reduced, and the performance of the device is improved; meanwhile, the blocking layer formed on the surface of the metal layer can further increase the withstand voltage of the device.
In some embodiments, the thickness of the dielectric layer 33 is greater than a predetermined threshold, and the isolation device achieves high withstand voltage by using a thicker dielectric layer.
In some embodiments, the material of the metal layer 31 may be metallic titanium (Ti). In other embodiments, the material of the metal layer 31 may also be titanium nitride (TiN).
In some embodiments, the material of the barrier layer 32 may be silicon nitride (SiN), and the material of the dielectric layer 33 may be silicon dioxide (SiO 2).
In some embodiments, the surface of the dielectric layer 33 may further include a hard mask layer (not shown), which is a hard mask layer remaining in the etching process for forming the semiconductor device, so as to further improve the withstand voltage and reliability of the device.
The connection structure 35 is used to connect the metal layer 31 of the isolation device with an external circuit. In this embodiment, the material of the connection structure 35 is tungsten metal. In other embodiments, the material of the connection structure 35 may be titanium nitride, metal silicide, copper, or copper tungsten alloy.
It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein, depending at least in part on the context, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a feature, structure, or combination of features in a plural sense. Similarly, terms such as "a," "an," or "the" may also be construed to express singular usage or plural usage depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to express a set of exclusive factors, but may instead, depending at least in part on the context, allow for other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected/coupled" means not only that one component is directly coupled to another component, but also that one component is indirectly coupled to another component through intervening components.
It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present invention and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present invention. In the foregoing embodiments, each embodiment is mainly described for differences from other embodiments, and the same/similar parts between the embodiments are referred to each other.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate, wherein an isolation device is formed in the substrate, and the isolation device is provided with a metal layer protruding out of the substrate;
forming a barrier layer coating the metal layer, and sequentially stacking a dielectric layer and a hard mask layer on the barrier layer;
etching the hard mask layer and the dielectric layer to form an initial through hole by taking the blocking layer as an etching stop layer;
cleaning the initial through hole;
etching the barrier layer until part of the surface of the metal layer is exposed by taking the etched hard mask layer as a mask, so as to form a target through hole;
cleaning the target through hole;
and forming a connection structure in contact with the metal layer in the target through hole to obtain the semiconductor structure.
2. The method of claim 1, wherein the step of forming a barrier layer surrounding the metal layer and a dielectric layer, a hard mask layer, sequentially stacked over the barrier layer further comprises:
depositing a blocking material on the surface of the substrate to form a blocking layer, wherein the blocking layer wraps the surface and two side surfaces of the metal layer, and the etching selectivity of the blocking layer is smaller than that of the dielectric layer;
depositing a dielectric material on the surface of the barrier layer to form a dielectric layer, wherein the thickness of the dielectric layer is larger than a preset threshold value;
and depositing a hard mask material on the surface of the dielectric layer to form the hard mask layer.
3. The method of claim 1, wherein the barrier layer and the hard mask layer are the same material.
4. The method of claim 1, wherein the step of forming an initial via using the barrier layer as an etch stop layer, etching the hard mask layer and the dielectric layer further comprises:
spin-coating a photoresist layer on the surface of the hard mask layer and patterning;
and etching the hard mask layer and the dielectric layer by taking the patterned photoresist layer as a mask and the barrier layer as an etching stop layer until part of the surface of the barrier layer is exposed, so as to form the initial through hole.
5. The method of claim 1, wherein the step of cleaning the initial via further comprises: and cleaning byproducts generated in the etching process by adopting an alkaline solution.
6. The method of claim 1, wherein etching the barrier layer to expose a portion of the surface of the metal layer with the etched hard mask layer as a mask to form a target via further comprises:
etching the barrier layer until part of the surface of the metal layer is exposed by taking the etched hard mask layer as a mask, so as to form the target through hole;
and removing the residual hard mask layer.
7. The method of claim 1, wherein the step of cleaning the target via further comprises: and cleaning byproducts generated in the etching process by adopting an alkaline solution.
8. The method of claim 1, wherein the step of forming a connection structure in contact with the metal layer within the target via further comprises:
depositing a conductive material within the target via and planarizing to form the connection structure, a bottom of the connection structure in contact with the metal layer, and a top of the connection structure substantially flush with a surface of the dielectric layer.
9. A semiconductor structure produced by the method of any one of claims 1 to 8, comprising:
a substrate in which an isolation device having a metal layer protruding from the substrate is formed;
the barrier layer is positioned on the surface of the metal layer and wraps two side surfaces of the metal layer;
the dielectric layer is positioned on the surface of the barrier layer;
and the connecting structure is formed in the blocking layer and the dielectric layer, the bottom of the connecting structure is in contact with the metal layer, and the top of the connecting structure is basically flush with the surface of the dielectric layer.
10. The semiconductor structure of claim 9, wherein a thickness of the dielectric layer is greater than a predetermined threshold.
CN202310651326.XA 2023-06-02 2023-06-02 Semiconductor structure and preparation method thereof Pending CN116682783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310651326.XA CN116682783A (en) 2023-06-02 2023-06-02 Semiconductor structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310651326.XA CN116682783A (en) 2023-06-02 2023-06-02 Semiconductor structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116682783A true CN116682783A (en) 2023-09-01

Family

ID=87780459

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310651326.XA Pending CN116682783A (en) 2023-06-02 2023-06-02 Semiconductor structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116682783A (en)

Similar Documents

Publication Publication Date Title
US9941199B2 (en) Two step metallization formation
EP0987745B1 (en) Metallization etching method using a hard mask layer
EP1233449A2 (en) A method of fabricating a semiconductor device
KR20100122701A (en) Method of manufacturing semiconductor device
US20160358859A1 (en) Reducing contact resistance in vias for copper interconnects
CN101452879A (en) Cleaning method after opening etching
US6872652B2 (en) Method of cleaning an inter-level dielectric interconnect
CN102148191A (en) Formation method for contact hole
CN105097650B (en) The forming method of contact plunger
CN106206408B (en) Method for forming semiconductor structure
KR100555512B1 (en) Manufacturing method for semiconductor device using poly silicon etching mask
US8258041B2 (en) Method of fabricating metal-bearing integrated circuit structures having low defect density
TWI579919B (en) Dry etching gas and method of manufacturing semiconductor device
WO2002039489A2 (en) Method for removing etch residue resulting from a process for forming a via
US8277674B2 (en) Method of removing post-etch residues
CN104979275B (en) Method for forming contact plug
US7125809B1 (en) Method and material for removing etch residue from high aspect ratio contact surfaces
CN116682783A (en) Semiconductor structure and preparation method thereof
US20070045227A1 (en) Method of stripping photoresist
US11688604B2 (en) Method for using ultra thin ruthenium metal hard mask for etching profile control
JP2000164569A (en) Manufacture of semiconductor device
JPH11204507A (en) Manufacture of semiconductor device
US7297630B2 (en) Methods of fabricating via hole and trench
JP4482217B2 (en) Semiconductor device cleaning agent and semiconductor device cleaning method
KR100835506B1 (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination