CN116682478A

CN116682478A - OTP memory cell detection method and device in chip test process

Info

Publication number: CN116682478A
Application number: CN202310373154.4A
Authority: CN
Inventors: 汪锡
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-04
Filing date: 2023-04-04
Publication date: 2023-09-01

Abstract

The disclosure provides a method and equipment for detecting one-time programmable OTP memory cells in a chip test process, and relates to the technical field of semiconductors. The method comprises the following steps: acquiring a first record file of the semiconductor chip after the semiconductor chip is tested by a first test station; obtaining first OTP unit state result record data according to a first record file; acquiring a second record file of the semiconductor chip after the semiconductor chip is tested by a second test station; obtaining second OTP unit state result record data according to the second record file; and obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data. According to the method and the device, the OTP unit with abnormal information is detected through the first OTP unit state result record data and the second OTP unit state result record data, so that the yield of the semiconductor chip is ensured.

Description

OTP memory cell detection method and device in chip test process

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a method and a device for detecting an OTP memory cell in a chip test process.

Background

One-time programmable (OTP) memory cells have found wide application in recent years due to their low cost and compatibility with logic processes. The OTP memory is used for programming necessary information, such as repair information, parameter information, and other chip-related information.

The information recorded by the OTP memory cell is critical to the proper operation of a semiconductor chip such as a dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM). In general, several thousands to hundreds of thousands of different OTP memory cells are designed in each semiconductor chip, and information abnormality of any one OTP memory cell may cause failure of the semiconductor chip, so it is important to detect the information abnormality of the OTP memory cell.

How to detect the OTP memory cell with abnormal information is a problem to be solved.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure provides an OTP memory cell detection method and device in a chip test process, which can detect an OTP memory cell with abnormal information.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to one aspect of the present disclosure, there is provided a one-time programmable OTP memory cell detection method in a chip test process, the method including: acquiring a first record file of the semiconductor chip after the semiconductor chip is tested by a first test station; obtaining first OTP unit state result record data according to the first record file; acquiring a second record file of the semiconductor chip after being tested by a second test station, wherein the first test station and the second test station are continuous front and rear test stations; obtaining second OTP unit state result record data according to the second record file; and obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result recording data and the second OTP unit state result recording data.

According to another aspect of the present disclosure, there is provided a one-time programmable OTP unit cell detection device in a chip test process, the device including: the acquisition module is used for acquiring a first record file of the semiconductor chip after the semiconductor chip is tested by the first test station; the acquisition module is further used for acquiring first OTP unit state result record data according to the first record file; the acquisition module is further used for acquiring a second record file of the semiconductor chip after the semiconductor chip is tested by a second test station, and the first test station and the second test station are two continuous front and rear test stations; the acquisition module is further used for acquiring second OTP unit state result record data according to the second record file; the detection module is used for obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result recording data and the second OTP unit state result recording data.

According to yet another aspect of the present disclosure, there is provided a computer device comprising one or more processors; a memory configured to store one or more programs that, when executed by the one or more processors, cause the computer device to implement a one-time programmable OTP unit cell detection method in a chip test procedure in any of the embodiments of the disclosure.

According to yet another aspect of the present disclosure, there is provided a computer readable storage medium storing a computer program adapted to be loaded and executed by a processor to cause a computer device having the processor to perform the one-time programmable OTP unit detection method in the chip test procedure in any of the embodiments of the present disclosure.

According to yet another aspect of the present disclosure, there is provided a computer program product that when executed by a processor implements a one-time programmable OTP unit cell detection method in a chip test process in any of the embodiments of the present disclosure.

According to the one-time programmable OTP unit detection method and device in the chip test process, a first record file after a semiconductor chip is tested by a first test site and a second record file after the semiconductor chip is tested by a second test site are respectively obtained, first OTP unit state result record data are obtained according to the first record file, second OTP unit state result record data are obtained according to the second record file, and cross-site OTP unit state detection results of the semiconductor chip are obtained according to the first OTP unit state result record data and the second OTP unit state result record data. According to the method and the device, the OTP unit with abnormal information is detected through the first OTP unit state result record data and the second OTP unit state result record data, so that the yield of the semiconductor chip is ensured.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 shows a schematic structural diagram of a wafer according to an embodiment of the disclosure.

Fig. 2 illustrates an OTP memory cell detection system provided by an embodiment of the disclosure.

Fig. 3 illustrates an OTP memory cell detection system of the present disclosure in an efuse full flow monitoring application scenario.

Fig. 4 is a flowchart illustrating an OTP memory cell detection method according to an embodiment of the disclosure.

Fig. 5 is a flowchart illustrating an OTP memory cell detection method according to another embodiment of the disclosure.

Fig. 6 shows a schematic diagram of the programming process of the present disclosure.

Fig. 7 is a flowchart of a method for in-station detection of OTP memory cells at any detection site according to an embodiment of the disclosure.

Fig. 8 is a flowchart illustrating an OTP memory cell detection method according to still another embodiment of the disclosure.

Fig. 9 is a schematic diagram of a one-time programmable OTP memory cell detection device during a chip test according to an embodiment of the disclosure.

Fig. 10 shows a schematic structural diagram of a computer device in an embodiment of the disclosure.

Fig. 11 shows a schematic diagram of a computer-readable storage medium in an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units.

It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to mean "one or more" unless the context clearly indicates otherwise, where "a plurality" means two or more.

The semiconductor manufacturing process may be divided into a preceding process and a following process. Specifically, the preceding process is a process for a whole Wafer (Wafer) which may include Wafer fabrication and Wafer testing (the test object is for each Die in the whole Wafer) in order to ensure that each Die in the whole Wafer substantially meets the device characteristics or design specifications, which may include verification of voltage, current, timing, function, etc.). The subsequent processes are all the processes for starting with each chip after being diced and packaged by the wafer, and can comprise the processes of packaging, final testing, finished product warehouse-in and the like.

Before the semiconductor chip is shipped, various tests are performed on the semiconductor chip, for example, fig. 1 shows a schematic structure of a wafer according to an embodiment of the disclosure. As shown in fig. 1, a Wafer (Wafer) 10 may include a plurality of dies (Die) 11 thereon. During the circuit probe Test (Circuit Probe Test, CP Test) phase, the wafer 10 can obtain different failed units under different Test conditions, and then repair the failed units by using the standby circuit. For another example, before shipment, FT (Final Test, post Test) and burn-in Test (Repair During Burn In, RDBI) are performed.

The inventor found through research that during the test process, one-time programmable (OTP, one-time programmable) memory cell abnormality may cause failure of the semiconductor chip. The OTP memory (hereinafter referred to as OTP cell) includes fuse (fuse) and antifuse (Anti-fuse) types, wherein the fuse includes electrical fuse (efuse) and laser-fuse (laser-fuse) types. For example, an antifuse (Anti-fuse) is formed by a high voltage breakdown gate oxide (gate oxide), and is in a high resistance state before breakdown, and in a low resistance state after breakdown, and is used for writing necessary information, and is widely used in semiconductor chip design production.

OTP memory cells are widely used in semiconductor chips such as DRAM, and for example, OTP memory cells are mainly used to record information in DRAM, for example, at least one of chip (chip) ID (Identity), trimming information (Trim information), repair information (Repair information), and the like. Information recorded by the OTP memory cells is critical to normal operation of the DRAM, often thousands to hundreds of thousands of different OTP memory cells are designed in each DRAM Die (Die), and information abnormality of any one OTP memory cell may cause failure of the DRAM chip, so it is critical to detect the OTP memory cell with abnormal information.

Based on this, the embodiment of the disclosure provides a method, a device, an electronic device and a storage medium for detecting an OTP memory cell in a chip test process, which can be applied to a semiconductor manufacturing scenario. The following embodiments are illustrated in the specific scenario of efuse detection applied to DRAM, or may also be the specific scenario of efuse state monitoring, analysis and processing, but the disclosure is not limited thereto. In the embodiment of the disclosure, the OTP memory cell with abnormal information is detected through the first OTP cell state result record data and the second OTP cell state result record data, so that the yield of the semiconductor chip is ensured.

In order to facilitate overall understanding of the technical solution provided by the embodiments of the present disclosure, an OTP memory cell detection system provided by the embodiments of the present disclosure is first described.

As shown in fig. 2, the OTP memory unit inspection system includes an OTP unit data acquisition module 21 and a controller 22, where the OTP unit data acquisition module 21 may acquire a first record file of a semiconductor chip after the semiconductor chip is tested by a first test site and acquire a second record file of the semiconductor chip after the semiconductor chip is tested by a second test site, the first test site and the second test site are two consecutive test sites, the OTP unit data acquisition module 21 sends the acquired first record file and second record file to the controller 22, the controller 22 obtains first OTP unit state result record data according to the first record file, obtains second OTP unit state result record data according to the second record file, and obtains a cross-site OTP unit state inspection result of the semiconductor chip based on the first OTP unit state result record data and the second OTP unit state result record data.

For example, as shown in fig. 3, the OTP memory cell detection system in the efuse full-process monitoring application scenario is a full-process monitoring system, which can be understood as monitoring all process data in the semiconductor chip production process, and clearly shows each process to be monitored through an interface. In fig. 3, it is assumed that the OTP memory cell inspection system includes 3 test sites, namely, a test site (CP test site) 31 for CP test and a test site (RDBI test site) 32 for RDBI test, a test site (FT test site) 33 for FT test, a die generates a w_fuse file after CP test is performed on CP test site 31 (CP test site 31 is the first test site at this time), the w_fuse file is a file for recording the test in CP test site 31, a first record file is obtained according to the w_fuse file, the first record file is stored in a Database (Database, DB 1), the die is packaged (Package) after CP test, a semiconductor chip is obtained, and the semiconductor chip enters RDBI test site 32 (RDBI test site 32 is the second test site at this time), an r_fuse file is generated, the r_fuse file is a file for recording the test in RDBI test site 32, a second record file is obtained according to the r_fuse file, and the second record file is stored in DB2. The controller can respectively obtain first OTP unit state result record data and second OTP unit state result record data according to the first record file stored in the DB1 and the second record file stored in the DB2, and perform first offline classification (offline sorting, also called offline classification) on the basis of the first OTP unit state result record data and the second OTP unit state result record data, so as to obtain a first cross-site OTP unit state detection result, perform first rejection or degradation on the semiconductor chips which do not meet the requirements according to the first cross-site OTP unit state detection result, and enter the semiconductor chips which meet the requirements into subsequent tests, so that the workload of the subsequent tests (FT tests) is reduced, and the test efficiency is improved. After that, the semiconductor chips meeting the requirements after the first offline classification may enter the FT test site 33 (at this time, the FT test site 33 corresponds to the second test site, and the RDBI test site 32 corresponds to the first test site, and obtains the first record file according to the corresponding r_fuse file) for performing the FT test, generating the f_fuse file, obtaining the second record file according to the f_fuse file, and storing the second record file in the DB3. The controller can respectively obtain first OTP unit state result record data and second OTP unit state result record data according to the first record file and the second record file, and carry out second offline classification based on the first OTP unit state result record data and the second OTP unit state result record data, so as to obtain a second cross-site OTP unit state detection result, reject or degrade the semiconductor chip which does not meet the requirements through multiple cross-site OTP unit state detection results, and improve the test accuracy.

It should be noted that, in the embodiment of the present disclosure, the cross-site test refers to a test for detecting whether information stored in the OTP memory unit is abnormal across two or more test sites, for example, in fig. 3, the cross-site test includes a test between a CP test site and an RDBI test site and/or a test between an RDBI test site and an FT test site, which is not limited in this disclosure, and any test may be used as long as it is a test between two adjacent test sites.

Firstly, an embodiment of the disclosure provides a method for detecting an OTP memory cell in a chip test process, which may be executed by any electronic device having a computing processing capability. The method may be performed by semiconductor test equipment such as automated test equipment (Automatic Test Equipment, ATE), for example, or by other processing devices communicatively coupled to the semiconductor test equipment, as is not particularly limited.

Fig. 4 is a flowchart illustrating a method for detecting an OTP memory cell during a chip test according to an embodiment of the disclosure, and as shown in fig. 4, the method provided in the embodiment of the disclosure may include the following steps S401 to S405.

S401, a first record file of the semiconductor chip after being tested by a first test site is obtained.

In the embodiment of the disclosure, the first test station refers to any one of two adjacent test stations through which the semiconductor chip sequentially passes in the test process. The first record file is a record file generated by the semiconductor chip after the test of the first test site is completed, and the first record file can comprise any relevant information of the semiconductor chip and any relevant information of the semiconductor chip for the test at the first test site. Any information related to the testing by the first test site includes one or more of programming state information of the OTP unit detected before the testing, programming state information of the OTP unit detected during the testing, and programming state information of the OTP unit detected after the testing is completed. For example, the first record file may include programming status information of an OTP memory cell included in the semiconductor chip and a chip identifier of the semiconductor chip, where the programming status information may be used to indicate a programming status of the OTP cell included in the semiconductor chip during the testing at the first test site, and the programming status may include programmed and un-programmed. The chip identifier may include one or more of a chip ID of the semiconductor chip, a wafer code of a wafer to which the semiconductor chip belongs, and a position coordinate of the semiconductor chip on the wafer to which the semiconductor chip belongs.

Note that a programming (blow) OTP unit is a process of recording information in an OTP unit, or may be also referred to as a programming program (program). For example, if the OTP unit indicates record information 0 before programming, record information 1 is indicated after programming; in contrast, if the OTP unit indicates record information 1 before programming, record information 0 is indicated after programming.

S402, obtaining first OTP unit state result record data according to the first record file.

In the embodiment of the disclosure, the first OTP unit state result record data refers to data related to the state of the OTP unit included in the semiconductor chip, which is recorded by the semiconductor chip through the test of the first test station, and may include, for example, the total number of the OTP units included in the semiconductor chip and first state information of each OTP unit, where the first state information is used to indicate a writing state of the OTP unit in the test process of the first test station, and the writing state includes writing and non-writing.

According to the embodiment of the disclosure, the files (the W_FUSE file, the R_FUSE file and the F_FUSE file) detected by programming in the recording site are simplified, the record files (the first record file or the second record file) are obtained, and the simplified record files are stored in the database, so that the database can store more record files of the testing site, wherein the files detected by programming in the recording site can be one of the W_FUSE file, the R_FUSE file and the F_FUSE file. For example, assuming that the first test site is a CP test site, the w_fuse file is obtained after the test is completed, and only the writing state information including the OTP unit detected after the test of the first test site is stored as the first record file in the database, without storing the writing state information including the OTP unit detected before the test of the first test site in the w_fuse file. It can be said that the data used for detecting the abnormality is stored in the database.

S403, obtaining a second record file of the semiconductor chip after the semiconductor chip is tested by a second test station, wherein the first test station and the second test station are continuous front and rear test stations.

In the embodiment of the disclosure, the second test station refers to another test station except the first test station from two adjacent test stations through which the semiconductor chip sequentially passes in the test process. For example, one of the two consecutive test stations is a first test station and the other is a second test station. The second log file may include any information related to the semiconductor chip that is tested at the second test station. Any information related to the test performed by the second test site includes one or more of programming state information of the OTP unit detected before the test, programming state information of the OTP unit detected during the test, and programming state information of the OTP unit detected after the test is completed. For example, the second record file may include programming status information of the OTP memory cell included in the semiconductor chip and a chip identifier of the semiconductor chip, where the programming status information may be used to indicate a programming status of the OTP cell included in the semiconductor chip during the second test site test, and the programming status may include programmed and un-programmed. The chip identifier may include one or more of a chip ID of the semiconductor chip, a wafer code of a wafer to which the semiconductor chip belongs, and a position coordinate of the semiconductor chip on the wafer to which the semiconductor chip belongs.

S404, obtaining second OTP unit state result record data according to the second record file.

In an embodiment of the disclosure, the second OTP unit state result record data refers to data related to the state of the OTP unit included in the semiconductor chip, which is recorded by the semiconductor chip through the test of the second test station, and may include, for example, the total number of the OTP units included in the semiconductor chip and second state information of each OTP unit, where the second state information is used to indicate a writing state of the OTP unit in the test process of the second test station, and the writing state includes writing and non-writing.

The embodiment of the disclosure can simplify the second OTP unit state result record data, and store the simplified data into the database, so that the database can store more data of the test sites. Illustratively, only the programming state information of the OTP cells detected before the second test site test is stored in the database, and the programming state information of the OTP cells detected after the second test site test is not stored. That is, data used for detecting whether an abnormality is present in the database.

S405, obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data.

The cross-site detection is to detect the abnormal situation of the OTP unit through the test data (the first OTP unit state result record data and the second OTP unit state result record data) of two adjacent test sites. The adjacent test sites refer to two tests sequentially performed in time, and are exemplified by a test site for performing CP test on the OTP unit first and a test site for performing RDBI test on the OTP unit later, wherein the test site for the CP test and the test site for the RDBI test are adjacent test sites.

The writing state of each OTP unit after test or the writing state in test of the first test site can be obtained according to the first OTP unit state result recording data, and the writing state of each OTP unit before writing of the second test site can be obtained according to the second OTP unit state result recording data, so that whether the OTP unit is abnormal or not is judged.

It should be noted that, the test of the semiconductor chip such as DRAM generally spans multiple test sites, and the multiple test sites may read and write the programming state of the OTP unit, so that whether the states between the sites are normal or not can be checked by the present disclosure, which is a key for guaranteeing the test quality of the semiconductor chip.

According to the embodiment of the disclosure, the cross-site OTP unit state detection result of the semiconductor chip is obtained according to the first OTP unit state result recording data and the second OTP unit state result recording data, so that the OTP unit with abnormal information is detected, and the shipment quality of the semiconductor chip is ensured.

According to the embodiment of the disclosure, the detection flow of the OTP memory cell of the semiconductor chip can be perfected through cross-site inspection, and the whole flow detection in the production process of the semiconductor chip can be realized, so that the quality of semiconductor shipment is further improved.

How to perform cross-site detection (cross stage check) is described below.

In an exemplary embodiment, the first OTP unit state result record data includes a total number of OTP units in the semiconductor chip and first state information of each OTP unit; the second OTP unit state result record data includes the total number of OTP units and second state information of each OTP unit. Obtaining a cross-site OTP unit state detection result of the semiconductor chip from the first OTP unit state result record data and the second OTP unit state result record data may include the following steps A1 to A3.

Step A1, counting the number of burnt OTP units after testing at a first test site according to first state information of each OTP unit; and obtaining the number of the un-programmed OTP units after the test of the first test site according to the total number of the OTP units and the number of the programmed OTP units after the test of the first test site.

Illustratively, the number of unwritten OTP cells after the first test site test is the difference between the total number of OTP cells and the number of unwritten OTP cells after the first test site test.

The first state information indicates a programming state of the OTP unit in the test process of the first test site, wherein the programming state information comprises programming state information of the OTP unit detected before the test of the first test site and programming state information of the OTP unit detected after the test is completed, and the programming state comprises programmed or un-programmed. The number of programmed OTP cells after the test at the first test site can be counted according to the first state information.

It should be noted that the number of the programmed OTP cells is the total number of the programmed OTP cells counted in the test of the first test site, where the total number of the programmed OTP cells includes the sum of the number of the OTP cells that have been programmed by the other test sites before the test of the first test site and the number of the OTP cells programmed in the test of the first test site.

In an embodiment of the disclosure, the first test station may be a wafer test CP station and the second test station may be a burn-in test RDBI station. Alternatively, the first test station is an RDBI station, and the second test station is a FT back-end test station.

Step A2, counting the number of burnt OTP units before the test of a second test site according to the second state information of each OTP unit; and obtaining the number of the un-programmed OTP units before the test of the second test station according to the total number of the OTP units and the number of the programmed OTP units before the test of the second test station.

Illustratively, the number of unwritten OTP cells prior to the second test site test is the difference between the total number of OTP cells and the number of unwritten OTP cells prior to the second test site test.

The second state information may include a programming state of the OTP cell detected by the second test station before the test and a programming state of the OTP cell detected after the test, the programming state including programmed or un-programmed.

Step A3, obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the number of the un-programmed OTP units after the test of the first test site and the number of the un-programmed OTP units before the test of the second test site; and/or obtaining a cross-site OTP cell state detection result of the semiconductor chip according to the number of the programmed OTP cells after the test of the first test site and the number of the programmed OTP cells before the test of the second test site.

Illustratively, the embodiments of the present disclosure may determine whether an OTP cell is abnormal by the number of unwritten OTP cells after the first test site test and the number of unwritten OTP cells before the second test site test. For example, if the number of the un-programmed OTP cells after the test at the first test station is not equal to the number of the un-programmed OTP cells before the test at the second test station, the semiconductor chip is abnormal, that is, the information programmed by the OTP cells of the semiconductor chip is abnormal. If the number of the un-programmed OTP units after the test of the first test station is equal to the number of the un-programmed OTP units before the test of the second test station, the semiconductor chip is normal.

Illustratively, the present disclosure may also determine whether the OTP cells are abnormal by the number of programmed OTP cells after the first test site test and the number of programmed OTP cells before the second test site test. For example, if the number of programmed OTP cells after the first test site test and the number of programmed OTP cells before the second test site test are not equal, the semiconductor chip is abnormal; if the number of programmed OTP cells after the test at the first test station is equal to the number of programmed OTP cells before the test at the second test station, the semiconductor chip is normal.

It should be noted that, the present disclosure may also determine whether the semiconductor chip is abnormal through a combination of the above two examples.

According to the embodiment of the disclosure, a cross-site OTP unit state detection result of a semiconductor chip is obtained through the number of the un-programmed OTP units after the test of a first test site and the number of the un-programmed OTP units before the test of a second test site; and/or, the number of the programmed OTP units after the test of the first test site and the number of the programmed OTP units before the test of the second test site obtain the state detection result of the cross-site OTP units of the semiconductor chip, so that the OTP units with abnormal information are detected, and the detection is simple and convenient and is convenient to realize.

In another exemplary embodiment, the first OTP unit state result record data includes a total number of OTP units in the semiconductor chip and first state information of each OTP unit; the second OTP unit state result record data includes a total number of OTP units and second state information of each OTP unit;

as shown in fig. 5, obtaining a cross-site OTP unit state detection result of the semiconductor chip from the first OTP unit state result record data and the second OTP unit state result record data may include S501 to S505.

S501, counting the number of first error OTP units with the state of programmed in the test process of the first test site and the state of un-programmed before the test of the second test site according to the first state information and the second state information of each OTP unit.

The specific details of the first status information and the second status information are described in the step A1 and the step A2, and are not described herein.

The state of the OTP unit in the test process of the first test site is the state of the OTP unit after programming.

For example, if the state is a programmed OTP cell during testing at the first test site, the state should also be a programmed state before testing at the next test site (the second test site), and if the state is inconsistent (the state is programmed during testing at the first test site and the state is not programmed before testing at the second test site), the OTP cell may be damaged for some reason during the cross-site process, or the first test site does not program the OTP cell (is not programmed), and similar abnormal situations may be found through the cross-site test according to the embodiment of the disclosure. For example, the number of first erroneous OTP cells is the number of OTP cells whose states are inconsistent.

S502, obtaining a programming failure ratio according to the number of the first error OTP units and the number of the programmed OTP units in the testing process of the first testing site.

The ratio of the write failure is obtained by the following formula 1:

wherein U1 is the programming failure ratio, Q1 is the number of first error OTP units, and Q is the number of programmed OTP units in the testing process of the first test site.

S503, counting the number of second error OTP units with the status of not programmed in the testing process of the first test site and the status of programmed before the testing of the second test site according to the first status information and the second status information of each OTP unit.

For example, if the state is not consistent (the state is not programmed during the test of the first test station and the state is programmed before the test of the second test station) during the test of the first test station, the OTP unit may be damaged for some reason during the cross-station process, or if the first test station does not program the OTP unit (is not programmed), similar abnormal conditions may be found by the cross-station test of the embodiment of the disclosure. For example, the number of second erroneous OTP cells is the number of OTP cells whose states are inconsistent.

S504, obtaining the error programming ratio according to the number of the second error OTP units and the number of the un-programmed OTP units in the testing process of the first testing site.

The ratio of the mis-writing is obtained by the following formula 2:

wherein M1 is the ratio of the programming error, P1 is the number of the second error OTP units, and P is the number of the un-programmed OTP units in the test process of the first test site.

And S505, performing degradation processing on the semiconductor chip under the condition that the programming failure ratio is larger than a first preset value or the error programming ratio is larger than a second preset value.

Illustratively, the level of the semiconductor chip is maintained in the case where the unwritten ratio is less than or equal to a first preset value and the miswritten ratio is less than or equal to a second preset value.

The present disclosure is not limited as to what the first preset value and the second preset value are, as long as the process requirement can be satisfied, for example, the first preset value is 0 and the second preset value is 0.

For example, in the case where the ratio of the write failure is greater than 0, or the ratio of the erroneous write is greater than 0, the degradation process is performed on the semiconductor chip. For another example, in the case where the un-programmed ratio is less than or equal to 0 and the mis-programmed ratio is less than or equal to 0, the rank of the semiconductor chip is maintained.

According to the embodiment of the disclosure, the semiconductor chips which are not in accordance with the requirements are degraded, so that the semiconductor chips which are in accordance with the requirements enter the subsequent test, the workload of the subsequent test is reduced, and the test efficiency is improved.

As shown in fig. 6, the OTP unit programming includes Direct Current (DC) programming for programming parameters such as internal voltage, adjustment information (Trim information), chip identification, etc., and Alternating Current (AC) programming for programming repair-related information, for example, repair information (Repair information). The DC programming and the AC programming are sometimes performed only once, and when the first programming is not performed, the second programming is required, and when the second programming is not performed, the third programming is required. Illustratively, re-programming (Re-assignment) is programming for a reassigned fuse (fuse) that was not programmed successfully in the previous AC programming test, for example, the location of a failed cell (Fail Bit) was originally intended to be repaired with an a redundancy allocation (Redundancy Allocation, RA), but the fuse was not successfully programmed, and may be replaced with a B redundancy allocation to be repaired, and the corresponding fuse for B is rebuilt after the replacement.

The DC programming and the AC programming can ensure that the OTP unit to be programmed is programmed without omission through multiple times of programming. It should be noted that, each time programming, a read operation is performed, and it is checked whether or not the information read (check) matches the information programmed. The process record file is a file for recording programming detection in the site, the process record file can comprise state information of all OTPs in each step and each semiconductor chip, the state information of the OTPs can comprise which OTPs need programming, and the OTP reading result shows which OTPs are programmed. And storing the record file containing the final writing state into a Database (DB), namely storing the first record file containing the first OTP unit state result record data and the second record file containing the second OTP unit state result record data into the database.

The first record file and the second record file both include data read under a first preset condition and data read under a second preset condition. The difference between the data read under the first preset condition, which is the data read with a tighter condition, and the data read under the second preset condition, which is the data read with a looser condition, is the read condition, wherein the tightness and looseness are the ease with which the OTP cell is judged to be successfully programmed. For example, when an electric fuse (efuse) is programmed, whether the efuse is blown or not is judged, the resistance of the efuse needs to be measured, and whether the efuse is blown or not is judged by comparing the measured resistance of the efues with a reference resistance. If the reference resistance value includes a first reference resistance value and a second reference resistance value, wherein the first reference resistance value is greater than the second reference resistance value, the first reference resistance value is selected to determine whether the efuse is blown in a manner of determining whether the efuse is blown under a first preset condition (tight), and the obtained measurement result is data read under the first preset condition. And similarly, selecting a second reference resistance value to judge whether the efuse is fused in a mode of judging the fusing under a second preset condition (loose), wherein the obtained measurement result is the data read under the second preset condition. For another example, when an antifuse (Anti-fuse) is programmed, whether the Anti-fuse is blown or not is determined, the resistance of the Anti-fuse needs to be measured, and whether the Anti-fuse is blown or not is determined by comparing the measured resistance of the Anti-fuse with a reference resistance. If the reference resistance value includes a first reference resistance value and a second reference resistance value, wherein the first reference resistance value is smaller than the second reference resistance value, the first reference resistance value is selected to determine whether the Anti-fuse is fused in a manner of determining fusing under a first preset condition (tight), and the obtained measurement result is data read under the first preset condition. And similarly, selecting a second reference resistance value to judge whether the Anti-fuse is fused in a mode of judging fusing under a second preset condition (loose), wherein the obtained measurement result is data read under the second preset condition.

The Anti-fuse can break down the gate oxide layer by high voltage, and shows a high resistance state before fusing and shows a low resistance state after fusing. And the efuse is opposite to the efuse, the efuse presents a low-resistance state before being fused, and presents a high-resistance state after being fused. Thus, the smaller the reference resistance, the tighter the condition for the Anti-fuse. While a larger reference resistance value is more conditioned on efuse. The cross-site inspection is performed by the data read under the first preset condition and the data read under the second preset condition, and 4 implementation schemes are totally adopted, and 1 st is that the cross-site OTP unit state detection result of the semiconductor chip is obtained according to the data read under the first preset condition (first OTP unit state result record data) obtained by the first test site and the data read under the first preset condition (second OTP unit state result record data) obtained by the second test site. And 2 nd is to obtain a cross-site OTP unit state detection result of the semiconductor chip according to the data (first OTP unit state result record data) read under the first preset condition obtained by the first test site and the data (second OTP unit state result record data) read under the second preset condition obtained by the second test site. And 3 rd is to obtain the cross-site OTP unit state detection result of the semiconductor chip according to the data (first OTP unit state result record data) read under the second preset condition obtained at the first test site and the data (second OTP unit state result record data) read under the first preset condition obtained at the second test site. And 4. Obtaining the cross-site OTP unit state detection result of the semiconductor chip according to the data (first OTP unit state result record data) read under the second preset condition obtained by the first test site and the data (second OTP unit state result record data) read under the second preset condition obtained by the second test site.

The first test station uses data read under a first preset condition as first state information, the second test station uses data read under a second preset condition as second state information, the number of the first error OTP units is screened according to the first state information and the second state information, the first test station uses data read under the second preset condition as first state information, the second test station uses data read under the first preset condition as second state information, and the number of the second error OTP units is screened according to the first state information and the second state information. Wherein the tightness and looseness are for the ease with which the OTP cell is judged to be successfully programmed. That is, the number accuracy of the first erroneous OTP cells read out is higher in the case where the programming is not easy to succeed, and the number accuracy of the second erroneous OTP cells read out is higher in the case where the programming is easy to succeed, thereby improving the accuracy of the detection of the present disclosure.

When the OTP unit is abnormal, re-programming (Re-assignment), reading and checking are required, so that the probability of missing programming the OTP unit can be reduced and the yield can be improved.

According to the embodiment of the disclosure, whether the OTP unit is abnormal or not is judged through the error programming ratio and the programming failure ratio, and the judgment accuracy is improved.

In still another exemplary embodiment, before obtaining the cross-site OTP unit state detection result of the semiconductor chip based on the first OTP unit state result record data and the second OTP unit state result record data, the OTP memory unit detection method may further include: acquiring a chip identifier of a semiconductor chip; and acquiring the first OTP unit state result record data and the second OTP unit state result record data which belong to the same semiconductor chip according to the chip identification.

The chip identifier is used to distinguish between different semiconductor chips, and may include one or more of a chip ID, wafer NO, and a location coordinate (die coordinate), but the embodiment of the present disclosure is not limited thereto.

Illustratively, obtaining the cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data may include: and obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data which belong to the same semiconductor chip.

The first OTP unit state result record data and the second OTP unit state result record data may be offline data.

According to the embodiment of the disclosure, the first OTP unit state result record data and the second OTP unit state result record data belonging to the same semiconductor chip can be rapidly determined through the chip identification, and further the first state information and the second state information belonging to the same OTP unit can be rapidly determined. The efficiency of anomaly detection is improved.

In-site detection (In stage check) is described below.

In an exemplary embodiment, the testing of the first test station may include the following steps B1 to B8.

And step B1, executing at least one burning test.

The burn-in test may refer to a burn-in test performed within the first test site. The burn-in test performed at the first test site may include one or more of a DC burn-in test, an AC burn-in test, and a reassigned AC burn-in test, which is not limited in this disclosure. For example, the burn-in test may include a DC burn-in test. As another example, the burn-in test may include a DC burn-in test and an AC burn-in test. As another example, as shown in fig. 7, the burn-in test includes a DC burn-in test, an AC burn-in test, and a reassignment AC burn-in test.

And B2, updating the first OTP unit state result record data after each programming test is completed until all programming tests are completed, and outputting a first record file containing the first OTP unit state result record data.

The first OTP unit state result record data includes a total number of OTP units in the semiconductor chip, first program information of each OTP unit, and first state information of each OTP unit.

The first status information is already described in step A1, and will not be described herein.

And B3, after each programming test is completed, counting the number of third error OTP units which are subjected to programming in the first test site and have the un-programmed state after the current programming test according to the first programming information and the first state information of each OTP unit in the updated first OTP unit test record data.

The first programming information indicates status information of whether programming is performed on the OTP unit cell during the test at the first test site, the status information including whether programming is performed and/or whether programming is not performed. The first state information corresponds to read (read) state information for indicating a programming state of the OTP cell during testing at the first test site, the programming state including programmed (programmed successful) or un-programmed.

Illustratively, the number of OTP cells that are programmed should be consistent with the number of OTP cells that have been programmed during the first test site test. If the states are inconsistent (burn-in has been performed in the first test site and the state is not burned-in after the current burn-in test), an exception is indicated for the semiconductor chip. If the states are consistent, the semiconductor chip is normal. For example, the number of third erroneous OTP units is the number of OTP units whose states are inconsistent.

It should be noted that the first test site test may include one of a CP site, an RDBI site, and an FT site.

And B4, calculating the ratio of the number of the third error OTP units to the number of the OTP units which are subjected to programming in the first test site, and obtaining the first in-site ratio corresponding to the current programming test.

The first intra-station ratio is obtained by the following formula 3:

wherein U2 is the first intra-station ratio, Y1 is the number of third erroneous OTP units, and Y is the number of OTP units on which programming has been performed in the first test station.

Step B5, obtaining the number of OTP units which are not programmed in the first test station according to the total number of OTP units and the number of OTP units which are programmed in the first test station.

The number of OTP cells that have not been programmed in the first test station is, for example, the difference between the total number of OTP cells and the number of OTP cells that have been programmed in the first test station.

Step B6, counting the number of fourth error OTP units which are not programmed in the first test site and are programmed after the current programming test according to the first programming information and the first state information of each OTP unit.

Illustratively, the number of OTP cells that are not programmed should be consistent with the number of OTP cells that are not programmed in the first test station when tested at the first test station. If the states are inconsistent (no programming is performed in the first test station and the state is programmed after the current programming test), an exception is indicated for the semiconductor chip. If the states are consistent, the semiconductor chip is normal. For example, the number of fourth erroneous OTP cells is the number of OTP cells whose states are inconsistent.

And B7, calculating the ratio of the number of the fourth error OTP units to the number of the OTP units which are not subjected to programming in the first test site, and obtaining a second in-site ratio corresponding to the current programming test.

The second intra-station ratio is obtained by the following equation 4:

Wherein M2 is the second intra-station ratio, X1 is the number of fourth erroneous OTP cells, and X is the number of OTP cells in the first test site that have not been programmed.

For example, as shown in fig. 3, the intra-site detection and the cross-site detection can be simultaneously detected, and the detection result is displayed through a detection report, so that the visualization effect is good. The detection area is more comprehensive through the simultaneous detection of the in-site detection and the cross-site detection, and the shipment quality of the semiconductor chips is further guaranteed.

And step B8, determining whether the semiconductor chip is subjected to degradation processing or not according to the first in-station ratio and the second in-station ratio.

According to the embodiment of the disclosure, whether the semiconductor chip is subjected to degradation treatment or not is judged through the first in-station ratio and the second in-station ratio, and the degradation treatment is performed on the semiconductor chip which does not meet the requirements, so that the workload of a subsequent manufacturing process can be reduced. Illustratively, during the direct current programming, the semiconductor chip with the first station ratio value greater than 0 or the second station ratio value greater than 0 is degraded.

According to the embodiment of the disclosure, the first in-station ratio and the second in-station ratio can be obtained through the first programming information and the first state information of each OTP unit, so that the OTP units with abnormal information are detected, and the shipment quality of the semiconductor chips is guaranteed.

In another exemplary embodiment, the first record file includes first OTP unit test record data corresponding to each test in the first test site; the first OTP unit test record data includes a total number of OTP units in the semiconductor chip, current programming information of each OTP unit, and current state information of each OTP unit; the testing of the first test station may include the following steps C1 to C8.

And step C1, executing at least one burning test.

The burn-in test may refer to a burn-in test performed within the first test site.

And C2, after each programming test is completed, acquiring first OTP unit test record data corresponding to the current programming test, and updating a first record file according to the first OTP unit test data corresponding to each programming test.

The first OTP unit test record data is data recorded by recording a file (process record file) of the burn-in test in the first test site, and the first record file is updated by the first OTP unit test record data, that is, the first OTP unit state result record data included in the first record file is updated by the first OTP unit test record data.

And C3, counting the number of third error OTP units which are subjected to programming in the testing process of the first test site and are in an un-programmed state after the current programming test according to the current programming information and the current state information of each OTP unit in the testing record data of the first OTP unit.

The current programming information is information recorded by a process record file and is used for indicating whether the programming is performed on the OTP unit or not in the test process of the first test site, and the state information comprises the programming performed and/or the programming not performed. The current state information is information recorded by a process record file and is used for indicating the programming state of the OTP unit in the test process of the first test site, wherein the programming state comprises programmed (programmed succeeded) or un-programmed.

And C4, calculating the ratio of the number of the third error OTP units to the number of the OTP units which are subjected to programming in the testing process of the first test site, and obtaining a first in-site ratio corresponding to the current programming test.

The calculation method of the first intra-station ratio is the same as that in step B4, and will not be described here again.

And step C5, obtaining the number of OTP units which are not subjected to programming in the test process of the first test site according to the total number of OTP units and the number of OTP units which are subjected to programming in the test process of the first test site.

The number of OTP units not programmed is the same as that calculated in step B5, and will not be described here.

And step C6, counting the number of fourth error OTP units which are not programmed in the test process of the first test site and have the programmed state after the current programming test according to the first programming information and the first state information of each OTP unit.

And C7, calculating the ratio of the number of the fourth error OTP units to the number of the OTP units which are not subjected to programming in the testing process of the first test site, and obtaining a second in-site ratio corresponding to the current programming test.

The calculation method of the second intra-station ratio is the same as that in step B7, and will not be described here again.

And step C8, determining whether the semiconductor chip is subjected to degradation processing or not according to the first in-station ratio and the second in-station ratio.

Illustratively, as shown in fig. 7, whether the semiconductor chip is degraded during the in-station test includes the following S701 to S712.

S701, judging whether the natural fusing ratio meets the requirement, if yes, executing S702, and if not, executing S712. Exemplary, if the natural blowing ratio is greater than 0, it indicates that there is a natural blown OTP unit cell, and degradation processing is performed on the semiconductor chip.

S702, performing DC programming test and updating the first record file.

S703, calculating a first station internal ratio and a second station internal ratio according to the first record file. The specific implementation manner of S703 may be referred to the description of step B4 and step B6 in the foregoing parts of the embodiments of the present disclosure, which is not repeated herein.

S704, if the first intra-station ratio U2 is greater than the third preset value, or the second intra-station ratio M2 is greater than the fourth preset value, S712 is performed. If the first intra-station ratio U2 is less than or equal to the third preset value and the second intra-station ratio M2 is less than or equal to the fourth preset value, S705 is executed. That is, if the first intra-station ratio U2 is greater than the third preset value or the second intra-station ratio M2 is greater than the fourth preset value, it indicates that the requirement is not satisfied, and the degradation process of the semiconductor chip needs to be performed S712. If the first intra-station ratio U2 is less than or equal to the third preset value and the second intra-station ratio M2 is less than or equal to the fourth preset value, it is indicated that the requirements are satisfied, and S705 is executed. It should be noted that, the order of executing the DC programming test or the AC programming test is not limited in the present disclosure, and the embodiment of the present disclosure executes the DC programming test first and then executes the AC programming test. The AC burn-in test may be performed first, followed by the DC burn-in test.

S705, performing an AC programming test, and updating the first record file.

S706, calculating the first station internal ratio and the second station internal ratio according to the first record file. The specific implementation manner of S706 may refer to the descriptions of the foregoing parts of the embodiments of the present disclosure regarding step B4 and step B6, which are not repeated herein.

S707, if the first intra-station ratio U2 is greater than the third preset value, or the second intra-station ratio M2 is greater than the fourth preset value, S708 is performed. If the first intra-station ratio U2 is less than or equal to the third preset value and the second intra-station ratio M2 is less than or equal to the fourth preset value, S711 is executed.

S708, performing a reassignment AC programming test, and updating the first record file. It should be noted that the in-station test may include a DC programming test, an AC programming test, and a reassigned AC programming test, and each programming may be performed to update the first record file once.

S709, calculating a first station internal ratio and a second station internal ratio according to the first record file. The specific implementation of S709 may refer to the description of step B4 and step B6 in the foregoing parts of the embodiments of the disclosure, which is not repeated herein.

S710, if the first intra-station ratio U2 is greater than the third preset value or the second intra-station ratio M2 is greater than the fourth preset value, S712 is performed. If the first intra-station ratio U2 is less than or equal to the third preset value and the second intra-station ratio M2 is less than or equal to the fourth preset value, S711 is executed.

S711, maintaining the level of the semiconductor chip, and outputting an updated first record file, where the first record file is used to perform cross-site detection.

And S712, performing degradation processing on the semiconductor chip.

It should be noted that, each test station has a corresponding complete test flow (such as the test flow shown in fig. 7), and the process between consecutive test stations can implement the test by a cross-station manner. That is, the embodiments of the present disclosure can perfect the detection flow of the OTP memory cell of the semiconductor chip by cross-site inspection.

According to the embodiment of the disclosure, whether the semiconductor chip is subjected to degradation treatment or not is judged through the first in-station ratio and the second in-station ratio, and the degradation treatment is performed on the semiconductor chip which does not meet the requirements, so that the workload of a subsequent manufacturing process can be reduced.

According to the embodiment of the disclosure, the first in-station ratio and the second in-station ratio can be obtained through the current programming information and the current state information of each OTP unit, so that the OTP units with abnormal information are detected, and the shipment quality of the semiconductor chips is ensured.

Whether the semiconductor chip is degraded will be described below.

In an exemplary embodiment, the burn-in test includes a direct current DC burn-in test and an alternating current AC burn-in test. Determining whether the semiconductor chip is degraded based on the first intra-station ratio and the second intra-station ratio may include: when the programming test executed in the first test station is a Direct Current (DC) programming test, if the first station internal ratio is larger than a third preset value or the second station internal ratio is larger than a fourth preset value, carrying out degradation treatment on the semiconductor chip; when the programming test executed in the first test station is an Alternating Current (AC) programming test, if the first station ratio is larger than a third preset value or the second station ratio is larger than a fourth preset value, the reassigned AC programming test is executed on the semiconductor chip, and if the first station ratio obtained after the reassigned programming test is larger than the third preset value or the second station ratio is larger than the fourth preset value, degradation treatment is executed on the semiconductor chip.

In another exemplary embodiment, in the case where the burn-in test performed in the first test station is a DC burn-in test, the level of the semiconductor chip is maintained in the case where the first in-station ratio is less than or equal to a third preset value and the second in-station ratio is less than or equal to a fourth preset value.

In still another exemplary embodiment, in the case where the burn-in test performed in the first test station is an AC burn-in test, if the first in-station ratio is less than or equal to a third preset value and the second in-station ratio is less than or equal to a fourth preset value, the rank of the semiconductor chip is maintained.

The present disclosure is not limited as to what the third preset value and the fourth preset value are, as long as the process needs can be satisfied. For example, the third preset value is 0, and the fourth preset value is 0.

Illustratively, in the case where the burn-in test performed at the first test station is a DC test, the semiconductor chip is subjected to degradation processing in the case where the first in-station ratio value is greater than 0, or the second in-station ratio value is greater than 0.

Illustratively, in the case where the burn-in test performed at the first test station is a DC burn-in test, the rank of the semiconductor chip is maintained in the case where the first intra-station ratio is less than or equal to 0, or the second intra-station ratio is less than or equal to 0.

In an exemplary case where the burn-in test performed at the first test site is an AC burn-in test, if the first in-site ratio is greater than 0, or if the second in-site ratio is greater than 0, the semiconductor chip is rewritten, and if the first in-site ratio obtained by the rewiring is greater than 0, or if the second in-site ratio is greater than 0, the semiconductor chip is degraded.

Illustratively, in the case where the burn-in test performed at the first test station is an AC burn-in test, if the first in-station ratio is less than or equal to 0 and the second in-station ratio is less than or equal to 0, the rank of the semiconductor chip is maintained.

It should be noted that, the in-site detection can realize real-time detection, and timely degrade the semiconductor chip with the abnormal OTP unit.

The presence of a naturally blown OTP cell, whether it is in-site or cross-site, is described below.

In an exemplary embodiment, the OTP memory cell detection method during the chip test may further include the following steps D1 to D3 before performing the at least one burn-in test.

Step D1, acquiring the number of the naturally fused OTP units and the total number of the OTP units of the semiconductor chip, and taking the number of the naturally fused OTP units and the total number of the OTP units as initial first OTP unit state result record data.

The number of naturally blown OTP cells is the number of OTP cells that have been blown before the burn-in test is performed.

And D2, calculating the ratio of the number of the OTP units fused naturally to the total number of the OTP units, and obtaining the natural fused ratio.

The natural fusing ratio can be calculated by the following formula 5:

wherein T is the natural fusing ratio, Z1 is the number of the OTP units fused naturally, and Z is the total number of the OTP units.

As shown in fig. 6, the record file includes the number of naturally blown OTP cells, which are OTP cells that have been blown before programming, and the total number of OTP cells.

And D3, performing degradation treatment on the semiconductor chip under the condition that the natural fusing ratio is larger than a fifth preset value.

In another exemplary embodiment, in the case where the natural fusing ratio is less than or equal to the fifth preset value, the rank of the semiconductor chip is maintained.

As to the fifth preset value, the present disclosure is not limited as long as the process requirement can be satisfied. For example, the fifth preset value is 0.

Illustratively, in the case where the natural fusing ratio is greater than 0, the semiconductor chip is subjected to degradation processing.

Illustratively, in the case where the natural fusing ratio is less than or equal to 0, the rank of the semiconductor chip is maintained.

According to the embodiment of the disclosure, the semiconductor chip which does not meet the requirements (abnormal exists) is degraded through the natural fusing ratio, and the semiconductor chip which meets the requirements is subjected to subsequent testing, so that the workload of the subsequent testing is reduced, and the testing efficiency is improved.

For example, as shown in fig. 8, the OTP memory cell detection method in the chip test process may include the following S801 to S809.

S801, judging whether the natural fusing ratio meets the requirement, if yes, executing S802, and if not, executing S808. Exemplary, if the natural blowing ratio is greater than 0, it indicates that there is a natural blown OTP unit cell, and degradation processing is performed on the semiconductor chip.

S802, detecting at a first test site to obtain a first record file.

S803, detecting at the second testing site to obtain a second record file.

S804, performing cross-site detection based on the first record file and the second record file. Obtaining first OTP unit state result record data according to the first record file, obtaining second OTP unit state result record data according to the second record file, and performing cross-site detection according to the first OTP unit state result record data and the second OTP unit state result record data.

S805, performing S808 degradation when the burn-in failure ratio U1 is larger than a first preset value or the error burn-in ratio M1 is larger than a second preset value. If the un-programmed ratio U1 is less than or equal to the first preset value and the mis-programmed ratio M1 is less than or equal to the second preset value, S807 is executed.

S806, whether all the semiconductor chips are detected completely, if so, executing S807; if not, S809 is performed.

S807, the rank of the semiconductor chip is maintained.

S808, performing degradation processing on the semiconductor chip.

S809, the next semiconductor chip is inspected. Note that the detection of the next semiconductor chip includes performing S801 to S805.

It should be noted that, each test station has a corresponding perfect test flow (such as the test flow shown in fig. 7), and the process between consecutive test stations can implement the test by a cross-station manner (such as the test flow shown in fig. 8), and the method for testing OTP memory cells of the present disclosure can cover the test flow of the semiconductor chip including multiple test stations, that is, the test flow in the station and the test flow between the stations. That is, the embodiments of the present disclosure can perfect the detection flow of the OTP memory cell of the semiconductor chip by cross-site inspection.

According to the embodiment of the disclosure, all semiconductor chips can be detected, so that the OTP units with abnormal information are detected, the semiconductor chips with abnormal OTP units are subjected to degradation treatment, and the shipment quality of the semiconductor chips is further ensured.

Based on the same inventive concept, the embodiments of the present disclosure further provide an OTP memory cell detection device in a chip test process, as described in the following embodiments. Since the principle of solving the problem of the embodiment of the device is similar to that of the embodiment of the method, the implementation of the embodiment of the device can be referred to the implementation of the embodiment of the method, and the repetition is omitted.

Fig. 9 is a schematic diagram of a one-time programmable OTP memory cell testing device in a chip testing process according to an embodiment of the disclosure, and as shown in fig. 9, the OTP memory cell testing device may include an acquisition module 91 and a detection module 92. The acquiring module 91 may be configured to acquire a first record file of the semiconductor chip after the semiconductor chip is tested by the first test station; the obtaining module 91 may be further configured to obtain first OTP unit state result record data according to the first record file; the obtaining module 91 may be further configured to obtain a second record file of the semiconductor chip after the semiconductor chip is tested by the second test station, where the first test station and the second test station are two consecutive front and back test stations; the obtaining module 91 may be further configured to obtain second OTP unit state result record data according to the second record file; the detection module 92 may be configured to obtain a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data.

In an embodiment, the first OTP unit state result record data includes a total number of OTP units in the semiconductor chip and first state information of each OTP unit; the second OTP unit state result record data includes the total number of OTP units and second state information of each OTP unit. The detection module 92 may be further configured to count the number of first erroneous OTP cells that are programmed during the testing process of the first test site and that are not programmed before the testing process of the second test site according to the first status information and the second status information of each OTP cell; obtaining a programming failure ratio according to the number of the first error OTP units and the number of programmed OTP units in the testing process of the first testing site; counting the number of second error OTP units with the states of not being programmed in the test process of the first test site and the states of programmed before the test of the second test site according to the first state information and the second state information of each OTP unit; obtaining a mis-programming ratio according to the number of the second error OTP units and the number of the un-programmed OTP units in the testing process of the first testing site; and carrying out degradation treatment on the semiconductor chip under the condition that the programming failure ratio is larger than a first preset value or the error programming ratio is larger than a second preset value.

In an embodiment, the detection module 92 may be further configured to maintain the level of the semiconductor chip when the unwritten ratio is less than or equal to a first preset value and the miswritten ratio is less than or equal to a second preset value.

In one embodiment, the first test station is a wafer test CP station and the second test station is a burn-in test RDBI station; alternatively, the first test station is an RDBI station and the second test station is a FT back-end test station.

In an embodiment, before obtaining the cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data, the obtaining module 91 may be further configured to obtain a chip identifier of the semiconductor chip; and acquiring the first OTP unit state result record data and the second OTP unit state result record data which belong to the same semiconductor chip according to the chip identification. The obtaining module 91 may be further configured to obtain a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data that belong to the same semiconductor chip.

In an embodiment, the chip identification includes one or more of a chip ID, a wafer code, and position coordinates.

In an embodiment, the first OTP cell state result record data includes a total number of OTP cells in the semiconductor chip, first programming information of each OTP cell, and first state information of each OTP cell. In testing at the first test station, the detection module 92 may also be used to perform at least one burn-in test; updating the first OTP unit state result record data after each programming test is completed until all programming tests are completed, and outputting a first record file containing the first OTP unit state result record data; after each programming test is completed, counting the number of third error OTP units which are subjected to programming in a first test site and have the state of being un-programmed after the current programming test according to the first programming information and the first state information of each OTP unit in the updated first OTP unit test record data; calculating the ratio of the number of third error OTP units to the number of OTP units which have been subjected to programming in the first test site, and obtaining a first in-site ratio corresponding to the current programming test; obtaining the number of OTP units which are not subjected to programming in the first test site according to the total number of OTP units and the number of OTP units which are subjected to programming in the first test site; counting the number of fourth error OTP units which are not programmed in the first test site and are programmed after the current programming test according to the first programming information and the first state information of each OTP unit; calculating the ratio of the number of the fourth error OTP units to the number of the OTP units which are not subjected to programming in the first test site, and obtaining a second in-site ratio corresponding to the current programming test; and determining whether the semiconductor chip is subjected to degradation processing or not according to the first in-station ratio and the second in-station ratio.

In one embodiment, the burn-in test includes a direct current DC burn-in test and an alternating current AC burn-in test. The detection module 92 may be further configured to perform degradation processing on the semiconductor chip if the first intra-station ratio is greater than a third preset value or the second intra-station ratio is greater than a fourth preset value when the burn-in test performed in the first test station is a DC burn-in test; when the programming test executed in the first test station is an Alternating Current (AC) programming test, if the first station ratio is larger than a third preset value or the second station ratio is larger than a fourth preset value, the reassigned AC programming test is executed on the semiconductor chip, and if the first station ratio obtained after the reassigned programming test is larger than the third preset value or the second station ratio is larger than the fourth preset value, degradation treatment is executed on the semiconductor chip.

In an embodiment, the fetching module 91 may be further configured to obtain the number of naturally blown OTP units and the total number of OTP units of the semiconductor chip before performing the at least one burn-in test, and record the number of naturally blown OTP units and the total number of OTP units as initial first OTP unit state result data; calculating the ratio of the number of the OTP units fused naturally to the total number of the OTP units to obtain a natural fusing ratio; and carrying out degradation treatment on the semiconductor chip under the condition that the natural fusing ratio is larger than a fifth preset value.

According to the OTP memory cell detection device in the chip test process disclosed by the embodiment of the disclosure, a cross-site OTP cell state detection result of the semiconductor chip is obtained according to the first OTP cell state result recording data and the second OTP cell state result recording data, so that an OTP cell with abnormal information is detected, and the shipment quality of the semiconductor chip is ensured.

Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a computer device according to an embodiment of the present disclosure. As shown in fig. 10, a computer device in an embodiment of the present disclosure may include: one or more processors 1001, memory 1002, and an input-output interface 1003. The processor 1001, memory 1002, and input/output interface 1003 are connected by a bus 1004. The memory 1002 is used for storing a computer program including program instructions, and the input-output interface 1003 is used for receiving data and outputting data, such as for data interaction between a host and a computer device, or for data interaction between respective virtual machines in the host; the processor 1001 is configured to execute program instructions stored in the memory 1002.

The processor 1001 may perform the following operations, among others: acquiring a first record file of the semiconductor chip after the semiconductor chip is tested by a first test station; obtaining first OTP unit state result record data according to a first record file; acquiring a second record file of the semiconductor chip after the semiconductor chip is tested by a second test station, wherein the first test station and the second test station are continuous front and rear test stations; obtaining second OTP unit state result record data according to the second record file; and obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data.

The memory 1002 may include read only memory and random access memory, and provides instructions and data to the processor 1001 and input output interface 1003. A portion of memory 1002 may also include non-volatile random access memory. In a specific implementation, the computer device may execute, through each built-in functional module, an implementation manner provided by each step in any method embodiment described above, and specifically may refer to an implementation manner provided by each step in a diagram shown in the method embodiment described above, which is not described herein again.

Embodiments of the present disclosure provide a computer device comprising: a processor, an input-output interface, and a memory, where the processor obtains a computer program in the memory, and performs the steps of the method shown in any of the embodiments above.

The embodiments of the present disclosure also provide a computer readable storage medium storing a computer program, fig. 11 shows a schematic diagram of a computer readable storage medium in an embodiment of the present disclosure, and fig. 11 shows a schematic diagram of a computer readable storage medium 1100 storing a program product capable of implementing the method of the present disclosure. The computer program is adapted to be loaded by the processor and to perform the method for detecting OTP memory cells during chip testing provided by the steps of any of the embodiments described above.

The disclosed embodiments also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the methods provided in the various alternatives of any of the embodiments described above.

Claims

1. The one-time programmable OTP memory cell detection method in the chip test process is characterized by comprising the following steps:

acquiring a first record file of the semiconductor chip after the semiconductor chip is tested by a first test station;

obtaining first OTP unit state result record data according to the first record file;

acquiring a second record file of the semiconductor chip after being tested by a second test station, wherein the first test station and the second test station are front and rear test stations which are continuously executed;

obtaining second OTP unit state result record data according to the second record file;

and obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result recording data and the second OTP unit state result recording data.

2. The method of claim 1, wherein the first OTP unit state result record data includes a total number of OTP units in the semiconductor chip and first state information of each OTP unit; the second OTP unit state result record data includes the total number of OTP units and second state information of each OTP unit;

wherein the obtaining the cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data includes:

Counting the number of first error OTP units with the state being programmed in the test process of the first test site and the state being un-programmed before the test of the second test site according to the first state information and the second state information of each OTP unit;

obtaining a programming failure ratio according to the number of the first error OTP units and the number of programmed OTP units in the testing process of the first testing site;

counting the number of second error OTP units with the states of not being programmed in the test process of the first test site and the states of programmed before the test of the second test site according to the first state information and the second state information of each OTP unit;

obtaining a mis-programming ratio according to the number of the second error OTP units and the number of the un-programmed OTP units in the testing process of the first testing site;

and carrying out degradation treatment on the semiconductor chip under the condition that the programming failure ratio is larger than a first preset value or the error programming ratio is larger than a second preset value.

3. The method according to claim 2, wherein the method further comprises:

and when the un-programmed ratio is smaller than or equal to a first preset value and the mis-programmed ratio is smaller than or equal to a second preset value, the grade of the semiconductor chip is maintained.

4. A method according to any one of claims 1 to 3, wherein the first test station is a wafer test CP station and the second test station is a burn-in test RDBI station;

or alternatively, the process may be performed,

the first test station is an RDBI station, and the second test station is an FT back-end test station.

5. A method according to any one of claims 1 to 3, wherein before the obtaining of the cross-site OTP unit state detection result of the semiconductor chip from the first OTP unit state result record data and the second OTP unit state result record data, the method further comprises:

acquiring a chip identifier of the semiconductor chip;

acquiring the first OTP unit state result record data and the second OTP unit state result record data belonging to the same semiconductor chip according to the chip identifier;

and obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result record data and the second OTP unit state result record data which belong to the same semiconductor chip.

6. The method of claim 5, wherein the chip identification comprises one or more of a chip ID, a wafer code, and a location coordinate.

7. The method of claim 1, wherein the first OTP unit state result record data includes a total number of OTP units in the semiconductor chip, first programming information for each OTP unit, and first state information for each OTP unit;

wherein the testing of the first test site comprises:

performing at least one burn-in test;

updating the first OTP unit state result record data after each programming test is completed until all programming tests are completed, and outputting a first record file containing the first OTP unit state result record data;

after each programming test is completed, counting the number of third error OTP units which are subjected to programming in the first test site and are in an un-programmed state after the current programming test according to the first programming information and the first state information of each OTP unit in the updated first OTP unit test record data;

calculating the ratio of the number of the third error OTP units to the number of the OTP units which are subjected to programming in the first test site, and obtaining a first in-site ratio corresponding to the current programming test;

Obtaining the number of OTP units which are not subjected to programming in the first test site according to the total number of OTP units and the number of OTP units which are subjected to programming in the first test site;

counting the number of fourth error OTP units which are not programmed in the first test site and are programmed after the current programming test according to the first programming information and the first state information of each OTP unit;

calculating the ratio of the number of fourth error OTP units to the number of OTP units which are not subjected to programming in the first test site, and obtaining a second in-site ratio corresponding to the current programming test;

and determining whether the semiconductor chip is subjected to degradation processing or not according to the first station internal ratio and the second station internal ratio.

8. The method of claim 7, wherein the burn-in test comprises a direct current DC burn-in test and an alternating current AC burn-in test;

wherein determining whether the semiconductor chip performs degradation processing according to the first intra-station ratio and the second intra-station ratio includes:

when the programming test executed in the first test station is a Direct Current (DC) programming test, if the first station internal ratio is larger than a third preset value or the second station internal ratio is larger than a fourth preset value, carrying out degradation treatment on the semiconductor chip;

And when the programming test executed in the first test station is an Alternating Current (AC) programming test, if the first station specific value is larger than a third preset value or the second station specific value is larger than a fourth preset value, the AC programming test is executed for the semiconductor chip, and if the first station specific value obtained after the re-programming test is larger than the third preset value or the second station specific value is larger than the fourth preset value, the degradation treatment is carried out for the semiconductor chip.

9. A method as claimed in claim 2 or 7, characterized in that,

before performing the at least one burn-in test, the method further comprises:

acquiring the number of the naturally fused OTP units and the total number of the OTP units of the semiconductor chip, and taking the number of the naturally fused OTP units and the total number of the OTP units as initial first OTP unit state result record data;

calculating the ratio of the number of the OTP units fused naturally to the total number of the OTP units to obtain a natural fused ratio;

and carrying out degradation treatment on the semiconductor chip under the condition that the natural fusing ratio is larger than a fifth preset value.

10. A one-time programmable OTP unit cell testing device in a chip testing process, comprising:

The acquisition module is used for acquiring a first record file of the semiconductor chip after the semiconductor chip is tested by the first test station;

the acquisition module is further used for acquiring first OTP unit state result record data according to the first record file;

the acquisition module is further used for acquiring a second record file of the semiconductor chip after the semiconductor chip is tested by a second test station, and the first test station and the second test station are two continuous front and rear test stations;

the acquisition module is further used for acquiring second OTP unit state result record data according to the second record file;

the detection module is used for obtaining a cross-site OTP unit state detection result of the semiconductor chip according to the first OTP unit state result recording data and the second OTP unit state result recording data.