CN116680212A - Hardware control method, computing device and server - Google Patents

Abstract

A hardware control method is executed by a computing device, the computing device comprises a processor, a BIOS and a PCIe device, an application program runs on the processor, a first address space of the application program and a second address space of the PCIe device are mapped with each other, and the PCIe address space and the second address space of the PCIe device are mapped with each other. When the application program controls the hardware to execute the control instruction, the hardware control instruction can be written into the first address space. The BIOS can read the control instruction from the second address space of the PCIe device by accessing the PCIe address space, and control the hardware to execute the corresponding function, so that the whole control process is not limited by the release of the operating system and the type of the operating system. The application program provides a hardware operation mechanism through the BIOS, so that the hardware operation mechanism is easier to realize than the direct operation of the application program, and is safer and more reliable.

Description

Hardware control method, computing device and server

Technical Field

The present application relates to the field of computer technologies, and in particular, to a hardware control method, a computing device, and a server.

Background

The Linux system is a multi-user, multi-tasking, multi-central processing unit (central processing unit, CPU) supporting multithreading based on portable operating system interfaces (portable operating system interface, POSIX). The server is typically installed with an operating system based on the Linux system. In order for the server to control the external hardware, a hardware debugging tool needs to be installed on the driving interface. The server calls a hardware debugging tool of the driving interface to control external hardware. With the development of the Linux system, the release of the Linux system is more, such as Redhat, centOS, ubuntu, and the drive interface needs to be provided with hardware debugging tools of the Linux system based on different release, so that the maintenance difficulty of the server is high and the cost is high.

Disclosure of Invention

In order to solve the above-mentioned problems, a hardware control method is provided in the embodiments of the present application, which decouples an application program from an operating system and establishes a coupling relationship with a BIOS. When the application program controls the hardware to execute the setting function, the hardware control program sent by the application program is transmitted to the BIOS through the PCIe device, so that the whole process bypasses the operating system, and the whole control process is not limited by the release of the operating system 111 and the type of the operating system 111. In addition, the application also provides a computing device and a server corresponding to the hardware control method and the computing device.

For this purpose, the following technical scheme is adopted in the embodiment of the application:

in a first aspect, the present application provides a hardware control method, performed by a computing device, where the computing device includes a processor, a BIOS, and a PCIe device, and an application program runs on the processor, where a first address space of the application program and a second address space of the PCIe device are mapped to each other, the PCIe address space and the second address space of the PCIe device are mapped to each other, and the first address space is an address space configured by the processor for the application program, where the method includes: the BIOS obtains a hardware control instruction written in a first address space by an application program in a second address space mapped by the PCIe address space by accessing the PCIe address space, wherein the hardware control instruction is used for indicating a hardware component of the computing device to execute a first operation; the BIOS controls the hardware component to execute a first operation according to the hardware control instruction; the BIOS obtains the execution result of the hardware control instruction and generates an execution result message; and the BIOS writes the execution result message into the PCIe address space to map the second address space through the PCIe address space so that the program obtains the execution result message from the first address space.

In this embodiment, when the application program controls the hardware to execute the control instruction, the hardware control instruction may be transmitted to the memory space of the PCIe device. The BIOS can read the control instruction of the memory space of the PCIe device, and control the hardware to execute the corresponding function. The application program is decoupled from the operating system and establishes a coupling relation with the BIOS, and the process of controlling hardware by the application program can bypass the operating system, so that the whole control process is not limited by the release of the operating system and the type of the operating system.

In one possible implementation, the BIOS obtains, from the second address space mapped by the PCIe address space, a hardware control instruction written by the application program in the first address space by accessing the PCIe address space, and the method further includes: and the BIOS polls the second address space through the PCIe address space, and detects that the interrupt identifier written by the application program in the first address space exists.

In one possible implementation, the BIOS obtains, from the second address space mapped by the PCIe address space, a hardware control instruction written by the application program in the first address space by accessing the PCIe address space, and the method further includes: and the PCIe device reads the interrupt identifier written in the first address space by the application program in the second address space and informs the BIOS to acquire the hardware control instruction.

With the possible implementation manner, the application program may inform the BIOS of the acquisition of the hardware control instruction through the interrupt identifier.

In one possible implementation, after the BIOS writes the execution result packet to the second address space mapped by the PCIe address space through the PCIe address space, the method further includes: the BIOS writes a first deleting instruction into the second address space, wherein the first deleting instruction instructs the PCIe device to delete the interrupt identifier written by the application program in the second address space. The BIOS can be prevented from constantly controlling the corresponding hardware of the hardware component to perform the first operation.

In one possible implementation, after the BIOS writes the execution result packet to the second address space mapped by the PCIe address space through the PCIe address space, the method further includes: and the BIOS writes a completion identifier into the second address space through the PCIe address space, and the completion status identifier indicates the application program to acquire the result message.

In one possible implementation, after the BIOS writes the completion identification to the second address space through the PCIe address space, the method further includes: and the application program polls the first address space, and detects that the first address space has the completion identification so as to acquire the execution result message.

In one possible implementation, after the BIOS writes the completion identification to the second address space through the PCIe address space, the method further includes: and the PCIe device reads the completion identification in the second address space and notifies the application program to acquire the execution result message.

With the possible implementation manners, the BIOS may notify the application program to obtain the execution result message through the completion identifier.

In one possible embodiment, the method further comprises: the application program sends a second deletion instruction to the first address space, wherein the second deletion instruction instructs the PCIe device to delete the completion identification. The application 112 may be prevented from continually detecting the corresponding hardware execution results of the hardware component 150.

In one possible implementation, the application program maps the first address space and the PCIe address space to each other through a memory mapped MMAP mode.

In one possible implementation, the PCIe device maps the PCIe address space and the second address space to each other by configuring an address translation unit.

In one possible implementation, the PCIe device is one of a baseboard management controller, a network card, a sound card, a built-in cat, and a disk array card.

In a second aspect, the present application provides a computing device comprising: the system comprises a processor, a BIOS and PCIe equipment, wherein an application program runs on the processor, a first address space of the application program and a second address space of the PCIe equipment are mapped mutually, the PCIe address space and the second address space of the PCIe equipment are mapped mutually, and the first address space is an address space configured by the processor for the application program. The BIOS is used for obtaining a hardware control instruction written by the application program in the first address space by accessing the PCIe address space and the second address space mapped by the PCIe address space, wherein the hardware control instruction is used for indicating a hardware component of the computing device to execute a first operation; the BIOS is also used for controlling the hardware component to execute a first operation according to the hardware control instruction; the BIOS is also used for obtaining the execution result of the hardware control instruction and generating an execution result message; the BIOS is further configured to write the execution result message into the PCIe address space map second address space through the PCIe address space, so that the application program obtains the execution result message from the first address space. The processor is used for writing the hardware control instruction into the first address space and also used for acquiring an execution result message from the first address space. In one possible implementation, the BIOS is further configured to poll the second address space through the PCIe address space to detect an interrupt identification written by the application in the first address space.

In one possible implementation, a PCIe device is configured to read in the second address space, and the application program notifies the BIOS of the interrupt identifier written in the first address space to obtain the hardware control instruction.

In one possible implementation, the BIOS writes a first delete instruction to the second address space, the first delete instruction instructing the PCIe device to delete the interrupt identifier written by the application 1 in the second address space.

In a possible implementation manner, the BIOS is further configured to write a completion identifier to the second address space through the PCIe address space, where the completion status identifier indicates that the application program obtains the result packet.

In a possible implementation manner, the application program is further configured to poll the first address space, detect that the first address space has the completion identifier, and obtain the execution result packet.

In one possible implementation manner, the PCIe device is configured to read the completion identifier in a second address space, and notify the application program to obtain the execution result packet.

In one possible implementation, the application is further configured to send a second delete instruction to the first address space, where the second delete instruction instructs the PCIe device to delete the completion identification.

In one possible implementation, the application program maps the first address space and the PCIe address space to each other through a memory mapped MMAP mode.

In one possible implementation, the PCIe device maps the PCIe address space and the second address space to each other by configuring an address translation unit.

In one possible implementation, the PCIe device is one of a baseboard management controller, a network card, a sound card, a built-in cat, and a disk array card.

In a third aspect, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the method as each possible implementation of the first aspect.

In a fourth aspect, the application provides a computer program product, characterized in that the computer program product stores instructions that, when executed by a computer, cause the computer to carry out the method as each possible implementation of the first aspect.

Drawings

The drawings that accompany the detailed description can be briefly described as follows.

FIG. 1 is a schematic diagram of a computing device architecture provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of an architecture of another computing device provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a mapping method for PCIe device address space and computing device address space provided in an embodiment of the present application;

fig. 4 is a flow chart of a hardware control method according to an embodiment of the present application;

fig. 5 is a schematic diagram of a structure in which a CPU of a server detects a hard disk temperature through a BMC according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

The term "and/or" herein is an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. The symbol "/" herein indicates that the associated object is or is a relationship, e.g., A/B indicates A or B.

The terms "first" and "second" and the like in the description and in the claims are used for distinguishing between different objects and not for describing a particular sequential order of objects. For example, the first response message and the second response message, etc. are used to distinguish between different response messages, and are not used to describe a particular order of response messages.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" means two or more, for example, the meaning of a plurality of processing units means two or more, or the like; the plurality of elements means two or more elements and the like.

Fig. 1 is a schematic structural diagram of a computing device according to an embodiment of the present application. As shown in fig. 1, the computing device 100 includes a processor 110, a memory 120, a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) device 140, a basic input output system (basic input output system, BIOS) 140, and hardware components 150. Computing device 100 may be a server, computer, base station, portable notebook computer, or the like.

The processor 110 may be a device having a processing function such as a CPU, a graphics processor (graphics processing unit, GPU), a Microprocessor (MP), a digital signal processor (digital signal processor, DSP), or the like. Processor 110 may run an operating system 111 stored by memory 120, and may run application programs 112 stored by memory 120, such that computing device 100 may implement various functions.

Operating system 111 is a set of interrelated system software programs that host and control the computer's operation, running, and execution of hardware, software resources, and providing common services to organize user interactions. The operating system 111 can perform scheduling work on each resource block of the computing device 100, including software and hardware devices, data information, and the like, the working intensity of manual resource allocation can be reduced by using the computer operating system, the operating intervention degree of a user on the computer is reduced, and the intelligent working efficiency of the computer can be greatly improved. In the present application, the operating system 111 is a Linux system.

Application 112 refers to a computer program that performs some particular task or tasks. The application 112 is installed on the operating system 111, and can interact with a user, and creates one or more execution tasks upon receiving an operation instruction from the user. Each application 112 runs in a separate process, having a separate address space.

The memory 120 may include volatile memory (RAM), such as random access memory (random access memory). The memory 120 may also include a non-volatile memory (ROM), such as a read-only memory (ROM), a flash memory, a mechanical hard disk (HDD), or a solid state disk (solid state drive, SSD).

The memory 230 has stored therein executable program code that the processor 110 executes to implement the aforementioned functions of the operating system 111 and the application programs 112, respectively, thereby implementing a hardware control method. That is, the memory 120 has instructions stored thereon for executing the hardware control method.

Alternatively, the memory 120 has stored therein executable codes that the processor 110 executes to realize the functions of the aforementioned operating system 111 and application programs 112, respectively, thereby realizing a hardware control method. That is, the memory 120 has instructions stored thereon for executing the hardware control method.

PCIe device 130 refers to a device that is connected to processor 110 via a PCIe bus. PCIe device 130 may be a baseboard management controller (baseboard management controller, BMC), network card, sound card, built-in cat (modem), disk array (redundant arrays of independent disks, RAID) card, or other device. In an embodiment of the present application, the interface managed by the operating system 111 deployed by the application 112 may establish a communication connection with the PCIe device 130 based on the PCIe protocol. The application 112 may communicate data packets with the PCIe device 130.

BIOS 140 is an industry standard firmware interface. BIOS 140 is a set of programs that are solidified onto a Read Only Memory (ROM) chip on the motherboard within the computer, and stores the most important basic input and output programs of the computer, the self-test programs after boot-up, and the system self-start programs. The primary function of the BIOS 140 is to provide the lowest, most direct hardware setup and control for the computer. For example, the BIOS 140 may control the hardware component 150, wherein the hardware component 150 may include underlying hardware such as sensors, registers, and the like. In some implementations, the hardware component 150 may include registers or sensors in the processor 110, or the hardware component 150 may also include a temperature sensor of the hard disk. In an embodiment of the present application, the interface managed by the BIOS 140 may establish a communication connection with the PCIe device 130 based on the PCIe protocol. The BIOS 140 may transfer data packets with the PCIe device 130.

Fig. 2 is a schematic diagram of a hardware control method according to an embodiment of the present application. As shown in FIG. 2, an application 112 running on the processor 110 may virtually create a virtual address space through a user-oriented process. For ease of description, the virtual space address may also be referred to as the first address space. In one embodiment, the first address space is located in memory 120 that stores application 112 data. A mapping relationship may be established between the virtual address space of the application 112 and the address space of the PCIe device 130 such that data written to the virtual address space by the application 112 may be mapped to the address space of the PCIe device 130. For ease of description, the address space of the PCIe device 130 may also be referred to as a second address space.

The first address space is a segment of address space maintained by the operating system 111 running the application 112, and may receive messages written by the application 112 and map to a second address space of the PCIe device 130. The second address space of PCIe device 130 may be a memory internal to PCIe device 130 for storing data packets in communication with application 112 and for storing data packets in communication with BIOS 140.

In one possible implementation, the second address space of the PCIe device 130 may divide the memory area into a control area and a data area according to the type of the data packet. The control area refers to storing signal messages transmitted by the application 112 and the BIOS 140, such as storing hardware control instructions, interrupt trigger identifiers, completion status identifiers, and the like. The data area refers to data messages transmitted by the storage application 112 and the BIOS 140.

Fig. 3 is a schematic diagram of a method for mapping an address space of a PCIe device and an address space of a computing device according to an embodiment of the present application. As shown in fig. 3, the first address space and the second address space may be mapped by a PCIe address space. PCIe devices may be mapped to the PCIe address space through a PCI bus, where each PCI device occupies a unique section of PCIe address, so that the processor is uniformly addressed through the PCI bus. Illustratively, the PCI bus has a 32-bit data/address multiplexed bus, so its PCIe address space is 2 to the power of 32 = 4GB, i.e., all devices on the PCI bus are mapped together onto this 4 GB. The application 112 may map the first address space with a PCIe address space. Alternatively, the application 112 may perform a mmap () system call to map the first address space to the PCIe address space through the PCI sysfs node.

Memory Map (MMAP) is a method for mapping a file in memory, i.e. mapping a file or other objects to the address space of a process, so as to realize a one-to-one mapping relationship between the disk address of the file and a segment of virtual address in the virtual address space of the process. After the application 112 establishes the mapping relationship, the process may read and write the memory section by using a pointer, and the system may automatically write back the dirty page to the corresponding file disk, so as to complete the file operation. PCI sysfs is a virtual memory-based file system. The file system can output information of devices (devices) and drivers (drivers) from the kernel to the user space, and can also be used to set the devices and drivers.

The PCIe device may map the second address space with a PCIe address space. Optionally, the PCIe device 130 may configure an address translation unit (address translation unit, ATU) to expose its own memory on the PCIe bus for access by a PCIe Root or other PCIe device to implement mapping of the second address space to the PCIe address space.

Illustratively, assume that the application 112 corresponds to a first address space of 0xe 0000000-0 xf0000000, a PCIe address space of 0xa 000000-0 xb0000000, and an address space of 0x 8000000-0 x90000000 for the RAM of the PCIe device 130. The mapping process is as follows: the application 112 maps the first address space to a PCIe address space and the PCIe device 130 maps the address space of the RAM to a PCIe address space through the ATU. Finally, a mapping relationship is established between the first address space of the application 112 being 0xe 0000000-0 xf0000000 and the address space of the RAM of the PCIe device 130 being 0x 8000000-0 x90000000, and the application 112 reading and writing the first address space, i.e., reading and writing the second address space of the PCIe device.

The hardware control instructions may instruct the corresponding hardware of the hardware component 150 to perform the corresponding operations. For example, the hardware control instructions may be to detect a temperature inside the computing device 100. At this time, the temperature sensor of the hardware component 150, upon receiving the hardware control instruction, detects the temperature inside the computing device 100 and feeds back the temperature data to the processor 110. In the embodiment of the present application, the hardware control command may be transmitted in a customized message format negotiated between the application 112 and the BIOS 140. It will be appreciated that the hardware control instructions are applicable to various different releases of the operating system 111, such as Redhat, centOS, ubuntu, etc., installed by the application 112, as well as to different types of operating systems 111, such as Linux systems, windows systems, unix systems, etc.

The BIOS 140 may establish a communication connection with the PCIe device 130 based on the PCIe protocol. The PCIe device may map the second address space with the PCIe address space, which means that the BIOS 140 accesses the PCIe address space, which means accessing the data in the second address space in the PCIe device 130.

The BIOS 140 may detect the corresponding hardware execution result of the hardware component 150, and after the corresponding hardware of the hardware component 150 completes the hardware instruction, encapsulate the execution result into a result packet, and transmit and write the result packet to the second address space of the PCIe device 130.

In the embodiment of the present application, when the application 112 controls the hardware to execute the control instruction, the hardware control instruction may be transmitted to the storage space of the PCIe device 130. In one aspect, the BIOS 140 may read a control instruction of the storage space of the PCIe device 130, and control the hardware to perform a corresponding function, so that the whole control process is not limited by the release of the operating system 111 and the type of the operating system 111. On the other hand, the application 112 provides a hardware operation mechanism through the BIOS, which is easier to realize and safer and more reliable than the application 112 directly operates hardware.

Fig. 4 is a flow chart of a hardware control method according to an embodiment of the present application. The method is applied to the computing device shown in fig. 1 and also can be applied to the architecture of the hardware control method shown in fig. 2. In the computing device, the first address space corresponding to the application 112 and the second address space of the PCIe device 130 are mapped to each other, and the second address space of the PCIe device 130 and the PCIe address space are mapped to each other. As shown in fig. 4, the method is performed by the components of the computing device 100 as follows:

in step S401, the application 112 writes a hardware control instruction into the first address space.

Specifically, when the application 112 needs to call hardware of the hardware component 150, hardware control instructions may be written into the first address space. As described above, the first address space corresponding to the application 112 and the second address space of the PCIe device 130 are mapped to each other, and the PCIe device 130 may directly read the hardware control instruction from the second address space. Equivalently, the application 112 sends and writes hardware control instructions to the second address space of the PCIe device 130, which bypasses the operating system 150, allowing the hardware control instructions to be applied to different releases of the operating system 111 installed by the application 112, as well as to different types of operating systems 111. The hardware control instruction is used to control the hardware component 150 to complete a corresponding operation, and may be transmitted in a customized message negotiated between the application 112 and the BIOS 140.

In one possible implementation, the application 112 may also write an interrupt identifier in the first address space, and after the application writes the interrupt identifier in the first address space, the BIOS may obtain the hardware control instruction in response to the interrupt identifier.

It will be appreciated that the application 112 may write the interrupt identification into the first address space again after writing the hardware control instructions into the first address space.

In step S402, the BIOS 140 obtains hardware control instructions by accessing the PCIe address space.

After the hardware control instruction is mapped in the second address space of the PCIe device, because the second address space of the PCIe device 130 and the PCIe address space are mapped to each other, the BIOS may obtain the hardware control instruction from the second address space mapped in the PCIe address space by accessing the PCIe address space.

In one possible implementation, after the BIOS 140 establishes a communication connection with the PCIe device 130, it polls a second address space of the PCIe device 130 through the PCIe address space to detect whether there is a new interrupt trigger. The BIOS 140 detects the new interrupt trigger and may again scan the second address space of the PCIe device 130 to obtain the hardware control instructions issued by the application 112.

In another possible implementation, the PCIe device 130 reads the interrupt identification in the second address space, informing the BIOS 140 to obtain the hardware control instructions.

In step S403, the BIOS 140 controls the hardware component to execute the first operation according to the hardware control instruction.

Specifically, after receiving the hardware control instruction, the BIOS 140 parses the hardware control instruction to obtain a specific hardware instruction. The BIOS 140 controls corresponding hardware in the hardware component 150 to perform operations corresponding to the hardware instructions based on the hardware instructions, and may also be referred to as a first operation for convenience of description. For example, the hardware control instructions may be to detect a temperature inside the computing device 100. At this time, the temperature sensor of the hardware component 150 detects the temperature inside the computing device 100 upon receiving the hardware control instruction.

In step S404, the BIOS 140 obtains the execution result of the hardware control instruction.

In step S405, the BIOS 140 generates an execution result packet, and writes the execution result packet into the second address space of the PCIe device 130 through the PCIe address space.

Specifically, the BIOS 140 may detect an execution result of the corresponding hardware of the hardware component 150, and after the corresponding hardware of the hardware component 150 completes the hardware instruction, encapsulate the execution result into a result packet, and write the result packet into the second address space of the PCIe device 130 through the PCIe address space.

In a possible implementation manner, the BIOS may further write a completion identifier, where the completion identifier indicates that the BIOS 140 controls corresponding hardware to have completed the hardware control instruction, and may enable the application 112 to obtain an execution result of the hardware component 150 to execute the hardware control instruction.

It is understood that the BIOS 140 may write the completion identifier to the PCIe address space after writing the execution result packet to the second address space of the PCIe device 130.

Alternatively, the BIOS 140 may send a first delete instruction to the PCIe device 130. The first delete instruction may indicate an interrupt identification for the PCIe device 130 to delete. After receiving the first delete instruction, the PCIe device 130 deletes the interrupt trigger identifier of the own second address space, so that the BIOS 140 can be prevented from continuously controlling the corresponding hardware of the hardware component 150 to perform the first operation.

In step S406, the application 112 reads the execution result message of the first address space mapping.

Specifically, after the BIOS 140 writes the result packet into the second address space of the PCIe device 130, because the second address space of the PCIe device 130 and the PCIe address space are mapped to each other, the application 112 may read the execution result packet in the first address space, and obtain an execution result of hardware corresponding to the hardware component 150.

In one possible implementation, when the application 112 polls the first address space, after the completion status identifier is polled, the first address space may be scanned to obtain an execution result message that the second address space of the PCIe device 130 maps to the first address space of the application 112. After the application 112 obtains the result message, the result message is parsed to obtain a corresponding hardware execution result of the hardware component 150.

In another possible implementation, the PCIe device 130 reads the completion identification in the second address space, informing the application 112 to obtain the execution result message.

Alternatively, the application 112 may send a second delete instruction to the PCIe device 130. The second delete instruction may instruct the PCIe device 130 to delete the completion identification. After receiving the second deletion instruction, the PCIe device 130 deletes the completion identifier of the own second address space update, so that the application 112 can be prevented from continuously detecting the corresponding hardware execution result of the hardware component 150.

In the embodiment of the present application, when the application 112 controls the hardware to execute the control instruction, the hardware control instruction may be transmitted to the storage space of the PCIe device 130. The BIOS 140 may read the control instructions of the memory space of the PCIe device 130, and control the hardware to perform corresponding functions, so that the whole control process is not limited by the release of the operating system 111 and the type of the operating system 111. In addition, the application 112 can also provide a hardware operation mechanism through the BIOS, which is easier to realize and safer and more reliable than the direct operation of the application 112.

Fig. 5 is a schematic diagram of a structure in which a CPU of a server detects a hard disk temperature through a BMC according to an embodiment of the present application. Take the computing device 100 as a server, the PCIe device 130 as a BMC, and the temperature sensor of the hardware component 150 as examples. The first address space corresponding to the application 112 and the second address space of the BMC are mapped to each other, and the second address space of the BMC and the PCIe address space are mapped to each other, and it is assumed that the hardware control instruction for the computing device 100 to read the hard disk temperature information is "regread0 xa004". The custom request message negotiated between the application and the BIOS is "0xff04ee01". The custom result message between the application program and the BIOS is 'actual temperature value +100'. As shown in fig. 5, the process of controlling hardware by the computing device 100 is specifically:

s501, the application writes "0xff04ee01" into the first address space.

S502, the application program writes an interrupt identifier of 0x1 into the first address space.

S503, when the BMC identifies the interrupt identification of the second address space, a notification instruction is sent to the BIOS.

S504, BIOS obtains instruction "0xff04ee01" and analyzes to obtain hardware instruction. The hardware instruction is "regread0 xa004".

S505, the BIOS controls the temperature sensor to execute the hardware instruction to obtain the temperature of the hard disk, which is 60 ℃.

In step S506, the BIOS encapsulates the execution result in the result packet, and writes the result packet into the second address space through the PCIe address space. The execution result message is "100+60".

In step S507, the BIOS writes the completion identifier to the second address space through the PCIe address space, and deletes the interrupt identifier of the second address space.

In step S508, the application program polls the completion identifier of the first address space, obtains the execution result message, analyzes to obtain that the hard disk temperature is 60 degrees celsius, and deletes the completion status identifier of the first address space. .

In the embodiment of the application, the application program is decoupled from the operating system and establishes a coupling relationship with the BIOS. Because a different operating system can be installed on a machine, only a specific BIOS can be installed, the application program is coupled to the BIOS only once, and the application program is coupled to the operating system only needs to be adapted multiple times. The application program realizes 'one-time compiling and running everywhere' on the operating system, thereby saving the development and maintenance cost of the drive. The BIOS provides a hardware operation mechanism, is easier to realize than the direct operation of the hardware by the application program, and is safer and more reliable.

There is also provided in an embodiment of the present application a computer-readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform any of the methods described in the foregoing fig. 1-5 and corresponding descriptions.

There is also provided in an embodiment of the application a computer program product storing instructions that, when executed by a computer, cause the computer to carry out any of the methods set out in figures 1-5 and the corresponding description above.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

Furthermore, various aspects or features of embodiments of the application may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein encompasses a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media can include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, or magnetic strips, etc.), optical disks (e.g., compact disk, CD, digital versatile disk, digital versatile disc, DVD, etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory, EPROM), cards, sticks, or key drives, etc. Additionally, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media capable of storing, containing, and/or carrying instruction(s) and/or data.

In the above-described embodiments, the computing device 100 in fig. 1 may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic of the processes, and should not constitute any limitation on the implementation process of the embodiments of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be embodied in essence or a part contributing to the prior art or a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or an access network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the embodiment of the present application, and the changes or substitutions are covered by the protection scope of the embodiment of the present application.

Claims (10)

1. A method of hardware control, performed by a computing device, the computing device comprising a processor, a basic input output system, BIOS, and a high-speed serial computer expansion bus, standard PCIe device, an application running on the processor, a first address space of the application and a second address space of the PCIe device being mapped to each other, the PCIe address space and the second address space of the PCIe device being mapped to each other, the first address space being an address space configured by the processor for the application, the method comprising:

the BIOS obtains a hardware control instruction written in the first address space by the application program from the second address space mapped by the PCIe address space by accessing the PCIe address space, wherein the hardware control instruction is used for indicating a hardware component of the computing device to execute a first operation;

the BIOS controls the hardware component to execute the first operation according to the hardware control instruction;

the BIOS obtains the execution result of the hardware control instruction;

the BIOS generates an execution result message;

and the BIOS writes the execution result message into the second address space mapped by the PCIe address space through the PCIe address space, so that the application program obtains the execution result message from the first address space.

2. The method of claim 1, wherein prior to the BIOS obtaining the hardware control instructions written by the application in the first address space from the second address space mapped by the PCIe address space by accessing the PCIe address space, the method further comprises:

and the BIOS polls the second address space through the PCIe address space, and detects that the interrupt identifier written by the application program in the first address space exists.

3. The method of claim 1, wherein prior to the BIOS obtaining the hardware control instructions written by the application in the first address space from the second address space mapped by the PCIe address space by accessing the PCIe address space, further comprising:

and the PCIe device reads the interrupt identifier written by the application program in the first address space from the second address space and informs the BIOS to acquire the hardware control instruction.

4. The method of any of claims 2 or 3, wherein after the BIOS writes the execution result message to the second address space of the PCIe address space map through the PCIe address space, the method further comprises:

the BIOS writes a first deletion instruction into the second address space, wherein the first deletion instruction instructs the PCIe device to delete the interrupt identifier written by the application program in the second address space.

5. The method of any of claims 1-4, wherein after the BIOS writes the execution result message to the second address space of the PCIe address space map through the PCIe address space, the method further comprises:

and the BIOS writes a completion identifier into the second address space through the PCIe address space, and the completion status identifier indicates the application program to acquire the result message.

6. The method of claim 5, wherein after the BIOS writes a completion identification to the second address space through the PCIe address space, the method further comprises:

and the application program polls the first address space, and detects that the first address space has the completion identification so as to acquire the execution result message.

7. The method of claim 5, wherein after the BIOS writes a completion identification to the second address space through the PCIe address space, the method further comprises:

and the PCIe device reads the completion identification in the second address space and notifies the application program to acquire the execution result message.

8. The method according to any one of claims 5-7, further comprising:

the application program sends a second deletion instruction to the first address space, wherein the second deletion instruction instructs the PCIe device to delete the completion identification.

9. The method of any of claims 1-8, wherein the PCIe device is one of a baseboard management controller, a network card, a sound card, a built-in cat, a disk array card.

10. A computing device comprising a processor, a basic input output system BIOS, and a high-speed serial computer expansion bus standard PCIe device, an application running on the processor, a first address space of the application and a second address space of the PCIe device being mapped to each other, the PCIe address space and the second address space of the PCIe device being mapped to each other, the first address space being an address space configured by the processor for the application:

the processor is configured to write a hardware control instruction of the application program in the first address space, where the hardware control instruction is configured to instruct a hardware component of the computing device to perform a first operation; the method is also used for acquiring an execution result message from the first address space;

the BIOS is configured to obtain the hardware control instruction from the second address space mapped by the PCIe address space by accessing the PCIe address space; the hardware component is further used for controlling the hardware component to execute the first operation according to the hardware control instruction; the method is also used for obtaining the execution result of the hardware control instruction and generating the execution result message; and the execution result message is written into the second address space mapped by the PCIe address space through the PCIe address space.