CN116671275A

CN116671275A - Ferroelectric memory, preparation method thereof and electronic equipment

Info

Publication number: CN116671275A
Application number: CN202180030983.1A
Authority: CN
Inventors: 黄伟川; 刘熹; 林军
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2023-08-29
Also published as: WO2023115580A1

Abstract

The ferroelectric memory comprises a substrate and at least one ferroelectric tunnel junction group positioned on the substrate, wherein each ferroelectric tunnel junction group comprises N ferroelectric tunnel junction units and N+1 layers of conductive metal layers which are overlapped, the N ferroelectric tunnel junction units and the N+1 layers of conductive metal layers are alternately arranged, and each ferroelectric tunnel junction unit comprises a first conductive oxide layer, a ferroelectric layer and a second conductive oxide layer which are sequentially overlapped, wherein N is an integer greater than or equal to 1. The application also provides a preparation method of the ferroelectric memory and electronic equipment. The ferroelectric memory of the application is beneficial to improving the switching ratio by compounding the conductive metal layer and the conductive oxide layer, and meanwhile, the ferroelectric tunnel junction group has an excellent ferroelectric/electrode interface, thereby being beneficial to improving the ferroelectric performance of the memory, reducing the risk of ferroelectric fatigue of the memory and improving the cycle times and the reliability of writing.

Description

Ferroelectric memory, preparation method thereof and electronic equipment

Technical Field

The present application relates to a ferroelectric memory, a method of manufacturing the ferroelectric memory, and an electronic apparatus including the ferroelectric memory.

Background

With the development of the technology of the internet of things (IoT) and the vehicle, the chip demand is rapidly growing, and the AI chip for the edge operation needs faster and lower power consumption embedded memories in the future. Nonvolatile memory devices that can be used as the embedded memory include nonvolatile magnetic random access memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (FeRAM), phase Change memory (PCRAM), resistive random access memory (Resistive Random Access Memory, RRAM), ferroelectric memory based on Ferroelectric tunnel junctions (Ferroelectric Tunneling Junction, FTJ), and the like.

The ferroelectric tunnel junction (Ferroelectric Tunneling Junction, FTJ) is a device having quantum tunneling effect and electro-resistance effect, in which an ultra-thin ferroelectric film is sandwiched between two electrodes as a tunneling barrier layer. By applying voltage to the electrodes, the ferroelectric polarization direction of the ferroelectric film in the FTJ memory can be turned over, and the interface charge state is changed, so that the FTJ memory can be switched between a high resistance value and a low resistance value. Compared with other novel memories, the FTJ Memory has significant advantages in power consumption and operating speed, the operating speed is comparable to that of a dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), and the read-write power consumption and a Static Random-Access Memory (SRAM) can be balanced, and the FTJ Memory also has nonvolatile characteristics, so that the FTJ Memory has been paid attention.

However, in the actual production and application process, the FTJ memory mainly has the following defects: as shown in fig. 1, the existing FTJ memory includes a bottom electrode 3', a ferroelectric layer 2' and a top electrode 1' sequentially stacked on a substrate, wherein the top electrode 1' and the bottom electrode 3' are made of metals commonly used in integrated circuits, and have conductive and blocking effects, but the ferroelectric tunnel junction has a poor interface of ferroelectric/electrode, and has serious interface defects, thereby causing ferroelectric fatigue problems and reducing the read-write times of the FTJ memory with the structure. On the basis of the FTJ memory in fig. 1, in order to obtain a high-quality ferroelectric film and reduce ferroelectric fatigue caused by ferroelectric/electrode interface defects, the top electrode 1 "and the bottom electrode 3" in the FTJ memory in fig. 2 are made of conductive oxides, but only the conductive oxides are used as electrodes, so that the lead resistance is large and the switch is relatively low. In addition, the ferroelectric tunnel junction in fig. 1 and 2 has no barrier layer, and the ferroelectric performance and reliability of the memory are poor.

Disclosure of Invention

In a first aspect, the present application provides a ferroelectric memory, including a substrate and at least one ferroelectric tunnel junction group located on the substrate, each of the ferroelectric tunnel junction groups including N ferroelectric tunnel junction units and n+1 conductive metal layers stacked, the N ferroelectric tunnel junction units and the n+1 conductive metal layers being alternately arranged, each of the ferroelectric tunnel junction units including a first conductive oxide layer, a ferroelectric layer, and a second conductive oxide layer stacked in this order, wherein N is an integer greater than or equal to 1.

It can be seen that, by arranging the conductive metal layers on the opposite surfaces of the ferroelectric tunnel junction unit respectively, when the first conductive oxide layer and the conductive metal layer adjacent to the first conductive oxide layer are composited to be used as the first electrode, and when the second conductive oxide layer and the conductive metal layer adjacent to the second conductive oxide layer are composited to be used as the second electrode, compared with the arrangement of the full conductive oxide electrodes on the two surfaces of the ferroelectric layer, the lead resistance of the electrodes can be effectively reduced, and the on-off ratio of the first electrode and the second electrode can be improved; because the ferroelectric layer and the conductive oxide layer and the conductive metal layer and the conductive oxide layer are provided with good interfaces, compared with the arrangement of all-metal electrodes on the two surfaces of the ferroelectric layer, the ferroelectric tunnel junction group has the advantages that the first conductive oxide layer and the second conductive oxide layer are added between the ferroelectric layer and the conductive metal layer, so that the good interface effect is provided between the layers of the ferroelectric tunnel junction group, the interface defect of the ferroelectric/electrode is reduced, and the ferroelectric performance of the ferroelectric tunnel junction group is improved; the ferroelectric/electrode interface defect of the ferroelectric tunnel junction group is beneficial to reducing the risk of ferroelectric fatigue of the ferroelectric memory after being reduced, thereby improving the cycle times and the reliability of writing of the ferroelectric memory and prolonging the service life of the ferroelectric memory. In addition, the application realizes multi-directional three-dimensional integration of a plurality of ferroelectric tunnel junction units, and improves the storage state of the ferroelectric memory.

With reference to the first aspect, in some embodiments, a first barrier layer is disposed between the ferroelectric tunnel junction cell and the conductive metal layer adjacent thereto.

It can be seen that by adding the first barrier layer between the conductive metal layer and the ferroelectric tunnel junction unit, the ferroelectric tunnel junction unit has a conductive effect and an excellent barrier effect, so that a good interface is formed between the ferroelectric tunnel junction unit and the conductive metal layer, interface defects of ferroelectric/electrode are reduced, the ferroelectric performance of the ferroelectric tunnel junction unit is improved, the ferroelectric fatigue risk of the ferroelectric memory is reduced, and the cycle times of writing of the ferroelectric memory are improved.

With reference to the first aspect, in some embodiments, the material of the first conductive oxide layer is La _1-x Sr _x MnO ₃ ，La _1- _x Ca _x MnO ₃ ，La _1-x Sr _x CoO ₃ ，YBaCuO ₂ ，SrRuO ₃ ，Nd:SrTiO ₃ And SrIrO ₃ Wherein 0 < x < 1; the material of the second conductive oxide layer is La _1-x Sr _x MnO ₃ ，La _1-x Ca _x MnO ₃ ，La _1-x Sr _x CoO ₃ ，YBaCuO ₂ ，SrRuO ₃ ，Nd:SrTiO ₃ And SrIrO ₃ Wherein 0 < x <1。

It can be seen that the materials of the first conductive oxide layer and the second conductive oxide layer are perovskite conductive materials, which can be beneficial to the superlattice epitaxial growth of the ferroelectric tunnel junction unit, thereby ensuring that the ferroelectric tunnel junction unit has a good ferroelectric/electrode interface and reducing interface defects of the ferroelectric/electrode.

With reference to the first aspect, in some embodiments, the ferroelectric layer is made of (Bi, la) FeO ₃ ，(Ba,Sr)TiO ₃ ，(Pb,La) _1- _x (Zr,Ti) _x O ₃ And at least one of Hf-based oxides.

It can be seen that the ferroelectric layer is made of the above-mentioned titanium ore material or Hf-based oxide ferroelectric material, which is favorable for the growth of the ferroelectric layer on the perovskite-type first conductive oxide layer, and is also favorable for the growth of the perovskite-type second conductive oxide layer on the ferroelectric layer of the above-mentioned material, so as to form an atomic ordered superlattice, and ensure that the ferroelectric tunnel junction unit has a good ferroelectric/electrode interface.

With reference to the first aspect, in some embodiments, the conductive metal layer is at least one of W, co and Al.

It can be seen that the cost can be reduced by using conventional metals to make the conductive metal layer.

With reference to the first aspect, in some embodiments, the material of the first barrier layer is at least one group of Ir/IrO, ru/RuO, ti/TiN, ta/TaN, ta/TaSiN, ti/TiSiN, zr/ZrO.

It can be seen that the selection of the above material is favorable for realizing the effect of both conductivity and blocking of the first blocking layer, the first blocking layer forms a potential barrier between the conductive metal layer and the ferroelectric tunnel junction unit, and if electrons pass through the potential barrier, a certain energy is required, if a positive voltage is applied to the conductive metal layer, the electric field in the potential barrier region is weakened, the potential barrier height is reduced, and part of electrons can pass through the potential barrier, so that forward current is formed, and the ferroelectric layer is promoted to flip in ferroelectric polarization direction; if a reverse voltage is applied to the first barrier layer, the direction of the applied electric field is the same as that of the electric field of the barrier region, but the barrier height is increased, at this time, electrons hardly cross the barrier, and the reverse current is very small, so that polarized electrons of the ferroelectric tunnel junction unit are prevented from diffusing into the conductive metal layer, thereby reducing the risk of ferroelectric fatigue of the ferroelectric tunnel junction unit, and further improving the reliability and service life of the ferroelectric tunnel junction unit.

With reference to the first aspect, in some embodiments, a buffer layer is provided on a surface of the substrate proximate to the ferroelectric tunnel junction group.

It can be seen that adding a buffer layer to the surface of the substrate optimizes the surface of the substrate, provides a lattice parameter matching with the subsequently grown sacrificial layer, reduces the internal stress of the ferroelectric tunnel junction group, and thus reduces the internal defects of the ferroelectric memory.

With reference to the first aspect, in some embodiments, the material of the buffer layer is SrTiO ₃ Or LaNiO ₃ 。

With reference to the first aspect, in some embodiments, the substrate includes at least one connection region and a thinned region around each connection region, each connection region is provided with one of the ferroelectric tunnel junction groups, and the conductive metal layer in each of the ferroelectric tunnel junction groups, which is adjacent to the substrate, extends to the corresponding thinned region.

With reference to the first aspect, in some embodiments, a surface of the substrate corresponding to each of the thinned regions is provided with a second barrier layer.

With reference to the first aspect, in some embodiments, the material of the second barrier layer is at least one group of Ir/IrO, ru/RuO, ti/TiN, ta/TaN, ta/TaSiN, ti/TiSiN, zr/ZrO.

With reference to the first aspect, in some embodiments, two openings are provided at two opposite side edges of each layer of the ferroelectric tunnel junction group, and sidewalls of each ferroelectric tunnel junction group, provided with the openings, are provided on an insulating layer, and the insulating layer extends into each opening.

It can be seen that by providing an insulating layer, each conductive metal layer and each ferroelectric tunnel junction cell can be effectively isolated.

In a second aspect, the present application provides a method for manufacturing a ferroelectric memory, the method comprising:

forming at least one fin body on the surface of a substrate, wherein each fin body comprises n+1 layers of sacrificial layers and N ferroelectric tunnel junction units which are alternately stacked, each ferroelectric tunnel junction unit comprises a first conductive oxide layer, a ferroelectric layer and a second conductive oxide layer which are sequentially stacked, and N is an integer greater than or equal to 1; and

removing each layer of the sacrificial layer in each fin body and forming a conductive metal layer at the position of the sacrificial layer to form at least one ferroelectric tunnel junction group, thereby obtaining the ferroelectric memory.

It can be seen that the preparation method of the application can avoid directly growing the ferroelectric tunnel junction unit on the surface of the conductive metal layer under the high temperature condition by firstly forming the sacrificial layer on the substrate and then replacing the sacrificial layer with the conductive metal layer, can realize the recombination of the conductive metal layer and the ferroelectric tunnel junction unit in the process, is beneficial to reducing the interface defects between all layers in the ferroelectric memory, and is especially beneficial to forming a good ferroelectric/electrode interface; in addition, a plurality of conductive metal layers which are vertically stacked and horizontally arranged can be formed at one time, so that the multi-directional three-dimensional integration of a plurality of ferroelectric tunnel junction units on a substrate is realized, and the storage state is improved. The preparation method is simple, simplifies the process, improves the production efficiency, is beneficial to reducing the cost, can be realized by adopting conventional forming equipment, is easy to operate, and is easy to realize industrialization.

With reference to the second aspect, in some embodiments, the method for preparing the at least one fin includes:

forming an N+1 intermediate sacrificial layer and N ferroelectric tunnel junctions on the surface of the substrate; and

patterning each of the intermediate sacrificial layer and each of the ferroelectric tunnel junction to form at least one of the sacrificial layer and at least one of the ferroelectric tunnel junction cells, respectively, to obtain the at least one fin.

It can be seen that the method for preparing at least one ferroelectric tunnel junction group can prepare a plurality of ferroelectric tunnel junction groups on one substrate simultaneously by forming the integrated intermediate sacrificial layer and the ferroelectric tunnel junction layer and then etching the intermediate sacrificial layer and the ferroelectric tunnel junction layer.

With reference to the second aspect, in some embodiments, before the removing each layer of the sacrificial layer in each fin body, the preparation method further includes:

locally etching two opposite side edge parts of each sacrificial layer in each fin body to form two openings; and

and forming an insulating layer on the side wall of each fin body, which is provided with the opening, wherein the insulating layer extends into each opening.

It can be seen that the insulating layer isolating each ferroelectric tunnel junction unit can be formed by the method, and the insulating layer can play a role in supporting the ferroelectric tunnel junction unit, so that the sacrificial layer can be removed conveniently and the subsequent operation can be performed at the position of the original sacrificial layer.

With reference to the second aspect, in some embodiments, between removing the sacrificial layer and forming the conductive metal layer, the method of preparing further comprises:

a first barrier layer is formed at the location of each of the sacrificial layers.

It can be seen that a first barrier layer is grown on the surface of the ferroelectric tunnel junction unit, and then a conductive metal layer is formed on the surface of the first barrier layer, so that the interface bonding force between the ferroelectric tunnel junction unit and the conductive metal layer is improved, an excellent ferroelectric/electrode interface is formed, the first barrier layer has a conductive effect and a blocking effect, the ferroelectric performance of the ferroelectric tunnel junction group can be improved, the ferroelectric fatigue risk of the ferroelectric memory is reduced, the writing cycle times and reliability of the ferroelectric memory are improved, and the service life of the ferroelectric memory is prolonged.

With reference to the second aspect, in some embodiments, each of the sacrificial layers and each of the ferroelectric tunnel junction units are formed on the surface of the substrate by using a superlattice epitaxial growth process, and the growth temperature is 400-800 ℃.

It can be seen that the superlattice epitaxial growth process is adopted to grow the ferroelectric tunnel junction unit with excellent ferroelectric/electrode interface, so that interface defects are reduced, the ferroelectric fatigue risk of the ferroelectric memory is reduced, and the ferroelectric performance of the ferroelectric memory is improved.

With reference to the second aspect, in some embodiments, the superlattice epitaxial growth comprises Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or Molecular Beam Epitaxy (MBE).

With reference to the second aspect, in some embodiments, before forming at least one fin on the surface of the substrate, the preparation method further includes:

and forming a buffer layer on the surface of the substrate.

It can be seen that by adding the buffer layer on the surface of the substrate, the surface of the substrate can be smoother, the buffer layer and the sacrificial layer have matched lattice parameters, so that the good-interface sacrificial layer and the ferroelectric tunnel junction unit can be grown conveniently, and meanwhile, the internal stress and internal defects of the ferroelectric memory can be reduced.

With reference to the second aspect, in some embodiments, the substrate includes at least one connection region and a thinned region around each connection region, each connection region is formed with one fin body, and the conductive metal layer in each fin body near the substrate extends to the corresponding thinned region.

It can be seen that each conductive metal layer near the substrate extends to the corresponding thinned region, so that the electrode on the surface of the substrate can be conveniently led out to be connected with a power supply.

With reference to the second aspect, in some embodiments, while forming the first barrier layer, the preparation method further includes:

and forming a second barrier layer on the surface of the substrate corresponding to each thinning area.

It can be seen that forming the second barrier layer in the thinned region is beneficial to growth of the thinned region metal conductive layer and reduces interface stress between the thinned region metal conductive layer and the substrate.

The preparation method further comprises the steps of forming a first barrier layer on the surface of each ferroelectric tunnel junction unit corresponding to each windowing region, and simultaneously: and forming a second barrier layer on the surface of the substrate corresponding to the windowing region.

With reference to the second aspect, in some embodiments, the material of each of the sacrificial layers is Sr ₃ Al ₂ O ₆ Or La (La) _1-x Sr _x MnO ₃ 。

In a third aspect, the application provides an electronic device comprising a ferroelectric memory as described above.

Drawings

Fig. 1 and 2 are schematic diagrams of two ferroelectric memories of the prior art.

Fig. 3 is a schematic diagram of a ferroelectric tunnel junction group according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of a ferroelectric memory according to an embodiment of the present application.

Fig. 5 is a cross-sectional view of the ferroelectric memory of fig. 4 taken along V-V.

Fig. 6 is a flowchart of a method for manufacturing a ferroelectric memory according to an embodiment of the present application.

Fig. 7A is a schematic diagram of a process for fabricating a ferroelectric memory according to an embodiment of the present application.

Fig. 7B is a schematic diagram of a second process for manufacturing a ferroelectric memory according to an embodiment of the present application.

Fig. 7C is a schematic diagram III of a ferroelectric memory according to an embodiment of the present application.

Fig. 7D is a schematic diagram of a process for fabricating a ferroelectric memory according to an embodiment of the present application.

Fig. 7E is a schematic diagram five of a ferroelectric memory according to an embodiment of the present application.

Fig. 7F is a schematic diagram six of a ferroelectric memory manufacturing process according to an embodiment of the present application.

Fig. 7G is a cross-sectional view of the schematic in fig. 7F taken along VIIG-VIIG.

Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

The ferroelectric/electrode interface of the ferroelectric tunnel junction which adopts the all-metal electrode is usually defective, and the ferroelectric fatigue problem of the ferroelectric memory is easily caused, thereby reducing the read-write times of the ferroelectric memory. A ferroelectric tunnel junction employing a fully conductive oxide electrode is typically employed as the electrode, with a large lead resistance and a relatively low switching ratio. And there is no barrier layer between the common all-metal electrode and the ferroelectric layer, and between the all-conductive oxide electrode and the ferroelectric layer, so that the ferroelectric property and reliability of the ferroelectric memory are poor.

In view of this, referring to fig. 3 to 5, in an embodiment of the present application, a ferroelectric memory 100 may be used as an embedded nonvolatile memory device in the fields of internet of things, information processing, and the like. The ferroelectric memory 100 comprises a substrate 1 and at least one ferroelectric tunnel junction group 10 located on the substrate 1. As shown in fig. 3, the ferroelectric tunnel junction group 10 includes N ferroelectric tunnel junction units 2 and n+1 conductive metal layers 3 stacked on a substrate 1, where the N ferroelectric tunnel junction units 2 and the n+1 conductive metal layers 3 are alternately arranged, and each of the ferroelectric tunnel junction units 2 includes a first conductive oxide layer 21, a ferroelectric layer 22, and a second conductive oxide layer 23 stacked in sequence, where N is an integer greater than or equal to 1. For example, when N is 1, the ferroelectric tunnel junction unit 2 is one, the conductive metal layer 3 is two, and the obtained ferroelectric tunnel junction group 10 has a structure in which one conductive metal layer 3, one ferroelectric tunnel junction unit 2, and another conductive metal layer 3 are sequentially stacked; when N is 2, the number of ferroelectric tunnel junction units 2 is two, the number of conductive metal layers 3 is four, the obtained ferroelectric tunnel junction group 10 is a structure of one conductive metal layer 3, one ferroelectric tunnel junction unit 2, another conductive metal layer 3, another ferroelectric tunnel junction unit 2 and another conductive metal layer 3 which are sequentially stacked, and at the moment, one conductive metal layer 3 is shared between the two ferroelectric tunnel junction units 2; similarly, the ferroelectric tunnel junction group 10 may implement a three-dimensional stacking of the ferroelectric tunnel junction groups 2, and it may be appreciated that the ferroelectric memory 100 may implement a horizontal arrangement of the ferroelectric tunnel junction groups 10, so that the ferroelectric memory 100 may have multiple storage states at the same time.

Since both the first conductive oxide 21 and the second conductive oxide 23 can be conductive, the first conductive oxide layer 21 and the conductive metal layer 3 adjacent thereto can be used as the first electrode a of the ferroelectric layer 22, and the second conductive oxide layer 23 and the conductive metal layer 3 adjacent thereto can be used as the second electrode b of the ferroelectric layer 22, and are respectively connected to the positive and negative electrodes of an external power source through the two conductive metal layers 3. According to the application, the conductive metal layer 3 is compounded with the first conductive oxide layer 21 (or the second conductive oxide layer 23) and then is used as an electrode to be connected with an external power supply, and compared with the case that the two opposite surfaces of the ferroelectric layer 22 are provided with all conductive oxide electrodes to be connected with the external power supply, the first electrode a and the second electrode b can effectively reduce the lead resistance of the electrodes, and are beneficial to improving the switching ratio; because the ferroelectric layer 22 and the first conductive oxide layer 21 (or the second conductive oxide layer 23), the conductive metal layer 3 and the first conductive oxide layer 21 (or the second conductive oxide layer 23) all have good interfaces, compared with the arrangement of pure metal electrodes on two opposite surfaces of the ferroelectric layer 22, the ferroelectric tunnel junction group 10 has the advantages that the first conductive oxide layer 21 and the second conductive oxide layer 23 are added between the ferroelectric layer 22 and the conductive metal layer 3, so that the good interface effect can be realized between the layers of the ferroelectric tunnel junction group 10, the interface defects of ferroelectric/electrode are reduced, and the ferroelectric performance of the ferroelectric tunnel junction group 10 is improved; since the interface defect of the ferroelectric/electrode, especially the interface stress, can cause the ferroelectric fatigue of the ferroelectric memory, the ferroelectric tunnel junction group 10 of the present application is beneficial to reduce the risk of ferroelectric fatigue of the ferroelectric memory 100 after the interface defect of the ferroelectric/electrode is reduced, thereby improving the cycle number and reliability of writing of the ferroelectric memory 100 and prolonging the service life of the ferroelectric memory 100. In addition, the application realizes multi-directional three-dimensional integration of a plurality of ferroelectric tunnel junction units 2, and improves the storage state of the ferroelectric memory 100.

As shown in fig. 3 and 5, the substrate 1 is made of a semiconductor material, such as a silicon substrate, and the substrate 1 includes a connection region a under each of the ferroelectric tunnel junction groups 10 and a thinned region B around each of the connection regions a, and the conductive metal layer 3 of each of the ferroelectric tunnel junction groups 10 disposed adjacent to the substrate 1 is located on a surface of the connection region a and extends to the thinned region B, thereby forming a contact electrode.

As shown in fig. 4, the ferroelectric tunnel junction unit 2 is made of superlattice, has an epitaxial structure with ordered atoms, and has small stress between the ferroelectric tunnel junction unit 2 and the conductive metal layer 3 and inside the ferroelectric tunnel junction unit 2, and dislocation and defect density at the interface are greatly reduced, so that the ferroelectric tunnel junction unit 2 has a good ferroelectric/electrode interface, ferroelectric performance of the ferroelectric tunnel junction unit 2 is improved, ferroelectric fatigue problem is reduced, and cycle number of writing of the ferroelectric memory 100 is improved.

As shown in fig. 3 and 5, the thickness of the ferroelectric layer 22 is 1nm-5nm, and if the thickness of the ferroelectric layer 22 is too thin, a large leakage current will occur, and it is difficult to show ferroelectricity in experiments; if the thickness of the ferroelectric layer 22 is too thick, quantum tunneling is difficult to occur, the device is no longer a tunnel junction device, and too thick ferroelectric layer 22 also increases the overall thickness of the ferroelectric tunnel junction cell 2 and the resulting ferroelectric memory 100, which is disadvantageous for the thin and short-sized ferroelectric memory 100.

The materials of the first conductive oxide layer 21 and the second conductive oxide layer 23 are ferromagnetic materials, and the thicknesses of the first conductive oxide layer 21 and the second conductive oxide layer 23 are greater than 3nm, so that ferromagnetism can be observed in experiments, and the ferromagnetism is better when the thickness is greater than or equal to 10nm, but when the thickness of the first conductive oxide layer 21 and the second conductive oxide layer 23 exceeds 50nm, the lead resistance of the electrode is larger, and the overall thickness of the ferroelectric memory 100 is increased, so that in the embodiment, the thicknesses of the first conductive oxide layer 21 and the second conductive oxide layer 23 are both 10-50nm.

The ferroelectric tunnel junction unit 2 composed of the ferroelectric layer 22, the first conductive oxide layer 21 and the second conductive oxide layer 23 having the above thicknesses has a nano-scale ultra-thin thickness, which is advantageous in realizing lamination of the multi-layered ferroelectric tunnel junction unit 2, thereby reducing the total thickness of the ferroelectric memory 100 while improving the memory state of the ferroelectric memory 100. In addition, the width and length of the ferroelectric tunnel junction unit 2 may be designed according to actual needs, and in this embodiment, the width and length of each ferroelectric tunnel junction unit 2 are 10nm-2um.

The ferroelectric layer 22 may be made of (Bi, la) FeO ₃ ，(Ba,Sr)TiO ₃ ，(Pb,La) _1-x (Zr,Ti) _x O ₃ And the like, but are not limited thereto. The material of the first conductive oxide layer 21 and the second conductive oxide layer 23 may be La _1-x Sr _x MnO ₃ ，La _1-x Ca _x MnO ₃ ，La _1-x Sr _x CoO ₃ ，YBaCuO ₂ ，SrRuO ₃ ，Nd:SrTiO ₃ And SrIrO ₃ The perovskite conductive material, wherein 0 < x < 1, but not limited thereto. The materials of the first conductive oxide layer 21 and the second conductive oxide layer 23 may be the same or different. The perovskite conductive material is favorable for epitaxially growing a ferroelectric layer with excellent ferroelectric/electrode interface, and simultaneously favorable for growing a conductive oxide film with excellent ferroelectric/electrode interface on the ferroelectric material, so that the first conductive oxide layer 21, the second conductive oxide layer 23 and the ferroelectric layer 22 are prepared from the materials, and the superlattice epitaxial growth of the first conductive oxide layer 21, the second conductive oxide layer 23 and the ferroelectric layer 22 can be favorable for forming an atomic ordered epitaxial structure, thereby ensuring that the ferroelectric layer 22 has good ferroelectric/electrode interface with the first conductive oxide layer 21 and the second conductive oxide layer 23 respectively, and further improving the iron Ferroelectric properties of the electric tunnel junction cell 2.

As shown in fig. 4 and 5, the material of the conductive metal layer 3 may be a conductive metal such as W, co, al, etc. By replacing part of the conductive oxide with conventional metal, the thicknesses of the first conductive oxide layer 21 and the second conductive oxide layer 23 which are epitaxially grown at high temperature can be effectively reduced, which is advantageous in reducing the lead resistance of the electrode and improving the switching ratio compared with the arrangement of all-metal electrodes on both surfaces of the ferroelectric layer 22.

As shown in fig. 4, a first barrier layer 4 is disposed between the ferroelectric tunnel junction unit 2 and the conductive metal layer 3 adjacent to the ferroelectric tunnel junction unit, the first barrier layer 4 is in contact with the conductive metal layer 3, the first barrier layer 4 forms a potential barrier between the conductive metal layer 3 and the ferroelectric tunnel junction unit 2, electrons must have a certain energy to pass through the potential barrier, if a positive voltage is applied to the conductive metal layer 3, the electric field in the potential barrier region is weakened, the potential barrier height is reduced, part of electrons in the conductive metal layer 3 can cross the potential barrier to form a forward current, and the ferroelectric layer 22 is promoted to flip the ferroelectric polarization direction; if a reverse voltage is applied to the first barrier layer 4, the direction of the applied electric field is the same as that of the electric field of the barrier region, but the barrier height is increased, at this time, electrons in the ferroelectric tunnel junction unit 2 are difficult to enter the conductive metal layer 3 through the barrier, and the reverse current is very small, so that the conductive and blocking effects between the first barrier layer 4 and the conductive metal layer 3 are realized. Since the first barrier layer 4 has a conductive effect and a blocking effect, as shown in fig. 5, when the first barrier layer 4 can conduct electricity after a forward voltage is applied, the first barrier layer 4 between the first conductive oxide layer 21 (or the second conductive oxide layer 23) and the conductive metal layer 3 can also serve as a part of the first electrode a (or the second electrode b). By adding the first barrier layer 4 between the conductive metal layer 3 and the ferroelectric tunnel junction unit 2, the ferroelectric tunnel junction unit has a conductive effect and an excellent blocking effect, and can block the diffusion effect of electrons of the ferroelectric tunnel junction unit 2 to the conductive metal layer 3, thereby being beneficial to reducing the risk of ferroelectric fatigue of the ferroelectric tunnel junction unit 2, improving the write cycle times of the ferroelectric memory 100 and prolonging the service life of the ferroelectric memory 100.

According to the above-mentioned conductive and blocking characteristics of the first blocking layer 4, a suitable material needs to be selected to achieve the purpose of improving the reliability and lifetime of the ferroelectric tunnel junction unit 2. In this embodiment, the material of the first barrier layer 4 may be at least one group of combinations of Ir/IrO, ru/RuO, ti/TiN, ta/TaN, ta/TaSiN, ti/TiSiN, zr/ZrO, etc., and the first barrier layer 4 formed by such material can effectively improve the conductive and blocking effects of the first barrier layer 4, thereby improving the reliability and lifetime of the ferroelectric memory 100.

The thickness of the first barrier layer 4 is 1nm-5nm, further 1nm-4nm, further 1nm-3.5nm, if the thickness of the first barrier layer 4 is greater than 5nm, tunneling carriers/charges are smaller, so that the reading current difference is smaller, and misreading is easy to occur; if the thickness is less than 1nm, the barrier function is not performed, and thus, the thickness of the first barrier layer 4 is selected from 1nm to 5nm.

As shown in fig. 4 and 5, the ferroelectric memory 100 further includes a buffer layer 6 disposed on the surface of the substrate 1, where the buffer layer 6 is disposed corresponding to the ferroelectric tunnel junction group 10. The buffer layer 6 is capable of planarizing the surface of the substrate 1 and providing a lattice parameter matching with a sacrificial layer 20 (fig. 7A is combined) to be grown later, which is beneficial for epitaxial growth of the ferroelectric tunnel junction unit 2 with excellent interface and ordered atoms; meanwhile, the addition of the buffer layer 6 may reduce internal stress, thereby improving ferroelectric performance of the ferroelectric memory 100.

The material of the buffer layer 6 may be SrTiO ₃ ，LaNiO ₃ Etc.; the thickness of the buffer layer 6 is 2nm-100nm, if the thickness of the buffer layer 6 is too thin, the effects of matching lattice parameters and reducing stress cannot be achieved, and if the thickness of the buffer layer 6 is too thick, the overall thickness of the ferroelectric memory 100 is directly caused to be thicker, which is not beneficial to the light, thin, short and small of the ferroelectric memory 100.

As shown in fig. 4 and fig. 5, the surface of the substrate 1 corresponding to each thinning area B is provided with a second barrier layer 5, and the second barrier layer 5 can optimize the surface of the substrate 1, so as to be beneficial to the growth of the conductive metal layer 3 on the surface of the thinning area B. The second barrier layer 5 also extends to the surface of the buffer layer 6 near the ferroelectric tunnel junction group 10, the thickness of the second barrier layer 5 is 1nm-5nm, the material of the second barrier layer 5 may be any combination of Ir/IrO, ru/RuO, ti/TiN, ta/TaN, ta/TaSiN, ti/TiSiN, zr/ZrO, etc., and the second barrier layer 5 is mainly used to improve the bonding strength between the conductive metal layer 3 and the substrate 1.

As shown in fig. 4, two openings 8 are formed at two opposite side edges of each layer of the conductive metal layer 3 in each ferroelectric tunnel junction group 10, and the side walls of each ferroelectric tunnel junction group 10 provided with the openings 8 are provided with insulating layers 7, the insulating layers 7 extend into each opening 8, and the insulating layers 7 are used for isolating the ferroelectric tunnel junction units 2 of different layers and the conductive metal layers 3 of different layers.

In the present application, as shown above, N may be an integer greater than or equal to 1, and thus, one or more of the ferroelectric tunnel junction units 2 may be included in one of the ferroelectric tunnel junction groups 10, and one or more of the ferroelectric tunnel junction groups 10 may be included in the ferroelectric memory 100. When each ferroelectric tunnel junction group 10 has a plurality of the ferroelectric tunnel junction units 2 arranged in a stacked manner, wherein the plurality of the ferroelectric tunnel junction units 2 may have different coercive field values, the coercive field is critical field strength of the ferroelectric material whose polarization state is inverted under the action of an external electric field, and thus the plurality of the ferroelectric tunnel junction units 2 may exhibit different polarization directions under different external excitation conditions, so that the ferroelectric memory 100 may have a plurality of different memory states at the same time. In this embodiment, as shown in fig. 4 and 5, the ferroelectric memory 100 includes a ferroelectric tunnel junction group 10, wherein the ferroelectric tunnel junction group 10 includes two ferroelectric tunnel junction cells 2 stacked.

When a plurality of the ferroelectric tunnel junction cells 2 are stacked, since the plurality of the ferroelectric tunnel junction cells 2 have different coercive field performance parameters, respectively, a plurality of different memory states can be realized by adjusting the following physical parameters between the plurality of the ferroelectric tunnel junction cells 2: 1) Adjusting the material type, thickness, molding process conditions, etc. of the ferroelectric layer 22 located in the different ferroelectric tunnel junction cells 2; 2) The current through the different ferroelectric tunnel junction cells 2 is regulated. By adjusting one or more of the above parameters, the coercive fields of the ferroelectric tunnel junction units 2 have larger difference, so that the ferroelectric tunnel junction units 2 are easier to modulate and have different resistance states, and the misreading probability of different ferroelectric tunnel junction units 2 is reduced. Since the first electrode a and the second electrode a are arranged on the two surfaces of each ferroelectric layer 22, the current flowing through the corresponding ferroelectric layer 22 can be controlled by regulating and controlling the electrodes corresponding to different ferroelectric tunnel junction units 2, the regulation and control are more accurate, the limitation of the lamination height of the ferroelectric tunnel junction units 2 is avoided, and the current cannot be too small and difficult to read due to the too high lamination height; moreover, since each ferroelectric tunnel junction unit 2 exists independently, the ferroelectric layers 22 in different ferroelectric tunnel junction units 2 do not affect each other, and the ferroelectric properties of each ferroelectric layer 22 are less affected by other layers, so that a plurality of resistance states with certain differences can be stably presented; in addition, since the electrode of each ferroelectric tunnel junction unit 2 can be independently controlled, the operation difficulty of the ferroelectric memory 100 is low, which is beneficial to the practical application of the ferroelectric memory 100.

According to the application, the conductive metal layers 3 are respectively arranged on the two opposite surfaces of the ferroelectric tunnel junction unit 2, when the first conductive oxide layer 21 and the conductive metal layer 3 adjacent to the first conductive oxide layer are composited to be used as the first electrode a, and the second conductive oxide layer 23 and the conductive metal layer 2 adjacent to the second conductive oxide layer are composited to be used as the second electrode b, compared with the ferroelectric layer 22, the two opposite surfaces of the ferroelectric layer are provided with all conductive oxide electrodes, the first electrode a and the second electrode b of the application can effectively reduce the lead resistance of the electrodes, and are beneficial to improving the switching ratio; because the ferroelectric layer 22 and the first conductive oxide layer 21 (or the second conductive oxide layer 23), the conductive metal layer 3 and the first conductive oxide layer 21 (or the second conductive oxide layer 23) all have good interfaces, compared with the arrangement of all-metal electrodes on the two surfaces of the ferroelectric layer 22, the ferroelectric tunnel junction group 10 has the advantages that the first conductive oxide layer 21 and the second conductive oxide layer 23 are added between the ferroelectric layer 22 and the conductive metal layer 3, so that the good interface effect can be achieved between the layers of the ferroelectric tunnel junction group 10, the interface defects of ferroelectric/electrodes are reduced, and the ferroelectric performance of the ferroelectric tunnel junction group 10 is improved; since the interface defect of the ferroelectric/electrode, especially the interface stress, can cause the ferroelectric fatigue of the ferroelectric memory 100, the ferroelectric tunnel junction group 10 of the present application is beneficial to reducing the risk of ferroelectric fatigue of the ferroelectric memory 100 after the interface defect of the ferroelectric/electrode is reduced, thereby improving the cycle number and reliability of writing of the ferroelectric memory and prolonging the service life of the ferroelectric memory. In addition, the application realizes multi-directional three-dimensional integration of a plurality of ferroelectric tunnel junction units 2, and improves the storage state of the ferroelectric memory 100.

The ferroelectric memory 100 can realize high-performance memory, and the ferroelectric memory 100 can be embedded in a complementary metal Oxide Semiconductor (cmos) chip (Complementary Metal-Oxide-Semiconductor, cmos), planar cmos, fin field effect transistor (FinFET), gate-All-Around FET (GAA FET), etc., thereby forming a high-performance chip of a nonvolatile embedded memory with ultra-fast, low power consumption.

As shown in fig. 6, the present application also provides a method for manufacturing the ferroelectric memory 100, which includes the following steps (it is understood that the following steps may be combined with fig. 7A to 7G).

S1, forming at least one fin body 30 on the surface of a substrate 1, wherein each fin body 30 comprises n+1 layers of sacrificial layers 20 and N ferroelectric tunnel junction units 2 which are alternately stacked, and each ferroelectric tunnel junction unit 2 comprises a first conductive oxide layer 21, a ferroelectric layer 22 and a second conductive oxide layer 23 which are sequentially stacked, wherein N is an integer greater than or equal to 1.

S2, removing each layer of the sacrificial layer 20 in each fin body 30 and forming a conductive metal layer 3 at a position of the sacrificial layer 20 to form at least one ferroelectric tunnel junction group 10, thereby obtaining the ferroelectric memory 100.

Referring to fig. 7A and 7B, in step S1, the specific forming method of the fin body 30 includes the steps of:

in step S11, referring to fig. 7A, n+1 intermediate sacrificial layers 20a and N ferroelectric tunnel junctions 2a are formed on the surface of the substrate 1. Each ferroelectric tunnel junction 2a comprises a first intermediate conductive oxide layer 21a, an intermediate ferroelectric layer 22a and a second intermediate conductive oxide layer 23a stacked in this order.

In this embodiment, the substrate 1 is a silicon substrate. An intermediate buffer layer 6a is also formed before the intermediate sacrificial layer 20a is formed on the surface of the substrate 1.

In this embodiment, the intermediate buffer layer 6a (corresponding to the buffer layer 6 formed later), the intermediate sacrificial layer 20a (corresponding to the sacrificial layer 20 formed later), and the ferroelectric tunnel junction 2a (corresponding to the ferroelectric tunnel junction unit 2 formed later) are grown on the surface of the substrate 1 by using a superlattice epitaxial growth method. The growth mode can be Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE) or the like. The growth temperature of superlattice epitaxial growth is 400-800 ℃.

Step S12 referring to fig. 7B, each of the intermediate sacrificial layer 20a and each of the ferroelectric tunnel junction units 2a is patterned to form at least one of the sacrificial layer 20 and at least one of the ferroelectric tunnel junction units 2, respectively, thereby obtaining the at least one fin body 30.

The substrate 1 includes at least one connection region a and a thinned region B around each connection region a, and each ferroelectric tunnel junction 2a and each intermediate sacrificial layer 20a corresponding to the thinned region B are removed by dry etching to form at least one fin body 30. Wherein, the substrate 1 is also partially etched corresponding to the thinned region B, and the etching depth is smaller than the thickness of the substrate 1. In this embodiment, the intermediate buffer layer 6 corresponding to the thinned region B is also etched simultaneously to form the buffer layer 6 located in the connection region a. In this embodiment, only one fin body 30 is formed on the surface of the substrate 1. It will be appreciated that in other embodiments, a plurality of fins 30 may be formed on the surface of the substrate 1 in a horizontal arrangement to facilitate the subsequent formation of a plurality of ferroelectric tunnel junction groups 10.

Each of the buffer layer 6, the sacrificial layer 20 and the ferroelectric tunnel junction unit 2 epitaxially grown by combining the growth temperature in the superlattice epitaxial growth manner in step S11 has an atomic order epitaxial structure, and simultaneously has an excellent interface effect between the respective layers.

In this embodiment, the material of the buffer layer 6 is SrTiO ₃ Or LaNiO ₃ The thickness of the buffer layer 6 is 2-100nm. The material of the sacrificial layer 20 is a material that can be selectively etched, in particular Sr ₃ Al ₂ O ₆ Or La (La) _1-x Sr _x MnO ₃ The thickness of the sacrificial layer 20 may be 10nm to 100nm.

By adding the buffer layer 6, the surface of the substrate 1 can be flattened, and the epitaxial growth quality of each layer is improved; moreover, the buffer layer 6 can also buffer the internal stress of the sacrificial layer 20 grown on the surface thereof, further improving the growth quality of each layer and reducing the internal stress and internal defects of the ferroelectric memory 100; in addition, by material selection, the buffer layer 6 can provide a lattice parameter matching with the sacrificial layer 20 grown on the surface thereof, the sacrificial layer 20 and the first conductive oxide layer 21 have a lattice parameter matching, and thus, by adding the buffer layer 6, it is advantageous to epitaxially grow the ferroelectric tunnel junction unit 2 having ordered atoms and excellent interfaces.

The thickness of the sacrificial layer 20 determines the thickness of the conductive metal layer 3 to be replaced later, and thus the thickness of the sacrificial layer 20 can be designed according to the actual thickness of the conductive metal layer 3. The number of layers of the ferroelectric tunnel junction cell 2 is not limited to the number of layers shown in fig. 7A, and may be any number of layers.

Referring to fig. 7C to 7G, the specific preparation method of the ferroelectric tunnel junction group 10 includes the steps of:

in step S21, referring to fig. 7C, two opposite side edge portions of each of the sacrificial layers 20 in each of the fin bodies 30 are partially etched to form two openings 8.

The opening 8 is formed by dry etching (for example, hydrochloric acid vapor etching), specifically, a hard mask layer is covered on a side surface of a middle portion of the fin body 30, a portion to be etched is exposed, the exposed sacrificial layer 20 is etched by hydrochloric acid vapor, and etching vapor does not affect the ferroelectric tunnel junction unit 2.

In the present embodiment, the number of the openings 8 increases as the number of the ferroelectric tunnel junction cells 2 stacked increases.

In step S22, referring to fig. 7D, an insulating layer 7 is formed on the sidewall of each fin body 30 having the opening 8, and the insulating layer 7 extends into each opening 8.

By forming the insulating layers 7 on opposite sidewalls of each fin 30, support may be provided for the subsequent formation of the fenestration regions 40, in conjunction with fig. 7E; meanwhile, the insulating layer 7 may be formed to isolate the ferroelectric tunnel junction cell 2 of different layers and the conductive metal layer 3 of different layers formed later, as shown in fig. 4.

In this embodiment, the insulating layer 7 may also extend to a portion of the surface of the fin body 30 away from the substrate 1.

In step S23, referring to fig. 7E, the remaining sacrificial layer 20 is removed by dry etching (e.g. steam etching with hydrochloric acid) to release the channel layer of the ferroelectric tunnel junction unit 2, thereby forming a window region 40. In the present embodiment, the number of the window regions 40 increases as the number of stacks of the ferroelectric tunnel junction unit 2 increases.

In step S23, referring to fig. 7F and fig. 7G, a barrier coating film 50 is formed on the surface of each ferroelectric tunnel junction unit 2 corresponding to each window region 40 and the surface of the substrate 1 corresponding to the window region 40, and a metal material is filled in the window region 40 with the barrier coating film 50 to form a conductive metal coating film 60, wherein the barrier coating film 50 and the conductive metal coating film 60 extend to the surface of the ferroelectric tunnel junction unit 2 not covered by the insulating layer 7.

In the present embodiment, the barrier coating film 50 and the conductive metal coating film 60 also extend to the thinned region B of the substrate 1.

In this embodiment, the material of the barrier coating film 50 may be Ir/IrO, ru/RuO, ti/TiN, ta/TaN, ta/TaSiN, ti/TiSiN, zr/ZrO, or the like. The barrier coating film 50 may be formed on the surface of the buffer layer 6 and the surface of the ferroelectric tunnel junction cell 2 by superlattice epitaxial growth, the specific growth method being referred to above.

In this embodiment, the material of the conductive metal coating film 60 may be a conductive metal such as W, co, al, etc., and may be formed on the surface of the barrier coating film 50 by PVD, ALD, MBE, etc. methods as described above.

In step S24, referring to fig. 4 and 5 in combination, the barrier coating film 50 and the conductive metal coating film 60 on the sidewalls of each ferroelectric tunnel junction cell 2 are removed to form a first barrier layer 4 on the opposite surfaces of each ferroelectric tunnel junction cell 2, a second barrier layer 5 on the substrate 1 and the buffer layer 6, and a conductive metal layer 3 on the surface of the first barrier layer 4.

The first barrier layer 4 and the conductive metal layer 3 formed on the opposite surfaces of each ferroelectric tunnel junction cell 2 are made non-conductive by etching away the barrier cladding film 50 and the conductive metal cladding film 60 on the sidewalls of each ferroelectric tunnel junction cell 2.

In this embodiment, the thickness of the first barrier layer 4 is 1nm-5nm. It will be appreciated that the thickness of the conductive metal layer 3 is the same as the thickness of the sacrificial layer 20 described above, specifically 10nm to 100nm.

By forming the integrated barrier coating film 50 and the conductive metal coating film 60 and then etching, the multi-layer first barrier layer 4 and the multi-layer conductive metal layer 3 can be formed at one time, thereby simplifying the process, remarkably improving the efficiency, ensuring the consistency of the thickness of each layer of the first barrier layer 4 and each layer of the conductive metal layer 3 and improving the ferroelectric performance of the ferroelectric memory 100. In addition, a first barrier layer 4 is grown on the surface of the ferroelectric tunnel junction unit 2, and then a conductive metal layer 3 is formed on the surface of the first barrier layer 4, which is favorable for the growth of the conductive metal layer 3, improves the interfacial bonding force between the ferroelectric tunnel junction unit 2 and the conductive metal layer 3 to form an excellent ferroelectric/electrode interface, and the first barrier layer 4 has a conductive effect and a blocking effect, which can be favorable for improving the ferroelectric performance of the ferroelectric tunnel junction group 10, reducing the risk of ferroelectric fatigue of the ferroelectric memory 100, improving the cycle times and reliability of writing of the ferroelectric memory 100, and prolonging the service life of the ferroelectric memory 100.

The preparation method of the ferroelectric memory 100 of the application adopts the method of lattice matching epitaxial growth to ferroelectric tunnel junction unit 2 on substrate 1, can ensure that ferroelectric tunnel junction unit 2 has good ferroelectric/electrode interface, is beneficial to improving ferroelectric performance of the ferroelectric memory 100 and improving cycle times of writing; by replacing the sacrificial layer 20 with the conductive metal layer 3, the ferroelectric tunnel junction unit 2 can be prevented from being directly grown on the surface of the conductive metal layer 3 under the high temperature condition, and the combination of the conductive metal layer 3 and the first conductive oxide layer 21 (or the second conductive oxide layer 23) can be realized in a process; in addition, the multi-layer conductive metal layers 3 which are vertically stacked and horizontally arranged can be formed at one time, so that the multi-directional three-dimensional integration of the ferroelectric tunnel junction units 2 is realized, and the storage state is improved. The preparation method is simple, simplifies the process, improves the production efficiency, is beneficial to reducing the cost, can be realized by adopting conventional forming equipment, is easy to operate, and is easy to realize industrialization.

As shown in fig. 8, an embodiment of the present application further provides an electronic device 200, which includes a housing 210 and the ferroelectric memory 100 as described above located in the housing 210. The electronic device 200 shown in fig. 8 is a mobile phone, but is not limited to a mobile phone.

It should be noted that the above is only a specific embodiment of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered by the scope of the present application; the embodiments of the present application and features in the embodiments may be combined with each other without conflict. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

The ferroelectric memory is characterized by comprising a substrate and at least one ferroelectric tunnel junction group positioned on the substrate, wherein each ferroelectric tunnel junction group comprises N ferroelectric tunnel junction units and N+1 layers of conductive metal layers which are stacked, the N ferroelectric tunnel junction units and the N+1 layers of conductive metal layers are alternately arranged, and each ferroelectric tunnel junction unit comprises a first conductive oxide layer, a ferroelectric layer and a second conductive oxide layer which are sequentially stacked, wherein N is an integer greater than or equal to 1.
The ferroelectric memory according to claim 1, wherein a first barrier layer is provided between said ferroelectric tunnel junction cell and said conductive metal layer adjacent thereto.
The ferroelectric memory according to claim 1 or 2, wherein the material of the first conductive oxide layer is La _1-x Sr _x MnO ₃ ，La _1-x Ca _x MnO ₃ ，La _1-x Sr _x CoO ₃ ，YBaCuO ₂ ，SrRuO ₃ ，Nd:SrTiO ₃ And SrIrO ₃ Wherein 0 < x < 1;

the material of the second conductive oxide layer is La _1-x Sr _x MnO ₃ ，La _1-x Ca _x MnO ₃ ，La _1-x Sr _x CoO ₃ ，YBaCuO ₂ ，SrRuO ₃ ，Nd:SrTiO ₃ And SrIrO ₃ Wherein 0 < x < 1.
The ferroelectric memory according to claim 1, wherein the ferroelectric layer is made of (Bi, la) FeO ₃ ，(Ba,Sr)TiO ₃ ，(Pb,La) _1-x (Zr,Ti) _x O ₃ And at least one of Hf-based oxides.
The ferroelectric memory of claim 1, wherein the conductive metal layer is at least one of W, co and Al.
The ferroelectric memory according to claim 2, wherein the material of the first barrier layer is at least one of Ir/IrO, ru/RuO, ti/TiN, ta/TaN, ta/TaSiN, ti/TiSiN, zr/ZrO.
The ferroelectric memory according to claim 1, wherein a buffer layer is provided on a surface of said substrate adjacent to said ferroelectric tunnel junction group.
The ferroelectric memory according to claim 7, wherein the material of the buffer layer is SrTiO ₃ Or LaNiO ₃ 。
The ferroelectric memory according to claim 1, wherein said substrate comprises at least one connection region and a thinned region around each of said connection regions, each of said connection regions being provided with one of said ferroelectric tunnel junction groups, said conductive metal layer of each of said ferroelectric tunnel junction groups adjacent to said substrate extending to a corresponding one of said thinned regions.
The ferroelectric memory according to claim 9, wherein a surface of the substrate corresponding to each of the thinned regions is provided with a second barrier layer.
The ferroelectric memory according to claim 10, wherein the material of the second barrier layer is at least one of Ir/IrO, ru/RuO, ti/TiN, ta/TaN, ta/TaSiN, ti/TiSiN, zr/ZrO.
The ferroelectric memory of claim 1, wherein two openings are provided at opposite side edges of each layer of said conductive metal layer in each of said ferroelectric tunnel junction groups, and wherein insulating layers are provided on sidewalls of each of said openings, said insulating layers extending into each of said openings.
A method of manufacturing a ferroelectric memory, comprising:

forming at least one fin body on the surface of a substrate, wherein each fin body comprises n+1 layers of sacrificial layers and N ferroelectric tunnel junction units which are alternately stacked, each ferroelectric tunnel junction unit comprises a first conductive oxide layer, a ferroelectric layer and a second conductive oxide layer which are sequentially stacked, and N is an integer greater than or equal to 1; and

removing each layer of the sacrificial layer in each fin body and forming a conductive metal layer at the position of the sacrificial layer to form at least one ferroelectric tunnel junction group, thereby obtaining the ferroelectric memory.
The method of manufacturing of claim 13, wherein the method of manufacturing of the at least one fin comprises:

forming an N+1 intermediate sacrificial layer and N ferroelectric tunnel junctions on the surface of the substrate; and

patterning each of the intermediate sacrificial layer and each of the ferroelectric tunnel junction to form at least one of the sacrificial layer and at least one of the ferroelectric tunnel junction cells, respectively, to obtain the at least one fin.
The method of manufacturing according to claim 13 or 14, wherein before removing each of the sacrificial layers in each of the fins, the method further comprises:

locally etching two opposite side edge parts of each sacrificial layer in each fin body to form two openings; and

and forming an insulating layer on the side wall of each fin body, which is provided with the opening, wherein the insulating layer extends into each opening.
The method of any one of claims 13 to 15, wherein, between removing the sacrificial layer and forming the conductive metal layer, the method further comprises:

a first barrier layer is formed at the location of each of the sacrificial layers.
The method of claim 13, wherein each of the sacrificial layers and each of the ferroelectric tunnel junction cells are formed on the surface of the substrate using a superlattice epitaxial growth process at a growth temperature of 400-800 ℃.
The method of claim 17, wherein the superlattice epitaxial growth comprises Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or Molecular Beam Epitaxy (MBE).
The method of manufacturing of claim 13, wherein prior to forming the at least one fin on the surface of the substrate, the method of manufacturing further comprises:

and forming a buffer layer on the surface of the substrate.
The method of manufacturing as claimed in claim 16, wherein the substrate includes at least one connection region and a thinned region around each connection region, each connection region being formed with one of the fin bodies, the conductive metal layer of each fin body adjacent to the substrate extending to the corresponding thinned region.
The method of manufacturing of claim 20, wherein the first barrier layer is formed simultaneously with the method of manufacturing further comprising:

and forming a second barrier layer on the surface of the substrate corresponding to each thinning area.
The method of claim 13, wherein the sacrificial layer is Sr ₃ Al ₂ O ₆ Or La (La) _1- _x Sr _x MnO ₃ 。
An electronic device comprising a ferroelectric memory as claimed in any one of claims 1 to 12.