CN116669533A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN116669533A CN116669533A CN202210146243.0A CN202210146243A CN116669533A CN 116669533 A CN116669533 A CN 116669533A CN 202210146243 A CN202210146243 A CN 202210146243A CN 116669533 A CN116669533 A CN 116669533A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000001039 wet etching Methods 0.000 claims abstract description 26
- 238000001312 dry etching Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 21
- 238000001035 drying Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- 239000000376 reactant Substances 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 28
- 238000010586 diagram Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000011282 treatment Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000004793 poor memory Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor device, which relates to the technical field of semiconductors, and adopts two modes of wet etching and dry etching to remove a sacrificial layer, reduce the thickness of a supporting structure, increase the contact area between a lower electrode and a dielectric layer, and enable the capacitance of a capacitor to be increased, thereby improving the storage performance of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: a substrate is provided. At least one laminate structure is formed on a substrate. Each laminated structure comprises a sacrificial layer and a supporting structure positioned on the sacrificial layer, wherein through holes are formed in the sacrificial layer and the supporting structure. And forming a lower electrode on the wall and the bottom of the via hole. And removing the sacrificial layer with a preset height by adopting a wet etching mode. And removing the residual sacrificial layer by adopting a dry etching mode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
As the semiconductor device is gradually miniaturized and the capacitance of the capacitor in the semiconductor device is gradually increased, the width of the lower electrode included in the capacitor is relatively large. In order to prevent the lower electrode included in the capacitor from collapsing or breaking before forming the dielectric layer, a support structure is formed at the outer circumference of the lower electrode. The support structure can support the lower electrode, so that the capacitor structure is more stable.
However, the support structure in the existing semiconductor device may affect the storage performance of the capacitor.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which adopts two modes of wet etching and dry etching to remove a sacrificial layer, reduces the thickness of a supporting structure, increases the contact area between a lower electrode and a dielectric layer, and leads the capacitance of a capacitor to be increased, thereby improving the storage performance of the semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming at least one laminated structure on a substrate, wherein each laminated structure comprises a sacrificial layer and a supporting structure positioned on the sacrificial layer, and through holes are formed in the sacrificial layer and the supporting structure;
forming a lower electrode on the wall and bottom of the via hole;
removing the sacrificial layer with a preset height by adopting a wet etching mode;
and removing the residual sacrificial layer by adopting a dry etching mode.
Compared with the prior art, in the manufacturing method of the semiconductor device, after the lower electrode is formed in the via hole formed in at least one laminated structure, the sacrificial layer with the preset height is removed only by adopting a wet etching mode. In other words, after the wet etching operation, a part of the sacrificial layer remains on the outer periphery of the lower electrode, that is, the lower electrode is not completely released. Under the above circumstances, when the structures such as the substrate and the lower electrode are cleaned and dried after the wet etching process, the supporting structure only needs to provide the supporting force for the released lower electrode with a predetermined height. Meanwhile, after the residual sacrificial layer is removed by adopting a dry etching mode, cleaning and drying treatments are not needed. At this time, the thickness of the support structure does not need to be set to be thicker in the prior art, and the lower electrode does not collapse or break. Therefore, the sacrificial layer in the laminated structure is removed by adopting two modes of wet etching and dry etching, the thickness of the supporting structure can be reduced, and the contact area between the supporting structure and the lower electrode is correspondingly reduced. The surface area of the lower electrode is a fixed value, the contact area between the supporting structure and the lower electrode is reduced, so that the surface area of the lower electrode exposed outside the supporting structure is increased, and the surface area of the lower electrode opposite to the upper electrode included in the capacitor is increased. Since the capacitor has a capacitance proportional to a surface area, a surface area of the lower electrode opposite to the upper electrode becomes large, so that the capacitor has a capacitance which becomes large, thereby improving the memory performance of the semiconductor device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a structure after forming a preformed structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after forming a via in an embodiment of the present invention;
FIG. 4 is a schematic diagram of the structure after forming the electrode material layer according to the embodiment of the invention;
FIG. 5 is a schematic diagram of the structure after forming the bottom electrode according to the embodiment of the invention;
FIG. 6 is a schematic diagram of a structure after removing a sacrificial layer with a predetermined height by wet etching in an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure after removing the remaining sacrificial layer by dry etching according to an embodiment of the present invention;
FIG. 8 is a schematic view of a structure after forming a dielectric layer around the lower electrode and the support structure according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a structure after forming an upper electrode according to an embodiment of the present invention.
Reference numerals:
1 is a laminated structure, 2 is a sacrificial layer, 3 is a supporting structure, 4 is a lower electrode, 5 is a dielectric layer, 6 is an upper electrode, 7 is a capacitor, 8 is a top supporting structure, 9 is a middle supporting structure, 10 is Liu Hanpan, 11 is an isolation structure, 12 is a preformed structure, 13 is a sacrificial material layer, 14 is a supporting material layer, 15 is a via hole, and 16 is an electrode material layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
As the semiconductor device is gradually miniaturized and the capacitance of the capacitor in the semiconductor device is gradually increased, the width of the lower electrode included in the capacitor is relatively large. In order to prevent the lower electrode included in the capacitor from collapsing or breaking between the formation of the dielectric layers, a support structure is formed at the outer circumference of the lower electrode. The support structure can support the lower electrode, so that the capacitor structure is more stable. On the basis, when the conventional semiconductor device is manufactured, a laminated structure of a sacrificial layer and a supporting material layer is sequentially formed on a substrate, and after a lower electrode is formed in the laminated structure, the sacrificial layer is generally removed only by wet etching to prepare for forming a dielectric layer included in a capacitor.
However, as the size of each portion in the semiconductor device gradually decreases, the pitch of adjacent lower electrodes gradually decreases. After the sacrificial layer is removed only by wet etching, the lower electrode can collapse or break under the action of capillary force when the structures such as the substrate, the lower electrode and the like are subjected to drying treatment. Therefore, in order to prevent the lower electrode from collapsing or breaking due to capillary force during the drying process, a supporting structure having a large thickness needs to be formed on the outer circumference of the lower electrode to provide sufficient supporting force for the lower electrode. In this case, the contact area between the support structure and the lower electrode becomes large. The surface area of the lower electrode is a fixed value, and the contact area between the supporting structure and the lower electrode is increased, so that the surface area of the lower electrode exposed outside the supporting structure is reduced, and the surface area of the lower electrode opposite to the upper electrode is reduced. Since the capacitor has a capacitance proportional to a surface area, a surface area of the lower electrode opposite to the upper electrode becomes smaller, so that the capacitor has a smaller capacitance, resulting in poor memory performance of the semiconductor device.
The method aims to solve the technical problems that the thickness of a supporting structure in the traditional semiconductor device is large, the surface area of a lower electrode exposed out of the supporting structure is reduced, the capacitance of a capacitor is reduced, and the storage performance of the semiconductor device is poor. The embodiment of the invention provides a manufacturing method of a semiconductor device. The sacrificial layer is removed by adopting two modes of wet etching and dry etching, the thickness of the supporting structure is reduced, the contact area between the lower electrode and the dielectric layer is increased, and the capacitance of the capacitor is increased, so that the storage performance of the semiconductor device is improved.
In view of the above technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 1, where the method for manufacturing a semiconductor device includes:
step S101: a substrate is provided. It should be appreciated that the substrate may be a single semiconductor material, such as monocrystalline silicon, polycrystalline silicon, and the like. Of course the substrate may also be a stack of already formed portions of the semiconductor structure. For example: when the semiconductor device is applied to a DRAM, the surface of a bit line structure formed over a transistor and the surface of a memory contact may be a substrate. The substrate has an active region. The active region may have a source and a drain formed therein. As for the number of active regions, it is possible to set according to the actual application scenario, and is not particularly limited herein.
In some cases, the semiconductor device further includes a landing pad 10 and an isolation structure 11 formed on the substrate. The isolation structure 11 is used to isolate two adjacent landing pads 10. The landing pads 10 are electrically connected with the corresponding active regions.
For the landing pad 10, the material of the landing pad 10 is a conductive material, and a common conductive material is tungsten or titanium nitride. In the isolation structure 11, the isolation structure 11 may be made of an insulating material such as SiBCN, siCN, siOCN or SiN.
Step S102: as shown in fig. 2 and 3, at least one laminated structure 1 is formed on a substrate, each laminated structure 1 including a sacrificial layer 2, and a support structure 3 on the sacrificial layer 2, the sacrificial layer 2 and the support structure 3 having a via 15 formed therein. It will be appreciated that the thickness of at least one of the stacked structures 1 affects the height of the subsequently formed lower electrode 4, so that the thickness of the stacked structure 1 may be set with reference to the height of the lower electrode 4. The number of the stacked structures 1 determines the number of the support structures 3 included in the semiconductor device, and therefore the number of the stacked structures 1 may be set according to the number of the support structures 3.
The number of the support structures 3 included in the semiconductor device and the specific thickness of the support structures 3 may be designed according to the practical application, and are not particularly limited herein.
Illustratively, when the semiconductor device includes a single support structure 3, the support structure 3 is located at the periphery of the top of the subsequently formed lower electrode 4. Of course, the height of the support structure 3 at the outer periphery of the lower electrode 4 and the thickness of the support structure 3 may be designed according to practical situations, and are not particularly limited herein.
When the semiconductor device includes a plurality of support structures 3, the plurality of support structures 3 surround the outer circumference of the lower electrode 4 in the height direction of the lower electrode 4 to be formed later. The specific number of the multi-layered support structures 3 can be set according to actual requirements. The thickness of these support structures 3, and the spacing between adjacent support structures 3 may be the same or different. For example, as shown in fig. 9, the plurality of support structures 3 includes a top support structure 8 and a middle support structure 9, the top support structure 8 surrounding the periphery of the top of the subsequently formed lower electrode 4. The central support structure 9 surrounds the periphery of the central portion of the lower electrode 4 to be formed later.
The material contained in the support structure 3 in the laminated structure 1 may be an insulating material such as silicon oxynitride, silicon nitride, silicon carbonitride or tantalum oxide. In the case of the sacrificial layer 2, the material contained in the sacrificial layer 2 may be an insulating material that is easy to remove. For example: silicon oxide. In addition, in order to ensure that the subsequent selective removal of the sacrificial layer 2 does not affect the support structure 3, the sacrificial layer 2 should comprise a material different from the material of the support structure 3. Illustratively, the sacrificial layer 2 comprises a material of SiO 2 The material contained in the support material layer 14 is SiN.
Specifically, forming at least one laminated structure 1 on a substrate includes:
step S102.1: as shown in fig. 2, at least one preformed structure 12 is formed on a substrate, each preformed structure 12 including a layer of sacrificial material 13, and a layer of support material 14 formed on the layer of sacrificial material 13. It will be appreciated that the respective parameters (number, thickness, etc.) of the preformed structures 12 formed on the substrate determine the respective parameters of the subsequently formed laminate structure 1, so that the respective parameters of the preformed structures 12 may be set with the respective parameters of the laminate structure 1 as described above.
Illustratively, when the support structure 3 includes the top support structure 8 and the middle support structure 9, two preformed structures 12 may be sequentially formed on the substrate along the height direction of the substrate by direct deposition or the like. In particular, the thickness of the layer of support material 14 comprised by each preformed structure 12 may be set with reference to the thickness of the top support structure 8 and the thickness of the middle support structure 9, respectively, as described above. The thickness of the sacrificial material layer 13 included in each of the preformed structures 12 may be set according to the height of the lower electrode 4 and the thickness of the support material layer 14.
Step S102.2: as shown in fig. 2 and 3, a via 15 is provided in at least one pre-formed structure 12 such that the remaining support material layer 14 forms the support structure 3 and such that the remaining sacrificial material layer 13 forms the sacrificial layer 2. The support structure 3 and the sacrificial layer 2 constitute a laminate structure 1. Illustratively, a dry etching process or a wet etching process may be used to etch down from the top of the preformed structures 12, and a via 15 is formed in at least one of the preformed structures 12. The via 15 extends through all of the preformed structures 12 formed on the substrate. Specifically, as described above, when the above semiconductor device further includes the landing pads 10 and the isolation structures 11 formed on the substrate, the bottoms of the vias 15 are in contact with the corresponding landing pads 10. After etching all of the preformed structures 12 to form the vias 15, the remaining layer of support material 14 within each preformed structure 12 forms the support structure 3.
Step S103: as shown in fig. 4 and 5, the lower electrode 4 is formed on the wall and bottom of the via hole 15. It should be understood that, as described above, when the above-described semiconductor device further includes the landing pads 10 and the isolation structures 11 formed on the substrate, the lower electrodes 4 are formed on the respective landing pads 10, i.e., the lower electrodes 4 may be electrically connected with the source (or drain) possessed by the respective active regions through the respective landing pads 10. In some cases, the lower electrode 4 is a cylindrical electrode. Of course, the lower electrode 4 may be an electrode of another shape as required.
For the lower electrode 4, the material contained in the lower electrode 4 is a conductive material, and a common conductive material is doped polysilicon, metal nitride, or the like. The thickness of the lower electrode 4 may be designed according to the practical application, and is not particularly limited herein.
By way of example, the electrode material layer 16 may be formed on the support structure 3 and within the via 15 by means of direct deposition or the like. Then, the electrode material layer 16 on the support structure 3 is removed by dry etching or wet etching, so that the parts of the electrode material layer 16 at the wall and bottom of the via hole 15 form the lower electrode 4. The material contained in the electrode material layer 16 may be set with reference to the material contained in the lower electrode 4 described above.
Step S104: as shown in fig. 6, the sacrificial layer 2 is removed to a predetermined height by wet etching. It will be appreciated that after formation of the lower electrode 4 and before formation of the dielectric layer 5, the sacrificial layer 2 located at the periphery of the lower electrode 4 needs to be removed. Specifically, the sacrificial layer 2 may be selectively etched using an HF solution to remove the sacrificial layer 2 to a predetermined height. The thickness of the sacrificial layer 2 removed by wet etching may be designed according to the practical application scenario, and is not specifically limited herein.
In an optional manner, after removing the sacrificial layer 2 with a predetermined height by wet etching, before removing the remaining sacrificial layer 2 by dry etching, the method for manufacturing the semiconductor device further includes:
step S104-5: the substrate, the lower electrode 4 and the support structure 3 are subjected to a drying process. It should be understood that the wet etching method is a method of etching a corresponding structure by reacting the corresponding structure with an etching solution. After etching part of the sacrificial layer 2 by wet etching, etching solution remains on the substrate, the lower electrode 4 and the support structure 3. In order not to interfere with the subsequent operations, it is necessary to dry the substrate, the lower electrode 4 and the support structure 3. For example, the substrate, the lower electrode 4, and the support structure 3 may be dried using an IPA drying process. Of course, other drying treatments may be used as desired.
After step S104 is performed, a part of the sacrificial layer 2 remains on the outer periphery of the lower electrode 4, that is, the lower electrode 4 is not released. In the above case, when the substrate, the lower electrode 4, and other structures are subsequently dried, the support structure 3 only needs to provide the supporting force for the released lower electrode 4 with a predetermined height. It can be seen that the thickness of the support structure 3, and thus the surface area of the lower electrode 4 opposite to the upper electrode 6, can be adjusted by adjusting the thickness of the sacrificial layer 2 removed by wet etching.
Step S105: as shown in fig. 7, the remaining sacrificial layer 2 is removed by dry etching.
It should be understood that, after the sacrificial layer 2 with a predetermined height is removed by wet etching, the support structure 3 can only ensure that the bottom electrode 4 with an aspect ratio less than 15 does not collapse or break when the substrate, the bottom electrode 4 and the support structure 3 are dried by an IPA drying process. In the above case, the residual sacrificial layer 2 is removed by dry etching, and the etched product of the residual sacrificial layer 2 can be pumped out of the reaction chamber without drying, so that the lower electrode 4 can be ensured not to collapse or break.
For example, HF and NH may be used 3 The remaining sacrificial layer 2 is removed by the mixed gas of (a) and (b). Wherein, HF and NH in the mixed gas 3 The ratio of (2) may be set according to the actual situation and is not particularly limited herein. NF may also be utilized 3 The reactants of the plasma of gas and the water vapour gas remove the remaining sacrificial layer 2.
It is noted that when the sacrificial layer 2 is removed by both wet etching and dry etching, it is ensured that the lower electrode 4 having an aspect ratio greater than 30 does not collapse or break, which is much greater than the aspect ratio of the lower electrode 4 by only wet etching.
In an alternative manner, after removing the remaining sacrificial layer 2 by dry etching, the method for manufacturing a semiconductor device further includes:
step S106: as shown in fig. 8, a dielectric layer 5 is formed on the outer circumferences of the lower electrode 4 and the support structure 3. It should be understood that the dielectric layer 5 comprised by each capacitor 7 may be formed only at the outer periphery of the support structure 3 and the lower electrode 4 comprised by the respective capacitor 7. Alternatively, the dielectric layers 5 comprised by each capacitor 7 may be connected together.
For example, when the dielectric layers 5 included in the respective capacitors 7 are connected together, the dielectric layers 5 covering the support structure 3 and the lower electrode 4 may be formed on the outer circumferences of the support structure 3 and the lower electrode 4 by atomic layer deposition or the like.
For the dielectric layer 5, the material of the dielectric layer 5 is an insulating material, and the commonly used insulating material is silicon oxide or a high K (dielectric constant) material. As for the layer thickness of the dielectric layer 5, it may be set according to the actual application scene. Specifically, the thickness of the dielectric layer 5 determines the spacing between the lower electrode 4 and the upper electrode 6. While the distance between the lower electrode 4 and the upper electrode 6 is inversely proportional to the capacitance of the capacitor 7, i.e., when the distance between the lower electrode 4 and the upper electrode 6 becomes smaller, the capacitance of the capacitor 7 becomes larger. And when the distance between the lower electrode 4 and the upper electrode 6 becomes large, the capacitance of the capacitor 7 becomes small.
Step S107: as shown in fig. 9, an upper electrode 6 is formed on the dielectric layer 5, and the lower electrode 4, the dielectric layer 5, and the upper electrode 6 constitute a capacitor 7. It should be understood that the upper electrode 6 included in each capacitor 7 may be covered only on the dielectric layer 5 included in each capacitor 7. Alternatively, the upper electrodes 6 included in the respective capacitors 7 may be connected together.
Illustratively, when the upper electrodes 6 included in the respective capacitors 7 are connected together, the upper electrodes 6 may be formed on the dielectric layer 5 by direct deposition or the like.
For the upper electrode 6, the upper electrode 6 contains a conductive material, and the common conductive material is doped polysilicon, metal nitride, or the like. The material contained in the lower electrode 4 may be the same as or different from the material contained in the upper electrode 6. The thickness of the upper electrode 6 may be designed according to practical application, and is not particularly limited herein.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (10)
1. A method of fabricating a semiconductor device, comprising:
providing a substrate;
forming at least one laminated structure on the substrate, wherein each laminated structure comprises a sacrificial layer and a supporting structure positioned on the sacrificial layer, and through holes are formed in the sacrificial layer and the supporting structure;
forming a lower electrode on the hole wall and the hole bottom of the via hole;
removing the sacrificial layer with a preset height by adopting a wet etching mode;
and removing the residual sacrificial layer by adopting a dry etching mode.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the lower electrode is a cylindrical electrode.
3. The method for manufacturing a semiconductor device according to claim 1, wherein after the sacrificial layer is removed by dry etching, the method for manufacturing a semiconductor device comprises:
forming a dielectric layer on the lower electrode and the periphery of the support structure;
an upper electrode is formed on the dielectric layer, and the lower electrode, the dielectric layer and the upper electrode constitute a capacitor.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the etching solution used for removing the sacrificial layer at a predetermined height by wet etching comprises an HF solution.
5. The method for manufacturing a semiconductor device according to claim 1, wherein after the sacrificial layer of a predetermined height is removed by wet etching, before the sacrificial layer is removed by dry etching, the method for manufacturing a semiconductor device further comprises:
and drying the substrate, the lower electrode and the supporting structure.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the drying process is an IPA drying process.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the etching gas used for removing the remaining sacrificial layer by dry etching is HF and NH 3 Is a mixed gas of (a) and (b).
8. The method of manufacturing a semiconductor device according to claim 1, wherein NF is used 3 The reactants of the plasma of gas and the water vapor gas remove the remaining sacrificial layer.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device comprises a top support structure surrounding an outer periphery of a top portion of the lower electrode and a middle support structure surrounding an outer periphery of a middle portion of the lower electrode.
10. The method of manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the substrate has an active region;
the semiconductor device further includes a landing pad formed on the substrate and an isolation structure for isolating adjacent two of the landing pads, the landing pads being electrically connected to the respective active regions, and the lower electrode being formed on the respective landing pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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