CN116667854A - Sigma-delta analog-to-digital converter and method for eliminating idle tone thereof - Google Patents
Sigma-delta analog-to-digital converter and method for eliminating idle tone thereof Download PDFInfo
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- CN116667854A CN116667854A CN202210152574.5A CN202210152574A CN116667854A CN 116667854 A CN116667854 A CN 116667854A CN 202210152574 A CN202210152574 A CN 202210152574A CN 116667854 A CN116667854 A CN 116667854A
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000012545 processing Methods 0.000 claims description 14
- 238000001914 filtration Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 231100000957 no side effect Toxicity 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/328—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither
- H03M3/33—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither the dither being a random signal
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Abstract
The invention provides an sigma-delta analog-to-digital converter and a method for eliminating idle tones thereof. The sigma-delta analog-to-digital converter comprises a loop filter, a quantizer, an adder and a digital-to-analog converter. The loop filter filters a difference between an analog input signal and an analog feedback signal to produce a filtered signal. The quantizer is coupled to the loop filter and generates a digital output signal according to the filtered signal. The adder is coupled to the quantizer and adds a digital dither signal to the digital output signal to generate a digital feedback signal. The digital-to-analog converter is coupled to the loop filter and generates the analog feedback signal according to the digital feedback signal.
Description
Technical Field
The present invention relates to Sigma-Delta (Sigma Delta) analog-to-digital converters, and more particularly to a Sigma-Delta analog-to-digital converter and a method for eliminating idle tones (idle tone) of the Sigma-Delta analog-to-digital converter.
Background
Sigma-Delta (Sigma Delta) analog-to-digital converters typically operate in an oversampled manner, wherein when the input signal is very small or zero (e.g., the voltage level of the input signal is maintained at a fixed value), the output signal of the Sigma-Delta analog-to-digital converter exhibits periodicity with clock-like behavior, but under oversampled operation, out-of-band signals are typically filtered out. Thus, in most cases, the periodic derived tone signal of the output signal does not significantly affect the final output result.
However, when the input signal is located in a certain dc level range, the single tone signal falls into the signal band, so that the sigma-delta analog-to-digital converter cannot or hardly output a correct signal, wherein the single tone signal that appears in the signal band due to the above situation may be referred to as an idle tone (idle tone). Because both the circuitry and the input environment provide noise, there is little opportunity for idle tones to appear in practice. But recently, due to the popularization of the bluetooth headset market and the increase of active noise reduction requirements, the opportunities for occurrence of idle tones are increasing when the specifications of analog-to-digital converters, such as Signal-to-noise ratio (SNR), are required to be higher and higher.
While some solutions to the idle tones have been proposed in the related art, these solutions typically require a large number of measurements to determine the required settings, and the parameter bias in the wafer manufacturing process also makes the related art difficult. Accordingly, a novel method is needed to solve the problems of the related art without or with less side effects.
Disclosure of Invention
An objective of the present invention is to provide a Sigma-delta analog-to-digital converter and a method for eliminating idle tones (idle tone) of the Sigma-delta analog-to-digital converter, so as to ensure that the manufactured chips can properly avoid the occurrence of idle tones under various conditions.
At least one embodiment of the present invention provides a sigma-delta analog-to-digital converter, wherein the sigma-delta analog-to-digital converter may include a loop filter, a quantizer, an adder, and a digital-to-analog converter. The loop filter may be used to filter a difference between an analog input signal and an analog feedback signal to produce a filtered signal. The quantizer is coupled to the loop filter and is operable to generate a digital output signal based on the filtered signal. The adder is coupled to the quantizer and is operable to add a digital dither (dithering) signal to the digital output signal to generate a digital feedback signal. The digital-to-analog converter is coupled to the loop filter and is operable to generate the analog feedback signal based on the digital feedback signal.
At least one embodiment of the present invention provides a method for eliminating idle tones of an sigma-delta analog-to-digital converter. The method may comprise: filtering a difference between an analog input signal and an analog feedback signal by using a loop filter of the sigma-delta analog-to-digital converter to generate a filtered signal; generating a digital output signal according to the filtered signal by using a quantizer of the sigma-delta analog-to-digital converter; adding a digital dithering (dithering) signal to the digital output signal by an adder of the sigma-delta analog-to-digital converter to generate a digital feedback signal; and generating the analog feedback signal according to the digital feedback signal by a digital-to-analog converter of the sigma-delta analog-to-digital converter.
The architecture and method provided by the embodiments of the present invention avoid the occurrence of idle tones by adding dither signals to the signal loop in the digital domain (digital domain). In particular, the energy level and spectral behavior of the dither signal can be precisely controlled in the digital domain where the signal is implemented, thus avoiding problems (e.g., loop saturation, signal dynamic range reduction) caused by adding additional signals to the overall system. In addition, the embodiment of the invention does not greatly increase the extra cost, so the invention can avoid the occurrence of idle tones under the condition of no side effect or less side effect.
Drawings
Fig. 1 is a schematic diagram of an sigma-delta analog-to-digital converter 10 according to an embodiment of the invention.
FIG. 2 is a flowchart of a method for eliminating idle tones of an integrated delta-sigma analog-to-digital converter according to one embodiment of the present invention.
Detailed Description
FIG. 1 is a schematic diagram of a Sigma-delta analog-to-digital converter (or "sum and difference analog-to-digital converter") 10 according to one embodiment of the present invention. As shown in fig. 1, the sigma-delta analog-to-digital converter 10 may include a loop filter 110, a quantizer such as an N-bit quantizer 120, an adder such as an N-bit adder 130, and a digital-to-analog converter 140, where N is a positive integer. In this embodiment, N may be a positive integer greater than one, and the sigma-delta analog-to-digital converter 10 may further include a decoder 150 and a data weighted average (data weighted averaging) logic 160. In some embodiments, N may be equal to one (e.g., an architecture using a single bit quantizer), and decoder 150 and data weighted average logic 160 may be omitted. However, idle tones typically occur more easily in high-specification (low-noise) architectures, where such architectures typically are implemented using multi-bit quantizers rather than single-bit quantizers. In addition, compared with the multi-bit quantizer, the quantization noise generated by the single-bit quantizer is larger, so that the occurrence of idle tones is less likely to be caused. Since the present invention is directed to improving the architecture with the risk of idle tone occurrence, the embodiments of the present invention are described with respect to the architecture using a multi-bit quantizer, but the present invention is not limited thereto.
In the present embodiment, the loop filter 110 may receive an analog input signal Ain with a first input terminal (indicated with "+" in fig. 1 for simplicity) and an analog feedback (feedback) signal Afb from the dac 140 with a second input terminal (indicated with "-" in fig. 1 for simplicity), wherein the loop filter 110 may be configured to filter a difference between the analog input signal Ain and the analog feedback signal Afb to generate a filtered signal Aft. The N-bit quantizer 120 is coupled to the loop filter 110 for receiving the filtered signal Aft and is configured to generate a digital output signal Dout according to the filtered signal Aft (e.g. outputting a corresponding digital code according to a voltage level of the filtered signal Aft). The N-bit adder 130 is coupled to the N-bit quantizer 120 to receive the digital output signal Dout, and may receive a digital dithering (dithering) signal Dn from the digital signal processing circuit 170 to add the digital output signal Dout to the digital dithering signal Dn to generate a digital feedback signal D1 (e.g., d1=dout+dn). The digital-to-analog converter 140 is coupled to the loop filter 110 and can be used to generate the analog feedback signal Afb according to the digital feedback signal D1 (e.g. different digital codes can correspond to different feedback charges/currents/voltages, respectively, and the digital-to-analog converter 140 can output the corresponding feedback charges/currents/voltages according to the digital codes of the digital feedback signal D1).
The digital-to-analog converter 140 may include a plurality of digital-to-analog converting units (e.g., 2N digital-to-analog converting units). In this embodiment, the decoder 150 may perform binary-to-thermometer code (binary-to-thermometer) conversion on the digital feedback signal D1 to convert the digital feedback signal D1 represented by the binary code into the digital feedback signal D2 represented by the thermometer code. In detail, the digital feedback signal D2 represented by the thermometer code may include 2N bits, and the 2N bits respectively correspond to the 2N digital-to-analog conversion units, for example, the digital-to-analog converter 140 may control the corresponding digital-to-analog conversion units according to the logic value of each of the 2N bits. In practice, the feedback signal amounts provided by the plurality of digital-to-analog conversion units are not completely identical. In order to avoid the above-mentioned mismatch of the dac cells causing harmonic tones (harmonic tones) in a signal band, the data weighted average logic 160 may logically operate the digital feedback signal D2 to generate the digital feedback signal D2' such that the power of the harmonic tones generated due to the mismatch of the components is evenly dispersed to a plurality of frequencies (e.g., by making each dac cell have approximately the same frequency used). Those skilled in the art will understand from the above description that the details of the implementation of the decoder 150 and the data weighted average logic 160 shown in fig. 1 are omitted for brevity.
In the embodiment of fig. 1, the sigma-delta analog-to-digital converter 10 is operated in an oversampling manner, for example, the operating frequency of the sigma-delta analog-to-digital converter 10 (sampling rate at which the analog input signal Ain is sampled) is more than twice the bandwidth of the signal band. As shown in fig. 1, the signal path sequentially formed by the loop filter 110, the N-bit quantizer 120, the N-bit adder 130, the decoder 150, the data weighted average logic 160, and the digital-to-analog converter 140 forms a negative feedback loop. Under the above-described oversampling and negative feedback operations, the sigma-delta analog-to-digital converter 10 can convert the analog input signal Ain into the digital output signal Dout by repeatedly correcting the error between the analog feedback signal Afb and the analog input signal Ain. When the analog input signal Ain is very small or completely zero (e.g., the analog input signal Ain is at a fixed dc voltage level), if the digital jitter signal Dn is zero (e.g., the digital signal processing circuit 170 is turned off temporarily), the digital output signal Dout can be transmitted backward without any change (i.e., the digital feedback signal D1 is equal to the digital output signal Dout), and the digital output signal Dout at this time will show periodicity. In particular, when the fixed dc voltage level of the analog input signal Ain falls within the dc interval, the process of negative feedback may exhibit a longer cycle periodicity, thereby generating a lower frequency tone (such as the idle tone described above).
In contrast, when the digital signal processing circuit 170 provides a non-zero digital jitter signal Dn to break the periodicity in the negative feedback (or pushes the periodicity out of the high frequency band such as the signal band), idle tones are avoided from occurring in the signal band. In order to avoid that the digital dither Signal Dn seriously affects the Signal-to-noise ratio (SNR) of the sigma-delta analog-to-digital converter 10, the power of the digital dither Signal Dn in the Signal band needs to be properly designed. In this embodiment, the digital signal processing circuit 170 may generate the digital dithering signal Dn according to the dithering data Dm. For example, the dither data Dm may be M-bit dither data, and the digital signal processing circuit 170 may process the M-bit dither data to generate N-bit dither data as the digital dither signal Dn, where M is a positive integer greater than N. In some embodiments, the jitter data Dm may be generated by a random number generator, and the digital signal processing circuit 170 may perform M-bit to N-bit conversion on the jitter data Dm, and make the power of the digital jitter signal Dn in the signal band (which may be considered as the noise level in the signal band of the sigma-delta analog-to-digital converter 10) lower than the power of the digital jitter signal out of the signal band (which may be considered as the noise level out of the signal band of the sigma-delta analog-to-digital converter 10) by digital signal processing (such as sigma-delta modulation or high-pass filtering).
In some embodiments, the digital dither signal Dn may comprise an out-of-band (out-band) tone signal outside of the signal band of the sigma-delta analog-to-digital converter 10. For example, the jitter data Dm may be a high-resolution single-tone signal, wherein the frequency of the single-tone signal is located outside the signal band. The digital signal processing circuit 170 may suppress the power in the signal band as much as possible when performing M-bit to N-bit conversion by digital signal processing (e.g., sigma-delta modulation) therein to ensure that the noise level in the signal band does not increase substantially due to the digital dither signal Dn.
Since the jitter data Dm and the digital jitter signal Dn are processed in the digital domain (digital domain), and the jitter data Dm can precisely control the total power of noise derived from the jitter data Dm by using a relatively high number of bits (e.g., M bits), the power of the digital jitter signal Dn in each frequency band (the total power of noise in the overall system of the sigma-delta analog-to-digital converter 10) can be precisely controlled to ensure that the signal-to-noise ratio of the sigma-delta analog-to-digital converter 10 does not severely deteriorate due to the digital jitter signal Dn.
FIG. 2 is a flowchart of a method for eliminating idle tones of an integrated delta-sigma analog-to-digital converter (e.g., the integrated delta-sigma analog-to-digital converter of FIG. 1, so that the coupling and signaling relationships of the circuits mentioned in FIG. 2 can also refer to the configuration of FIG. 1) according to an embodiment of the present invention. It should be noted that the workflow shown in fig. 2 is for illustrative purposes only and is not a limitation of the present invention. If the same result is obtained, one or more steps may be added, deleted or modified in the workflow shown in fig. 2, and these steps are not necessarily performed entirely in the order shown in fig. 2.
In step S210, the sigma-delta analog-to-digital converter may filter a difference between an analog input signal and an analog feedback signal by using a loop filter therein to generate a filtered signal.
In step S220, the sigma-delta analog-to-digital converter may generate a digital output signal according to the filtered signal using a quantizer therein.
In step S230, the sigma-delta analog-to-digital converter may use an adder therein to add a digital dither signal to the digital output signal to generate a digital feedback signal.
In step S240, the sigma-delta analog-to-digital converter may generate the analog feedback signal according to the digital feedback signal by using a digital-to-analog converter therein.
In summary, embodiments of the present invention provide for digitally controlling the dither signal by adding the dither signal to the digital domain of the sigma-delta analog-to-digital converter 10. Compared to adding dither signals at the analog domain (analog domain) of the overall system, such as the input of loop filter 110 or the input of N-bit quantizer 120, embodiments of the present invention do not require additional design of a high-specification digital-to-analog converter for adding dither signals in the analog domain, and the present invention is less prone to sacrificing the input dynamic range of the overall system due to the additional addition of dither signals. In addition, the embodiments of the present invention can properly perform under various process variations, and thus do not need to be additionally adjusted according to the process variations. Therefore, the invention can avoid the occurrence of idle tone without side effect or less side effect, thereby solving the problems of the related technology.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
[ symbolic description ]
10: sigma-delta analog-to-digital converter
110: loop filter
120: n-bit quantizer
130: n-bit adder
140: digital-to-analog converter
150: decoder
160: data weighted average logic circuit
170: digital signal processing circuit
Ain: analog input signal
Aft: filtered signal
Afb: analog feedback signal
Dout: digital output signal
D1, D2': digital feedback signal
Dn: digital dither signal
Dm: dithering data
S210 to S240: step (a)
Claims (10)
1. An Sigma-delta analog-to-digital converter, comprising:
a loop filter for filtering a difference between an analog input signal and an analog feedback signal to generate a filtered signal;
a quantizer coupled to the loop filter for generating a digital output signal according to the filtered signal;
an adder coupled to the quantizer for adding a digital dithering (dithering) signal to the digital output signal to generate a digital feedback signal; and
and a digital-to-analog converter coupled to the loop filter for generating the analog feedback signal according to the digital feedback signal.
2. The sigma-delta analog-to-digital converter of claim 1, wherein the power of the digital dither signal is lower in a signal band than the power of the digital dither signal outside the signal band.
3. The sigma-delta analog-to-digital converter of claim 1, wherein the digital dither signal includes an out-of-band (out-band) tone signal outside of a signal band of the sigma-delta analog-to-digital converter.
4. The sigma-delta analog-to-digital converter of claim 1, wherein the quantizer is an N-bit quantizer, the adder is an N-bit adder, and N is a positive integer.
5. The sigma-delta analog-to-digital converter of claim 4, further comprising:
and a digital signal processing circuit coupled to the adder for processing M-bit dithering data to generate N-bit dithering data as the digital dithering signal, wherein M is a positive integer greater than N.
6. A method for eliminating idle tones (idle tones) of an integrated delta-sigma analog-to-digital converter, comprising:
filtering a difference between an analog input signal and an analog feedback signal by using a loop filter of the sigma-delta analog-to-digital converter to generate a filtered signal;
generating a digital output signal according to the filtered signal by using a quantizer of the sigma-delta analog-to-digital converter;
adding a digital dithering (dithering) signal to the digital output signal using an adder of the sigma-delta analog-to-digital converter to generate a digital feedback signal; and
a digital-to-analog converter utilizing the sigma-delta analog-to-digital converter generates the analog feedback signal according to the digital feedback signal.
7. The method of claim 6, wherein the digital dither signal has a lower power within a signal band than the digital dither signal has outside the signal band.
8. The method of claim 6, wherein the digital dither signal includes an out-of-band (out-band) tone signal outside of a signal band of the sigma-delta analog-to-digital converter.
9. The method of claim 6, wherein the quantizer is an N-bit quantizer, the adder is an N-bit adder, and N is a positive integer.
10. The method of claim 9, further comprising:
processing M-bit jitter data by a digital signal processing circuit to generate N-bit jitter data as the digital jitter signal, wherein M is a positive integer greater than N.
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