CN116667300A - Solid-state DC current limiter - Google Patents
Solid-state DC current limiter Download PDFInfo
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- CN116667300A CN116667300A CN202310689089.6A CN202310689089A CN116667300A CN 116667300 A CN116667300 A CN 116667300A CN 202310689089 A CN202310689089 A CN 202310689089A CN 116667300 A CN116667300 A CN 116667300A
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- 230000000670 limiting effect Effects 0.000 claims abstract description 107
- 239000003990 capacitor Substances 0.000 claims abstract description 48
- 239000007787 solid Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000002457 bidirectional effect Effects 0.000 claims description 3
- 230000002829 reductive effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 238000011084 recovery Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/028—Current limitation by detuning a series resonant circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
Abstract
The application discloses a solid-state direct current limiter, which comprises a current limiting module and a diode bridge module, wherein the current limiting module and the diode bridge module are connected in parallel; the current limiting module comprises a current limiting inductor L fcl And a current-limiting capacitor C fcl The method comprises the steps of carrying out a first treatment on the surface of the Current-limiting inductance L fcl Is used as the input end of the solid DC current limiter, and the current-limiting inductance L fcl The other end of (C) is connected with a current-limiting capacitor C fcl Is a current-limiting capacitor C fcl The other end of the first-stage direct current limiter is used as an output end of the solid-state direct current limiter; current-limiting inductance L fcl And a current-limiting capacitor C fcl Carrying out series resonance for current limiting; when the line is operating normally, the line current dc Flowing through the diode bridge module from the input terminal to the output terminal; when the line fails and no over-current signal is detected, the fault current dcf Flow from the input to the output through the current limiting module and the diode bridge module; when the line fault clears, the fault current dcf From the input to the output through the current limiting module.
Description
Technical Field
The application relates to the technical field of protection of direct-current distribution networks, in particular to a solid-state direct-current limiter.
Background
With the development of power electronic devices such as converters, direct-current transformers and the like, the direct-current distribution network can effectively integrate the distribution characteristics of various new energy sources and loads and carry out multiple complementation. The direct current distribution network has gained more attention by virtue of the advantages of large power supply capacity, good economy, high reliability, low loss, high electric energy quality and the like.
However, since the dc power grid composed of the power electronic devices is a "low inertia, low impedance" line, according to the dc fault characteristics, the current of the entire line will rise rapidly after the fault occurs, and the dc voltage will drop rapidly, which will cause serious damage to the dc power grid, especially vulnerable equipment. In the prior art, a current limiter is usually connected into a power grid so as to reduce damage to a direct current power grid when a fault occurs; however, in the prior art, the current limiter is limited by adopting an inductor, and the following defects still exist:
1) The current-limiting inductor is easy to generate inductance saturation along with the increase of fault current in the current-limiting process, so that the current-limiting capacity is lost;
2) The current limiter needs to increase the line inductance value to achieve better current limiting effect, but increasing the inductance causes the cost and the volume of the current limiter to increase;
3) When the current limiting of the current limiter is finished, the partial current limiter is designed into an inductance automatic bypass design, but larger current still exists in a line when a fault is cut off, so that the direct current breaker needs to have larger current stress, and the design cost of the direct current breaker is increased;
4) The fault current in the direct current line develops rapidly and reaches a peak value in a few milliseconds, so the design of the fault current limiter needs to consider the fault detection delay time.
Disclosure of Invention
The present application aims to solve at least one of the above technical problems.
Therefore, the application provides a solid-state direct current limiter, which solves the problem that the current limiting inductance in the existing current limiter is easy to saturate by utilizing the series resonance of the inductance and the capacitance, and has lower cost.
The solid-state direct current limiter provided by the embodiment of the application comprises a current limiting module and a diode bridge module, wherein the current limiting module and the diode bridge module are connected in parallel;
the current limiting module comprises a current limiting inductor L fcl And a current-limiting capacitor C fcl The method comprises the steps of carrying out a first treatment on the surface of the The current-limiting inductance L fcl Is used as the input end of the solid-state DC current limiter, the current-limiting inductance L fcl The other end of the capacitor is connected with the current-limiting capacitor C fcl Is one end of the current-limiting capacitor C fcl The other end of the solid-state direct current limiter is used as an output end of the solid-state direct current limiter; the current-limiting inductance L fcl And the current-limiting capacitor C fcl Carrying out series resonance for current limiting;
when the line is operating normally, the line current i dc Flowing from the input terminal through the diode bridge module to the output terminal; when the line fails and no over-current signal is detected, the fault current i dcf Flowing from the input terminal through the current limiting module and the diode bridge module to the output terminal; when the line fault clears, the fault current i dcf From the input to the output through the current limiting module.
According to some embodiments of the application, the diode bridge module comprises a diode bridge leg and a bias leg, the diode bridge leg and the bias leg being connected in parallel; the diode bridge branch is used for realizing bidirectional current limiting; the bias branch is used for bypassing the current limiting module when the line normally operates.
According to some embodiments of the application, the diode bridge branch comprises a first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 The method comprises the steps of carrying out a first treatment on the surface of the The first diode D 1 And the third diode D 3 Serially connected into a first sub-branch; the second diode D 2 And the fourth diode D 4 Serially connected into a second sub-branch; the first sub-branch and the second sub-branch are connected in parallel to form the diode bridge branch.
According to some embodiments of the application, the bias branch comprises a bias inductance L connected in series in turn b Bias power supply U b And transistor T b The method comprises the steps of carrying out a first treatment on the surface of the The bias power supply U b Is connected with the bias inductance L b Is connected with the bias power supply U b Is connected with the positive electrode of the transistor T b A collector C of (2); the bias inductance L b The other end of the first sub-branch is connected with a node between the first sub-branch and the second sub-branch; the transistor T b Is connected to the other node between the first sub-branch and the second sub-branch.
According to some embodiments of the application, the first diode D 1 And the third diode D 3 The node between the two is connected with the input end; the second diode D 2 And a fourth diode D 4 The node between the two is connected with the output end.
According to some embodiments of the application, when the line is operating normally, and the line current i dc Is smaller than the bias power supply U b The generated steady-state current i b When the first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 Are all conducted, the line current i dc From the input terminal through the first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 To the output;
when the line fails to limit current, the fault current i dcf Greater than the steady state current i b And when the line does not detect the overcurrent signal, the second diode D 2 And a third diode D 3 Turn off, the fault current i dcf From the input terminal through the first diode D 1 Bias branch and fourth diode D 4 Out and through the current limiting inductance L fcl And the current-limiting capacitor C fcl To the output.
According to some embodiments of the application, when a line fails to limit current and the line detects the over-current signal, the fault current i dcf From the input end through the current-limiting inductance L fcl And a current-limiting capacitor C fcl To the output.
According to some embodiments of the application, the current limiting circuitSense of L fcl The relationship between the inductance value of the line inductance in the protection section is as follows:
L fcl ≥kL l
wherein k is a safety margin coefficient (k is not less than 1), L l Is the equivalent inductance of the circuit.
According to some embodiments of the application, the current limiting capacitor C fcl Is such that the fault current i dcf Is equal to 1.5i dc 。
According to some embodiments of the application, the bias power supply U b The generated steady-state current is i b Greater than or equal to the line current i dc 。
The solid-state direct current limiter provided by the embodiment of the application has at least the following beneficial effects:
1) And the inductance saturation is effectively inhibited. The direct current flowing through the current limiting module is converted into high-frequency alternating current through the series resonance effect of the current limiting inductor and the current limiting capacitor, and the fault current is restrained below a safety threshold.
2) The current change of the direct current line is not affected. When the line is in normal operation, the current limiting module bypasses, so that the line current does not flow through the current limiting module.
3) The breaking loss of the circuit breaker is reduced, and the service life of the circuit breaker is prolonged. When a line is in fault, zero crossing points are provided for fault current through the series resonance action of the current limiting inductor and the current limiting capacitor, so that the circuit breaker can be selectively disconnected near the zero crossing points of the fault current, and the disconnection loss of the circuit breaker is greatly reduced.
4) The cost of the solid state dc current limiter is reduced. Compared with the topological structures of other current limiters, the solid-state direct-current limiter has fewer electronic components, and the cost of the solid-state direct-current limiter is greatly reduced.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a topology diagram of a solid state DC current limiter according to an embodiment of the present application;
FIG. 2 is a current flow diagram of a circuit according to an embodiment of the present application during normal operation;
FIG. 3 is a current flow diagram of an embodiment of the present application when a line fault occurs and no over-current signal is detected;
FIG. 4 is a current flow diagram of an embodiment of the present application when a line fault occurs and an over-current signal is detected;
FIG. 5 is a current flow diagram of a line fault clearing process according to an embodiment of the present application;
FIG. 6 is a current flow diagram of a line fault clearing recovery according to an embodiment of the present application;
FIG. 7 is an equivalent circuit diagram of the output side capacitor according to the embodiment of the application when discharging;
FIG. 8 is a graph showing the comparison of theoretical analysis and simulation results in accordance with an embodiment of the present application;
FIG. 9 is a graph showing the effect of the current limiting inductor of the present application on fault current when different inductance values are adopted;
FIG. 10 is a graph showing the effect of the current limiting capacitor of the present application on fault current when different capacitance values are obtained;
reference numerals:
current limiting module 10, diode bridge module 20, diode bridge branch 21, bias branch 22
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. The meaning of a number is one or more, and the meaning of a number is two or more, greater than, less than, exceeding, etc. are understood to exclude the present number, and the meaning of a number above, below, within, etc. are understood to include the present number.
The application aims to provide a solid-state direct current limiter with low cost, which solves the problem that a current limiting inductor in the existing current limiter is easy to saturate by utilizing series resonance of an inductor and a capacitor, and solves the problem that the direct current breaker is difficult to break fault current in a direct current distribution line by changing fault current into high-frequency alternating current through the series resonance of the inductor and the capacitor to generate a current zero crossing point.
As shown in fig. 1, an embodiment of the present application provides a solid-state dc current limiter, which includes a current limiting module 10 and a diode bridge module 20, wherein the current limiting module 10 is a main current limiting module, and is mainly used for suppressing fault current by using series LC resonance; the main function of the diode bridge module 20 is to pass current through the diode during normal operation and to utilize the bias power supply U during failure b Fast input current limiting inductor L b Current limiting (principle is that when fault current is greater than I b At time D 2 、D 3 Automatic closing, L b Automatic input), at this time L b As an initial current limit (current limiting capability is weaker but failure can be responded quickly), the following closing T b Using series connection L C The resonance is current limited (current limiting capability is strong). The current limiting module 10 and the diode bridge module 20 are connected in parallel; one end node of the current limiting module 10 and the diode bridge module 20 which are connected in parallel is used as an input end of the solid-state direct current limiter, and the other end node of the current limiting module 10 and the diode bridge module 20 which are connected in parallel is used as an input end of the solid-state direct current limiterAn outlet end; the input end of the solid-state direct current limiter is connected with the direct current breaker, and the output end of the solid-state direct current limiter is connected with a load. When the line is operating normally, line current flows from the input to the output through the diode bridge module 20; when the line fails and no over-current signal is detected, fault current flows from the input terminal through the current limiting module 10 and the diode bridge module 20 to the output terminal; when a line fault clears, fault current flows from the input to the output through the current limiting module 10. In the present application, a line current i is used for a line current when the line is operating normally dc Represented as line current i when operating normally with the line dc For distinction and convenience of description, hereinafter fault current i is used dcf Representing the line current when the line fails.
In some embodiments of the present application, the current limiting module 10 includes a current limiting inductance L fcl And a current-limiting capacitor C fcl Current limiting inductance L fcl And a current-limiting capacitor C fcl And (3) connecting in series. Current-limiting inductance L fcl Non-current limiting capacitor C fcl One end of the connection is used as an input end of the current limiting module 10, namely an input end of the solid-state direct current limiter; current-limiting capacitor C fcl Non-current limiting inductance L fcl The connected end serves as the output end of the current limiting module 10, namely the output end of the solid-state direct current limiter.
In some embodiments of the present application, diode bridge module 20 includes a diode bridge leg 21 and a bias leg 22, diode bridge leg 21 and bias leg 22 being connected in parallel; the diode bridge branch 21 is used for realizing bidirectional current limiting; the bias branch 22 is used for bypassing the current limiting module 10 when the line is operating normally, so as to prevent the current limiting module 10 from affecting the normal power flow variation of the line.
In some embodiments of the present application, the diode bridge leg 21 includes a first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 The method comprises the steps of carrying out a first treatment on the surface of the First diode D 1 And a third diode D 3 Connected in series into a first sub-branch, in particular a first diode D 1 Is connected with a third diode D 3 A cathode of (a); second diode D 2 And a fourth diode D 4 Series connection of the first sub-branch and the second sub-branchThe body is a second diode D 2 The anode of the fourth diode D4 is connected to the cathode of the fourth diode D4; the first sub-branch and the second sub-branch are connected in parallel again to form a diode bridge branch 21.
When a fault occurs on one side of the input terminal, a fault current flows from the output terminal to the input terminal, and a first diode D 1 And a fourth diode D 4 Automatically closing the device when the device fails; when a fault occurs on one side of the output terminal, a fault current flows from the input terminal to the output terminal, and a second diode D 2 And a third diode D 3 The automatic closing, biasing branch 22 is engaged in limiting the current.
In some embodiments of the present application, the bias branch 22 includes a bias inductance L b Bias power supply U b And transistor T b . In the present application, the transistor T b Insulated gate bipolar transistor IGBT is selected. Bias inductance L b Bias power supply U b And transistor T b In series, in particular bias supply U b Is connected with a bias inductance L by a negative electrode b Is a bias power supply U b The positive electrode of (a) is connected with transistor T b A collector C of (2); bias inductance L b The other end of the first branch is connected with a node between the first branch and the second branch, in particular a first diode D 1 And a second diode D 2 A cathode of (a); transistor T b The emitter E of (a) is connected to another node between the first sub-branch and the second sub-branch, in particular a third diode D 3 And a fourth diode D 4 Is a positive electrode of (a).
In the present application, the diode bridge module 20 is connected in parallel with the current limiting module 10, specifically, a node between the first diode D1 and the third diode D3 is connected to an input end of the current limiting module 10, and a node between the second diode D2 and the fourth diode D4 is connected to an output end of the current limiting module 10.
It should be noted that the line operation includes four working states, namely, a normal operation state, a fault current limiting state, a fault clearing state and a fault recovery state. After the solid-state direct current limiter is connected to a circuit, corresponding modules are invoked to work according to different working states of the circuit, and the specific process is as follows:
1) Normal operating state
When the line is operating normally, the current flows as shown in FIG. 2 (grey in the drawing indicates no current flows), transistor T b Conduction and bias power supply U b Generating steady-state current i b The method comprises the steps of carrying out a first treatment on the surface of the When the line current i dc <i b In this case, according to kirchhoff's law, the four diodes are connected with equal resistances, and thus the bias power supply U b The resulting current flows through the first diode D 1 And a third diode D 3 And current flowing through the second diode D 2 And a fourth diode D 4 Is equal to the current of the other. Likewise, line current i dc The diode-flowing diode bridge branch 21 is also divided equally by the line current i dc The flow direction of (2) is positive, so the currents flowing through the four diodes are respectively:
when the line is operating normally, the four diodes are all turned on, line current i dc Through a first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 Through the solid state DC current limiter, i b >i dc Both the current limiting module 10 and the bias branch 22 are bypassed and the line current i dc And does not flow through the current limiting module 10 and the bias arm 22. Therefore, the solid-state direct current limiter does not affect the normal power flow variation of the line.
2) Fault current limiting state
When a fault occurs in the line, the line current increases rapidly, and the current flows as shown in fig. 3 (gray in the drawing indicates that no current flows), when the fault current i dcf Exceeding bias supply U b The generated steady-state current i b And no over-current (i) is detected by the line dc >i b Indicating that the system has failed), the second diode D2 and the third diode D3 are turned off rapidly by a reverse voltage drop, the fault current i dcf Commutating to the bias branch 22, the bias branch 22Bias inductance L b Simultaneously with the current limiting module 10, current limiting is put in. In particular fault current i dcf From the input of the solid-state DC current limiter through the first diode D 1 A bias branch 22 and a fourth diode D 4 And flows through a current-limiting inductance L fcl And a current-limiting capacitor C fcl To the output of the solid state dc current limiter.
In order to obtain better current limiting effect, when the line detects an overcurrent signal, the transistor T is immediately turned off b Cut off the bias power supply U b At this point the diode bridge branch 21 is fully blocked and the current flows as shown in fig. 4. Current limiting inductance L of current limiting module 10 fcl And a current-limiting capacitor C fcl Series fault line, fault current i dcf From the input of the solid DC current limiter through the current-limiting inductance L fcl And a current-limiting capacitor C fcl To the output of the solid state dc current limiter. Due to the current-limiting inductance L fcl And a current-limiting capacitor C fcl Is suppressed from the series resonance effect of the fault current i dcf And through the current limiting inductance L fcl And a current-limiting capacitor C fcl To cause a fault current i dcf Generating zero crossings and presenting a sine wave, which more reliably cuts off the fault current i for the direct current circuit breaker dcf The protection is provided, and the breaking capacity of the direct current breaker is reduced.
3) Fault clearing state
Through a current-limiting inductance L fcl And a current-limiting capacitor C fcl To act as series resonance of fault current i dcf Converted to alternating current. After the fault has continued for a period of time, when the detector detects a fault current i dcf When zero crossing occurs, the main breaker of the direct current breaker is disconnected, the lightning arrester is put into operation, the auxiliary breaker better cuts off a fault line, and the breaking capacity of the direct current breaker is reduced. At this time, the current in the line flows as shown in FIG. 5 (gray in the drawing indicates that no current flows), and the fault current i dcf From the input of the solid DC current limiter through the current-limiting inductance L fcl And a current-limiting capacitor C fcl To the output of the solid state dc current limiter.
4) Failure recovery state
After the fault is released, the faulty line is reconnected to the normal line. Due to the transistor T in case of failure b Is turned off, bias power supply U b Is turned off when the current of the bias branch 22 is equal to zero. Thus, the current of the bias branch 22 needs to be restored to the steady state current i b (under normal conditions i) b For a fixed value, ignore the first diode D 1 Second diode D 2 Third diode D 3 Fourth diode D 4 And transistor T b Internal resistance change of (c). When the current of the bias branch 22 is restored, the transistor T is triggered b Turning on bias power supply U b The line resumes to the normal through-flow state. At this time, the current flow in the line is as shown in fig. 6 (gray in the drawing indicates that no current flows).
The current limiting process of the solid-state dc current limiter proposed in the present application is theoretically analyzed as follows:
when the bipolar short circuit fault occurs at the output side of the line, the capacitor at the output side of the line still has energy interaction with the line, so as to simplify theoretical analysis, and the dynamic characteristics of the discharge of the capacitor of the converter station are temporarily not considered, so that the DC source U is used dc Instead of this. Considering the extreme case that a fault occurs near the line output, it is assumed that the line inductance is very small and the line resistance is zero. When the fault current exceeds the current limiting setting value, the fault current instantaneously shifts into the bias branch 22, and the bias inductance L of the bias branch 22 b The fault current can be limited without any time delay, the first time the fault current is suppressed from increasing, and then the transistor T is immediately turned off b The fault current flows into the current limiting module 10, and the fault current flowing through the current limiting module 10 is theoretically analyzed as follows.
Based on the solid-state direct current limiter, an equivalent circuit shown in fig. 7 is established, an image function of fault response current is established by using a loop current method, and a time domain expression of the fault current is obtained through inverse Laplace transformation.
Wherein I is trip Is a transistor T b Line current at turn-off, l=l l +L fcl ，
Inverse Laplace transform of (4) gives i dcf (t)，
The theoretical analysis result is compared with the simulation analysis result, and as shown in fig. 8, the simulation result is basically consistent with the theoretical analysis result.
The parameter selection process of the related components in the solid-state direct current limiter provided by the application is as follows:
1) Determining a current limiting inductance L in a current limiting module 10 based on an inductance value of a faulty line fcl Is a function of the inductance value of the capacitor.
The line needs to provide stable electrical characteristics during fault, and fig. 9 shows the current limiting capacitor C when the inductance of the fault line (i.e. the line inductance in the protection section where the solid state dc current limiter is located) takes a value of 100 μh fcl When the value is 100 mu F, the current-limiting inductor L fcl And taking a current diagram of the circuit output when different inductance values are adopted. As shown in fig. 9 (a), the current limiting inductor L fcl Value 10 mu H, current-limiting inductance L fcl Less than the line inductance, the current-limiting inductance L fcl The energy of the line inductance cannot be absorbed completely, so that the current output by the line after the fault is attenuated rapidly, and stable electrical quantity characteristics cannot be provided continuously. As shown in fig. 9 (b), the current limiting inductor L fcl Value 1mH, current-limiting inductance L fcl Is larger than the line inductance, the current-limiting inductance L fcl The energy of the line inductance can be completely absorbed, the line outputs stable ground current after the fault, and stable electric quantity characteristics can be continuously provided. Therefore, the current-limiting inductance L fcl The inductance value of (a) should be greater than the inductance value of the line inductance in the protection section.
L fcl ≥kL l (5)
Wherein k is a safety margin coefficient (k is not less than 1), L l Is the equivalent inductance of the circuit.
2) Based on fault current i dcf Determining the current limiting capacitance C in the current limiting module 10 fcl Is a capacitance value of (a).
When a direct-current bipolar short circuit occurs at the output side of the line, a fault current with proper magnitude needs to be output to provide a criterion for line protection, so that subsequent fault clearing and fault positioning are facilitated. FIG. 10 shows the current limiting inductance L when the line inductance takes a value of 100 μH fcl When the value is 1mH, the current-limiting capacitor C fcl Taking the current diagram of the circuit output when different capacitance values are adopted. As shown in fig. 10 (a), the current limiting capacitor C fcl When the value is 0.1 mu F, the current limiting effect is obvious, and the fault current is continuously restrained below 0.3p.u. rated current. As shown in fig. 10 (b), the current limiting capacitor C fcl At a value of 8mF, the current limiting effect is reduced as the capacitance increases, and the fault current exceeds 2p.u. rated current. As can be seen from fig. 10, the current limiting capacitor C fcl The value of (2) has great influence on the peak value of fault current; if the capacitance is larger, the fault current i dcf The peak value of the voltage is too high, so that the overcurrent of a circuit in a circuit is easy to occur; if the capacitance is too small, the fault current i dcf Too small a peak value can easily lead to failure to locate the fault. To facilitate subsequent fault clearing and fault locating, current limiting capacitor C fcl The value of (C) is such that the line provides a stable electrical characteristic during a fault, thus limiting the current of the capacitor C fcl The value of (2) should be such that the fault current i dcf Line current I with peak suppression of 1.5 times dc Nearby.
The specific calculation process is as follows:
for fault current i dcf (t) extremum is calculated, and the calculation formula is that
D[i dcf (t)]＝0 (6)
Solving the method through mathematical software to obtain the abscissa t of the extreme point 1 ，t 2 Etc., take in i dcf (t) obtainingTo extremum i dcf (t 1 )，i dcf (t 2 ) Etc.
Because other values are known, the optimal current-limiting capacitance value can be obtained by solving the unitary one-time equation through mathematical software.
3) Based on bias inductance L b Maximum value U of discharge voltage of (2) Lb_max Determining a first diode D 1 Second diode D 2 Third diode D 3 Fourth diode D 4 Bias inductance L b And transistor T b Is a parameter of (a).
According to the working principle of the solid-state direct current limiter in the application, the first diode D 1 Second diode D 2 Third diode D 3 Fourth diode D 4 Bias inductance L b And transistor T b The rated operating current of (1) should be greater than the current set threshold I b And a certain margin needs to be given to prevent the transistor T b The switch-off is not in time. In addition, transistor T b The rated operating voltage of (a) should be greater than the current-limiting inductance L thereof b Two groups of diode bridge arms and transistor T b The bias inductance L needs to be born b Is a discharge voltage of the bias inductance L b Maximum value U of discharge voltage of (2) Lb_max Is that
U T ≥k T U Lb_max (10)
Wherein k is D ，k T Is a safety margin coefficient and is larger than 1; u (U) D Representing each diodePressure resistance value of the tube. Based on the above analysis, the first diode D in the solid state DC current limiter can be determined 1 Second diode D 2 Third diode D 3 Fourth diode D 4 Bias inductance L b And transistor T b Is a parameter of (a).
4) Determining bias power supply U based on maximum load current b 。
Bias power supply U according to the working principle of solid-state direct current limiter b The generated steady-state current i b Should not be smaller than the line current i during normal operation of the line dc The solid-state direct current limiter is used for preventing the influence on the normal operation of the direct current circuit, and particularly the quick transient response and the stability of the direct current circuit are influenced. On the other hand, for the fault current i generated when the line fails dcf Fast response limiting, i b Should not be too large, therefore, i b The maximum load current or the current slightly larger than the maximum load current is set, so that the solid-state direct-current limiter can quickly respond to the line faults under the normal operation condition and does not influence the normal operation of the line.
By adopting the solid-state direct current limiter in the technical scheme, the problem of inductance saturation of the traditional solid-state current limiter is solved, and the size of the reactor is reduced; specifically, the solid-state dc current limiter passes through the current limiting inductor L in the current limiting module 10 fcl And a current-limiting capacitor C fcl The series resonance function of the current limiting module 10 converts the direct current flowing through the current limiting module into high-frequency alternating current, effectively inhibits inductance saturation and converts fault current I dcf Is suppressed below a safety threshold and provides a fault current I at fault dcf Is a zero crossing point of (c). In the second aspect, the normal power flow change of the line is not affected. When the circuit operates normally, the solid-state direct current limiter is directly connected into the circuit in series and passes through the bias power supply U b The current limiting module 10 and the bias branch 22 are bypassed so that normal line current does not flow through the current limiting module 10 and the bias branch 22, and therefore the solid-state direct current limiter does not affect the current change, stability, response speed and the like of the direct current line. In the third aspect, the breaking loss of the circuit breaker is reduced, and the circuit breaker is prolongedAnd the service life is prolonged. The solid-state DC current limiter can provide fault current I when in fault dcf To make the breaker selectively at the fault current I dcf The breaking loss of the circuit breaker is greatly reduced. In a fourth aspect, the cost of the solid state dc current limiter is substantially reduced. Compared with the topological structures of other current limiters, the solid-state direct current limiter has fewer electronic components, greatly reduces the cost of the solid-state direct current limiter, reduces the control complexity of the solid-state direct current limiter and improves the control reliability of the solid-state direct current limiter.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the above embodiment, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present application, and these equivalent modifications or substitutions are included in the scope of the present application as defined in the appended claims.
Claims (10)
1. A solid state dc current limiter comprising a current limiting module (10) and a diode bridge module (20), the current limiting module (10) and the diode bridge module (20) being connected in parallel;
the current limiting module (10) comprises a current limiting inductance L fcl And a current-limiting capacitor C fcl The method comprises the steps of carrying out a first treatment on the surface of the The current-limiting inductance L fcl Is used as the input end of the solid-state DC current limiter, the current-limiting inductance L fcl The other end of the capacitor is connected with the current-limiting capacitor C fcl Is one end of the current-limiting capacitor C fcl The other end of the solid-state direct current limiter is used as an output end of the solid-state direct current limiter; the current-limiting inductance L fcl And the current-limiting capacitor C fcl Carrying out series resonance for current limiting;
when the line is operating normally, the line current dc -passing through the diode bridge module (20) from the input to the output; when the line fails and no over-current signal is detected, the fault current dcf -passing from the input to the output through the current limiting module (10) and the diode bridge module (20); when the line fault clears, the fault current dcf Slave houseThe input flows through the current limiting module (10) to the output.
2. The solid state dc current limiter of claim 1, wherein the diode bridge module (20) comprises a diode bridge leg (21) and a bias leg (22), the diode bridge leg (21) and the bias leg (22) being connected in parallel; the diode bridge branch (21) is used for realizing bidirectional current limiting; the bias branch (22) is used for bypassing the current limiting module (10) when the circuit is in normal operation.
3. A solid state dc current limiter according to claim 2, characterized in that the diode bridge leg (21) comprises a first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 The method comprises the steps of carrying out a first treatment on the surface of the The first diode D 1 And the third diode D 3 Serially connected into a first sub-branch; the second diode D 2 And the fourth diode D 4 Serially connected into a second sub-branch; the first sub-branch and the second sub-branch are connected in parallel to form the diode bridge branch (21).
4. A solid state dc current limiter according to claim 3, characterized in that the bias branch (22) comprises a bias inductance L in series in turn b Bias power supply U b And transistor T b The method comprises the steps of carrying out a first treatment on the surface of the The bias power supply U b Is connected with the bias inductance L b Is connected with the bias power supply U b Is connected with the positive electrode of the transistor T b A collector C of (2); the bias inductance L b The other end of the first sub-branch is connected with a node between the first sub-branch and the second sub-branch; the transistor T b Is connected to the other node between the first sub-branch and the second sub-branch.
5. A solid state dc current limiter according to claim 3, wherein a node between the first diode D1 and the third diode D3 is connected to the input terminal; the node between the second diode D2 and the fourth diode D4 is connected to the output terminal.
6. A solid state DC current limiter according to claim 3,
when the line is operating normally, and the line current dc Is smaller than the bias power supply U b The generated steady-state current i b When the first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 All are conducted, the line current dc From the input terminal through the first diode D 1 Second diode D 2 Third diode D 3 And a fourth diode D 4 To the output;
when the line fails to limit the current, the fault current dcf Greater than the steady state current i b And when the line does not detect the overcurrent signal, the second diode D2 and the third diode D3 are turned off, and the fault current dcf From the input terminal through the first diode D 1 A bias branch (22) and a fourth diode D 4 Out and through the current limiting inductance L fcl And the current-limiting capacitor C fcl To the output.
7. The solid state dc current limiter of claim 6, wherein the fault current is when a line fails to limit current and the line detects the over current signal dcf From the input end through the current-limiting inductance L fcl And a current-limiting capacitor C fcl To the output.
8. The solid state dc current limiter of claim 6 wherein the current limiting inductance L fcl The relationship between the inductance value of the line inductance in the protection section is as follows:
L fcl ≥kL l
wherein k is a safety margin coefficient (k is not less than 1), L l Is the equivalent inductance of the circuit.
9. The solid state dc current limiter of claim 6, wherein the current limiting capacitor C fcl Is such that the fault current dcf Is equal to 1.5 dc 。
10. The solid state dc current limiter of claim 6, wherein the bias supply U b The generated steady-state current is i b More than or equal to the line current dc 。
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