CN116666349A - Semiconductor packaging structure - Google Patents

Abstract

The embodiment of the application discloses a semiconductor packaging structure, which comprises: a substrate including a center region, at least one edge region located at a corner of the substrate, and an isolation region located between the edge region and the center region; the central area comprises a dielectric layer and a plurality of layers of metal layers distributed on two opposite surfaces and inside the dielectric layer; the modulus of the material of the isolation region is smaller than that of the metal layer; and a plurality of solder balls arranged on the bottom surfaces of the central area and the edge area of the substrate.

Description

Semiconductor packaging structure

Technical Field

The embodiment of the application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure.

Background

Solder ball cracking is a common reliability failure mode of integrated circuit (Integrated Circuit, IC) packages, typically occurring at the corners of the package. For example, in flip chip ball grid array (Flip Chip Ball Grid Array, FCBGA) products, the stress of the underlying solder balls cannot be released due to the high modulus of the substrate, resulting in rapid accumulation of solder ball stress strain, cracking, and other problems leading to premature failure.

Disclosure of Invention

In view of the above, the embodiment of the application provides a semiconductor package structure.

The technical scheme of the embodiment of the application is realized as follows:

an embodiment of the present application provides a semiconductor package structure, including:

a substrate comprising a central region, at least one edge region located at a corner of the substrate, and an isolation region located between the edge region and the central region; the central area comprises a dielectric layer and a plurality of layers of metal layers distributed on two opposite surfaces and inside the dielectric layer; the material modulus of the isolation region is less than the modulus of the metal layer;

and a plurality of solder balls arranged on the bottom surfaces of the central area and the edge area of the substrate.

In some embodiments, the edge region includes an isolation layer and a metal layer at least on a bottom surface of the isolation layer;

the solder balls are formed on the surfaces of the metal layers on the bottom surfaces of the central area and the edge area.

In some embodiments, the metal layer in the edge area comprises a plurality of metal patterns which are arranged separately, and the metal patterns are separated by the isolating layer;

the material modulus of the isolating layer is smaller than the modulus of the metal layer.

In some embodiments, the dielectric layer of the central region extends into the isolation region and the edge region;

the dielectric layer located in the edge region acts as the isolation layer.

In some embodiments, the metal layers in the edge regions are symmetrically disposed in a direction perpendicular to the substrate surface;

and/or the edge area is centrosymmetric along the central axis of the substrate, and at least comprises the vertex angle of the substrate.

In some embodiments, at least 2 to 4 rows or 2 to 4 columns of the solder balls are formed in the edge region.

In some embodiments, the metal layer on the top surface of the central region is electrically connected to the metal layer on the top surface of the edge region; the metal layer on the bottom surface of the central region is electrically connected with the metal layer on the bottom surface of the edge region.

In some embodiments, the metal layer at the top or bottom surfaces of the central region and the edge region is a first type of metal layer; the metal layers positioned in the substrate form a second-type metal layer; the substrate further comprises a protective layer covering the first metal layer; the isolation region between the first type metal layers is filled with the protection layer;

the isolation areas between the second-type metal layers are filled with the dielectric layers;

the first type metal layer and the second type metal layer in the edge area are separated by the protective layer and the dielectric layer respectively.

In some embodiments, the metal pattern in the edge region has at least an arcuate edge; the metal patterns of the different layers are the same or different.

In some embodiments, the semiconductor package structure further includes: at least one chip;

the at least one chip is attached to the central area and is electrically connected with the substrate.

An embodiment of the present application provides a semiconductor package structure, including: a substrate including a center region, at least one edge region at a corner of the substrate, and an isolation region between the edge region and the center region; the central area comprises a dielectric layer and a plurality of layers of metal layers distributed on two opposite surfaces and inside the dielectric layer; the modulus of the material of the isolation region is smaller than that of the metal layer; and a plurality of solder balls arranged on the bottom surfaces of the central area and the edge area of the substrate. In the embodiment of the application, the isolation area between the central area and the edge area of the substrate is filled with the material with the modulus smaller than that of the metal layer, and partial stress can be absorbed by the material with low modulus, so that the stress transferred from the semiconductor packaging structure to the solder balls arranged on the bottom surface of the edge area of the substrate can be reduced, and the reliability of the semiconductor packaging structure can be improved.

Drawings

FIG. 1 is a schematic view of a three-dimensional structure of a substrate of a package according to the related art;

FIG. 2 is a cross-sectional view of the substrate shown in FIG. 1;

FIG. 3 is a top view of a copper layer in the substrate of FIG. 1;

fig. 4 is a cross-sectional view of a substrate of a related art package;

FIG. 5 is a schematic diagram of a failure structure of the corner solder ball shown in FIG. 4;

fig. 6 is a perspective view of a related art package;

FIG. 7 is a stress simulation of solder balls in the package of FIG. 6;

fig. 8 to 11 are schematic structural views of a semiconductor package structure according to an embodiment of the present application;

fig. 12 is a schematic three-dimensional structure of a substrate in a semiconductor package structure according to an embodiment of the present application;

FIG. 13 is a cross-sectional view of the substrate shown in FIG. 12;

FIG. 14 is a top view of the metal layer in the substrate shown in FIG. 12;

fig. 15 to 20 are schematic structural views of a substrate according to an embodiment of the present application;

fig. 21 to 23 are schematic structural diagrams of metal patterns in an edge region according to an embodiment of the present application;

FIG. 24 is a corner solder ball strain energy density cloud of a conventional corner-position copper-clad substrate structure;

FIG. 25 is a corner solder ball strain energy density cloud of a corner-position decoppered substrate structure;

fig. 26 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the application are shown in the drawings, it should be understood that the application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Solder ball cracking is a common reliability failure mode of integrated circuit packages, typically occurring at the corners of the package. Fig. 1 is a schematic three-dimensional structure of a substrate of a package in the related art, wherein a right view in fig. 1 is an enlarged view of a left-view dotted frame structure, and fig. 2 is a cross-sectional view of the substrate shown in fig. 1; fig. 3 is a top view of a copper layer in the substrate shown in fig. 1, fig. 4 is a cross-sectional view of a substrate of a package in the related art, fig. 5 is a schematic diagram of a failure structure of a corner solder ball shown in fig. 4, and fig. 6 is a perspective view of the package in the related art. The reason for the corner solder ball cracking in the package is described below with reference to fig. 1-6.

As shown in fig. 1 to 6, the package 100 in the related art includes at least a substrate 10 and solder balls 20 fixedly connected to a bottom surface of the substrate 10. Wherein the substrate 10 comprises a plurality of copper layers 101 and an insulating layer 102 (shown in fig. 2) between the copper layers 101. Copper layer 101, which is a layer of copper wire, copper block or large area copper material, typically has a copper content of up to 80% or more, as shown in fig. 3, copper layer 101 includes an inner region 1011 and an outer region 1012, wherein inner region 1011 is typically formed with copper traces (i.e., metal patterns, not shown in fig. 3), and outer region 1012 is typically plated with copper or is connected with a high density copper ratio, and because of the high modulus of copper material, the stress of the underlying solder balls cannot be released, resulting in a rapid accumulation of stress strain of the solder balls (i.e., solder balls at the corners of the substrate) in contact with outer region 1012, causing cracking (as shown in fig. 5) and premature failure.

Fig. 7 is a stress simulation of solder balls in the package of fig. 6, wherein the brighter the color of the solder balls 20 (lighter the color), the more concentrated the stress (i.e., the higher the stress). As shown in fig. 7, the solder balls 20 at the corners of the package 100 are brightest in color, which further confirms that the solder balls at the corners in the package 100 are most concentrated in stress and are most prone to cracking.

In order to prevent solder ball cracking at corners in the related art, the following two methods are generally adopted for improvement: firstly, replacing tin ball materials; and secondly, replacing the packaging material. However, replacement of the solder ball material increases the material and development costs, which increases the manufacturing cost of the package, and replacement of the package material leads to exceeding of package warpage performance of the package.

Based on this, an embodiment of the present application provides a semiconductor package structure, including: a substrate including a center region, at least one edge region at a corner of the substrate, and an isolation region between the edge region and the center region; the central area comprises a dielectric layer and a plurality of layers of metal layers distributed on two opposite surfaces and inside the dielectric layer; the modulus of the material of the isolation region is smaller than that of the metal layer; and a plurality of solder balls arranged on the bottom surfaces of the central area and the edge area of the substrate. In the embodiment of the application, the isolation area between the central area and the edge area of the substrate is filled with the material with the modulus smaller than that of the metal layer, and partial stress can be absorbed by the material with low modulus, so that the stress transferred from the semiconductor packaging structure to the solder balls arranged on the bottom surface of the edge area of the substrate can be reduced, and the reliability of the semiconductor packaging structure can be improved.

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Before describing the embodiments of the present application, three directions describing the semiconductor package structure that may be used in the following embodiments are defined, for example, a thickness direction of the substrate may be defined as a Z-axis direction, and two directions intersecting each other (for example, perpendicular to each other) are defined as an X-axis direction and a Y-axis direction in a plane where a top surface or a bottom surface of the substrate is located, respectively.

In an embodiment of the present application, please refer to fig. 8 to 11, which illustrate a schematic structural diagram of a semiconductor package structure provided in an embodiment of the present application, wherein fig. 8 is a top view, fig. 9 to 11 are side views, and as shown in fig. 8 to 11, a semiconductor package structure 700 includes:

a substrate 70 including a central region 701, at least one edge region 702 located at a corner of the substrate 70, and an isolation region 703 located between the edge region 702 and the central region 701; the central region 701 includes a dielectric layer 7011 and a plurality of metal layers 7012 disposed on two opposing surfaces and within the dielectric layer 7011; the material modulus of the isolation region 703 is less than the modulus of the metal layer 7012.

A plurality of solder balls 71 are disposed on the bottom surfaces of the center region 701 and the edge region 702 of the substrate 70.

In the embodiment of the present application, the substrate 70 may be various types of package substrates such as a cored FCBGA package substrate, a coreless FCBGA package substrate, and the like. The substrate 70 includes a top surface and a bottom surface disposed opposite in the Z-axis direction. Solder balls 71 are typically disposed on the bottom surface of the substrate 70, and the solder balls 71 are used to connect the substrate 70 to a printed circuit board or an interposer, and a functional circuit layer is typically formed on the top surface of the substrate 70 for connection with other electronic components such as a chip.

It should be noted that, the edge area 702 of the substrate 70 is located at each corner of the substrate 70, and the other areas of the substrate 70 except for the edge area 702 constitute a central area 701 and an isolation area 703; where the isolation region 703 is located at the intersection of the central region 701 and the edge region 702, it is understood that the isolation region 703 separates the central region 701 and the edge region 702.

It should be noted that, the specific position of the edge region 702 may be set according to the stress distribution condition of the substrate transferred to the solder ball, for example, the edge region 702 may also cover the edge region (for example, at the side length position) except the corner.

It should be further noted that, the central region 701 includes a dielectric layer 7011 and a plurality of metal layers 7012 distributed on top and bottom surfaces of the dielectric layer 7011 and inside, wherein the metal layers 7012 are used to form circuit patterns, and the dielectric layer 7011 is used to isolate two adjacent circuit patterns and the circuit patterns in the same metal layer 7012.

The modulus of the material filled in the isolation region 703 is smaller than the modulus of the metal layer 7012, and the modulus may be a single layer modulus or an average modulus.

Specifically, when a chip is stacked on the surface of the substrate 70, the edge region 702 is typically used for grounding, and at this time, the metal layer in the edge region 702 and the metal layer in the central region 701 may be disconnected, that is, disconnected by the material in the isolation region 703. When a plurality of chips are stacked on the surface of the substrate 70, in the case where the layout area of the circuit pattern is tight, a part of the circuit pattern may be formed in the edge region 702 to realize a more complex circuit function (for example, electrical signal extraction), and at this time, metal layers located at the top and bottom of the edge region 702 need to be connected with metal layers located at the top and bottom of the central region 701 (as shown in fig. 11), and at this time, part of the material layers near the top and bottom of the isolation region 703 also need to be filled with the same metal layer (or metal material) as the edge region 702 (or the central region 701) to realize the circuit connection between the edge region 702 and the central region 701, and the circuit distribution density in the middle part of the isolation region 703 is relatively small, so that it is unnecessary to layout a circuit in this region, and it is unnecessary to fill with a metal material. That is, when one chip is stacked on the surface of the substrate 70, the material filled in the isolation region 703 is not a metal material, but a material having a smaller modulus than the metal material; at this time, the single-layer modulus of the material filled in the isolation region 703 is smaller than that of the metal layer. When a plurality of chips are stacked on the surface of the substrate 70, the top layer and the bottom layer in the isolation region 703 need to be filled with a metal material, and the middle region in the isolation region 703 does not need to be filled with a metal material, but can be filled with a material having a smaller modulus than the metal material of the substrate; at this time, the average modulus between the material with a small modulus filled in the isolation region 703 and the metal material is smaller than the average modulus of the metal layer.

Note that the material filled in the isolation region 703 may be the same as that of the dielectric layer 7011, and may be, for example, an Ajinomoto build-up film (ABF).

In some embodiments, the shape of the edge region 702 may be square, triangular, curved, or other shapes including corners of the substrate 70, and in embodiments of the present application, the shape of the edge region 702 is not limited.

In the embodiment of the application, the isolation region 703 between the central region 701 and the edge region 702 of the substrate is filled with a material with a modulus smaller than that of the metal layer 7022, and because the material with a low modulus can absorb part of stress, the stress transferred from the semiconductor packaging structure to the solder balls arranged on the bottom surface of the edge region of the substrate can be reduced, so that the reliability of the semiconductor packaging structure can be improved.

In some embodiments, with continued reference to fig. 9, the edge region 702 includes an isolation layer 7021 and a metal layer 7022 at least on a bottom surface of the isolation layer 7021; solder balls 71 are formed on the metal layer surfaces of the bottom surfaces of the center region 701 and the edge region 702.

It should be noted that, in the embodiment of the present application, the edge area 702 may include the isolation layer 7021 except for the bottom surface connected to the solder ball 71, which includes the metal layer 7022, and the modulus of the isolation layer 7021 is smaller than that of the metal layer 7022. In this way, the stress of the solder balls disposed on the bottom surface of the edge region of the substrate can be reduced, and the reliability of the semiconductor package structure can be improved.

In some embodiments, the material filled in isolation region 703 may be the same as isolation layer 7021, which may be ABF, for example.

It should also be noted that in other embodiments, the material filled in the isolation region 703 may be another material than the isolation layer 7021 and the dielectric layer 7011, such that the isolation region 703 forms a dam-like structure that isolates the central region 701 from the edge regions 702.

In other embodiments, referring to fig. 10, the edge region 702 may also have the same structure as the central region 701, for example, including an isolation layer 7021 and a plurality of metal layers 7022 distributed on two opposite surfaces and inside the isolation layer 7021.

In some embodiments, with continued reference to fig. 11, the metal layer 7012 at the top surface of the central region 701 is electrically connected to the metal layer 7022 at the top surface of the edge region 702; the metal layer 7012 at the bottom surface of the center region 701 is electrically connected to the metal layer 7022 at the bottom surface of the edge region 702.

In some embodiments, with continued reference to fig. 9-11, the metal layer 7012 on the top and bottom surfaces of the central region 701 is electrically connected to the plurality of metal layers 7012 within the central region 701; the metal layers 7022 located on the top and bottom surfaces of the edge regions 702 are electrically connected to the multi-layer metal layers 7022 within the edge regions 702.

Specifically, the electrical connection between the metal layer 7012 of the top surface or bottom surface in the central region 701 and the multi-layer metal layer 7012 inside the central region 701 may be achieved by the conductive pillars 704, or the electrical connection between the metal layer 7022 of the top surface or bottom surface in the edge region 702 and the multi-layer metal layer 7022 inside the edge region 702 may be achieved by the conductive pillars 705, for example. At this time, when the top and bottom layers in the isolation region 703 are provided with metal materials (i.e., when the metal layers on the top surfaces of the central region 701 and the edge region 702 are interconnected, and the metal layers on the lower surfaces of the central region 701 and the edge region 702 are interconnected), the interconnection of the metal layers in the entire substrate can be achieved, thereby achieving certain specific circuit functions.

Note that the conductive pillars 704 are formed in the dielectric layer 7011 between the plurality of metal layers 7012, and the conductive pillars 705 are formed in the isolation layer 7021 between the plurality of metal layers 7022.

In some embodiments, referring to fig. 10, the metal layer 7022 in the edge region 701 includes a plurality of metal patterns 80 disposed separately, and the plurality of metal patterns 80 are separated by a separation layer 7021; the modulus of the material of the barrier layer 7021 is less than the modulus of the metal layer.

In the embodiment of the present application, since the material modulus of the isolation layer 7021 is smaller than the modulus of the metal layer, the isolation layer 7021 fills the gaps between the plurality of discrete metal patterns 80 in the edge region 701, so that the stress in the semiconductor package structure can be absorbed, thereby reducing the stress transferred to the solder balls disposed on the bottom surface of the edge region of the substrate, and further improving the reliability of the semiconductor package structure.

In some embodiments, please continue with reference to fig. 10 and 8, the metal layer 7022 in the edge region 702 is symmetrically disposed along a direction perpendicular to the surface of the substrate 70 (i.e., the Z-axis direction) (see fig. 10); and/or, the edge region 702 is centrosymmetric along a central axis of the substrate 70 (i.e., a central axis extending along the Z-axis direction) (refer to fig. 8), and the edge region 702 includes at least a top corner of the substrate 70.

It should be noted that, the metal layer 7022 in the edge region 702 is symmetrically disposed along the Z-axis direction (as shown in fig. 10), so that the mass distribution of the edge region 702 of the substrate 70 along the Z-axis direction is symmetrical, and the stress release is relatively uniform, so that excessive stress concentration in the upper portion or the lower portion of the edge region 702 is not caused, and the reliability of the substrate is damaged, thereby affecting the reliability of the semiconductor package structure. In addition, the metal layers 7022 in the edge region 702 are symmetrically arranged along the Z-axis direction, so that balance can be achieved, and corner warpage of the substrate can be prevented.

It should be further noted that, the edge region 702 is centrally symmetrical along the central axis of the substrate 70 (as shown in fig. 8), so that the stress in the entire plane of the substrate is released relatively uniformly, that is, the stress is uniformly dispersed to the 4 corners of the substrate, so that excessive concentration of the stress on the edge region at a certain corner of the substrate is not caused, and the reliability of the substrate is damaged, thereby affecting the reliability of the semiconductor package structure. In addition, the edge region 702 is centrally symmetrical along the central axis of the substrate 70, so that balance can be achieved, and corner warpage of the substrate can be prevented.

Note that only one row or column of solder balls 71 is formed below the edge region 702 shown in fig. 8 to 11. In practice, at least 2 to 4 rows or 2 to 4 columns of solder balls are formed in the edge region 702. The area of the edge region 702 is increased, so that the edge region 702 can cover a solder ball region with larger stress concentration, and therefore, partial stress can be absorbed through a low-modulus material in the edge region 702, and further, the stress transferred to the solder ball region by the semiconductor packaging structure can be reduced, and the reliability of the semiconductor packaging structure is improved.

In another embodiment of the present application, fig. 12 is a schematic three-dimensional structure of a substrate in the semiconductor package structure provided in the embodiment of the present application, wherein a right view in fig. 12 is an enlarged view of a left-view dashed-line frame structure, and fig. 13 is a cross-sectional view of the substrate shown in fig. 12; fig. 14 is a top view of the metal layer in the substrate shown in fig. 12. Referring to fig. 12 to 14, a semiconductor structure 700 according to an embodiment of the present application includes: a substrate 70 and solder balls 71. The substrate 70 includes a central region 701, at least one edge region 702 (see fig. 14) located at a corner of the substrate 70, and an isolation region 703 located between the edge region 702 and the central region 701. A plurality of solder balls 71 are disposed on the bottom surfaces of the center region 701 and the edge region 702 of the substrate 70.

Note that, in fig. 14, only the center region 701 and the edge region 702 are shown, and the isolation region 703 between the edge region 702 and the center region 701 is not shown, and it is understood that in fig. 14, the isolation region is located at the boundary between the edge region 702 and the center region 701, and for the specific position and structure of the isolation region 703, reference is made to fig. 13.

Note that, in fig. 14, a metal pattern (not shown) is formed inside the central region 701 for realizing the circuit function of the substrate.

With continued reference to fig. 13, the central region 701 includes a dielectric layer 7011 and a plurality of metal layers 7012 disposed on opposite surfaces and interiorly of the dielectric layer 7011. The edge region 702 includes an isolation layer and metal layers at the top and bottom of the isolation layer, metal layers 7022a and 7022b, respectively.

It should be noted that, in other embodiments, the edge region 702 may be provided as an isolation layer except for the region contacting the solder balls 71, which includes a metal layer.

It should be further noted that the edge region 702 may also have a similar structure to the central region 701, for example, the edge region 702 includes an isolation layer and a plurality of metal layers distributed on two opposite surfaces and inside the isolation layer.

In some embodiments, with continued reference to fig. 13, the dielectric layer 7011 of the central region 701 extends into the isolation region 703 and the edge region 702; the dielectric layer 7011 located in the edge region 702 acts as a spacer. The dielectric layer 7011 may be ABF material.

When the dielectric layer 7011 in the central region 701 extends into the isolation region 703 and the edge 702, the dielectric layer 7011 of the substrate 70 may be considered to be a complete layer and formed at the same time.

It should be further noted that, the modulus of the dielectric layer 7011 is smaller than that of the metal layer, and since the low modulus dielectric layer 7011 can absorb part of the stress, the stress transferred from the semiconductor package structure to the solder balls disposed on the bottom surface of the edge region of the substrate can be reduced, so that the reliability of the semiconductor package structure can be improved.

In some embodiments, with continued reference to fig. 13, the substrate 70 further includes a protective layer 7014, the protective layer 7014 covering the metal layer 7012a of the top surface and the metal layer 7012b of the bottom surface of the central region 701, and the metal layer 7022a of the top surface and the metal layer 7022b of the bottom surface of the edge region 702. Here, the protective layer 7014 may be a Solder Resist (SR).

Table 1 below shows a comparison of modulus between the protective layer SR, the dielectric layer ABF and the metallic layer copper:

table 1:

	copper (Cu)	ABF	SR
				Modulus (Jipa/Gpa))	128	7.5	3.7

As can be seen from table 1, the modulus of copper in the metal layer is ten times or more than that of the protective layer SR and the dielectric layer ABF, and thus, the modulus of the dielectric layer used in the embodiment of the present application is much smaller than that of the metal layer.

In some embodiments, please refer to fig. 13, which illustrates a first type of metal layer formed of a metal layer located on the top or bottom surfaces of the central region 701 and the edge region 702.

Specifically, the metal layer 7012a located on the top surface of the central region 701, the metal layer 7012b located on the bottom surface of the central region 701, the metal layer 7022a located on the top surface of the edge region 702, and the metal layer 7022b located on the bottom surface of the edge region 702 constitute a first type of metal layer. The isolation region 703 between the first type metal layers fills the protective layer 7014.

It should be noted that, since the first metal layer is typically located on the top surface or the bottom surface of the substrate, i.e., on the exposed surface of the substrate, the substrate needs to be formed with a solder resist layer (i.e., the protective layer 7014) between the exposed metal layers after the substrate is formed, so as to prevent oxidation of the substrate and occurrence of solder bridges during subsequent signal extraction, thereby causing short circuits between metal patterns. The solder mask layer has a lower modulus relative to the metal layer, so that the isolation region 703 between the first metal layers is filled with the protective layer 7014, which not only can release the stress transmitted from the semiconductor structure to the solder balls at the corners of the substrate, but also can simplify the manufacturing process of the semiconductor package structure, save the cost and improve the reliability of the semiconductor package structure.

In some embodiments, referring to fig. 13, a plurality of metal layers within the substrate 70 form a second metal layer.

Specifically, the plurality of metal layers 7012c located in the central region 701 of the substrate 70 constitute a second type of metal layer.

Note that, the dielectric layer 7011 is filled between the first metal layer and the second metal layer in the central region 701 and between the plurality of second metal layers, and the dielectric layer 7011 may extend into the isolation region 703 and the edge region 702 as an isolation layer in the edge region 702.

In some embodiments, the metal layer within the edge region 702 includes a plurality of separately disposed metal patterns, and the first and second metal layers within the edge region 702 are separated by a protective layer 7014 and a dielectric layer 7011, respectively.

It should be noted that, in the embodiment of the present application, the metal layer is not disposed or a part of the metal layer is disposed at the corner position of the substrate 70, so that the stress of the semiconductor package structure is reduced to be transferred to the solder balls at the corner, and the reliability of the semiconductor package structure is improved.

Fig. 15 to 20 are schematic structural views of a substrate according to an embodiment of the present application; in some embodiments, at the layout design stage of the substrate, the edge region 702 shown in the right-hand view of fig. 15, and in fig. 17-20, may be designed at the corners of the substrate 70 (shown in the left-hand view of fig. 15) using design software (e.g., EDA software).

It should be noted that, in the substrate 70 shown in fig. 15 and fig. 17 to 19, only for the convenience of understanding the shape of the edge region 702 in the substrate 70 and the position of the edge region 702 on the substrate 70, the wiring condition in the central region 701 is not shown, and in fact, a large number of metal patterns are formed in the central region 701 for realizing different circuit functions.

In some embodiments, as shown in fig. 17-19, the edge region 702 may be completely stripped of metal material (i.e., not include a metal layer), completely filled with dielectric layers and protective layers.

In other embodiments, as shown in fig. 20, the edge region 702 may also include a plurality of discrete metal patterns 80, with the metal patterns 80 being filled with a dielectric layer (or a dielectric layer and a protective layer).

It should be noted that, when the metal layer may not be included in the edge region 702, at least a metal layer or a metal Pad (Pad) connected to the solder ball in the corner region needs to be remained.

In some embodiments, the edge area 702 may cover areas of 1 to 4 rows and 1 to 4 columns of solder balls at corners, such as the edge area 702 in fig. 16 covering 2 rows and 2 columns of solder ball areas. Considering that there is also a distance between solder balls 71 and the edge of substrate 70, when the solder ball 71 pitch is 0.5 millimeters (mm), edge region 702 ranges from about 0.75mm to 2.25mm; when the solder ball 71 pitch is 1mm, the edge area 702 ranges from about 1.25mm to 3.75mm.

In some embodiments, the copper removal may be customized according to different requirements to form edge regions 702 having different shapes, such as rectangular edge regions 702 as shown in fig. 17, triangular edge regions 702 as shown in fig. 18, and curved edge regions 702 including corners as shown in fig. 19.

It should be noted that, in other embodiments, the shape of the edge region 702 may be any other possible shape including the corners of the substrate 70, which is not listed here.

In some embodiments, the metal pattern 80 within the edge region 702 has at least an arcuate edge; for example, circular as shown in fig. 21, or elliptical.

In other embodiments, the metal pattern 80 within the edge region 702 may not have arcuate edges, such as rectangular as shown in fig. 22, or hexagonal as shown in fig. 23.

It should be noted that, in other embodiments, the shape of the metal pattern 80 in the edge area 702 may be any other possible shape, which is not listed here.

In some embodiments, the metal patterns 80 of different layers within the edge region 702 are the same or different.

For example, it is assumed that there are 4 layers of metal patterns 80 within the edge region 702, wherein the shape of the metal patterns 80 may be circular, elliptical, rectangular, square, diamond, polygonal, etc., wherein the shape of the first layer of metal patterns 80 may be rectangular, the shape of the second layer of metal patterns 80 may be elliptical, the shape of the third layer of metal patterns 80 may be square, the shape of the fourth layer of metal patterns 80 may be elliptical, etc. Alternatively, each of the metal patterns 80 may have a circular shape.

In other embodiments, the edge region 701 is axisymmetric along the central axis in the plane of the substrate 70, and the shapes of the metal patterns 80 located on the symmetrical layers are the same above and below the central axis, for example, assuming that the edge region 702 has 8 layers of metal patterns 80, then the 1 st layer and 8 th layer of metal patterns 80 are the same, the 2 nd layer and 7 th layer of metal patterns 80 are the same, the 3 rd layer and 6 th layer of metal patterns 80 are the same, and the 4 th layer and 5 th layer of metal patterns 80 are the same, so that balance can be achieved to prevent warpage of the substrate.

In some embodiments, some layers within the edge region 702 may include the metal pattern 80, and some layers may not include the metal pattern 80 (i.e., for a demetallized layer design).

In the embodiment of the application, copper is not designed at the corner position of the substrate metal layer (for example, copper layer) or discontinuous point copper distribution is designed at the corner position when the substrate is designed, and soft ABF or SR with small modulus is filled, so that the stress of the semiconductor packaging structure is reduced to be transferred to the solder ball (for example, tin ball) corresponding to the corner position (corresponding to the edge region 702) and the reliability of the semiconductor packaging structure is improved. For the Copper layer at the bottom of the corner position, only the Copper bonding Pad (coppers Pad) is reserved for being connected with the solder balls, and for the Copper layer at the top of the corner position, the Copper bonding Pad is also reserved as the Copper bonding Pad at the bottom, so that balance is realized, and corner warpage is eliminated.

As can be seen from fig. 2, the stress of the package in the related art is concentrated on the corner solder balls, and the side area is not significantly concentrated, so that the design of the substrate in the present application is applied to the critical corner position, and the side area can leave more wiring (Trace Routing) space. In addition, in the embodiment of the present application, in the case where the wiring space is sufficient, the side length region may be provided with 1 to 2 columns of solder ball regions as the edge region.

Fig. 24 is a corner solder ball strain energy density cloud of a conventional corner-position copper-clad substrate structure, fig. 25 is a corner solder ball strain energy density cloud of a corner-position copper-removed substrate structure, and table 2 below shows strain energy densities (Stress energy density, SED) of the differently numbered corresponding regions of fig. 24 and 25 in units of: megajoules (mJ).

Table 2:

region numbering in FIG. 24	Strain energy Density/mJ	Region numbering in FIG. 25	Strain energy Density/mJ
				a1	0.83033	a2	0.76634
b1	0.75427	b2	0.67181
				c1	0.67821	c2	0.59272
d1	0.60215	d2	0.51362
				e1	0.52609	e2	0.43453
f1	0.45003	f2	0.35543
				g1	0.37397	g2	0.27634
h1	0.22185	h2	0.19724
				i1	0.14579	i2	0.11815

It can be seen that the strain energy density at each location of the corner solder balls is reduced in the solution of the present application.

Table 3 below shows the overall strain energy density after solder ball testing at the corners of the two substrate structures, the other locations structure unchanged, corner placement and corner placement copper removal:

table 3:

the strain energy density in table 3 is a value obtained by weighting the strain energy density in each region of the solder ball in table 2, and reflects the strain energy density of the whole solder ball.

As can be seen from table 2 and table 3, the corner-position decoppered (the present application) substrate has a smaller strain energy density of the corner solder balls after the corner-position decoppered compared with the corner-position decoppered (related art) substrate, so that it can be further explained that the corner-position decoppered can reduce the stress transmitted to the semiconductor package structure and the solder balls disposed on the bottom surface of the edge region of the substrate, thereby improving the reliability of the semiconductor package structure.

The advantages of this solution have the following three points:

firstly, stress of solder balls at corner positions is reduced, and reliability of a semiconductor packaging structure is improved;

secondly, the original process flow is not changed, and copper at the corner position in the design drawing is removed in advance through design software only when the substrate is designed; easy to operate.

Thirdly, copper can be removed according to the winding condition of the substrate and the customer requirement to form punctiform copper (corresponding to the metal pattern), and the punctiform copper can be square, round or any other shape.

In some embodiments, referring to fig. 26, the semiconductor package structure further includes: at least one chip 90; at least one chip 90 is attached to the central region 701 and electrically connected to the substrate 70.

It should be noted that, the electrical connection between the chip 90 and the substrate 70 may be electrically connected by various soldering or bonding methods, or may be connected by wire bonding, which is not limited in the embodiment of the present application.

In an embodiment of the present application, the Chip 90 may be a System On Chip (SOC) including a circuit board and a bus, a functional module (hardware), etc. disposed on a circuit. In other embodiments, the chip 90 may also be a Memory chip or a logic chip, and the Memory chip may include, for example, a static random access Memory (Static Random Access Memory, SRAM) chip, a dynamic random access Memory (Dynamic Random Access Memory, DRAM) chip, a Phase-Change Memory (PCM) chip, a NAND Flash (Flash) chip, and a Nor Flash chip.

In the several embodiments provided by the present application, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly. The features disclosed in the several method or structure embodiments provided by the application can be arbitrarily combined without conflict to obtain new method embodiments or structure embodiments.

The above embodiments are only some embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions should be covered in the protection scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims (10)

1. A semiconductor package structure, comprising at least:

a substrate comprising a central region, at least one edge region located at a corner of the substrate, and an isolation region located between the edge region and the central region; the central area comprises a dielectric layer and a plurality of layers of metal layers distributed on two opposite surfaces and inside the dielectric layer; the material modulus of the isolation region is less than the modulus of the metal layer;

and a plurality of solder balls arranged on the bottom surfaces of the central area and the edge area of the substrate.

2. The semiconductor package according to claim 1, wherein the edge region comprises an isolation layer and a metal layer at least on a bottom surface of the isolation layer;

the solder balls are formed on the surfaces of the metal layers on the bottom surfaces of the central area and the edge area.

3. The semiconductor package structure of claim 2, wherein the metal layer in the edge region comprises a plurality of metal patterns arranged separately, and the metal patterns are separated by the isolation layer;

the material modulus of the isolating layer is smaller than the modulus of the metal layer.

4. The semiconductor package according to claim 3,

the dielectric layer of the central region extends into the isolation region and the edge region;

the dielectric layer located in the edge region acts as the isolation layer.

5. The semiconductor package according to claim 2,

the metal layers in the edge area are symmetrically arranged along the direction vertical to the surface of the substrate;

and/or the edge area is centrosymmetric along the central axis of the substrate, and at least comprises the vertex angle of the substrate.

6. The semiconductor package according to claim 1, wherein at least 2 to 4 rows or 2 to 4 columns of the solder balls are formed in the edge region.

7. The semiconductor package according to claim 2,

the metal layer positioned on the top surface of the central area is electrically connected with the metal layer positioned on the top surface of the edge area; the metal layer on the bottom surface of the central region is electrically connected with the metal layer on the bottom surface of the edge region.

8. The semiconductor package according to claim 4, wherein the metal layer is a first type of metal layer formed of a metal layer on a top surface or a bottom surface of the central region and the edge region; the metal layers positioned in the substrate form a second-type metal layer; the substrate further comprises a protective layer covering the first metal layer; the isolation region between the first type metal layers is filled with the protection layer;

the isolation areas between the second-type metal layers are filled with the dielectric layers;

the first type metal layer and the second type metal layer in the edge area are separated by the protective layer and the dielectric layer respectively.

9. The semiconductor package according to claim 3, wherein the metal pattern in the edge region has at least an arc-shaped edge; the metal patterns of the different layers are the same or different.

10. The semiconductor package structure according to any one of claims 1 to 9, further comprising: at least one chip;

the at least one chip is attached to the central area and is electrically connected with the substrate.