CN116666230A - Fan-out type chip packaging method and packaging device - Google Patents

Fan-out type chip packaging method and packaging device Download PDF

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Publication number
CN116666230A
CN116666230A CN202310611071.4A CN202310611071A CN116666230A CN 116666230 A CN116666230 A CN 116666230A CN 202310611071 A CN202310611071 A CN 202310611071A CN 116666230 A CN116666230 A CN 116666230A
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Prior art keywords
chip
passivation layer
conductive
carrier plate
layer
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Inventor
刘在福
郭瑞亮
焦洁
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Suzhou Tongfu Chaowei Semiconductor Co ltd
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Suzhou Tongfu Chaowei Semiconductor Co ltd
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Priority to CN202310611071.4A priority Critical patent/CN116666230A/en
Publication of CN116666230A publication Critical patent/CN116666230A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The embodiment of the disclosure provides a fan-out chip packaging method and a packaging device, wherein the packaging method comprises the following steps: providing a carrier plate, a first chip and a second chip respectively, wherein the first chip is provided with a conductive connecting structure penetrating through the thickness of the first chip; fixing the first surface of the first chip on the carrier plate; forming a passivation layer on the surface of the carrier plate facing the first chip, wherein the passivation layer wraps the first chip; forming a conductive post on the passivation layer through its thickness; interconnecting the second chip to the second surface of the first chip and to one side of the passivation layer facing away from the carrier plate; and removing the carrier plate and forming a signal output layer on the first surface of the first chip and the surface of the passivation layer, which is away from the second chip. The packaging method simplifies the packaging process flow, shortens the process period, saves the process cost and improves the yield of chip packaging; the warpage problem of the first chip is improved, the first chip is prevented from being broken due to the warpage of the chip, the damage to the first chip, which is derived in the packaging process, is reduced, and the quality of chip packaging is improved.

Description

Fan-out type chip packaging method and packaging device
Technical Field
The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out chip packaging method and a packaging device.
Background
In the current fan-out chip packaging process, a packaging device is single, and the application of the fan-out chip packaging process has certain limitation. In the existing fan-out chip packaging process, after a wafer is cut, a chip is connected to a carrier plate or a plastic package frame, and then the chip is subjected to a plastic package process. Thus, the time from the plastic packaging process to the ball mounting process is longer, the packaging process period is longer, and the yield of the chip packaging device is reduced. Meanwhile, in the existing fan-out type chip packaging technology, the chip is fixed on the carrier plate or on the plastic packaging frame through the plastic packaging technology, and the chip can warp or crack under the action of high temperature, so that the quality of a chip packaging device is reduced. In addition, the ball planting process is performed after plastic packaging, and high process cost is required.
In view of the foregoing, it is desirable to provide a fan-out chip packaging method and a packaging device that are reasonably designed and that can effectively solve the foregoing problems.
Disclosure of Invention
The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a fan-out type packaging method and a packaging device.
An aspect of an embodiment of the present disclosure provides a fan-out chip packaging method, the method comprising
The packaging method comprises the following steps:
providing a carrier plate, a first chip and a second chip respectively, wherein the first chip is provided with a conductive connection structure penetrating through the thickness of the first chip;
fixing the first surface of the first chip on the carrier plate;
forming a passivation layer on the surface of the carrier plate facing the first chip, wherein the passivation layer wraps the first chip;
forming a conductive post through the thickness of the passivation layer;
interconnecting the second chip to the second surface of the first chip and the surface of the passivation layer facing away from the carrier plate;
and removing the carrier plate, and forming a signal output layer on the first surface of the first chip and the surface of the passivation layer, which is away from the second chip.
Optionally, before the interconnecting the second chip to the first surface of the first chip and the side of the passivation layer facing away from the carrier, the method further includes:
forming a rewiring layer at a position, which is away from the surface of the carrier plate, of the passivation layer and corresponds to the conductive connection structure and the conductive column; wherein, the liquid crystal display device comprises a liquid crystal display device,
the rewiring layer is electrically connected with the conductive connection structure and the conductive column respectively.
Optionally, the interconnecting the second chip to the first surface of the first chip and a side of the passivation layer facing away from the carrier plate includes:
forming a conductive bump on the rewiring layer, wherein the conductive bump is electrically connected with the rewiring layer;
and flip-chip mounting the second chip on the rewiring layer through the conductive bump.
Optionally, the forming a conductive pillar on the passivation layer through its thickness includes:
patterning the passivation layer to form a first opening on the passivation layer on the second surface of the first chip and a second opening on the passivation layer on the carrier plate, respectively;
and filling conductive materials in the first opening and the second opening respectively to form a first conductive column and a second conductive column.
Optionally, a passivation layer is formed on a surface of the carrier facing the first chip, and the passivation layer wraps the first chip, including:
and coating passivation materials on the second surface of the first chip and the surface of the carrier plate facing the first chip by adopting a coating process.
Optionally, the removing the carrier, and forming a signal output layer on the second surface of the first chip and the surface of the passivation layer facing away from the second chip, includes:
removing the carrier plate, and thinning the first surface of the first chip to expose the conductive connection structure of the first chip;
forming a plurality of bonding pads on the first surface of the thinned first chip and the surface of the passivation layer, which faces away from the second chip; wherein, the liquid crystal display device comprises a liquid crystal display device,
the plurality of bonding pads are respectively and electrically connected with the conductive connecting structure and the conductive column;
and implanting balls on the bonding pads to form a plurality of solder balls.
Another aspect of an embodiment of the present disclosure provides a fan-out chip package device, the package device comprising:
the first chip is provided with a conductive connection structure penetrating through the thickness of the first chip;
a passivation layer surrounding the first chip; wherein, the passivation layer is provided with a through hole penetrating through the thickness direction of the passivation layer;
the conductive column is arranged on the through hole;
the second chip is arranged on the surface of the first chip and the passivation layer;
and the signal output layer is arranged on the surfaces of the first chip and the passivation layer, which are away from the second chip.
Optionally, a rewiring layer is further included;
the rewiring layer is arranged on one side of the passivation layer, which faces the second chip; wherein, the liquid crystal display device comprises a liquid crystal display device,
the rewiring layer is electrically connected with the conductive connection structure and the conductive column respectively.
Optionally, the device further comprises a conductive bump;
the conductive bump is clamped between the second chip and the rewiring layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the conductive bump is electrically connected with the rewiring layer.
Optionally, a first through hole is formed on the passivation layer on the first chip, and a second through hole is formed on the passivation layer on the outer side of the first chip;
the conductive posts include a first conductive post and a second conductive post; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first conductive column is arranged in the first through hole, and the second conductive column is arranged in the second through hole.
According to the fan-out type chip packaging method and the fan-out type chip packaging device, after the first surface of the first chip is fixed on the carrier plate, the passivation layer is formed on the carrier plate and the second surface of the first chip, patterning is conducted on the passivation layer, the first chip is placed on the carrier plate after being cut, and a plastic packaging process is conducted, so that the process flow is simplified, the process period is shortened, the process cost is saved, and the yield of chip packaging is improved; in addition, a high-temperature compression molding plastic packaging process is not needed, the passivation layer is adopted to protect the first chip, the problem of warping of the first chip caused by high temperature is solved, the first chip is prevented from being cracked caused by warping of the chip, damage to the first chip caused by the damage to the first chip in the packaging process is reduced, and the quality of chip packaging is improved.
According to the packaging device disclosed by the embodiment of the disclosure, the conductive connection structure penetrating through the thickness of the first chip is arranged on the first chip, so that on one hand, input and output wiring can be formed at the top and the bottom of the first chip, the wiring flow is simplified, on the other hand, multiple chips or modules can be stacked on the two sides of the first chip through the conductive connection structure, and the packaging size is further reduced by adopting the short-distance connection mode of the conductive connection structure.
The packaging method of the embodiment of the disclosure can complete the whole packaging flow in the tin bump process, does not need other packaging processes and packaging equipment, saves the cost and shortens the process cycle.
According to the packaging method, the thickness of the first chip is adjustable through thinning the first chip, and the packaging height is reduced.
The whole packaging device formed by the packaging method can be used as a through silicon via chip to realize the functions, and the packaging device can be connected with various chip stacking structures through a conductive connecting structure and a conductive column to realize more complex functions and wider application.
Drawings
FIG. 1 is a flow chart of a fan-out chip packaging method according to one embodiment of the present disclosure;
fig. 2 to 10 are schematic views of a packaging process of a fan-out chip packaging method according to another embodiment of the disclosure;
fig. 11 is a schematic structural diagram of a fan-out chip package device according to another embodiment of the disclosure.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.
As shown in fig. 1, an aspect of an embodiment of the present disclosure provides a fan-out type packaging method S100, where the packaging method S100 includes:
s110, providing a carrier plate, a first chip and a second chip respectively, wherein the first chip is provided with a plurality of conductive connection structures penetrating through the thickness of the first chip.
Specifically, as shown in fig. 2 and 8, a carrier 110, a first chip 120 and a second chip 130 are provided, respectively, wherein the first chip 120 is provided with a conductive connection structure 140 penetrating through the thickness thereof. Wherein, the first chip 120 and the second chip 130 are both functional chips.
It should be noted that, the carrier plate 110 may be a silicon wafer or a glass sheet, and may be selected according to actual needs, which is not limited in this embodiment.
It should be further noted that, in this embodiment, the conductive connection structure 140 adopts a through silicon via, and by providing the through silicon via on the first chip 120, on one hand, input/output wirings can be formed on the top and bottom of the first chip 120, so as to simplify the wiring flow; on the other hand, a plurality of chips or modules may be stacked on both sides of the first chip 120 through the conductive connection structure 140, further reducing the package size.
It should be noted that, as shown in fig. 2, in the present embodiment, the plurality of conductive connection structures 140 are equally spaced apart from the first chip 120, and of course, the plurality of conductive connection structures 140 may also be non-equally spaced apart from the first chip 120, which may be selected according to actual needs, and the present embodiment is not limited specifically.
S120, fixing the first surface of the first chip on the carrier plate.
Specifically, as shown in fig. 2, the first surface 121 of the first chip 120 is fixed to the carrier 110. It should be understood that the first surface of the first chip 120 may be the front surface of the first chip 120 or the back surface of the first chip 120, which may be specifically selected according to practical needs. Hereinafter, the first surface 121 of the first chip 120 is referred to as a back surface of the first chip 120, and the second surface 122 of the first chip 120 is referred to as a front surface of the first chip 120. That is, in the present embodiment, the back surface of the first chip 120 is fixed to the carrier 110. As an example, as shown in fig. 2, the back surface of the first chip 120 may be adhered to the carrier plate 110 through an adhesive layer 150.
S130, forming a passivation layer on the surface, facing the first chip, of the carrier plate, wherein the passivation layer wraps the first chip.
As shown in fig. 3, a passivation layer 160 is formed on the surface of the carrier 110 facing the first chip 120, and the passivation layer 160 wraps the first chip 120 to protect the first chip 120.
Specifically, as shown in fig. 3, a passivation material is applied to the front surface of the first chip 120 and the surface of the carrier plate 110 facing the first chip 120 by a coating process, that is, the passivation material is applied to the top surface of the first chip 120 and the top surface of the carrier plate 110, so as to form a passivation layer 160 as shown in fig. 3, and it is easy to understand that the surface of the passivation layer 160 is higher than the top surface of the first chip 120, so as to protect the first chip 120.
In this embodiment, the material of the passivation layer 160 may be an insulating film, a passivation material, or a repassivation material, such as silicon dioxide or silicon nitride, which may be any material that may perform passivation, and the embodiment is not particularly limited and may be selected according to actual needs.
In the embodiment of the disclosure, after the first surface of the first chip is fixed on the carrier plate, a passivation layer is formed on the carrier plate and the second surface of the first chip, patterning is carried out on the passivation layer, the process of placing the first chip on the carrier plate for plastic packaging after cutting is skipped, the process flow is simplified, the process period is shortened, the process cost is saved, and the yield of chip packaging is improved; in addition, a high-temperature compression molding plastic packaging process is not needed, the passivation layer is adopted to protect the first chip, the problem of warping of the first chip caused by high temperature is solved, the first chip is prevented from being cracked caused by warping of the chip, damage to the first chip caused by the damage to the first chip in the packaging process is reduced, and the quality of chip packaging is improved.
And S140, forming a conductive column penetrating through the thickness of the passivation layer.
As shown in fig. 4 and 5, conductive pillars are formed throughout the thickness of passivation layer 160.
Specifically, in order to form the conductive pillars as shown on the passivation layer 160, the following patterning process may be employed.
First, a photoresist layer (not shown) is formed on the surface of the passivation layer 160, and a reticle (not shown) is placed on the photoresist layer.
Next, the photoresist layer is exposed and developed using the reticle as a mask to form an opening (not shown) in the photoresist layer.
Then, as shown in fig. 4, the passivation layer 160 is etched along the openings by an etching process, and a first opening 161 is formed on the passivation layer 160 on the front surface of the first chip 120 and a second opening 162 is formed on the passivation layer 160 on the surface of the carrier plate 110, respectively. That is, the first openings 161 are formed on the passivation layer 160 on the top surface of the first chip 120, and the second openings 162 are formed on the passivation layer 160 on the top surface of the carrier 110, respectively.
Then, as shown in fig. 5, a deposition process, such as electroplating or sputtering, is used to fill the first opening 161 and the second opening 162 with a conductive material, respectively, to form a first conductive pillar 163 and a second conductive pillar 164. Wherein, the first conductive posts 163 are in one-to-one correspondence with the conductive connection structures 140. The conductive material can be metallic copper or other conductive materials, and can be selected according to actual needs.
Finally, the photoresist layer is removed by adopting a plasma dry process and the like.
It should be noted that, in addition to the above patterning process for forming the conductive pillars, a person skilled in the art may select other patterning modes according to actual needs, which is not limited in this embodiment.
As shown in fig. 5, the first conductive pillars 163 and the second conductive pillars 164 are equally spaced apart from the passivation layer 160. Of course, the first conductive pillars 163 and the second conductive pillars 164 may be distributed in the passivation layer 160 at unequal intervals, and may be selected according to actual needs, which is not limited in this embodiment.
In the embodiment, the first conductive column can lead out signals of the chip on one hand, and can realize vertical electrical interconnection on the other hand, so that the packaging volume is reduced; the second conductive pillars can realize vertical electrical interconnection, and reduce packaging volume.
And S150, interconnecting the second chip to the second surface of the first chip and the surface of the passivation layer, which faces away from the carrier plate.
As shown in fig. 6 to 8, the second chip 130 is interconnected to the front surface of the first chip 120 and the surface of the passivation layer 160 facing away from the carrier plate 110.
It should be noted that, as shown in fig. 8, in the present embodiment, the size of the second chip 130 is larger than that of the first chip 120.
Illustratively, prior to interconnecting the second chip to the first surface of the first chip and the surface of the passivation layer facing away from the carrier, the method further comprises:
as shown in fig. 6, a redistribution layer 170 is formed on the surface of the passivation layer 160 facing away from the carrier 110 and corresponding to the conductive connection structure 140 and the conductive pillars. Wherein the redistribution layer 170 is electrically connected to the conductive connection structure 140 and the conductive pillars, respectively.
In order to form the re-wiring layer 170 as shown in fig. 6 on the surface of the passivation layer 160 facing away from the carrier plate 110, the following patterning process may be used.
First, a metal layer is formed on the surface of the passivation layer 160 facing away from the carrier plate 110 through a sputtering or electroplating process.
Next, an etching process is used to pattern the metal layer, and a redistribution layer 170 is formed on the passivation layer 160 at a position corresponding to the conductive connection structure 140 and the conductive pillar on the surface facing away from the carrier 110.
Note that, the redistribution layer 170 may be made of a metallic copper material, or may be made of another metallic material, which is not particularly limited in this embodiment and may be selected according to actual needs.
It should be further noted that, in addition to the formation of the redistribution layer 170 by using the patterning process, those skilled in the art may select other patterning methods according to actual needs, which is not limited in this embodiment.
In this embodiment, the redistribution layer 170 may enable signal extraction from the first chip 120 while also increasing the interconnect density of the first chip 120.
Illustratively, interconnecting the second chip to the first surface of the first chip and a side of the passivation layer facing away from the carrier plate specifically includes:
first, as shown in fig. 7, a conductive bump 180 is formed on the re-wiring layer 170, wherein the conductive bump 180 is electrically connected to the re-wiring layer 170.
Note that, the conductive bump 180 may be a tin bump, or may be a conductive bump made of other materials, which is not particularly limited in this embodiment.
Next, as shown in fig. 8, the second chip 130 is flip-chip mounted on the redistribution layer 170 through the conductive bumps 180 under high temperature and high pressure conditions.
Note that, the conductive bump 180 may be formed on the side of the second chip 130 facing the first chip 120, and the second chip 130 is flip-chip mounted on the redistribution layer 170 through the conductive bump 170, which may be selected according to actual needs, and the embodiment is not limited specifically.
It should be further noted that, the second chip 130 may be interconnected to the front surface of the first chip 120 in other manners besides the flip-chip manner described in the present embodiment, and the present embodiment is not limited thereto.
S160, removing the carrier plate, and forming a signal output layer on the first surface of the first chip and the surface of the passivation layer, which is away from the second chip.
Exemplary, removing the carrier, and forming a signal output layer on the first surface of the first chip and the surface of the passivation layer facing away from the second chip, specifically including:
first, as shown in fig. 9, the carrier 110 is removed, and the first surface of the first chip 120 is thinned to expose the conductive connection structure 140 of the first chip 120.
It should be noted that, the carrier plate 110 may be removed by using a grinding process, so that the first chip 120 and the passivation layer 160 are separated from the carrier plate 110, and the separation method may be a thermal separation method, a laser separation method, an ultraviolet separation method, a mechanical separation method, or the like.
Next, as shown in fig. 9, after the carrier 110 is removed, the adhesive layer 150 is removed by using a grinding process, and the back surface of the first chip 120 is thinned to expose the conductive connection structure 140 of the first chip 120.
Again, as shown in fig. 10, a plurality of pads 191 are formed on the back surface of the thinned first chip 120 and the surface of the passivation layer 160 facing away from the second chip 130. Wherein the plurality of pads 191 are electrically connected to the conductive connection structure 140 and the conductive pillars, respectively.
Note that, the material of the pad 191 may be metallic copper, or may be other materials, and the embodiment is not particularly limited.
Finally, as shown in fig. 10, balls are implanted on the pads 191 using an electroplating or sputtering process, and a plurality of solder balls 192 are formed on the pads 191 to form a signal output layer. The entire packaged device is electrically connected to the outside world through a plurality of solder balls 192.
Note that, the material of the solder ball 192 may be tin metal, or may be other materials, and the embodiment is not particularly limited.
It should be further noted that, the signal output layer may take other forms besides the plurality of solder balls described in this embodiment, and this embodiment is not limited specifically.
According to the packaging method, the thickness of the first chip is adjustable through thinning the first chip, so that the packaging height is reduced, and the packaging device is thinned.
It should be noted that, the whole packaging device 100 formed by the packaging method S100 may be used as a through silicon via chip to realize the functions thereof, and the packaging device 100 may be connected to a plurality of chip stacking structures through a conductive connection structure and a conductive column to realize more complex functions and wider application. For example, a plurality of other chip modules may be stacked on the package device 100, and through-silicon vias or conductive pillars are formed on the other chip modules, and the other chip modules are electrically connected to the conductive connection structures and the conductive pillars of the package device 100 through the through-silicon vias or the conductive pillars.
As shown in fig. 11, another aspect of the disclosed embodiments provides a fan-out chip package device 100, the package device 100 comprising:
the first chip 120, wherein the first chip 120 is provided with a conductive connection structure 140 penetrating its thickness. In this embodiment, the conductive connection structure 140 is a through silicon via, and the input/output wiring can be formed on the top and bottom of the first chip 120 by providing the through silicon via on the first chip 120, so as to simplify the wiring flow.
The passivation layer 160, the passivation layer 160 wraps the first chip 120, and protects the first chip 120. Wherein the passivation layer 160 is provided with a through hole (not shown) penetrating through its thickness direction.
The conductive column is arranged in the through hole. The material of the conductive post may be metallic copper, or may be other conductive materials, which is not specifically limited in this embodiment. The conductive posts can realize vertical electrical interconnection, reduce the packaging height and reduce the packaging volume.
The second chip 130 is disposed on the surface of the first chip 120 and the passivation layer 160. The second chip 130 may be disposed on the front side of the first chip 120 or on the back side of the first chip 120, and may be selected according to actual needs, and in this embodiment, the second chip 130 is disposed on the front side of the first chip 120 for illustration.
The signal output layer is disposed on the surface of the first chip 120 and the passivation layer 160 facing away from the second chip 130. That is, in the present embodiment, the signal output layer is disposed on the back surface of the first chip 120.
Illustratively, as shown in fig. 11, the packaged device 100 further includes a redistribution layer 170, the redistribution layer 170 being disposed on a side of the passivation layer 160 facing the second chip 130. Wherein the redistribution layer 170 is electrically connected to the conductive connection structure 140 and the conductive pillars, respectively.
Note that, the redistribution layer 170 may be made of a metallic copper material, or may be made of another metallic material, which is not particularly limited in this embodiment and may be selected according to actual needs.
In this embodiment, the redistribution layer 170 may enable signal extraction from the first chip 120 while also increasing the interconnect density of the first chip 120.
Illustratively, as shown in fig. 11, the packaged device 100 further includes conductive bumps 180, the conductive bumps 180 being sandwiched between the second chip 130 and the redistribution layer 170. Wherein the conductive bump 180 is electrically connected to the redistribution layer 170. That is, the second chip 130 is interconnected to the rewiring layer 170 on the first chip 120 by the conductive bumps 180.
Note that, the conductive bump 180 may be a tin bump, or may be a conductive bump made of other materials, which is not particularly limited in this embodiment.
Illustratively, a first via is disposed on the passivation layer 160 on the first chip 120, and a second via is disposed on the passivation layer 160 on the outside of the first chip 120.
The conductive posts include a first conductive post 163 and a second conductive post 164, wherein the first conductive post 163 is disposed in the first through hole, and the second conductive post 164 is disposed in the second through hole.
In this embodiment, the first conductive columns 163 may lead out signals of the chip on one hand, and may realize vertical electrical interconnection on the other hand, so as to reduce the package volume; the second conductive pillars 164 may enable vertical electrical interconnection, reducing package volume.
Illustratively, as shown in fig. 11, the signal output layer includes a plurality of pads 191 and a plurality of solder balls 192 corresponding to the pads 191. The entire packaged device 100 is electrically connected to the outside world through a plurality of solder balls 192.
A plurality of pads 191 are disposed on the back side of the first chip 120 and the surface of the passivation layer 160 facing away from the second chip 130. Wherein the plurality of pads 191 are electrically connected to the conductive connection structure 140 and the conductive pillars, respectively.
A plurality of solder balls 192 are disposed on the pads 191 corresponding thereto.
Note that, the material of the pad 191 may be copper metal, or may be another metal material, and the embodiment is not particularly limited. The material of the solder ball 192 may be metallic tin, or other materials, and the embodiment is not particularly limited.
It should be further noted that, the signal output layer may take other forms besides the plurality of solder balls described in this embodiment, and this embodiment is not limited specifically.
It should be noted that, the whole packaging device 100 formed by the packaging method S100 may be used as a through silicon via chip to realize the functions thereof, and the packaging device 100 may be connected to a plurality of chip stacking structures through a conductive connection structure and a conductive column to realize more complex functions and wider application. For example, a plurality of other chip modules may be stacked on the package device 100, and through-silicon vias or conductive pillars are formed on the other chip modules, and the other chip modules are electrically connected to the conductive connection structures and the conductive pillars of the package device 100 through the through-silicon vias or the conductive pillars.
According to the fan-out type chip packaging device, the passivation layer is used for wrapping the first chip and wiring the passivation layer in a patterning way, and the passivation layer is used for replacing the plastic sealing layer, so that the problem of warping of the first chip in the plastic sealing process is solved, chip cracking caused by the warping of the first chip is prevented, damage to the chip caused by the warping of the first chip in the packaging process is reduced, and the quality of chip packaging is improved; the passivation body is provided with the conductive column penetrating through the thickness of the passivation body, and the packaging volume is reduced by adopting a short-distance connection mode; the packaging device can be connected with various chip stacking structures through the conductive posts, so that more complex functions and wider application are realized.
According to the packaging device disclosed by the embodiment of the disclosure, the conductive connection structure penetrating through the thickness of the first chip is arranged on the first chip, the input/output wiring can be formed at the top and the bottom of the first chip, the wiring flow is simplified, and the packaging volume is reduced by adopting the short-distance connection mode of the conductive connection structure. Multiple chips or modules can be stacked on both sides of the first chip, and the packaging size is further reduced.
The whole packaging device can be used as a through silicon via chip to realize the functions, and the packaging device can be connected with various chip stacking structures through the conductive connecting structure and the conductive column to realize more complex functions and wider application.
It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.

Claims (10)

1. A fan-out chip packaging method, the packaging method comprising:
providing a carrier plate, a first chip and a second chip respectively, wherein the first chip is provided with a conductive connection structure penetrating through the thickness of the first chip;
fixing the first surface of the first chip on the carrier plate;
forming a passivation layer on the surface of the carrier plate facing the first chip, wherein the passivation layer wraps the first chip;
forming a conductive post through the thickness of the passivation layer;
interconnecting the second chip to the second surface of the first chip and the surface of the passivation layer facing away from the carrier plate;
and removing the carrier plate, and forming a signal output layer on the first surface of the first chip and the surface of the passivation layer, which is away from the second chip.
2. The method of claim 1, wherein the interconnecting the second chip to the first surface of the first chip and the passivation layer is on a side facing away from the carrier plate is preceded by:
forming a rewiring layer at a position, which is away from the surface of the carrier plate, of the passivation layer and corresponds to the conductive connection structure and the conductive column; wherein, the liquid crystal display device comprises a liquid crystal display device,
the rewiring layer is electrically connected with the conductive connection structure and the conductive column respectively.
3. The method of claim 2, wherein interconnecting the second chip to the first surface of the first chip and the side of the passivation layer facing away from the carrier plate comprises:
forming a conductive bump on the rewiring layer, wherein the conductive bump is electrically connected with the rewiring layer;
and flip-chip mounting the second chip on the rewiring layer through the conductive bump.
4. A method according to any one of claims 1 to 3, wherein said forming a conductive pillar over the passivation layer through its thickness comprises:
patterning the passivation layer to form a first opening on the passivation layer on the second surface of the first chip and a second opening on the passivation layer on the carrier plate, respectively;
and filling conductive materials in the first opening and the second opening respectively to form a first conductive column and a second conductive column.
5. A method according to any one of claims 1 to 3, wherein forming a passivation layer on a surface of the carrier facing the first chip, the passivation layer wrapping the first chip, comprises:
and coating passivation materials on the second surface of the first chip and the surface of the carrier plate facing the first chip by adopting a coating process.
6. A method according to any one of claims 1 to 3, wherein said removing the carrier plate and forming a signal output layer on the second surface of the first chip and the surface of the passivation layer facing away from the second chip comprises:
removing the carrier plate, and thinning the first surface of the first chip to expose the conductive connection structure of the first chip;
forming a plurality of bonding pads on the first surface of the thinned first chip and the surface of the passivation layer, which faces away from the second chip; wherein, the liquid crystal display device comprises a liquid crystal display device,
the plurality of bonding pads are respectively and electrically connected with the conductive connecting structure and the conductive column;
and implanting balls on the bonding pads to form a plurality of solder balls.
7. A fan-out chip package device, the package device comprising:
the first chip is provided with a conductive connection structure penetrating through the thickness of the first chip;
a passivation layer surrounding the first chip; wherein, the passivation layer is provided with a through hole penetrating through the thickness direction of the passivation layer;
the conductive column is arranged on the through hole;
the second chip is arranged on the surface of the first chip and the passivation layer;
and the signal output layer is arranged on the surfaces of the first chip and the passivation layer, which are away from the second chip.
8. The packaged device of claim 7, further comprising a rewiring layer;
the rewiring layer is arranged on one side of the passivation layer, which faces the second chip; wherein, the liquid crystal display device comprises a liquid crystal display device,
the rewiring layer is electrically connected with the conductive connection structure and the conductive column respectively.
9. The packaged device of claim 8, further comprising a conductive bump;
the conductive bump is clamped between the second chip and the rewiring layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the conductive bump is electrically connected with the rewiring layer.
10. The packaged device of any one of claims 7 to 9 wherein a first via is provided on the passivation layer on the first chip and a second via is provided on the passivation layer on the outside of the first chip;
the conductive posts include a first conductive post and a second conductive post; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first conductive column is arranged in the first through hole, and the second conductive column is arranged in the second through hole.
CN202310611071.4A 2023-05-29 2023-05-29 Fan-out type chip packaging method and packaging device Pending CN116666230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310611071.4A CN116666230A (en) 2023-05-29 2023-05-29 Fan-out type chip packaging method and packaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310611071.4A CN116666230A (en) 2023-05-29 2023-05-29 Fan-out type chip packaging method and packaging device

Publications (1)

Publication Number Publication Date
CN116666230A true CN116666230A (en) 2023-08-29

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Application Number Title Priority Date Filing Date
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Country Link
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