CN116663482B - Layout method and system of CNFET (carbon field effect transistor) circuit - Google Patents
Layout method and system of CNFET (carbon field effect transistor) circuit Download PDFInfo
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Abstract
The invention discloses a layout method and a layout system of a CNFET circuit, and belongs to the technical field of semiconductor devices. The invention adopts a statistical static time sequence analysis mode to select the key segment group, then carries out the determination of the optimal position of the key gate of each key segment based on a segment statistical delay model which can more accurately evaluate the delay of the circuit and more effectively optimize the time sequence yield of the circuit, and completes the layout of the CNFET circuit.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and in particular, to a method and a system for layout of CNFET circuits.
Background
Among the many new semiconductor devices, carbon Nanotube Field Effect Transistors (CNFETs) are receiving attention for their excellent electrical properties. Compared to conventional MOSFET devices, CNFET devices have higher carrier mobility and smaller leakage current, and thus can achieve higher performance and lower power consumption.
However, limited by CNT (Carbon Nanotube) growth processes, the development of large-scale CNFET circuits presents challenges including the presence of metallic CNTs in the CNFET, misalignment of CNT arrays, and variations in CNT density. Wherein CNT density variation is increasingly becoming a major factor affecting CNFET circuit performance and stability.
In the conventional integrated circuit design process, layout is one of the important links in EDA (Electronic Design Automation, semiconductor device) physical design, and its function is to determine the positions and interconnection manners of circuit elements so as to achieve the functional requirements and performance requirements of the circuit. Conventional layout methods are typically based on silicon-based circuit designs, and CNT density variations make it difficult for conventional layout methods to accommodate carbon-based circuit layouts. Therefore, in order to accommodate the effects of the specific nature of CNFETs and CNT density variations, new layout methods need to be developed to address these issues.
The layout technology of conventional silicon-based integrated circuits is well established, and can be broadly divided into two categories according to their algorithmic optimization strategies: 1. starting from the existing initial layout result, according to the principle of local preference, a certain unit subset is selected to adjust the position and the direction in a local range so as to form a new layout. The search process is repeated until no more optimal layout is found. For example, the "pair swap and minimum cut" algorithm belongs to this class of methods. 2. Based on linear programming or nonlinear programming, taking the position of the unit module as an independent variable, constructing a linear or nonlinear equation set according to a certain optimization target, and solving iteratively to finally obtain a layout scheme. For example, a "force vector layout algorithm" belongs to this class of methods. 3. In order to solve the problem of the calculated amount explosion caused by the increase of the circuit layout scale, a plurality of heuristic algorithms, such as simulated annealing, genetic algorithm, evolutionary algorithm, neural network, ant colony algorithm and the like, are provided, and the heuristic algorithm based on random optimization is widely researched in the layout and obtains a good layout result.
At present, some layout methods for CNFET integrated circuits have been proposed, and most of them pay more attention to the timing yield of the circuits, and how to reduce the time required for circuit layout while ensuring the timing yield is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a CNFET circuit layout method and system, so as to reduce the time required by circuit layout while ensuring the time sequence yield.
In order to achieve the above object, the present invention provides the following solutions:
the invention provides a layout method of a CNFET circuit, which comprises the following steps:
constructing a segment statistical delay model of the CNFET circuit;
dispersing standard units in the CNFET circuit by adopting a time sequence driving global layout algorithm;
selecting a key segment group from a plurality of standard units by adopting a statistical static time sequence analysis mode;
determining the optimal position of a key gate of each key segment in the key segment group and the segment delay metric value of the current iteration by adopting a mode of optimizing the statistical delay based on the segment statistical delay model;
and returning to the step of selecting the key segment group from the plurality of standard units by adopting a statistical static time sequence analysis mode, and performing the next iteration until the absolute value of the difference between the segment delay metric value of the current iteration and the segment delay metric value of the previous iteration is smaller than a first preset threshold value.
Optionally, the segment statistical delay model is:
；
wherein,for the segment delay metric, +.>For the mean term coefficient, ++>Is the standard deviation term coefficient->Delay for all gate trees in a segment, +.>And->Function of averaging and function of standard deviation, respectively, +.>Delay for the ith gate tree, n is the number of gate trees in the segment, +.>Vector consisting of delays for each gate tree in a segment, < >>For the moment of correlation of CNFET circuitsAn array.
Optionally, determining an optimal position of a key gate of each key segment in the key segment group and a segment delay metric value of the current iteration by adopting a mode of optimizing statistical delay based on the segment statistical delay model specifically includes:
initializing adjacent subareas of an ith key gate;
calculating a section delay metric value of the key section when an ith key gate in the key section moves to the center of each adjacent subarea respectively based on a section statistical delay model, and obtaining a section delay metric value corresponding to each adjacent subarea;
judging whether the minimum section delay metric value in the section delay metric values corresponding to each adjacent subarea is smaller than the optimal section statistical delay value or not, and obtaining a judging result;
if the judgment result shows that the key gate in the key section is moved to the center of the adjacent subarea corresponding to the minimum section delay metric value, updating the optimal section statistical delay value to the minimum section delay metric value, returning to the step of calculating the section delay metric value of the key section when the i key gate in the key section is respectively moved to the center of each adjacent subarea based on the section statistical delay model, and obtaining the section delay metric value corresponding to each adjacent subarea;
if the judging result shows that the size of each adjacent subarea is not equal to the first preset threshold, reducing the size of each adjacent subarea, returning to a step of calculating a section delay metric value of the key section when the ith key gate in the key section moves to the center of each adjacent subarea respectively based on the section statistical delay model, obtaining a section delay metric value corresponding to each adjacent subarea until the size of each adjacent subarea is smaller than the second preset threshold, and outputting the current position of the ith key gate as the optimal position of the ith key gate;
and (3) increasing the value of i by 1, returning to the step of initializing the adjacent subareas of the ith key gate until the optimal positions of all the key gates in the key segment are output, and calculating the segment delay metric value when each key gate in the key segment is at the optimal position of the key gate as the segment delay metric value of the current iteration.
A layout system for a CNFET circuit, the system comprising:
the segment statistical delay model building module is used for building a segment statistical delay model of the CNFET circuit;
the dispersion module is used for dispersing standard units in the CNFET circuit by adopting a time sequence driving global layout algorithm;
the key segment group selecting module is used for selecting a key segment group from a plurality of standard units by adopting a statistical static time sequence analysis mode;
the optimal position determining module is used for determining the optimal position of the key gate of each key segment in the key segment group and the segment delay metric value of the current iteration by adopting a mode of optimizing the statistical delay based on the segment statistical delay model;
and the return calling module is used for returning to the key segment group selection module and carrying out the next iteration until the absolute value of the difference between the segment delay metric value of the current iteration and the segment delay metric value of the previous iteration is smaller than a first preset threshold value.
Optionally, the segment statistical delay model is:
；
wherein,for the segment delay metric, +.>For the mean term coefficient, ++>Is the standard deviation term coefficient->Delay for all gate trees in a segment, +.>And->Function of averaging and function of standard deviation, respectively, +.>Delay for the ith gate tree, n is the number of gate trees in the segment, +.>Vector consisting of delays for each gate tree in a segment, < >>Is a correlation matrix of CNFET circuits.
Optionally, the optimal position determining module specifically includes:
an initializing unit, which is used for initializing the adjacent subareas of the ith key gate;
the segment delay metric value calculation unit is used for calculating the segment delay metric value of the key segment when the ith key gate in the key segment moves to the center of each adjacent subarea respectively based on the segment statistical delay model, and obtaining the segment delay metric value corresponding to each adjacent subarea;
the judging unit is used for judging whether the minimum section delay metric value in the section delay metric values corresponding to each adjacent subarea is smaller than the optimal section statistical delay value or not, and obtaining a judging result;
the key gate moving unit is used for moving the ith key gate in the key section to the center of the adjacent subarea corresponding to the minimum section delay metric value if the judging result shows yes, updating the optimal section statistical delay value to the minimum section delay metric value and returning to the calling section delay metric value calculating unit;
the adjacent subarea size updating unit is used for reducing the size of each adjacent subarea if the judging result indicates no, returning to the calling section delay metric value calculating unit until the size of the adjacent subarea is smaller than a second preset threshold value, and outputting the current position of the ith key door as the optimal position of the ith key door;
and the return unit is used for increasing the value of i by 1, returning to the call initialization unit until the optimal positions of all the key gates in the key segment are output, and calculating the segment delay metric value when each key gate in the key segment is positioned at the optimal position of the key gate as the segment delay metric value of the current iteration.
An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method described above when executing the computer program.
A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method described above.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the embodiment of the invention provides a layout method and a system of a CNFET circuit, wherein the method comprises the following steps: constructing a segment statistical delay model of the CNFET circuit; dispersing standard units in the CNFET circuit by adopting a time sequence driving global layout algorithm; selecting a key segment group from a plurality of standard units by adopting a statistical static time sequence analysis mode; determining the optimal position of a key gate of each key segment in the key segment group and the segment delay metric value of the current iteration by adopting a mode of optimizing the statistical delay based on the segment statistical delay model; and returning to the step of selecting the key segment group from the plurality of standard units by adopting a statistical static time sequence analysis mode, and performing the next iteration until the absolute value of the difference between the segment delay metric value of the current iteration and the segment delay metric value of the previous iteration is smaller than a first preset threshold value. The invention adopts a statistical static time sequence analysis mode to select the key segment group, then carries out the determination of the optimal position of the key gate of each key segment based on a segment statistical delay model which can more accurately evaluate the delay of the circuit and more effectively optimize the time sequence yield of the circuit, and completes the layout of the CNFET circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a layout method of a CNFET circuit in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a CNFET circuit layout method and system, so as to reduce the time required by circuit layout while ensuring the time sequence yield.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Example 1
The embodiment of the invention provides a layout method of a CNFET circuit, which is mainly divided into two steps. First, a segment statistical delay model of the CNFET circuit is built, which is related to the circuit timing yield. Secondly, according to the segment statistical delay model obtained in the first step, position adjustment is performed on key gates in the middle segment of the CNFET circuit (statistical analysis is not performed on each segment when the invention is implemented, but key segment groups are selected firstly and key gates of key segments in the key segment groups are analyzed when iterating each time) so as to optimize the time sequence yield of the circuit.
As shown in fig. 1, the method comprises the steps of:
step 101, constructing a segment statistical delay model of the CNFET circuit, which specifically comprises the following steps:
step 1: segment delay modeling. When the delay of a complex circuit is analyzed, the circuit is generally divided into a plurality of layers, and then the analysis and delay modeling are carried out step by step, so that the complexity of the circuit can be effectively reduced, and the analysis and calculation are simplified.
Step 1.1: and modeling gate delay. For CNFET circuits, CNT density variations may cause the number of CNTs contained in the push-up network and the PDN (pull-down network) in the logic gates to be different, and thus a conventional CMOS circuit gate delay model is required:improvement is made in which->Representing gate delay +_>Load voltage for gate output, < >>Is constant (I)>In order to input the rate of change,indicating the gate delay when the PUN is on, +.>Represents the output resistance when PUN is on, +.>Indicates gate delay when PDN is on, +.>Representing the output resistance when PDN is on.
The above formula can be bound, and the standard cell gate delay of a CNFET circuit can be expressed as:the method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>Is->And->Is selected from the group consisting of a larger value of (c),is->And->Is a larger value of (a).
Step 1.2: and modeling the gate tree delay. A gate tree is defined as a tree structure of interconnected driving gates and driven gates in a circuit, which describes the logical relationships and signal transmission paths in the gate circuit. The interconnect between the driving and driven gates is represented by a pi model, modeled as an RC tree. By applying the gate delay model to the RC tree, the delay caused by driving the gate output resistance and the interconnect line delay can be obtained. The gate tree delay can thus be expressed as:
。
wherein,delay for the ith gate tree, +.>For the inherent delay of the ith gate tree, < +.>Input rate of change coefficient for ith gate tree,/->Is the ith gate treeInput rate of change, ++>Output resistor for ith gate tree, +.>Parasitic capacitance of interconnection line of ith gate tree and jth gate tree, m is number of gate tree in section, +.>For input capacitance +.>Is the parasitic resistance of the interconnect line of the ith and jth gate trees.
Step 1.3: segment delay modeling. A segment is defined as part of a path in a CNFET circuit. The section contains n gates. One gate tree in each gate drive segment. The segment delay can then be defined as the sum of all gate tree delays within the segment:
。
wherein,is the delay of all gate trees within a segment.
Step 2: statistical delay of segments. In the case where the number of CNTs covered by a CNFET approximately follows a normal distribution, the delay of the CNFET circuit is a random variable. Assuming that the mean and standard deviation of the circuit delay areAnd->Can be used forAs an objective function of the layout algorithm, the timing yield of the circuit is improved by minimizing this objective function.
Step (a)2.1: calculation ofAnd->All gates in the circuit need to be used, which results in a large computational effort. However, optimizing only the critical section delay can effectively improve the overall circuit performance. Then several critical sections of the circuit are selected (i.e. the following critical sections) will be +.>As a segment statistical delay. The mean and variance of its delay can be calculated for each segment:
。
。
wherein,is the mean of the delays of all gate trees in the segment, < >>Variance of delay for all gate trees in a segment, +.>Standard deviation of delay for all gate trees in a segment, +.>Representing the correlation coefficients of the gate trees i and j.
Step 2.2: if for any segment, define:
this is a vector containing n elements, each element representing the delay of a respective gate tree within a segment. Variance of the segment delayCan be simplified as:
。
step 2.3: combining the steps 2.1 and 2.2, a segment statistical delay model can be obtained as follows:
；
wherein,for the segment delay metric, +.>For the mean term coefficient, ++>Is the standard deviation term coefficient->Delay for all gate trees in a segment, +.>And->Function of averaging and function of standard deviation, respectively, +.>Delay for the ith gate tree, n is the number of gate trees in the segment, +.>Vector consisting of delays for each gate tree in a segment, < >>Is a correlation matrix of CNFET circuits. If->And->The same line is->。
In the embodiment of the invention, when the segment delay measurement value of the key segment is carried out based on the segment statistical delay model, the segment of the segment statistical delay model corresponds to the key segment, and one gate tree in the segment corresponds to one key gate.
Step 102, dispersing standard cells in the CNFET circuit by adopting a time sequence driving global layout algorithm.
The specific implementation manner of step 102 in the embodiment of the invention is as follows:
first, an initial layout is performed on the circuit netlist of the input CNFET circuit to distribute the standard cells. Then, using the timing driven global layout algorithm Kraftwerk2, the force required to allocate the standard cells is divided into a holding force for holding the position of the standard cells and a moving force for driving the cells to move, and when the two are balanced, the standard cells are dispersed, and the convergence result is that each layout iteration reduces the overlap of the standard cells until the standard cell overlap percentage is less than a preset threshold. Next, a loop optimization phase is entered, i.e. steps 103-105.
And 103, selecting a key segment group from the plurality of standard units by adopting a statistical static time sequence analysis mode.
Step 104, determining the optimal position of the key gate of each key segment in the key segment group and the segment delay metric value of the current iteration by adopting a mode of optimizing the statistical delay based on the segment statistical delay model.
Step 105, returning to step 103, performing the next iteration until the absolute value of the difference between the segment delay metric value of the current iteration and the segment delay metric value of the previous iteration is smaller than the first preset threshold.
The steps 103-105 of the invention are steps of a cyclic optimization stage, and specifically comprise: before each iteration starts, statistical static time sequence analysis is executed, the time sequence path of each standard unit in the CNFET circuit is extracted, the time sequence is subjected to statistical analysis, so that the latest statistical time sequence information of the CNFET circuit is obtained, then a key segment group is selected according to the information, and the statistical delay is optimized for each key segment in the key segment group.
In the iterative process, the termination condition is checked. If the segment delay metric value of the current iteration is greater than the segment delay metric value of the last iteration, returning a layout result of the last iteration, and if the absolute value of the segment delay metric value difference between two successive iterations is less than a preset threshold (i.e., a first preset threshold, which is 0.02 times the statistical delay of the initially input layout scheme), returning a layout result of the current iteration. When the termination condition is satisfied, the iteration stops.
The specific process of statistical static time sequence analysis can be summarized as the following steps: probability modeling: the parameters in the circuit are subjected to probability modeling, and the statistical properties of the changes of the parameters are considered. And (3) time sequence analysis: and extracting and modeling a time sequence path in the circuit, and carrying out statistical analysis on the time sequence. Statistical analysis: and calculating indexes such as average time delay, maximum time delay, time sequence deviation and the like based on the probability model and the statistical information of the time sequence paths, and indexes such as time sequence sensitivity, fault coverage rate and the like. Further, all vertices with a probability of violation greater than a threshold are identified and then connected into segments, i.e., key segments.
For each key segment, embodiments of the present invention employ a grid-based approach to optimize key gate positions to minimize statistical delay. The algorithm is divided into two phases: the first stage uses a parallel computing method to compute a segment delay metric value when the key gate moves to the center of each adjacent subarea; the second stage uses greedy search algorithm to find key gatesIs defined in the drawings. The method comprises the following specific steps: for each key gate->Firstly, obtaining the boundary box of the input and output network, dividing the surrounding area into eight adjacent subareas, and the widths of the adjacent subareasAnd the height is set to 1/3 of the bounding box width and height. Next, the critical gate is moved to the center of each adjacent sub-region and a segment delay metric value for the critical segment is calculated. Then the adjacent sub-region that gives the smallest segment delay metric value among the eight adjacent sub-regions is selected. If the minimum segment delay metric value is less than the optimum segment statistical delay value for the critical segment, the critical gate is moved to the center of the adjacent sub-region and the eight adjacent sub-regions around the new location are searched again for a better location. Otherwise, the width and height of adjacent sub-areas are halved and the surrounding eight adjacent sub-areas of reduced size are searched for a better location. When the adjacent sub-region is smaller than the threshold h (second preset threshold), the adjustment of the key gate position is stopped, and the next key gate is started to be adjusted. The algorithm repeats this process until all key gate positions are optimized.
The method in the embodiment of the invention can be realized by adopting the following two nested algorithms:
algorithm 1 overall description:
input: a circuit netlist of CNFET circuits.
And (3) outputting: and (5) final layout result.
Step1. Perform the initial layout.
Step2. Performing a timing driven global layout algorithm until the standard cell overlap percentage is less than the set threshold.
Step3, circularly optimizing until the absolute value of the difference between the segment delay metric values of two successive iterations is smaller than a first preset threshold.
Step3.1. statistical static timing analysis.
Step3.2. Using the circuit statistics timing information, select a set of key segments.
Step3.2.1 performs algorithm 2 to optimize the statistical delay for each critical segment within the set of critical segments.
Step4. Returning the final layout result.
The algorithm 2 comprises the following steps:
input: the key segment sg contains N key gates.
And (3) outputting: critical segment sg with optimal gate position to minimize segment statistical delay.
Step1, calculating an initial segment statistical delay measurement value of the key segment sg to serve as an initial optimal segment statistical delay value.
Step2. For each key gate within a key segment sg, its surrounding area is divided into eight adjacent sub-areas.
Step2.1. Calculate in parallel the segment delay metric value for the critical segment when moving to the center of the eight adjacent sub-regions.
Step2.2. Get the minimum segment delay metric value and the corresponding adjacent sub-region.
Step2.3, when the minimum section delay metric value is less than the optimum section statistical delay value, moving the key gate to the center of the corresponding adjacent subarea; otherwise, the neighbor sub-region size re-search will be reduced.
Step2.4. Stopping the position adjustment when the adjacent sub-area size is smaller than the second preset threshold.
Step3, finishing optimizing the key segment sg, and outputting the layout result of the key segment sg.
Experiments on a plurality of test circuits are carried out on the method provided by the embodiment of the invention, and the results show that the method provided by the embodiment of the invention can obviously improve the time sequence yield of the CNFET circuit. Taking the 32-bit multiplier provided by OpenCores as an example, three methods (method a is a change-aware global layout method, method B is a path healing method, and method C is a method proposed by the embodiment of the present invention) are used for testing. In order to obtain more reliable results, each method was run repeatedly five times. According to the experimental results, method a has the best circuit delay optimization effect, reaching 34.9728%, but the average run time is long, about 14.7462 seconds. While the optimization effect of the method C provided by the embodiment of the invention is slightly inferior to that of the method A, the average running time is greatly shortened, about 7.9819 seconds, which is acceptable in a large-scale circuit. The circuit delay optimization effect of method B was the weakest, only 1.7426% and the average run time was 12.1978 seconds. In order to better compare the performance of three algorithms, the embodiment of the invention provides a new evaluation index: unit time delay optimization, which is the percentage of optimization divided by the average run time. The algorithm proposed by the embodiment of the invention can be found to perform best in terms of unit time delay optimization, and the path healing algorithm performs worst. In summary, compared with the existing method, the method provided by the embodiment of the invention is more excellent in running time, is also popular in circuit delay optimization effect, and has potential of application in actual CNFET circuit design.
Example 2
Embodiment 2 of the present invention provides a layout system of a CNFET circuit, the system including:
and the segment statistical delay model construction module is used for constructing a segment statistical delay model of the CNFET circuit.
And the dispersion module is used for dispersing standard units in the CNFET circuit by adopting a time sequence driving global layout algorithm.
The key segment group selecting module is used for selecting the key segment group from the plurality of standard units by adopting a statistical static time sequence analysis mode.
And the optimal position determining module is used for determining the optimal position of the key gate of each key segment in the key segment group and the segment delay metric value of the current iteration by adopting a mode of optimizing the statistical delay based on the segment statistical delay model.
And the return calling module is used for returning to the key segment group selection module and carrying out the next iteration until the absolute value of the difference between the segment delay metric value of the current iteration and the segment delay metric value of the previous iteration is smaller than a first preset threshold value.
Wherein the segment statistical delay model is:
；
wherein,for the segment delay metric, +.>For the mean term coefficient, ++>Is the standard deviation term coefficient->Delay for all gate trees in a segment, +.>And->Function of averaging and function of standard deviation, respectively, +.>Delay for the ith gate tree, n is the number of gate trees in the segment, +.>Vector consisting of delays for each gate tree in a segment, < >>Is a correlation matrix of CNFET circuits.
The optimal position determining module specifically comprises:
and the initializing unit is used for initializing the adjacent subareas of the ith key gate.
And the segment delay metric value calculation unit is used for calculating the segment delay metric value of the key segment when the ith key gate in the key segment moves to the center of each adjacent subarea respectively based on the segment statistical delay model, and obtaining the segment delay metric value corresponding to each adjacent subarea.
And the judging unit is used for judging whether the minimum section delay metric value in the section delay metric values corresponding to each adjacent subarea is smaller than the optimal section statistical delay value or not, and obtaining a judging result.
And the key gate moving unit is used for moving the ith key gate in the key section to the center of the adjacent subarea corresponding to the minimum section delay metric value if the judging result shows yes, updating the optimal section statistical delay value to the minimum section delay metric value and returning to the calling section delay metric value calculating unit.
And the adjacent subarea size updating unit is used for reducing the size of each adjacent subarea if the judging result indicates no, returning to the calling section delay metric value calculating unit until the size of the adjacent subarea is smaller than a second preset threshold value, and outputting the current position of the ith key door as the optimal position of the ith key door.
And the return unit is used for increasing the value of i by 1, returning to the call initialization unit until the optimal positions of all the key gates in the key segment are output, and calculating the segment delay metric value when each key gate in the key segment is positioned at the optimal position of the key gate as the segment delay metric value of the current iteration.
Example 3
An embodiment 3 of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the method described above when executing the computer program.
Example 4
Embodiment 4 of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method described above.
Based on the embodiment, the technical scheme of the invention has the beneficial effects that:
compared with the traditional layout algorithm, the method can evaluate the delay of the circuit more accurately and optimize the circuit time sequence yield more effectively, and meanwhile, the algorithm adopts a cyclic optimization mode to further improve the optimization effect.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (6)
1. A method of layout of a CNFET circuit, the method comprising the steps of:
constructing a segment statistical delay model of the CNFET circuit;
dispersing standard units in the CNFET circuit by adopting a time sequence driving global layout algorithm;
selecting a key segment group from a plurality of standard units by adopting a statistical static time sequence analysis mode;
determining the optimal position of a key gate of each key segment in the key segment group and the segment delay metric value of the current iteration by adopting a mode of optimizing the statistical delay based on the segment statistical delay model;
returning to the step of selecting a key segment group from a plurality of standard units by adopting a statistical static time sequence analysis mode, and performing the next iteration until the absolute value of the difference between the segment delay metric value of the current iteration and the segment delay metric value of the previous iteration is smaller than a first preset threshold;
the segment statistical delay model is:
wherein S is a segment delay metric value, alpha is a mean term coefficient, beta is a standard deviation term coefficient, d seg For the delay of all gate trees in a segment, μ () and σ () are averaged and standard deviation functions, d tree，i For the delay of the ith gate tree, n is the number of gate trees in the segment,the vector of delays for each gate tree within a segment, M is the correlation matrix for the CNFET circuit.
2. The method of arranging CNFET circuits according to claim 1, wherein determining the optimal position of the key gate for each key segment in the set of key segments and the segment delay metric value for the current iteration by optimizing the statistical delay based on the segment statistical delay model comprises:
initializing adjacent subareas of an ith key gate;
calculating a section delay metric value of the key section when an ith key gate in the key section moves to the center of each adjacent subarea respectively based on a section statistical delay model, and obtaining a section delay metric value corresponding to each adjacent subarea;
judging whether the minimum section delay metric value in the section delay metric values corresponding to each adjacent subarea is smaller than the optimal section statistical delay value or not, and obtaining a judging result;
if the judgment result shows that the key gate in the key section is moved to the center of the adjacent subarea corresponding to the minimum section delay metric value, updating the optimal section statistical delay value to the minimum section delay metric value, returning to the step of calculating the section delay metric value of the key section when the i key gate in the key section is respectively moved to the center of each adjacent subarea based on the section statistical delay model, and obtaining the section delay metric value corresponding to each adjacent subarea;
if the judging result shows that the size of each adjacent subarea is not equal to the preset threshold value, reducing the size of each adjacent subarea, calculating the segment delay metric value of the key segment when the ith key gate in the key segment moves to the center of each adjacent subarea respectively based on the segment statistical delay model, and obtaining the segment delay metric value corresponding to each adjacent subarea until the size of each adjacent subarea is smaller than the preset threshold value, and outputting the current position of the ith key gate as the optimal position of the ith key gate;
and (3) increasing the value of i by 1, returning to the step of initializing the adjacent subareas of the ith key gate until the optimal positions of all the key gates in the key segment are output, and calculating the segment delay metric value when each key gate in the key segment is at the optimal position of the key gate as the segment delay metric value of the current iteration.
3. A layout system for a CNFET circuit, the system comprising:
the segment statistical delay model building module is used for building a segment statistical delay model of the CNFET circuit;
the dispersion module is used for dispersing standard units in the CNFET circuit by adopting a time sequence driving global layout algorithm;
the key segment group selecting module is used for selecting a key segment group from a plurality of standard units by adopting a statistical static time sequence analysis mode;
the optimal position determining module is used for determining the optimal position of the key gate of each key segment in the key segment group and the segment delay metric value of the current iteration by adopting a mode of optimizing the statistical delay based on the segment statistical delay model;
the return calling module is used for returning to the key segment group selection module to carry out the next iteration until the absolute value of the difference between the segment delay metric value of the current iteration and the segment delay metric value of the previous iteration is smaller than a first preset threshold value;
the segment statistical delay model is:
wherein S is a segment delay metric value, alpha is a mean term coefficient, beta is a standard deviation term coefficient, d seg For the delay of all gate trees in a segment, μ () and σ () are averaged and standard deviation functions, d tree，i For the delay of the ith gate tree, n is the number of gate trees in the segment,the vector of delays for each gate tree within a segment, M is the correlation matrix for the CNFET circuit.
4. The CNFET circuit layout system of claim 3, wherein the optimal position determination module specifically comprises:
an initializing unit, which is used for initializing the adjacent subareas of the ith key gate;
the segment delay metric value calculation unit is used for calculating the segment delay metric value of the key segment when the ith key gate in the key segment moves to the center of each adjacent subarea respectively based on the segment statistical delay model, and obtaining the segment delay metric value corresponding to each adjacent subarea;
the judging unit is used for judging whether the minimum section delay metric value in the section delay metric values corresponding to each adjacent subarea is smaller than the optimal section statistical delay value or not, and obtaining a judging result;
the key gate moving unit is used for moving the ith key gate in the key section to the center of the adjacent subarea corresponding to the minimum section delay metric value if the judging result shows yes, updating the optimal section statistical delay value to the minimum section delay metric value and returning to the calling section delay metric value calculating unit;
the adjacent subarea size updating unit is used for reducing the size of each adjacent subarea if the judging result indicates no, returning to the calling section delay metric value calculating unit until the size of the adjacent subarea is smaller than a second preset threshold value, and outputting the current position of the ith key door as the optimal position of the ith key door;
and the return unit is used for increasing the value of i by 1, returning to the call initialization unit until the optimal positions of all the key gates in the key segment are output, and calculating the segment delay metric value when each key gate in the key segment is positioned at the optimal position of the key gate as the segment delay metric value of the current iteration.
5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 2 when executing the computer program.
6. A computer readable storage medium, characterized in that a computer program is stored thereon, which program, when being executed by a processor, implements the method of any of claims 1 to 2.
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| CN113544688A (en) * | 2018-09-10 | 2021-10-22 | 麻省理工学院 | System and method for designing integrated circuits |
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| WO2008127773A2 (en) * | 2007-02-28 | 2008-10-23 | Motorola, Inc. | Carbon nanotube circuits design methodology |
| CN113544688A (en) * | 2018-09-10 | 2021-10-22 | 麻省理工学院 | System and method for designing integrated circuits |
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