CN116662006A - Method, system, device and medium for managing renaming resources of multithreaded processor - Google Patents
Method, system, device and medium for managing renaming resources of multithreaded processor Download PDFInfo
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Abstract
The invention provides a renaming resource management method, a renaming resource management system, a renaming resource management device and a renaming resource management medium for a multithreading processor, wherein the renaming resource management method comprises the following steps: responding to thread instruction receiving, sequentially carrying out pipeline processing on the thread instruction according to the sequence of instruction fetching decoding, renaming, instruction scheduling and instruction submitting; when a thread instruction enters a renaming stage, a virtual renaming resource number is allocated for the thread instruction in a virtual renaming resource domain, and a resource corresponding mark is added to the virtual renaming resource number; when the thread instruction enters the instruction scheduling stage, judging whether the virtual renaming resource number corresponds to the real renaming resource according to the resource correspondence mark, if so, distributing the real renaming resource number for the thread instruction and scheduling the execution, otherwise, waiting until the virtual renaming resource number is converted into the real renaming resource number and then scheduling the execution. The invention can effectively reduce the probability that the linear instruction in the processor is blocked in the renaming stage due to insufficient renaming resources, and improve the running efficiency of the multithreading processor.
Description
Technical Field
The present invention relates to the field of processor design technologies, and in particular, to a method, a system, an apparatus, and a medium for managing renaming resources of a multithreaded processor.
Background
Insufficient register renaming resources are a common cause of blocking pipeline operation in processor operation. The processing mode of insufficient resources in register renaming is generally to block the front-end instruction from being submitted first, wait for renaming resources to be ready, and then release the blocked instruction stream. The simple blocking instruction flow processing mode does not have great influence on a single-thread processor with higher instruction correlation, and for a multithreaded processor, when a certain type of renaming resources are insufficient, threads which do not need the renaming resources are blocked, so that the false correlation of instruction processing among different threads is increased, all thread instructions are blocked in a renaming pipeline, and the running efficiency of the multithreaded processor is further reduced.
Although the existing method of increasing the number of renaming resources of a processor can effectively reduce the pipeline blocking probability of a multithreaded processor, the method inevitably causes the excessive processor area, and further introduces the problem of increased timing convergence difficulty.
Disclosure of Invention
The invention aims to provide a renaming resource management method of a multithreading processor, which dynamically manages renaming resources which are distributed in a renaming stage and are directly used after the renaming stage by setting a virtual renaming resource domain, delays a pipeline blocking period to a reservation station, eliminates the false correlation among multithreading instructions, solves the application defect of the prior renaming resource management method of the multithreading processor, reduces the probability that the thread instructions in the multithreading processor are blocked at a front pipeline due to insufficient renaming resources, and improves the running efficiency of the multithreading processor.
In order to achieve the above object, it is necessary to provide a method and a system for renaming resource management of a multithreaded processor.
In a first aspect, an embodiment of the present invention provides a renaming resource management method for a multithreaded processor, in response to receiving a thread instruction, performing pipeline processing on the thread instruction sequentially in the order of instruction fetch decoding, renaming, instruction scheduling, and instruction submission, where the method includes the following steps:
when the thread instruction enters a renaming stage, distributing a corresponding virtual renaming resource number for the thread instruction in a preset virtual renaming resource domain, and adding a resource corresponding mark to the virtual renaming resource number;
When the thread instruction enters an instruction scheduling stage, judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark, if so, distributing the real renamed resource number for the thread instruction and scheduling execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling execution.
Further, the step of presetting the virtual renaming resource domain includes:
and setting a virtual renaming resource domain with a preset size according to the real renaming resource number and the reservation station entry number of the multithreading processor.
Further, the resource correspondence indicia includes a corresponding real resource and a non-corresponding real resource; the step of adding the virtual renamed resource number with a resource corresponding mark comprises the following steps:
obtaining the number of remaining renamed resources in the true renamed resource domain according to a preset resource counter; the upper limit of the count of the resource counter is the real renamed resource number of the multithreaded processor;
when the number of the remaining renamed resources is zero, setting the resource corresponding mark of the virtual renamed resource number as a real resource which is not corresponding to the virtual renamed resource number;
And when the number of the remaining renamed resources is not zero, setting the resource corresponding mark of the virtual renamed resource number as the corresponding real resource.
Further, the step of adding the virtual renaming resource number with a resource correspondence flag includes:
when the resource corresponding mark is not corresponding to the real resource, respectively generating a corresponding first real resource conversion request and a corresponding second real resource conversion request according to the corresponding virtual renamed resource number and thread number;
and writing the first real resource conversion request into a thread sub first-in first-out buffer memory corresponding to the thread instruction, and simultaneously writing the second real resource conversion request into a main first-in first-out buffer memory shared by all thread instructions.
Further, the step of converting the corresponding virtual renamed resource number into the real renamed resource number includes:
acquiring the current residual real renamed resource number according to the resource counter, and acquiring monitoring information of each thread number when the current residual real renamed resource number is not zero; obtaining corresponding real resource conversion priority according to the monitoring information of each thread number, and obtaining at least one thread number to be converted according to the real resource conversion priority of each thread number;
Obtaining a virtual rename resource number to be converted according to the thread number to be converted, and distributing a corresponding real rename resource number for the virtual rename resource number to be converted;
and responding to the completion of the allocation of the real renamed resource numbers corresponding to the virtual renamed resource numbers to be converted, and clearing the corresponding first real resource conversion request and second real resource conversion request.
Further, the monitoring information comprises thread priority, thread instruction number of the fetch decoding stage and first real resource conversion request number of the thread sub first-in first-out buffer.
Further, the step of obtaining the corresponding real resource conversion priority according to the monitoring information of each thread includes:
and carrying out weighted summation on each monitoring information according to the corresponding preset weight value to obtain the real resource conversion priority.
Further, the step of obtaining at least one thread number to be converted according to the real resource conversion priority of each thread number includes:
and selecting the maximum value in all the real resource conversion priorities, and taking the thread number corresponding to the maximum value as the thread number to be converted.
Further, the step of obtaining the number of the virtual renamed resource to be converted according to the number of the thread to be converted includes:
When the thread number to be converted is one, reading a first real resource conversion request written first in a corresponding thread sub first-in first-out buffer memory, and taking a virtual rename resource number corresponding to the first real resource conversion request written first as the virtual rename resource number to be converted;
when the number of the threads to be converted is multiple, reading a first written second real resource conversion request corresponding to the threads to be converted from the main first-in first-out buffer memory, taking the thread number corresponding to the first written second real resource conversion request as a preferred conversion thread number, reading a first real resource conversion request which is written first in the thread sub first-in first-out buffer memory corresponding to the preferred conversion thread number, and taking a virtual renaming resource number corresponding to the first real resource conversion request which is written first as the virtual renaming resource number to be converted.
In a second aspect, an embodiment of the present invention provides a multi-threaded processor renaming resource management system, responsive to receipt of a thread instruction, for sequentially pipeline processing the thread instruction in an order of instruction fetch decode, renaming, instruction scheduling, and instruction commit, the system comprising:
The virtual resource allocation module is used for allocating corresponding virtual renaming resource numbers for the thread instructions in a preset virtual renaming resource domain when the thread instructions enter a renaming stage, and adding resource corresponding marks to the virtual renaming resource numbers;
and the real resource conversion module is used for judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark when the thread instruction enters the instruction scheduling stage, if so, distributing the real renamed resource number for the thread instruction and scheduling execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling execution.
In a third aspect, an embodiment of the present invention further provides a multi-threaded processor renaming resource management apparatus, the apparatus including:
a memory storing executable program code;
an actuator coupled to the memory;
the executor invokes the executable program code stored in the memory to perform the method steps described above.
In a fourth aspect, embodiments of the present invention also provide a computer storage medium having stored thereon computer instructions which, when invoked, perform the above-described method steps.
The application provides a method, a system, a device and a medium for managing renamed resources of a multithreaded processor, which are used for realizing the pipeline processing of the thread instructions according to the sequence of instruction fetching decoding, renaming, instruction scheduling and instruction submitting in turn in response to the thread instruction receiving. Compared with the prior art, the renaming resource management method of the multithreading processor dynamically manages renaming resources which are distributed in a renaming stage and can be directly used after the renaming stage by setting the virtual renaming resource domain, delays the pipeline blocking period to a reservation station, eliminates the false correlation among multithreading instructions, effectively reduces the probability that the thread instructions in the multithreading processor are blocked at the front pipeline due to insufficient renaming resources, improves the operation efficiency of the multithreading processor, and further provides reliable technical support for the efficient operation of the multithreading processor while not increasing the area of the processor and not increasing the time sequence convergence difficulty.
Drawings
FIG. 1 is a schematic diagram of a multithreaded instruction processing flow for a conventional multithreaded processor;
FIG. 2 is a schematic diagram of pipeline processing flow with pipeline blocking in rename stage when existing rename resources are insufficient;
FIG. 3 is a flow chart of a method for renaming resources in a multithreaded processor in accordance with an embodiment of the application;
FIG. 4 is a schematic flow diagram of a pipeline process employing multi-threaded processor renaming resource management in accordance with the present application;
FIG. 5 is a flow chart of converting a virtual renamed resource into a real renamed resource in an embodiment of the application;
FIG. 6 is a schematic diagram of a multi-threaded processor renaming resource management system in accordance with an embodiment of the application;
FIG. 7 is a block diagram of a multi-threaded processor renaming resource management apparatus in accordance with an embodiment of the application.
Detailed Description
In order to make the objects, technical solutions and advantageous effects of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples, and it is apparent that the examples described below are part of the examples of the present application, which are provided for illustration only and are not intended to limit the scope of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The renaming resource management method of the multithreading processor provided by the invention is based on the fact that when renaming resources are unavailable in a renaming stage of a certain thread instruction in the operation of the multithreading processor shown in the prior art in FIG. 1, the renaming resource allocation management method shown in FIG. 2 is adopted, so that other subsequent thread instructions which are not related to the renaming resource allocation management method can be blocked, the renaming resource management defect of the pipeline efficiency of the multithreading processor is greatly reduced, and the pipeline efficiency of the multithreading processor is reliably improved by setting a renaming resource which is only allocated but not directly used in a virtual renaming resource domain dynamic management renaming stage. The following examples will illustrate the multi-threaded processor renaming resource management method of the present invention in detail.
In one embodiment, as shown in FIG. 3, a method for renaming resources in a multithreaded processor is provided, in response to receiving a thread instruction, pipelining the thread instruction sequentially in the order of instruction fetch decode, renaming, instruction scheduling, and instruction commit, comprising the steps of:
In this embodiment, the pipeline processing still employs a general pipeline timing, which includes four pipeline processing stages: 1) A finger-taking decoding stage; 2) A renaming stage; 3) An instruction scheduling stage; 4) Instruction commit phase. For a multithreaded processor, thread instructions input by the instruction fetching decoding stage and the renaming stage are sequentially executed, and in the instruction scheduling stage, instructions are dynamically scheduled to execute according to whether resources required by instruction processing are available or not, namely the stage of instructions are converted from sequential execution to out-of-order execution, so that even if the resources required by the instructions entering the instruction scheduling stage earlier are not available, the processor can select the instructions with available resources from the instructions entering the instruction scheduling stage after the instruction execution stage; therefore, the instruction scheduling stage ensures the utilization rate of a processor pipeline to a certain extent by utilizing the non-relevant out-of-order processing mode among instructions, and further improves the running efficiency of the multithreaded processor.
Based on the characteristics of processing each stage in a processor pipeline operation mechanism, in order to better exert the advantage effect that the out-of-order processing of the instruction scheduling stage improves the pipeline utilization rate on the basis of avoiding the disadvantage effect of the pipeline efficiency caused by the fact that the sequential processing of the renaming stages is reduced as much as possible, and further improve the operation efficiency of the multithreaded processor, the embodiment is preferred to simply and reliably solve the problem of false correlation among low-correlation instructions of different threads caused by the fact that the existing renaming stages are blocked by adding a virtual renaming resource domain and combining with the processing optimization of the renaming stages and the instruction scheduling stage on the basis of keeping the existing processor pipeline processing time sequence, so that efficient and reliable allocation management of each renaming resource in the real renaming resource domain is truly realized.
S11, when the thread instruction enters a renaming stage, distributing a corresponding virtual renaming resource number for the thread instruction in a preset virtual renaming resource domain, and adding a resource corresponding mark to the virtual renaming resource number; the virtual renaming resource domain is understood to be a virtual resource set which is used for replacing the real renaming resource domain in advance and realizing the functions required to be met by the real renaming resource domain which is only allocated and not used really in the renaming stage. In order to avoid the adverse effect of the pipeline efficiency caused by sequential processing of renaming stages as much as possible, in principle, the size of the virtual renaming resource domain only needs to be larger than that of the real renaming resource domain to meet the requirement of reducing the pipeline blocking probability of the renaming stages to a certain extent, but considering the limitation of the processing performance of each stage of the pipeline of the actual processor, in order to effectively reduce the front-end pipeline blocking probability on the basis of not reducing the processing performance of each stage of the pipeline, the embodiment preferably increases the size of the virtual renaming resource domain as much as possible under the condition that the storage performance of an instruction scheduling stage can be supported; specifically, the step of presetting the virtual renaming resource domain includes:
Setting a virtual renaming resource domain with a preset size according to the real renaming resource number and the reserved station entry number of the multithreading processor; the reservation station is understood to be a storage structure used for storing instruction information in an instruction scheduling stage, and in practical application, when an instruction operand or renamed resource is not ready, the instruction information stays in the reservation station and cannot be moved out until the instruction scheduling condition is met and scheduled to be executed; the preset size of the virtual renaming resource domain in this embodiment is set to meet the application requirement of the above analysis as much as possible, and is preferably set to be the sum of the number of reserved entries and the number of actual renaming resources.
The resource correspondence flag may be understood as a record of whether the real renamed resource in the real renamed resource domain can be used while the virtual renamed resource number is allocated when the program instruction processing enters the instruction renaming stage; correspondingly, the resource corresponding mark comprises a corresponding real resource and a non-corresponding real resource, wherein the corresponding real resource can be understood as the fact that the thread instruction which enters a renaming stage currently allocates a virtual renaming resource number and simultaneously has available real renaming resources in a real renaming resource domain, and can be directly dispatched and executed in an instruction dispatching stage subsequently; similarly, the fact that the thread instruction which does not correspond to the real resource can be understood as that when the thread instruction which enters the renaming stage currently allocates the virtual renaming resource number, the real renaming resource domain does not have available real renaming resources, and the real renaming resource which is released later needs to be dynamically scheduled to allocate the real renaming resource and then be scheduled to be executed; in order to ensure the reliability of the label, the embodiment preferably dynamically updates the number of available real renamed resources by introducing a resource counter so as to realize accurate recording of the resource corresponding label of each virtual renamed resource number; specifically, the step of adding the resource corresponding mark to the virtual renamed resource number includes:
Obtaining the number of remaining renamed resources in the true renamed resource domain according to a preset resource counter; the upper limit of the count of the resource counter is the real renamed resource number of the multithreaded processor;
when the number of the remaining renamed resources is zero, setting the resource corresponding mark of the virtual renamed resource number as a real resource which is not corresponding to the virtual renamed resource number;
and when the number of the remaining renamed resources is not zero, setting the resource corresponding mark of the virtual renamed resource number as the corresponding real resource.
In practical application, after the accurate recording of the resource corresponding marks of the virtual renaming resource numbers of each thread instruction is realized through the method steps, the real renaming resources can be dynamically allocated according to a certain dynamic management rule by inquiring the corresponding resource corresponding marks in the instruction scheduling stage, but in consideration of that although all the instructions of all the threads are sequentially allocated with the resource numbers in the virtual renaming resource domain according to the time sequence of entering the renaming stage without branching threads, the real renaming resources can not be allocated, the execution can be scheduled after the instructions are required to be allocated with the real renaming resources in the subsequent instruction scheduling stage, in order to be convenient for the instruction scheduling stage to effectively perceive which thread instructions do not correspond to the real renaming resources, and in order to realize the efficient multi-thread processing while following the working time sequence of the existing pipeline, the virtual renaming resources which do not correspond to the real renaming resources are efficiently and reasonably converted into the real renaming resources, the virtual renaming resources can be reliably provided for the high-efficient processing of the instructions in the multi-thread processor according to the time sequence of entering the corresponding instruction, the virtual renaming resources can be reliably set up and the corresponding instruction is input to the corresponding instruction with the real renaming resources of all the corresponding threads by the prior instruction, the priority is set up a plurality of the priority instruction is input to the corresponding to the virtual renaming resources, the priority instruction is input to the corresponding instruction with the real renaming resources, the priority instruction is input to the corresponding instruction is input to the real renaming resources, and the real renaming resources are not corresponding to real renamed resources, providing reliable basis for dynamically screening threads which are preferentially allocated with real renamed resources and corresponding virtual renamed resource numbers in the instruction scheduling stage;
Specifically, as shown in fig. 5, the step of adding the resource corresponding label to the virtual renamed resource number includes:
when the resource corresponding mark is not corresponding to the real resource, respectively generating a corresponding first real resource conversion request and a corresponding second real resource conversion request according to the corresponding virtual renamed resource number and thread number;
writing the first real resource conversion request into a thread sub-first-in first-out buffer memory corresponding to the thread instruction, and simultaneously writing the second real resource conversion request into a main first-in first-out buffer memory shared by all thread instructions; the number of the thread sub-first-in first-out caches is the same as the total number of the threads running in the processor, and the size of each thread sub-first-in first-out cache is consistent with the total number of entries supported to be stored by the reservation station; meanwhile, the size of the main first-in first-out buffer memory is consistent with the total number of entries supported to be stored by the reservation station.
S12, when the thread instruction enters an instruction scheduling stage, judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark, if so, distributing the real renamed resource number for the thread instruction and scheduling the execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling the execution;
In practical application, when the processing of the thread instruction enters the instruction scheduling stage, it is checked whether the resource corresponding mark corresponding to the allocated virtual renamed resource number is a corresponding real renamed resource: if yes, judging that the instruction can be scheduled to be executed, and distributing a real rename resource number for the instruction when the instruction is scheduled to be executed; if not, the instruction is judged to be needed to be executed after waiting to be allocated with real renamed resources in a dispatching stage. Therefore, how to dynamically allocate real rename resources according to the information recorded by the main first-in first-out buffer and each thread sub first-in first-out buffer will directly affect the operation efficiency of the multithreaded processor.
Considering that the correlation of instructions of different threads in the multithreaded processor is low, if the requests are converted (real renaming resources are allocated) only according to the sequence of converting requests generated by the instructions, the false correlation of the instructions among the different threads is caused, and the efficiency of the multithreaded processor is further damaged; specifically, as shown in fig. 5, the step of converting the corresponding virtual renamed resource number into the real renamed resource number includes:
Acquiring the current residual real renamed resource number according to the resource counter, and acquiring monitoring information of each thread number when the current residual real renamed resource number is not zero; obtaining corresponding real resource conversion priority according to the monitoring information of each thread number, and obtaining at least one thread number to be converted according to the real resource conversion priority of each thread number; the monitoring information can be set according to actual running requirements of different multithreaded processors, in principle, the more relevant information is acquired, the more reliable the scheduling basis is obtained according to the monitoring information, but in order to realize the balance between the effective guarantee of the scheduling basis and the occupation of the processor resources, the preferred monitoring information in the embodiment comprises thread priority, the thread instruction number of the instruction fetching decoding stage and the first real resource conversion request number of the thread sub first-in first-out buffer;
meanwhile, considering that the influence of each monitoring information on the instruction processing priority is different, how to reasonably utilize each monitoring information directly influences the reliability of the real resource conversion priority of each thread, and further influences the reasonability of the dynamic allocation of the real renamed resources of the processor; specifically, the step of obtaining the corresponding real resource conversion priority according to the monitoring information of each thread includes:
Each monitoring information is weighted and summed according to the corresponding preset weight value, and the real resource conversion priority is obtained; the detailed process of real resource conversion priority calculation can be realized by referring to the following examples: for example, the number of entries in each thread sub-fifo buffer is the number of entries to be converted for each thread, and the preset weight value of such monitoring information may be set to 1; taking instructions of each thread in the instruction decoding stage as instructions to be in a renaming stage, and setting a preset weight value of the monitoring information to be 0.4; the priority of each thread in the processor can be dynamically set according to the high, medium and low grades, and corresponding preset weight values are respectively given to be 3, 2 and 1; finally, accumulating the calculated priorities of various monitoring information of each thread; if the thread 0 has high priority, the number of requests to be converted in the thread sub-first-in first-out buffer memory is x, the instruction number of the instruction belonging to the thread 0 in the instruction fetching and decoding stage is y, and the calculated real resource conversion priority of the thread 0 is 3+x+0.4y; it should be noted that, the setting of the preset weight values of the various monitoring information in the above calculation process is only described as an example, and may be preferably set according to the actual situation in practical application, which is not limited herein.
In addition, in order to meet the timeliness requirement of each thread instruction processing on the basis of following the timeliness of each thread instruction input as far as possible, and further effectively ensure the high efficiency of the operation of the multithreaded processor, in this embodiment, preferably, when there is a real resource conversion request in the processor and a real renamed resource domain has residual available real renamed resources, the processor will perform priority conversion on one thread with the highest conversion priority; specifically, the step of obtaining at least one thread number to be converted according to the real resource conversion priority of each thread number includes:
and selecting the maximum value in all the real resource conversion priorities, and taking the thread number corresponding to the maximum value as the thread number to be converted.
Obtaining a virtual rename resource number to be converted according to the thread number to be converted, and distributing a corresponding real rename resource number for the virtual rename resource number to be converted; the thread numbers to be converted are determined according to the maximum value obtained by sequencing the real resource conversion priorities corresponding to the threads, and in practical application, a plurality of threads have the highest real resource conversion priority at a certain moment, so that more than one thread number to be converted is obtained through screening, at the moment, other selection basis is needed to be introduced to further determine the final preferred conversion thread number, and then a priority conversion request is determined according to the preferred conversion thread number; based on the diversity of the application scenes of the actual dynamic allocation of the actual renamed resources, in order to ensure the high efficiency and the accuracy of the scheduling of each priority conversion request, in this embodiment, different priority conversion request scheduling schemes are preferably set for different application scenes of which the thread numbers to be converted are one or more; specifically, the step of obtaining the number of the virtual renamed resource to be converted according to the number of the thread to be converted includes:
When the thread number to be converted is one, reading a first real resource conversion request written first in a corresponding thread sub first-in first-out buffer memory, and taking a virtual rename resource number corresponding to the first real resource conversion request written first as the virtual rename resource number to be converted; it should be noted that when the thread number to be converted is one, the corresponding thread sub first-in first-out buffer memory can be directly read according to the thread number to be converted, the conversion request (the oldest first real resource conversion request written into the buffer memory at the top end) at the top end in the thread sub first-in buffer memory is read out, and the real renamed resource number is allocated to the conversion request, so that the mapping between the virtual renamed resource number corresponding to the request and the real renamed resource number is realized, and preparation is provided for the subsequent instruction scheduling execution;
when the number of the threads to be converted is multiple, reading a first written second real resource conversion request corresponding to the threads to be converted from the main first-in first-out buffer memory, taking the thread number corresponding to the first written second real resource conversion request as a preferred conversion thread number, reading a first real resource conversion request which is written first in the thread sub first-in first-out buffer memory corresponding to the preferred conversion thread number, and taking a virtual renaming resource number corresponding to the first real resource conversion request which is written first as the virtual renaming resource number to be converted; when the number of the threads to be converted is multiple, each thread number to be converted is required to be matched with the thread number written in the main first-in first-out buffer according to the time sequence, the oldest second real resource conversion request which is written in first and is corresponding to one of the thread numbers to be converted is found, then the thread number in the second real resource conversion request is read as the preferred conversion thread number, the corresponding thread sub first-in first-out buffer is read according to the preferred thread number, the oldest first real resource conversion request which is written first in the buffer is obtained, and the real renaming resource number is allocated to the oldest first real resource conversion request, so that the mapping of the virtual renaming resource number corresponding to the request and the real renaming resource number is realized, and preparation is provided for the subsequent instruction scheduling execution; for example, the record from top to top in the main fifo buffer is "thread 1 thread 2 thread 3 thread 2", and the threads to be converted are thread 2 and thread 3, then the first written conversion request screened from the main fifo buffer is the second real resource conversion request with the content of "thread 2", the corresponding preferred conversion thread number (thread 2) can be obtained by reading the request, then the first written real resource conversion request at the top of the sub fifo buffer corresponding to thread 2 is read to obtain the virtual renaming resource number (e.g. 15) to be converted, and then the real renaming resource numbers corresponding to the virtual renaming resource numbers (15) respectively.
Responding to the completion of the allocation of the real renamed resource numbers corresponding to the virtual renamed resource numbers to be converted, and clearing the corresponding first real resource conversion request and second real resource conversion request;
after the effective conversion between the virtual renaming resources and the real renaming resources is realized, the screened first real resource conversion request is cleared from the thread sub-first-in first-out buffer, and the oldest second real resource conversion request of the thread recorded in the main first-in first-out buffer is also deleted in time, so that the high efficiency and the reliability of the dynamic allocation management of the subsequent real resource renaming resources can be effectively ensured while the invalid occupation of the buffer resources is avoided.
According to the embodiment of the application, the thread instruction is sequentially subjected to pipeline processing according to the sequences of instruction fetching decoding, renaming, instruction scheduling and instruction submission, when the thread instruction enters a renaming stage, corresponding virtual renaming resource numbers are allocated for the thread instruction in a preset virtual renaming resource domain, resource corresponding marks are added to the virtual renaming resource numbers, when the thread instruction enters an instruction scheduling stage, according to the corresponding resource corresponding marks, whether the corresponding virtual renaming resource numbers correspond to real renaming resources or not is judged, if so, the real renaming resource numbers are allocated for the thread instruction and execution is scheduled, otherwise, the virtual renaming resource numbers are waited until the corresponding virtual renaming resource numbers are converted into the real renaming resource numbers, then the execution is rescheduled, by setting the virtual renaming resource domain, the renaming resource which is allocated in the renaming stage and is directly used after the stage is dynamically managed, the probability that the instruction in the renaming stage is blocked is reduced, the influence of the renaming resource deletion is prolonged to the instruction scheduling stage, the false relativity among the multithreading instruction is eliminated, the processor is improved, the efficiency of the multiple thread processor can be balanced when the multiple thread processors are not in terms of the time sequence information, the priority is balanced, the efficiency of the processing of the multiple thread processor is improved, and the time sequence resource is not balanced, and the processing efficiency of the multiple thread processor can be reasonably used in terms of the time sequence information is guaranteed, reliable technical support is provided for efficient operation of the multithreaded processor.
Although the steps in the flowcharts described above are shown in order as indicated by arrows, these steps are not necessarily executed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders.
In one embodiment, as shown in FIG. 6, a multi-threaded processor renaming resource management system is provided that, in response to receipt of a thread instruction, sequentially pipeline the thread instruction in the order of instruction fetch decode, renaming, instruction scheduling, and instruction commit, the system comprising:
the virtual resource allocation module 1 is configured to allocate a corresponding virtual rename resource number to the thread instruction in a preset virtual rename resource domain when the thread instruction enters a rename stage, and add a resource corresponding mark to the virtual rename resource number; the resource corresponding mark comprises a corresponding real resource and a non-corresponding real resource;
and the real resource conversion module 2 is used for judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark when the thread instruction enters the instruction scheduling stage, if so, distributing the real renamed resource number for the thread instruction and scheduling the execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling the execution.
For a specific limitation of a multi-threaded processor renaming resource management system, reference may be made to the limitation of a multi-threaded processor renaming resource management method hereinabove, and the corresponding technical effects may be equally obtained, which will not be described herein. The various modules in a multi-threaded processor renaming resource management system described above may be implemented in whole or in part in software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, as shown in FIG. 7, there is provided a multi-threaded processor renaming resource management apparatus comprising: a memory storing executable program code; an actuator coupled to the memory; the executor performs the above method steps when calling executable program code stored in the memory.
In one embodiment, a computer storage medium having stored thereon computer instructions which when invoked perform the above method steps is provided.
In summary, the multithread processor renaming resource management method, system, device and medium provided by the embodiment of the invention realizes the technical scheme of sequentially carrying out pipeline processing on thread instructions according to the sequences of instruction fetching decoding, renaming, instruction scheduling and instruction submission by responding to thread instruction receiving, when the thread instructions enter a renaming stage, distributing corresponding virtual renaming resource numbers for the thread instructions in a preset virtual renaming resource domain, adding resource corresponding marks to the virtual renaming resource numbers, judging whether the corresponding virtual renaming resource numbers correspond to real renaming resources according to the corresponding resource corresponding marks when the thread instructions enter an instruction scheduling stage, if so, distributing real renaming resource numbers for the thread instructions and scheduling execution, otherwise, waiting for the corresponding virtual renaming resource numbers to be converted into the real renaming resource numbers, dynamically managing renaming resources which are directly used after the stage by the thread instructions, eliminating blocking period to a corresponding thread station after the renaming stage, reducing the probability of converting the multithread instruction into the multithread processor to be used in the multithread processor when the multithread processor is not in the multithread instruction renaming stage, and the multithread processor has the history information is fully utilized, the dynamic scheduling of the real renamed resources is reasonably balanced with the occupation of the processor resources according to the validity guarantee, so that the running efficiency of the multithreaded processor is improved, and reliable technical support is provided for the efficient running of the multithreaded processor while the area of the processor is not increased and the timing sequence convergence difficulty is not increased.
In this specification, each embodiment is described in a progressive manner, and all the embodiments are directly the same or similar parts referring to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments. It should be noted that, any combination of the technical features of the foregoing embodiments may be used, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few preferred embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present application, and such modifications and substitutions should also be considered to be within the scope of the present application. Therefore, the protection scope of the patent of the application is subject to the protection scope of the claims.
Claims (12)
1. A method for renaming resources in a multithreaded processor, responsive to receipt of a thread instruction, for pipelining the thread instruction sequentially in the order of instruction fetch decoding, renaming, instruction scheduling, and instruction submission, the method comprising the steps of:
when the thread instruction enters a renaming stage, distributing a corresponding virtual renaming resource number for the thread instruction in a preset virtual renaming resource domain, and adding a resource corresponding mark to the virtual renaming resource number;
when the thread instruction enters an instruction scheduling stage, judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark, if so, distributing the real renamed resource number for the thread instruction and scheduling execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling execution.
2. The method of claim 1, wherein the step of pre-setting a virtual rename resource domain comprises:
and setting a virtual renaming resource domain with a preset size according to the real renaming resource number and the reservation station entry number of the multithreading processor.
3. The multi-threaded processor renaming resource management method of claim 1 wherein the resource correspondence indicia includes corresponding real resources and non-corresponding real resources; the step of adding the virtual renamed resource number with a resource corresponding mark comprises the following steps:
obtaining the number of remaining renamed resources in the true renamed resource domain according to a preset resource counter; the upper limit of the count of the resource counter is the real renamed resource number of the multithreaded processor;
when the number of the remaining renamed resources is zero, setting the resource corresponding mark of the virtual renamed resource number as a real resource which is not corresponding to the virtual renamed resource number;
and when the number of the remaining renamed resources is not zero, setting the resource corresponding mark of the virtual renamed resource number as the corresponding real resource.
4. The method of claim 3, wherein the step of adding a resource correspondence tag to the virtual rename resource number comprises:
when the resource corresponding mark is not corresponding to the real resource, respectively generating a corresponding first real resource conversion request and a corresponding second real resource conversion request according to the corresponding virtual renamed resource number and thread number;
And writing the first real resource conversion request into a thread sub first-in first-out buffer memory corresponding to the thread instruction, and simultaneously writing the second real resource conversion request into a main first-in first-out buffer memory shared by all thread instructions.
5. The method of claim 4, wherein the step of converting the corresponding virtual rename resource number to a real rename resource number comprises:
acquiring the current residual real renamed resource number according to the resource counter, and acquiring monitoring information of each thread number when the current residual real renamed resource number is not zero; obtaining corresponding real resource conversion priority according to the monitoring information of each thread number, and obtaining at least one thread number to be converted according to the real resource conversion priority of each thread number;
obtaining a virtual rename resource number to be converted according to the thread number to be converted, and distributing a corresponding real rename resource number for the virtual rename resource number to be converted;
and responding to the completion of the allocation of the real renamed resource numbers corresponding to the virtual renamed resource numbers to be converted, and clearing the corresponding first real resource conversion request and second real resource conversion request.
6. The method of claim 5, wherein the monitoring information includes thread priority, a number of thread instructions to fetch a decode stage, and a first real resource translation request number of a thread child first-in-first-out cache.
7. The method of claim 5, wherein the step of obtaining the corresponding real resource conversion priority based on the monitoring information of each thread comprises:
and carrying out weighted summation on each monitoring information according to the corresponding preset weight value to obtain the real resource conversion priority.
8. The method of claim 5, wherein the step of obtaining at least one thread number to be translated based on real resource translation priorities of respective thread numbers comprises:
and selecting the maximum value in all the real resource conversion priorities, and taking the thread number corresponding to the maximum value as the thread number to be converted.
9. The method of claim 5, wherein the step of obtaining a virtual rename resource number to be converted from the thread number to be converted comprises:
When the thread number to be converted is one, reading a first real resource conversion request written first in a corresponding thread sub first-in first-out buffer memory, and taking a virtual rename resource number corresponding to the first real resource conversion request written first as the virtual rename resource number to be converted;
when the number of the threads to be converted is multiple, reading a first written second real resource conversion request corresponding to the threads to be converted from the main first-in first-out buffer memory, taking the thread number corresponding to the first written second real resource conversion request as a preferred conversion thread number, reading a first real resource conversion request which is written first in the thread sub first-in first-out buffer memory corresponding to the preferred conversion thread number, and taking a virtual renaming resource number corresponding to the first real resource conversion request which is written first as the virtual renaming resource number to be converted.
10. A multithreaded processor renaming resource management system for sequentially pipelining thread instructions in the order of instruction fetch decoding, renaming, instruction scheduling, and instruction submission in response to thread instruction receipt, the system comprising:
The virtual resource allocation module is used for allocating corresponding virtual renaming resource numbers for the thread instructions in a preset virtual renaming resource domain when the thread instructions enter a renaming stage, and adding resource corresponding marks to the virtual renaming resource numbers;
and the real resource conversion module is used for judging whether the corresponding virtual renamed resource number corresponds to the real renamed resource according to the corresponding resource corresponding mark when the thread instruction enters the instruction scheduling stage, if so, distributing the real renamed resource number for the thread instruction and scheduling execution, otherwise, waiting until the corresponding virtual renamed resource number is converted into the real renamed resource number and then scheduling execution.
11. A multi-threaded processor renaming resource management device, the device comprising:
a memory storing executable program code;
an actuator coupled to the memory;
the executor invoking the executable program code stored in the memory to perform the multi-threaded processor renaming resource management method of any of claims 1-9.
12. A computer storage medium having stored thereon computer instructions which, when invoked, perform the multi-threaded processor renaming resource management method of any of claims 1-9.
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| US7290261B2 (en) * | 2003-04-24 | 2007-10-30 | International Business Machines Corporation | Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor |
| CN101601008A (en) * | 2007-01-24 | 2009-12-09 | 高通股份有限公司 | Be used for the use of the register rename system of forwarding intermediate result between the composition instruction of extended instruction |
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